Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a storage system and a manufacturing method of the semiconductor device. The semiconductor device includes: a bit line extending in a first direction; the laminated structure comprises a first dielectric layer and a gate layer which are mutually stacked in a second direction, and the second direction intersects with the first direction; the plurality of semiconductor columns penetrate through the laminated structure along the second direction and are respectively connected with the bit lines, and the gate layer surrounds the semiconductor columns; and the selection gate cutting line penetrates through at least one gate layer, and in the first direction, the selection gate cutting line is located between at least part of two adjacent semiconductor columns.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a storage system, and a method for manufacturing a semiconductor device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device, which consists of many repeated memory cells. However, due to process conditions, semiconductor devices usually have problems such as weak gate control performance. Summary of the Invention

[0003] The present application provides a semiconductor device, a storage system, and a method for manufacturing a semiconductor device that can at least partially solve the above problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: bit lines extending in a first direction; a stacked structure including a first dielectric layer and a gate layer stacked on each other in a second direction, the second direction intersecting the first direction; a plurality of semiconductor pillars penetrating the stacked structure in the second direction and respectively connected to the bit lines, the gate layer surrounding the semiconductor pillars; and a select gate cut line penetrating at least one layer of the gate layer, in the first direction, the select gate cut line being located between at least some adjacent two semiconductor pillars.

[0005] In some embodiments, the gate layer penetrated by the select gate cut line includes a first part and a second part, the first part and the second part being respectively located on two sides of the select gate cut line in the first direction.

[0006] In some embodiments, the select gate cut line includes a top select gate cut line, the top select gate cut line being located on a side of the stacked structure away from the bit lines and penetrating at least one layer of the gate layer farthest from the bit lines.

[0007] In some embodiments, the bit lines include a plurality of bit line contact structures spaced apart in the first direction, the semiconductor pillars being connected to the bit line contact structures; in the first direction, the size of the bit line contact structure is larger than the size of the semiconductor pillar.

[0008] In some embodiments, the number of bit lines is multiple, and the multiple bit lines are spaced apart in a third direction, the third direction intersecting the first direction and the second direction.

[0009] In some embodiments, the semiconductor device further includes: an isolation layer located between adjacent two bit line contact structures of each bit line and between adjacent two bit lines.

[0010] In some embodiments, the semiconductor device further includes: a gate line gap structure that penetrates the stacked structure in the second direction, and the gate line gap structure extends in the third direction to divide the stacked structure into at least two partitions in the first direction, where the third direction intersects the first direction and the second direction.

[0011] In some embodiments, the top select gate tangent line extends in the third direction, and in the first direction, a top select gate tangent line is disposed between every two adjacent semiconductor pillars within the partition.

[0012] In some embodiments, the semiconductor device further includes: a gate line gap structure that penetrates the stacked structure in the second direction, and the gate line gap structure extends in the first direction to divide the stacked structure into at least two partitions in the third direction.

[0013] In some embodiments, the top select gate tangent line extends in the third direction, and in the first direction, a top select gate tangent line is disposed between every two adjacent semiconductor pillars within the partition.

[0014] In some embodiments, the size of the top select gate tangent line in the first direction is smaller than the size of the gate line gap structure in the first direction, or smaller than the size of the gate line gap structure in the third direction.

[0015] In some embodiments, a gate dielectric layer is disposed between the gate layer and the semiconductor pillar, and the gate dielectric layer includes an extension portion that extends in the first direction and is located between the gate layer and the first dielectric layer; wherein, the extension portion of the gate dielectric layer corresponding to the gate layer that is closest to the bit line and farthest from the bit line and not penetrated by the top select gate tangent line is connected to the side of the top select gate tangent line close to the bit line.

[0016] In some embodiments, the semiconductor device further includes: a connection layer located on the side of the semiconductor pillar away from the bit line, and in the first direction or the third direction, the size of the connection layer is greater than or equal to the size of the semiconductor pillar, where the third direction intersects the first direction and the second direction.

[0017] In some embodiments, the semiconductor device further includes: a capacitor structure located on the side of the connection layer away from the semiconductor pillar.

[0018] In a second aspect, some embodiments of the present application provide a storage system. The storage system includes: a semiconductor device as described in any embodiment of the first aspect; and a controller coupled to the semiconductor device.

[0019] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes: forming bit lines that extend along a first direction; forming an initial stacked structure on one side of the bit lines, the initial stacked structure including a first dielectric layer and a second dielectric layer stacked with each other in a second direction, the second direction intersecting the first direction; forming a plurality of semiconductor pillars, the plurality of semiconductor pillars penetrating the initial stacked structure along the second direction and respectively connected to the bit lines; removing the second dielectric layer to form voids in the initial stacked structure, filling the voids and forming a gate layer, the gate layer surrounding the semiconductor pillars; and forming a selection gate cut line between at least some adjacent two semiconductor pillars in the first direction, the selection gate cut line penetrating at least one layer of the gate layer.

[0020] In some embodiments, forming the bit lines includes: forming a plurality of bit lines spaced apart in a third direction, the third direction intersecting the first direction and the second direction.

[0021] In some embodiments, the bit lines include a plurality of bit line contact structures spaced apart in the first direction. Forming the plurality of semiconductor pillars includes: forming a plurality of first holes in the initial stacked structure, the first holes penetrating the initial stacked structure along the second direction and exposing the bit line contact structures, the plurality of first holes being spaced apart in both the first direction and the third direction; and forming semiconductor pillars in the first holes, the semiconductor pillars being connected to the bit line contact structures.

[0022] In some embodiments, forming the semiconductor pillars in the first holes includes: performing epitaxial growth using the bit line contact structures and forming semiconductor pillars in the first holes, the materials of the bit line contact structures and the semiconductor pillars being single-crystalline silicon.

[0023] In some embodiments, an isolation layer is provided between adjacent two bit line contact structures of each bit line or between adjacent two bit lines. Removing the second dielectric layer to form voids in the initial stacked structure, filling the voids and forming the gate layer includes: forming a gate line gap that penetrates the initial stacked structure along the second direction and exposes the isolation layer, the gate line gap extending along the third direction to divide the initial stacked structure into at least two partitions in the first direction, or the gate line gap extending along the first direction to divide the initial stacked structure into at least two partitions in the third direction; removing the second dielectric layer through the gate line gap to form voids; and filling the voids and forming the gate layer, the gate layers corresponding to adjacent two semiconductor pillars in the partition being connected in the third direction.

[0024] In some embodiments, the gate layer extends from the voids to the sidewalls and bottom surface of the gate line gap. The method for manufacturing the semiconductor device further includes: removing the gate layer located on the sidewalls and bottom surface of the gate line gap.

[0025] In some embodiments, the selection gate cut line includes a top selection gate cut line. Forming a selection gate cut line between at least some adjacent pairs of semiconductor pillars includes: in a first direction, forming a top selection gate opening extending in a third direction between each adjacent pair of semiconductor pillars within a partition, the top selection gate opening penetrating at least the layer of gate dielectric farthest from the bit line from a side of the initial stack structure away from the bit line; and filling the top selection gate opening to form the top selection gate cut line.

[0026] According to one or more embodiments of the present application, the semiconductor device, storage system, and method of manufacturing a semiconductor device provided by the present application have a stack structure including a first dielectric layer and a gate dielectric layer stacked on each other in a second direction. A plurality of semiconductor pillars penetrate the stack structure and are respectively connected to bit lines, and the gate dielectric layer surrounds the semiconductor pillars, which is beneficial to enhancing the gate control performance of the semiconductor device. In addition, the selection gate cut line is located between at least some adjacent pairs of semiconductor pillars in the first direction, which is beneficial to achieving partition control of different semiconductor pillars. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects, and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments with reference to the following drawings. Among them:

[0028] Figure 1A is a top view schematic diagram of a semiconductor device according to an embodiment of the present application;

[0029] Figure 1B is Figure 1A an enlarged schematic diagram of region I in

[0030] Figure 1C is along Figure 1B a cross-sectional schematic diagram taken along line A-A' shown in

[0031] Figure 1D is Figure 1C an enlarged schematic diagram of region II in

[0032] Figure 1E is along Figure 1C a cross-sectional schematic diagram taken along line D-D' shown in

[0033] Figure 1F is along Figure 1B a cross-sectional schematic diagram taken along line B-B' shown in

[0034] Figure 1G is along Figure 1B a cross-sectional schematic diagram taken along line C-C' shown in

[0035] Figure 1H is a semiconductor device with a capacitive structure according to an embodiment of the present application along Figure 1BSchematic cross-sectional view taken along line A-A' as shown;

[0036] Figure 2A Top view of region I of a semiconductor device according to another embodiment of the present application;

[0037] Figure 2B is along Figure 2A Schematic cross-sectional view taken along line A-A' as shown;

[0038] Figure 2C is Figure 2B Enlarged view of region III in;

[0039] Figure 3 System block diagram of a system with a storage system according to an embodiment of the present application;

[0040] Figure 4 Flow block diagram of a method for manufacturing a semiconductor device according to an embodiment of the present application; and

[0041] Figures 5A to 13 Schematic structural view of a semiconductor device during manufacturing according to an embodiment of the present application. Detailed Embodiments

[0042] To better understand the present application, more detailed descriptions of various aspects of the present application will be made with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] It should be noted that in this specification, the expressions such as first, second, etc. are only used to distinguish one feature from another feature and do not represent any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of the present application, the first direction discussed in the present application may also be referred to as the second direction, and vice versa.

[0044] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0045] It should also be understood that expressions such as "including", "comprising", "having", "containing" and / or "comprising of" are open-ended rather than closed-ended expressions in this specification, which means that the stated features, elements and / or components exist, but do not exclude the existence of one or more other features, elements, components and / or their combinations. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features, rather than just an individual element in the list. In addition, when describing embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0046] Unless otherwise defined, all terms used herein (including engineering terms and technical terms) have the same meaning as commonly understood by those of ordinary skill in the art to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in a common dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense.

[0047] It should be noted that, without conflict, the embodiments in this application and the features in the embodiments may be combined with each other. In addition, unless clearly defined or in contradiction with the context, the specific steps included in the methods described in this application do not have to be limited to the recited order, but can be executed in any order or executed in parallel.

[0048] In addition, when using "connected" or "coupled" in this application, it may mean direct contact or indirect contact between the corresponding components, unless there are clear other limitations or can be deduced from the context.

[0049] The present application will be described in detail below with reference to the drawings and in conjunction with embodiments.

[0050] An embodiment of the present application provides a semiconductor device. Figure 1A is a top view schematic diagram of a semiconductor device according to an embodiment of the present application. Figure 1B is Figure 1A an enlarged schematic diagram of region I in Figure 1C is along Figure 1B a cross-sectional schematic diagram taken along line A-A' shown in Figure 1D is Figure 1C an enlarged schematic diagram of region II in Figure 1E is along Figure 1C a cross-sectional schematic diagram taken along line D-D' shown in Figure 1F is along Figure 1B a cross-sectional schematic diagram taken along line B-B' shown in Figure 1G is along Figure 1BA schematic cross-sectional view taken along line CC' is shown. Figure 1H A semiconductor device having a capacitor structure according to an embodiment of the present application is provided along Figure 1B The cross-sectional schematic diagram taken along the line AA' is shown. The semiconductor device may be a memory or a part of a memory. For example, the memory may be a DRAM memory.

[0051] It should be noted that, hereinafter, the first direction is referred to as the D1 direction, the second direction is referred to as the D2 direction, and the third direction is referred to as the D3 direction. The D1 direction, the D2 direction, and the D3 direction in each figure show the spatial relationship of the components in the semiconductor device. For example, the D2 direction is the stacking direction of the laminated structure, and the D1 direction and the D3 direction are two directions that intersect (e.g., are perpendicular) to each other on a plane that intersects (e.g., is perpendicular) to the stacking direction. In addition, the D1 direction, the D2 direction, and the D3 direction in each figure include not only the direction indicated by the arrow, but also the direction away from the arrow. In other words, the arrows in the D1 direction, the D2 direction, and the D3 direction do not have a restrictive meaning. The same concept will be used throughout this application to describe the spatial relationship of the components in the semiconductor device.

[0052] like Figure 1A , Figure 1B and Figure 1C As shown, the semiconductor device 100 includes a bit line 110, a stacked structure 120, a plurality of semiconductor pillars 130, and a selection gate cut line 151. The bit line 110 may extend along the D1 direction. The stacked structure 120 may include a first dielectric layer 121 and a gate layer 122 stacked on each other in the D2 direction. The plurality of semiconductor pillars 130 may penetrate the stacked structure 120 along the D2 direction and be connected to (e.g., contacted with) the bit line 110 respectively, wherein the gate layer 122 may surround the semiconductor pillars 130. The selection gate cut line 151 may penetrate at least one layer of the gate layer 122, and in the D1 direction, the selection gate cut line 151 may be located between at least part of two adjacent semiconductor pillars 130. The portion of the gate layer penetrated by the selection gate cut line 151 is called a selection gate.

[0053] The material of the first dielectric layer 121 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or any other suitable insulating material. The material of the gate layer 122 may include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Gu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polycrystalline silicon (poly-Si), or any other suitable conductive material. For example, the material of the first dielectric layer 121 may be silicon oxide (SiO2 ), the material of the gate layer 122 can be tungsten (W). The materials of the bit line 110 and the semiconductor pillar 130 can include but are not limited to single crystal silicon. The material of the select gate cut line 151 can include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials. For example, the material of the select gate cut line 151 can be silicon nitride (Si 3 N 4 ).

[0054] For the semiconductor device provided according to the above embodiments of the present application, the semiconductor pillar penetrates the stacked structure and contacts the bit line, and the gate layer in the stacked structure surrounds the periphery of the semiconductor pillar, that is, the gate layer is a Gate-All-Around (GAA). The GAA structure can enable the semiconductor pillar to be wrapped by the gate layer in its circumferential direction, greatly reducing problems such as leakage current, capacitance effect, and short channel effect, reducing the occupied area of the gate layer in the stacking direction, and being beneficial to enhancing the gate control performance of the semiconductor device. In addition, the select gate cut line is located between at least some adjacent two semiconductor pillars in the D1 direction, and the select gate is separated into multiple parts, and different semiconductor pillars can be controlled by controlling different parts of the select gate.

[0055] To further elaborate on the spatial relationship of the components in the semiconductor device 100, the semiconductor device 100 will be illustrated by way of example below in conjunction with Figures 1A to 1H .

[0056] In some embodiments, as shown in Figure 1B , Figure 1C and Figure 1F , the number of the bit lines 110 can be multiple, and the multiple bit lines 110 are arranged at intervals in the D3 direction. For each bit line 110, each bit line 110 includes a bit line body 112 and a plurality of bit line contact structures 111. The bit line body 112 can extend along the D1 direction, and the plurality of bit line contact structures 111 can be arranged at intervals along the D1 direction on the bit line body 112. An isolation layer 113 is provided between each adjacent two bit lines 110 and between each adjacent two bit line contact structures 111. The top surface of the isolation layer 113 is substantially flush with the top surface of the bit line contact structure 111 (for example, the error is less than or equal to ±10%). The material of the isolation layer 113 can include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y) or one or more of any other suitable insulating materials. For example, the material of the isolation layer 113 can be silicon nitride (Si 3 N 4 ). By providing the isolation layer 113 between two adjacent bit line contact structures 111 and between two adjacent bit lines 110, electrical isolation between adjacent bit line contact structures 111 and between adjacent bit lines 110 can be achieved. The material of the bit line body 112 and the material of the bit line contact structure 111 can be the same.

[0057] In some embodiments, as Figure 1B 、 Figure 1C and Figure 1F show, a plurality of semiconductor pillars 130 are arranged in an array. The D1 direction is defined as the row direction, and the D3 direction is defined as the column direction. The semiconductor device 100 may include, for example, m×n semiconductor pillars 130, where m is the number of rows of the semiconductor pillars 130 and n is the number of columns of the semiconductor pillars 130. The plurality of semiconductor pillars 130 are spaced apart in both the D1 direction and the D3 direction. For each semiconductor pillar 130, the semiconductor pillar 130 can be connected (e.g., in contact) to the bit line contact structure 111. In the D1 direction and / or the D3 direction, the size of the bit line contact structure 111 can be larger than the size of the semiconductor pillar 130 so that the end of the semiconductor pillar 130 close to the bit line 110 is in full contact with the bit line contact structure 111. The number of semiconductor pillars 130 and the number of bit line contact structures 111 can be the same. The shape of the semiconductor pillar 130 can be generally cylindrical.

[0058] It should be noted that the number of semiconductor pillars 130 and bit line contact structures 111 is not specifically limited in this application. For example, the number of bit line contact structures 111 corresponds to the number of semiconductor pillars 130, and the number of semiconductor pillars 130 can be designed according to actual storage requirements. Generally speaking, the more the number of semiconductor pillars 130, the more the number of subsequent capacitor structures connected thereto, the higher the integration degree of the semiconductor device 100, and the higher the storage density.

[0059] In some embodiments, as Figure 1C 、 Figure 1E and Figure 1F show, the stacked structure 120 can include at least one stacked pair, and each stacked pair is a structure formed by a first dielectric layer 121 and a gate layer 122. For each stacked pair, the gate layer 122 is farther from the bit line 110 than the first dielectric layer 121. In the D2 direction, the plurality of gate layers 122 corresponding to the same semiconductor pillar 130 are discontinuous (e.g., not continuously extended) through the first dielectric layer 121.

[0060] The extension dimension of the gate layer 122 in the D1 direction is substantially the same as that of the first dielectric layer 121 in the D1 direction. The extension dimension of the gate layer 122 in the D3 direction can be smaller than that of the first dielectric layer 121 in the D3 direction. Moreover, the surface of the uppermost stack pair (e.g., the stack pair farthest from the bit line 110) away from the bit line 110 is covered with the first dielectric layer 121, and in the D1 direction and / or the D3 direction, the extension dimension of the first dielectric layer 121 can be substantially the same as that of the first dielectric layer 121 in the stack pair.

[0061] It should be noted that the present application does not specifically limit the dimensions and quantities of the first dielectric layer 121 and the gate layer 122. For example, each first dielectric layer 121 can have the same or different dimensions, and each gate layer 122 can also have the same or different dimensions.

[0062] In some embodiments, the gate layer 122 can include a select gate and a non-select gate 1222. The select gate can include a top select gate 1221 and / or a bottom select gate. The top select gate 1221 can include at least one gate layer farthest from the bit line 110, and the bottom select gate can include at least one gate layer closest to the bit line 110. For example, the select gate is the top select gate 1221 and can include one or two gate layers farthest from the bit line 110. Hereinafter, the case where the select gate is the top select gate 1221 will be used as an example for illustration.

[0063] Reference Figure 1D and Figure 1E , in the D1 direction, the top select gates 1221 corresponding to two adjacent semiconductor pillars 130 are discontinuous (e.g., not continuously extended), that is, the top select gates 1221 corresponding to two adjacent semiconductor pillars 130 in each row are not continuously extended. In the D3 direction, the top select gates 1221 corresponding to two adjacent semiconductor pillars 130 are connected (e.g., in contact), that is, the top select gates 1221 corresponding to two adjacent semiconductor pillars 130 in each column are continuously extended.

[0064] In the D1 direction, at least part of the non-select gates 1222 corresponding to two adjacent semiconductor pillars 130 are discontinuous (e.g., not continuously extended), and at least part of the non-select gates 1222 corresponding to two adjacent semiconductor pillars 130 are connected (e.g., in contact). In the D3 direction, the non-select gates 1222 corresponding to two adjacent semiconductor pillars 130 are connected (e.g., in contact), that is, the non-select gates 1222 corresponding to two adjacent semiconductor pillars 130 in each column are continuously extended. Multiple non-select gates 1222 corresponding to the same semiconductor pillar 130 can be respectively led out through multiple lead-out structures, and the non-select gates 1222 and the lead-out structures are in one-to-one correspondence.

[0065] It should be noted that the present application does not specifically limit the number of select gates and non-select gates 1222. For example, the number of select gates can be determined according to actual process conditions. The present application does not specifically limit the type of select gates. For example, the select gates can be at least one of a top select gate 1221 and a bottom select gate. The structure of the bottom select gate is similar to that of the top select gate 1221, and will not be described in detail herein.

[0066] In some embodiments, as Figure 1C , Figure 1D and Figure 1F shown, for each semiconductor pillar 130, a gate dielectric layer 123 can be disposed between the semiconductor pillar 130 and the gate layer 122. The material of the gate dielectric layer 123 can include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials. For example, the material of the gate dielectric layer 123 can be silicon nitride (Si 3 N 4 ).

[0067] The gate dielectric layer 123 can include a surrounding portion 1231 and an extending portion 1232. The surrounding portion 1231 can surround the periphery of the semiconductor pillar 130 and be located between the gate layer 122 and the semiconductor pillar 130, and the surrounding portion 1231 extends along the D2 direction. The extending portion 1232 can extend outward (e.g., continuously extend) from the two end portions of the surrounding portion 1231 in the D2 direction within the plane defined by the D1 direction and the D3 direction, and the extending portion 1232 is located between the gate layer 122 and the adjacent first dielectric layer 121. In the D1 direction, the extending portion 1232 corresponding to the top select gate 1221 is discontinuous (e.g., does not continuously extend), and at least part of the extending portion 1232 corresponding to the non-select gate 1222 is discontinuous (e.g., does not continuously extend). In the D3 direction, the extending portion 1232 corresponding to the top select gate 1221 or the non-select gate 1222 is connected (e.g., in contact).

[0068] Each stack pair includes the above-mentioned gate dielectric layer 123. For each stack pair, the extending dimension of the surrounding portion 1231 in the D2 direction can be substantially the same as the extending dimension of the gate layer 122 in the D2 direction, and, in the D1 direction and / or the D3 direction, the extending dimension of the extending portion 1232 can be substantially the same as the sum of the extending dimensions of the gate layer 122 and the surrounding portion 1231.

[0069] It should be noted that the present application does not specifically limit the size and number of the gate dielectric layer 123. For example, the number of the gate dielectric layers 123 corresponds to the number of the gate layers 122 in the above, and each gate dielectric layer 123 may have the same or different sizes.

[0070] In some embodiments, as Figure 1B , Figure 1C and Figure 1E shown, the semiconductor device 100 may further include a gate line slot structure 140. The gate line slot structure 140 may penetrate the stacked structure 120 along the D2 direction and be connected to the isolation layer 113. The gate line slot structure 140 may extend (e.g., continuously extend) along the D3 direction to divide the stacked structure 120 into at least two partitions in the D1 direction. In the D1 direction, a gate line slot structure 140 is disposed between at least some adjacent two semiconductor pillars 130, and the adjacent two gate line slot structures 140 may define a partition and provide electrical isolation between the adjacent two partitions. In the D1 direction, the size of the portion of the gate line slot structure 140 for connecting to the isolation layer 113 may be smaller than the size of the isolation layer 113. The material of the gate line slot structure 140 may include but is not limited to one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), tetraethyl orthosilicate (TEOS) or any other suitable insulating material. For example, the material of the gate line slot structure 140 may be silicon oxide (SiO 2 ).

[0071] In some embodiments, the selected gate tangent line 151 may include a top selected gate tangent line 150 and / or a bottom selected gate tangent line. The top selected gate tangent line 150 is located on the side of the stacked structure 120 away from the bit line 110 and penetrates at least one gate layer furthest from the bit line 110. The bottom selected gate tangent line is located on the side of the stacked structure 120 close to the bit line 110 and penetrates at least one gate layer closest to the bit line 110. The gate layers penetrated by the selected gate tangent line 151 include a first portion 12211 and a second portion 12212, and the first portion 12211 and the second portion 12212 are respectively located on both sides of the selected gate tangent line 151 in the D1 direction. Hereinafter, an example is given with the selected gate tangent line 151 being the top selected gate tangent line 150.

[0072] Refer to Figure 1B , Figure 1C and Figure 1E, the top selection gate cutting line 150 can penetrate the top selection gate 1221 along the D2 direction, and the penetrated top selection gate 1221 is cut into two independent parts. For example, the top selection gate 1221 penetrated by the top selection gate cutting line 150 includes a first part 12211 and a second part 12212, and the first part 12211 and the second part 12212 are respectively located on both sides of the top selection gate cutting line 150 in the D1 direction. The top selection gate cutting line 150 can extend along the D3 direction (for example, continuously extend). In the D1 direction, a top selection gate cutting line 150 is provided between every two adjacent semiconductor columns 130 in the same partition.

[0073] A top selection gate cutting line 150 or a gate line gap structure 140 is provided between every two adjacent semiconductor columns 130 in the D1 direction. In other words, two adjacent top selection gate cutting lines 150 can define an area, or a gate line gap structure 140 and a top selection gate cutting line 150 can define an area. The size of the top selection gate cutting line 150 in the D1 direction can be smaller than the size of the gate line gap structure 140 in the D1 direction. Compared with the gate line gap structure 140, the top selection gate cutting line 150 has a smaller size, thereby reducing the occupied space of the isolation structure (for example, the top selection gate cutting line 150 and the gate line gap structure 140) and increasing the occupied space of the semiconductor column 130, thus improving the storage density of the semiconductor device.

[0074] It should be noted that the structure of the bottom selection gate cutting line is similar to that of the top selection gate cutting line 150, and will not be elaborated one by one in this application.

[0075] In some embodiments, as Figure 1C and Figure 1E shown, in the D1 direction, the top selection gates 1221 corresponding to every two adjacent semiconductor columns 130 are interrupted by the top selection gate cutting line 150 or the gate line gap structure 140. For the semiconductor column 130 closest to the gate line gap structure 140, one side of the top selection gate 1221 in the D1 direction is connected (for example, in contact) to the top selection gate cutting line 150, and the other side is connected (for example, in contact) to the gate line gap structure 140. For the semiconductor column 130 not close to the gate line gap structure 140, the two sides of the top selection gate 1221 in the D1 direction are respectively connected (for example, in contact) to two adjacent top selection gate cutting lines 150.

[0076] Continue to refer to Figure 1D, for each semiconductor pillar 130, the surrounding portion 1231 corresponding to the top selection gate 1221 surrounds the periphery of the semiconductor pillar 130 and extends outward from the outer wall surface of the semiconductor pillar 130 in the plane defined by the D1 direction and the D3 direction. The extension portions 1232 respectively take the two end portions in the D2 direction of the surrounding portion 1231 as centers and extend outward from the two end portions in the D2 direction of the surrounding portion 1231 in the plane defined by the D1 direction and the D3 direction (for example, continuously extend). In the D1 direction, the two side portions of the extension portion 1232 far from the surrounding portion 1231 are respectively in contact with the top selection gate tangent 150 or the gate line slot structure 140. In the D3 direction, the extension portions 1232 corresponding to two adjacent semiconductor pillars 130 are in contact.

[0077] Continue to refer to Figure 1E , the top selection gate 1221 surrounds the periphery of the surrounding portion 1231 and extends outward from the outer wall surface of the surrounding portion 1231 in the plane defined by the D1 direction and the D3 direction. The top selection gate 1221 is located between the two extension portions 1232 extending from the two end portions in the D2 direction of the surrounding portion 1231. In the D1 direction, the two side portions of the top selection gate 1221 far from the surrounding portion 1231 are respectively in contact with the top selection gate tangent 150 or the gate line slot structure 140. In the D3 direction, the top selection gates 1221 corresponding to two adjacent semiconductor pillars 130 are in contact. The gate line slot structure 140 can divide the stacked structure 120 into different partitions in the D1 direction, and the top selection gates 1221 corresponding to two adjacent semiconductor pillars 130 in the D1 direction within the same partition are separated into multiple parts by the top selection gate tangent 150, and the individual control of each semiconductor pillar 130 is achieved by controlling the top selection gates 1221 of different parts.

[0078] In some embodiments, as Figure 1C and Figure 1D shown, for the semiconductor pillar 130 closest to the gate line slot structure 140, the non-selection gate 1222 is connected (for example, in contact) with the gate line slot structure 140 at the side portion close to the gate line slot structure 140 in the D1 direction, and the non-selection gate 1222 is connected (for example, in contact) with the non-selection gate 1222 of the adjacent semiconductor pillar 130 at the side portion far from the gate line slot structure 140 in the D1 direction. For the semiconductor pillar 130 not close to the gate line slot structure 140, the non-selection gate 1222 is connected (for example, in contact) with the non-selection gate 1222 of the adjacent semiconductor pillar 130 at both side portions in the D1 direction.

[0079] In some embodiments, as Figure 1D and Figure 1GAs shown, the side of the top select gate cut line 150 closer to the bit line 110 is connected (e.g., contacted) to the extension 1232 of the gate dielectric layer 123 corresponding to the gate layer 122 that is farthest from the bit line 110 and not penetrated by the top select gate cut line 150. For example, the side of the top select gate cut line 150 closer to the bit line 110 is connected (e.g., contacted) to the extension 1232 corresponding to the non-select gate 1222. In other examples, the side of the top select gate cut line 150 closer to the bit line 110 may be connected (e.g., contacted) to the first dielectric layer 121.

[0080] In some embodiments, as Figure 1D shown, the gate dielectric layer 123 may further include a portion extending from the second portion 1232 to the sidewall and bottom of the gate line gap structure 140. For example, the side of the gate line gap structure 140 closer to the bit line 110 may be in contact with the isolation layer 113 through the gate dielectric layer 123.

[0081] In some embodiments, as Figure 1B 、 Figure 1C 、 Figure 1F and Figure 1H shown, the semiconductor device 100 may further include a connection layer 160 and a capacitor structure 180. The connection layer 160 may be located on the side of the semiconductor pillar 130 away from the bit line 110 and connected (e.g., contacted) to the semiconductor pillar 130. The capacitor structure 180 may be located on the side of the connection layer 160 away from the semiconductor pillar 130 and connected (e.g., contacted) to the connection layer 160. The number of the connection layer 160 and the capacitor structure 180 may be the same as the number of the semiconductor pillars 130, that is, each semiconductor pillar 130 corresponds to one connection layer 160 and one capacitor structure 180. In the D1 direction and / or the D3 direction, the size of the connection layer 160 may be greater than or equal to the size of the semiconductor pillar 130. The material of the connection layer 160 may include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), or any other suitable conductive material. For example, the material of the connection layer 160 may be tungsten (W).

[0082] The surface of the connection layer 160 away from the bit line 110 may be substantially flush with the surface of the stacked structure 120 away from the bit line 110 (e.g., the error is less than or equal to ±10%). Or, the surface of the semiconductor pillar 130 away from the bit line 110 may be substantially flush with the surface of the stacked structure 120 away from the bit line 110 (e.g., the error is less than or equal to ±10%), and the surface of the connection layer 160 away from the bit line 110 is not aligned with the surface of the stacked structure 120 away from the bit line 110.

[0083] It should be noted that the present application does not specifically limit the dimensions and quantities of the connection layer 160 and the capacitor structure 180. For example, each connection layer 160 may have the same or different dimensions. The quantity of the connection layer 150 corresponds to the quantity of the capacitor structure 180, and the quantity of the capacitor structure 180 can be designed according to actual storage requirements. Generally speaking, the more the quantity of the capacitor structure 180, the higher the integration degree and the storage density of the semiconductor device 100.

[0084] In some embodiments, the semiconductor device 100 may include a plurality of memory cells, and each memory cell includes a transistor structure and a capacitor structure, and the capacitor structure is used to store data written into the memory cell. For each transistor structure, the transistor structure includes a semiconductor pillar 130 and a gate structure. The semiconductor pillar 130 may include a channel structure, a source electrode, and a drain electrode, and the source electrode and the drain electrode are respectively located at two ends of the channel structure in the D2 direction. For example, the end of the semiconductor pillar 130 far from the bit line 110 is doped to form the source electrode, and the end of the semiconductor pillar 130 close to the bit line 110 is doped to form the drain electrode. The source electrode of the semiconductor pillar 130 can be connected to the capacitor structure, and the drain electrode of the semiconductor pillar 130 can be connected to the bit line 110. The gate structure surrounds the channel structure of the semiconductor pillar 130 and includes a gate layer 122 and a gate dielectric layer 123. The plurality of gate layers 122 corresponding to the same transistor structure are discontinuous and are respectively led out through different lead-out structures. Thus, the gate layer 122 can form a word line.

[0085] Figure 2A is a top view schematic diagram of region I of a semiconductor device according to another embodiment of the present application. Figure 2B is along Figure 2A The cross-sectional schematic diagram taken along the line A-A' shown. Figure 2C is Figure 2B The enlarged schematic diagram of region III in. For the purpose of concise description, the same content as the previous embodiment will not be repeated in this embodiment.

[0086] In some embodiments, as Figures 2A to 2C shown, the gate line gap structure 240 can penetrate the stacked structure 220 along the D2 direction and be connected to the isolation layer 213. The gate line gap structure 240 can extend along the D1 direction (for example, continuously extend) to divide the stacked structure 220 into at least two partitions in the D3 direction. In the D3 direction, a gate line gap structure 240 is provided between at least part of two adjacent semiconductor pillars 230, and two adjacent gate line gap structures 240 can define a partition and provide electrical isolation between two adjacent partitions. In the D1 direction, the dimension of the part of the gate line gap structure 240 for connecting to the isolation layer 213 can be smaller than the dimension of the isolation layer 213. The material of the gate line gap structure 240 can be silicon oxide (SiO2 )。

[0087] In some embodiments, such as Figures 2A to 2C shown, the top selection gate tangent line 250 can penetrate through the top selection gate 2221 along the D2 direction, and the penetrated top selection gate 2221 is cut into two independent parts. The top selection gate tangent line 250 can extend along the D3 direction (e.g., continuously extend). In the D1 direction, a top selection gate tangent line 250 is provided between every two adjacent semiconductor columns 230 within the same partition.

[0088] A top selection gate tangent line 250 is provided between every two adjacent semiconductor columns 230 in the D1 direction. The dimension of the top selection gate tangent line 250 in the D1 direction can be smaller than the dimension of the gate line gap structure 240 in the D3 direction. Compared with the gate line gap structure 240, the top selection gate tangent line 250 has a smaller size, thereby being able to reduce the occupied space of the isolation structure (e.g., the top selection gate tangent line 250) and increase the occupied space of the semiconductor column 230, thus improving the storage density of the semiconductor device.

[0089] In some embodiments, such as Figures 2A to 2C shown, the top selection gates 2221 corresponding to two adjacent semiconductor columns 230 in the D1 direction are discontinuous (e.g., do not continuously extend), that is, the top selection gates 2221 corresponding to two adjacent semiconductor columns 230 in each row do not continuously extend. In the D3 direction, the top selection gates 2221 corresponding to two adjacent semiconductor columns 230 within the same partition are connected (e.g., in contact), that is, the top selection gates 2221 corresponding to two adjacent semiconductor columns 230 in each column within the same partition continuously extend.

[0090] For each semiconductor column 230, the two side portions of the top selection gate 2221 in the D1 direction are respectively connected (e.g., in contact) to two adjacent top selection gate tangent lines 250. For the semiconductor column 230 closest to the gate line gap structure 240, the side portion of the top selection gate 2221 in the D3 direction close to the gate line gap structure 240 is connected (e.g., in contact) to the gate line gap structure 240, and the side portion away from the gate line gap structure 240 is connected (e.g., in contact) to the top selection gate 2221 of the adjacent semiconductor column 230. For the semiconductor column 230 not close to the gate line gap structure 240, the two side portions of the top selection gate 2221 in the D3 direction are respectively connected (e.g., in contact) to the top selection gates 2221 of the adjacent semiconductor columns 230.

[0091] In some embodiments, such as Figures 2A to 2CAs shown, the non-selective gate electrodes 2222 corresponding to two adjacent semiconductor pillars 230 in the D1 direction are connected (e.g., in contact), that is, the non-selective gate electrodes 2222 corresponding to two adjacent semiconductor pillars 230 in each row extend continuously. In the D3 direction, the non-selective gate electrodes 2222 corresponding to two adjacent semiconductor pillars 230 within the same partition are connected (e.g., in contact), that is, the non-selective gate electrodes 2222 corresponding to two adjacent semiconductor pillars 230 in each column within the same partition extend continuously. For the semiconductor pillar 230 closest to the gate line gap structure 240, the non-selective gate electrode 2222 is connected (e.g., in contact) with the gate line gap structure 240 at the side close to the gate line gap structure 240 in the D3 direction, and is connected (e.g., in contact) with the non-selective gate electrode 2222 of the adjacent semiconductor pillar 230 at the side away from the gate line gap structure 240.

[0092] An embodiment of the present application also provides a storage system. Figure 3 It is a system block diagram of the system provided by the embodiment of the present application with a storage system.

[0093] As Figure 3 shown, the system 300 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has a storage system 310 located therein). As Figure 3 shown, the system 300 may include a host 320 and a storage system 310. The storage system 310 has one or more three-dimensional memories 311 and a controller 312. The host 320 can be a processor of the electronic device, such as a central processing unit (CPU), or can be a system-on-chip (SoC), such as an application processor (AP). The host 320 can be configured to send or receive data to and from the three-dimensional memory 311.

[0094] The three-dimensional memory 311 can include the semiconductor devices described in any embodiment of the present application. For example, Figures 1A to 1H the semiconductor device 100 shown or Figures 2A to 2CThe semiconductor device 200 shown. According to some embodiments, the controller 312 is coupled to the 3D memory 311 and the host 320, and is configured to control operations of the 3D memory 311 such as read, erase, and program operations. The controller 312 can also manage the data stored in the 3D memory 311 and communicate with the host 320. For example, the controller 312 can communicate with an external device (e.g., the host 320) according to a specific communication protocol.

[0095] Embodiments of the present application also provide a method for manufacturing a semiconductor device. Figure 4 It is a flowchart of the method for manufacturing a semiconductor device provided by the embodiments of the present application. As Figure 4 shown, the method 400 for manufacturing a semiconductor device (hereinafter simply referred to as the manufacturing method 400) includes the following steps.

[0096] S410, forming bit lines that extend in a first direction.

[0097] S420, forming an initial stacked structure on one side of the bit lines, the initial stacked structure including a first dielectric layer and a second dielectric layer stacked with each other in a second direction, the second direction intersecting the first direction.

[0098] S430, forming a plurality of semiconductor pillars that penetrate the initial stacked structure in the second direction and are respectively connected to the bit lines.

[0099] S440, removing the second dielectric layer to form a void in the initial stacked structure, filling the void and forming a gate layer that surrounds the semiconductor pillars.

[0100] S450, forming a select gate cut line between at least some adjacent two semiconductor pillars in the first direction, the select gate cut line penetrating at least one layer of the gate layer.

[0101] According to the method 400 for manufacturing a semiconductor device provided by the embodiments of the present application, the semiconductor pillars penetrate the stacked structure and are in contact with the bit lines, and the gate layer in the stacked structure surrounds the periphery of the semiconductor pillars, that is, the gate layer is a Gate-All-Around (GAA). The GAA structure can enable the semiconductor pillars to be wrapped by the gate layer in their circumferential directions, greatly reducing problems such as leakage current, capacitance effect, and short channel effect, reducing the occupied area of the gate layer in the stacking direction, and being beneficial to enhancing the gate control performance of the semiconductor device. In addition, the select gate cut line is located between at least some adjacent two semiconductor pillars in the D1 direction and separates the select gate into multiple parts, and different semiconductor pillars can be controlled by controlling different parts of the select gate.

[0102] Figures 5A to 13 It is a schematic structural diagram of the semiconductor device provided by the embodiments of the present application during manufacturing. For example,Figures 5A to 13 It can be an intermediate structure formed according to Figure 4 the manufacturing method 400 shown, and is used to form a semiconductor device 100 as Figures 1A to 1H shown. The following further describes in conjunction with Figures 5A to 13 the Figure 4 manufacturing method 400 shown.

[0103] S410, form bit lines that extend in a first direction.

[0104] Specifically, a substrate is provided. The substrate may have a plurality of bit lines 510. The plurality of bit lines 510 are spaced in the D3 direction, and each bit line 510 can extend along the D1 direction. The substrate can be a semiconductor substrate, and the semiconductor substrate can include but is not limited to one of a silicon substrate, a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate. For example, the semiconductor substrate can be a single-crystalline silicon substrate, that is, the material of the bit line 510 can be single-crystalline silicon.

[0105] For each bit line 510, each bit line 510 includes a bit line body 512 and a plurality of bit line contact structures 511. The bit line body 512 can extend along the D1 direction, and the plurality of bit line contact structures 511 can be spaced along the D1 direction on the bit line body 512. An isolation layer 513 is provided between every two adjacent bit lines 510 and between every two adjacent bit line contact structures 511. The top surface of the isolation layer 513 is substantially flush with the top surface of the bit line contact structure 511 (for example, the error is less than or equal to ±10%). The material of the isolation layer 513 can include but is not limited to one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), or any other suitable insulating material. For example, the material of the isolation layer 513 can be silicon nitride (Si 3 N 4 ). By providing the isolation layer 513 between two adjacent bit line contact structures 511 and between two adjacent bit lines 510, electrical isolation between adjacent bit line contact structures 511 and between adjacent bit lines 510 can be achieved. The material of the bit line body 512 and the material of the bit line contact structure 511 can be the same.

[0106] S420, form an initial stack structure on one side of the bit lines. The initial stack structure includes a first dielectric layer and a second dielectric layer that are stacked on top of each other in a second direction, and the second direction intersects the first direction.

[0107] Figure 5A and Figure 5B show a cross-sectional schematic diagram of the intermediate structure 500a after forming the initial stacked structure. Specifically, Figure 5A is (refer to Figure 1CSchematic cross-sectional view of the intermediate structure 500a taken along the D1 direction. Figure 5B is (reference Figure 1F ) Schematic cross-sectional view of the intermediate structure 500a taken along the D3 direction.

[0108] In step S420, as Figure 5A and Figure 5B shown, an initial stacked structure 520 is formed on the surface of the substrate provided with the bit line contact structure 511. The initial stacked structure 520 includes a first dielectric layer 521 and a second dielectric layer 524 stacked relative to each other. For example, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to alternately form the first dielectric layer 521 and the second dielectric layer 524. The material of the first dielectric layer 521 and the material of the second dielectric layer 524 can be different from each other, so that the two have different etching selectivity ratios with respect to the same etching material. The material of the first dielectric layer 521 may include silicon oxide (SiO 2 ), and the material of the second dielectric layer 524 may include silicon nitride (Si 3 N 4 ). The initial stacked structure 520 may include a plurality of initial stacked pairs, and each initial stacked pair is a structure formed by the first dielectric layer 521 and the second dielectric layer 524. The surface of the uppermost initial stacked pair (for example, the initial stacked pair farthest from the bit line 510) away from the bit line 510 is covered with the first dielectric layer 521.

[0109] S430, form a plurality of semiconductor pillars that penetrate the initial stack structure in the second direction and are respectively connected to the bit lines.

[0110] In step S430, a plurality of first holes 571 are formed in the initial stacked structure 520. The first holes 571 penetrate the initial stacked structure 520 along the D2 direction and expose the bit line contact structure 511. The plurality of first holes 571 are spaced apart in both the D1 direction and the D3 direction; and semiconductor pillars 530 are formed in the first holes 571, and the semiconductor pillars 530 are connected to the bit line contact structure 511.

[0111] Figure 6A and Figure 6B show a schematic cross-sectional view of the intermediate structure 500b after forming a plurality of first holes in the initial stacked structure. Specifically, Figure 6A is (reference Figure 1C ) Schematic cross-sectional view of the intermediate structure 500b taken along the D1 direction. Figure 6B is (reference Figure 1FSchematic cross-sectional view of the intermediate structure 500b taken along the D3 direction. Figure 7A and Figure 7B Schematic cross-sectional view of the intermediate structure 500c after forming semiconductor pillars in the first holes. Specifically, Figure 7A is (refer to Figure 1C ) Schematic cross-sectional view of the intermediate structure 500c taken along the D1 direction. Figure 7B is (refer to Figure 1F ) Schematic cross-sectional view of the intermediate structure 500c taken along the D3 direction.

[0112] As Figure 6A and Figure 6B shown, a plurality of first holes 571 penetrating the initial stacked structure 520 along the D2 direction are formed by an etching process (e.g., dry etching and / or wet etching). The plurality of first holes 571 are spaced apart in both the D1 direction and the D3 direction. For each first hole 571, the first hole 571 can expose the bit line contact structure 511, so as to directly form a semiconductor pillar 530 connected thereto through the bit line contact structure 511 subsequently. The shape of the first hole 571 can be generally cylindrical.

[0113] As Figure 7A and Figure 7B shown, epitaxial growth is carried out using the bit line contact structure 511, and semiconductor pillars 530 are formed in the first holes 571. The material of the semiconductor pillars 530 is the same as that of the bit line contact structure 511, both being single crystal silicon. The number of semiconductor pillars 530 can be the same as the number of bit line contact structures 511. Forming the semiconductor pillars 530 by epitaxial growth using the bit line contact structure 511 can enable the semiconductor pillars 530 to have good interface defect states, thereby improving the carrier (e.g., electron or hole) mobility.

[0114] S440, remove the second dielectric layer to form a void in the initial stack structure, fill the void, and form a gate layer that surrounds the semiconductor pillars.

[0115] In step S440, in the D1 direction, a gate line gap 572 is formed between at least some adjacent two semiconductor pillars 530. The gate line gap 572 penetrates the initial stacked structure 520 along the D2 direction and exposes the isolation layer 513. The gate line gap 572 extends in the D3 direction to divide the initial stacked structure 520 into at least two partitions in the D1 direction; through the gate line gap 572, the second dielectric layer 524 is removed to form a void 573; and the void 573 is filled and a gate layer 522 is formed. In the D3 direction, the gate layers 522 corresponding to adjacent two semiconductor pillars 530 in the same partition are connected.

[0116] Figure 8 Schematic cross-sectional view of the intermediate structure 500d after forming the gate line gap. Specifically,Figure 8 is a schematic cross-sectional view of the intermediate structure 500d taken along the D1 direction (for reference Figure 1C ). Figure 9A And Figure 9B shows a schematic cross-sectional view of the intermediate structure 500e after removing the second dielectric layer to form a void. Specifically, Figure 9A is a schematic cross-sectional view of the intermediate structure 500e taken along the D1 direction (for reference Figure 1C ). Figure 9B is a schematic cross-sectional view of the intermediate structure 500e taken along the D3 direction (for reference Figure 1F ). Figure 10A And Figure 10B shows a schematic cross-sectional view of the intermediate structure 500f after filling the void and forming a gate layer. Specifically, Figure 10A is a schematic cross-sectional view of the intermediate structure 500f taken along the D1 direction (for reference Figure 1C ). Figure 10B is a schematic cross-sectional view of the intermediate structure 500f taken along the D3 direction (for reference Figure 1F ).

[0117] As Figure 8 shown, a gate line gap 572 is formed between at least some adjacent semiconductor columns 530 in the D1 direction by using an etching process (e.g., dry etching and / or wet etching). The gate line gap 572 penetrates the initial stacked structure 520 in the D2 direction and exposes the isolation layer 513. The gate line gap 572 may extend in the D3 direction to divide the initial stacked structure 520 into at least two partitions in the D1 direction.

[0118] As Figure 9A and Figure 9B shown, by using the gate line gap 572, the second dielectric layer 524 is removed to form a void 573. For example, a wet etching process is used to etch the second dielectric layer 524 from both sides in the D1 direction through the gate line gap 572, and by controlling the etching time, the second dielectric layer 524 is completely removed, and the area where the second dielectric layer 524 is located forms a void 573.

[0119] As Figure 10A and Figure 10BAs shown, a gate layer 522 is formed in the void 573 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and the gate layer 522 surrounds the periphery of the semiconductor pillar 530. For example, a gate dielectric layer 523 is pre-formed in the void 573 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. At this time, the gate dielectric layer 523 does not fill the entire area of the void 573. Then, the gate layer 522 is formed in the remaining area of the void 573 that is not filled by the gate dielectric layer 523. The material of the gate layer 522 may include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material. The material of the gate dielectric layer 523 may include, but is not limited to, one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), or any other suitable insulating material. Among them, the distribution and positional relationship of the gate layer 522 and the gate dielectric layer 523 have been described in detail above, and will not be elaborated herein. After this step, the initial stacked structure 520 can be converted into the stacked structure described above (reference Figure 1C ).

[0120] In some embodiments, as shown in Figure 10A and Figure 10B , the gate dielectric layer 523 may further extend to the sidewalls and bottom surface of the gate line gap 572. The gate layer 522 may further extend to the sidewalls and bottom surface of the gate line gap 572. The manufacturing method 400 may include: removing the gate layer 522 located on the sidewalls and bottom surface of the gate line gap 572.

[0121] Figure 11 shows a cross-sectional schematic diagram of the intermediate structure 500g after removing the gate layer on the sidewalls and bottom surface of the gate line gap. Specifically, Figure 11 is a cross-sectional schematic diagram of the intermediate structure 500g taken along the D1 direction (reference Figure 1C ). As shown in Figure 11 , the gate layer 522 on the sidewalls and bottom of the gate line gap 572 is removed by an etching process (e.g., dry etching and / or wet etching) so that the gate layers 522 of the same semiconductor pillar 530 are discontinuous in the D2 direction. In the example, the gate layer 522 may further extend to the surface of the initial stacked structure 520 away from the bit line 510, and the gate layer 522 on the surface of the initial stacked structure 520 away from the bit line 510 may be removed by an etching process (e.g., dry etching and / or wet etching).

[0122] In some embodiments, the manufacturing method 400 may include: forming a gate line slot structure 540 within the gate line slot 572, and the gate line slot structure 540 is connected to the isolation layer 513.

[0123] Figure 12 The cross-sectional schematic diagram of the intermediate structure 500h after forming the gate line slot structure is shown. Specifically, Figure 12 is (refer to Figure 1C ) the cross-sectional schematic diagram of the intermediate structure 500h taken along the D1 direction. As Figure 12 shown, a thin film deposition process such as CVD, PVD, ALD or any combination thereof is used to form the gate line slot structure 540 within the gate line slot 572. The gate line slot structure 540 can be, for example, an insulating structure with an air gap. The material of the gate line slot structure 540 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), tetraethyl orthosilicate (TEOS) or any other suitable insulating material(s). For example, the material of the gate line slot structure 540 can be silicon oxide (SiO 2 ). Among them, the distribution and positional relationship of the gate line slot structure 540 have been described in detail above, and will not be elaborated herein.

[0124] In some embodiments, the manufacturing method 400 may further include: forming a connection layer 560 on the side of the semiconductor pillar 530 away from the bit line 510, and the connection layer 560 is connected to (e.g., in contact with) the semiconductor pillar 530; and forming a capacitor structure on the side of the connection layer 560 away from the semiconductor pillar 530, and the capacitor structure is connected to (e.g., in contact with) the connection layer 560. The number of the connection layer 560 and the capacitor structure can be the same as the number of the semiconductor pillars 530, that is, each semiconductor pillar 530 corresponds to one connection layer 560 and one capacitor structure. In the D1 direction and / or the D3 direction, the size of the connection layer 560 can be greater than or equal to the size of the semiconductor pillar 530. The material of the connection layer 560 may include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN) or any other suitable conductive material(s). For example, the material of the connection layer 560 can be tungsten (W). Among them, the distribution and positional relationship of the connection layer 560 and the capacitor structure have been described in detail above, and will not be elaborated herein.

[0125] S450, in the first direction, form a select gate cut between at least some adjacent semiconductor pillars. The select gate cut penetrates at least one gate layer.

[0126] The selection gate cutting line may include a top selection gate cutting line and / or a bottom selection gate cutting line. Hereinafter, the case where the selection gate cutting line is the top selection gate cutting line is taken as an example to illustrate this step. In step S450, in the D1 direction, a top selection gate opening 574 extending in the D3 direction is formed between every two adjacent semiconductor pillars 530 within the same partition. The top selection gate opening 574 penetrates at least one gate layer 522 that is farthest from the bit line 510 from the side of the initial stack structure 520 away from the bit line 510; and the top selection gate opening 574 is filled to form a top selection gate cutting line. After this step, the Figure 1C semiconductor device shown can be formed.

[0127] Figure 13 FIG. shows a cross-sectional schematic diagram of the intermediate structure 500i after forming the top selection gate notch. Specifically, Figure 13 is a cross-sectional schematic diagram of the intermediate structure 500i taken along the D1 direction (reference Figure 1C ).

[0128] As Figure 13 shown, in the D1 direction, a top selection gate opening 574 is formed between every two adjacent semiconductor pillars 530 within the same partition by using an etching process (e.g., dry etching and / or wet etching). The top selection gate opening 574 penetrates the top selection gate 5221 in the D2 direction and exposes the gate dielectric layer 523 of the non-selection gate 5222. The top selection gate opening 574 cuts the penetrated top selection gate 5221 into two independent parts. The top selection gate opening 574 extends in the D3 direction. In the D1 direction, one top selection gate opening 574 is provided between every two adjacent semiconductor pillars 530 within the same partition.

[0129] After forming the top selection gate opening 574, a top selection gate cutting line is formed within the top selection gate opening 574 by using a thin film deposition process such as CVD, PVD, ALD or any combination thereof (reference Figure 1C ). The side of the top selection gate cutting line close to the bit line 510 is connected (e.g., in contact) to the extension 5232 of the non-selection gate 5222. The material of the top selection gate cutting line may include, but is not limited to, one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the top selection gate cutting line may be silicon nitride (Si 3 N 4) Among them, the distribution and positional relationship of the top selection gate cut lines have been described in detail above, and will not be elaborated herein. The formation method of the bottom selection gate cut lines is similar to that of the top selection gate cut lines, and will not be elaborated one by one in this application.

[0130] In another embodiment, in step S440, in the D3 direction, a gate line gap 572 is formed between at least some adjacent semiconductor pillars 530. The gate line gap 572 penetrates the initial stacked structure 520 in the D2 direction and exposes the isolation layer 513. The gate line gap 572 extends in the D1 direction to divide the initial stacked structure 520 into at least two partitions in the D3 direction; through the gate line gap 572, the second dielectric layer 524 is removed to form a void 573; and the void 573 is filled to form a gate layer 522. In the D3 direction, the gate layers 522 corresponding to two adjacent semiconductor pillars 530 in the same partition are connected.

[0131] Specifically, an etching process (e.g., dry etching and / or wet etching) is used to form the gate line gap 572 between at least some adjacent semiconductor pillars 530 in the D3 direction. The gate line gap 572 penetrates the initial stacked structure 520 in the D2 direction and exposes the isolation layer 513. The gate line gap 572 may extend in the D1 direction to divide the initial stacked structure 520 into at least two partitions in the D3 direction. Using a wet etching process, the second dielectric layer 524 is etched from both sides in the D3 direction through the gate line gap 572, and by controlling the etching time, the second dielectric layer 524 is completely removed, and the area where the second dielectric layer 524 is located forms a void 573.

[0132] A thin film deposition process such as CVD, PVD, ALD or any combination thereof is used to form the gate layer 522 in the void 573, and the gate layer 522 surrounds the periphery of the semiconductor pillar 530. For example, a gate dielectric layer 523 is pre-formed in the void 573 using a thin film deposition process such as CVD, PVD, ALD or any combination thereof. At this time, the gate dielectric layer 523 does not fill the entire area of the void 573. Then, the gate layer 522 is formed in the remaining area of the void 573 that is not filled by the gate dielectric layer 523. Among them, the distribution and positional relationship of the gate layer 522 and the gate dielectric layer 523 have been described in detail above, and will not be elaborated herein. After this step, the initial stacked structure 520 can be converted into the stacked structure described above (refer to Figure 2B ).

[0133] As an example, the manufacturing method 400 may include: forming a gate line gap structure 540 within the gate line gap 572, and the gate line gap structure 540 is connected to the isolation layer 513. For example, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof is used to form the gate line gap structure 540 within the gate line gap 572. Among them, the distribution and positional relationship of the gate line gap structure 540 have been described in detail above, and will not be elaborated herein in this application.

[0134] As an example, in the D1 direction, a top select gate opening 574 is formed between every two adjacent semiconductor pillars 530 within the same partition. The top select gate opening 574 penetrates at least one gate layer 522 that is farthest from the bit line 110 on the side of the initial stack structure 520 away from the bit line 110. In other words, the top select gate opening 574 penetrates the top select gate 5221 along the D2 direction and exposes the gate dielectric layer 523 of the non-select gate 5222. The top select gate opening 574 cuts the penetrated top select gate 5221 into two independent parts. The top select gate opening 574 extends along the D3 direction. In the D1 direction, one top select gate opening 574 is provided between every two adjacent semiconductor pillars 530 within the same partition. After forming the top select gate opening 574, the top select gate opening 574 is filled and a top select gate tangent line is formed within the top select gate opening 574. After this step, the semiconductor device shown can be formed. Among them, the distribution and positional relationship of the top select gate tangent line have been described in detail above, and will not be elaborated herein in this application. The formation method of the bottom select gate tangent line is similar to that of the top select gate tangent line, and will not be elaborated one by one in this application. Figure 2B The semiconductor device shown. Among them, the distribution and positional relationship of the top select gate tangent line have been described in detail above, and will not be elaborated herein in this application. The formation method of the bottom select gate tangent line is similar to that of the top select gate tangent line, and will not be elaborated one by one in this application.

[0135] The above description is only for the embodiments of the present application and the description of the applied technical principles. Those skilled in the art should understand that the protection scope involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, comprising: bit lines extending in a first direction; a stacked structure including a first dielectric layer and a gate layer stacked on each other in a second direction, the second direction intersecting the first direction; a plurality of semiconductor pillars penetrating the stacked structure in the second direction and respectively connected to the bit lines, and the gate layer surrounding the semiconductor pillars; and a select gate cut line penetrating at least one layer of the gate layer, and in the first direction, the select gate cut line is located between at least some adjacent two of the semiconductor pillars.

2. The semiconductor device according to claim 1, wherein, the gate layer penetrated by the select gate cut line includes a first part and a second part, and the first part and the second part are respectively located on two sides of the select gate cut line in the first direction.

3. The semiconductor device according to claim 1 or 2, wherein, the select gate cut line includes a top select gate cut line, the top select gate cut line is located on a side of the stacked structure away from the bit lines, and penetrates at least one layer of the gate layer farthest from the bit lines.

4. The semiconductor device according to claim 3, wherein, the bit lines include a plurality of bit line contact structures arranged at intervals in the first direction, and the semiconductor pillars are connected to the bit line contact structures; in the first direction, the size of the bit line contact structures is larger than the size of the semiconductor pillars.

5. The semiconductor device according to claim 4, wherein, the number of the bit lines is multiple, and the multiple bit lines are arranged at intervals in a third direction, the third direction intersecting the first direction and the second direction.

6. The semiconductor device according to claim 5, wherein, further comprising: an isolation layer located between adjacent two of the bit line contact structures of each bit line and between adjacent two of the bit lines.

7. The semiconductor device according to claim 3, wherein, further comprising: a gate line slot structure penetrating the stacked structure in the second direction, the gate line slot structure extending in a third direction to divide the stacked structure into at least two partitions in the first direction, the third direction intersecting the first direction and the second direction.

8. The semiconductor device according to claim 7, wherein, the top select gate cut line extends in the third direction, and in the first direction, the top select gate cut line is provided between each adjacent two of the semiconductor pillars in the partition.

9. The semiconductor device according to claim 3, wherein, further comprising: a gate line slot structure penetrating the stacked structure in the second direction, the gate line slot structure extending in the first direction to divide the stacked structure into at least two partitions in the third direction.

10. The semiconductor device according to claim 9, wherein, the top select gate cut line extends in the third direction, and in the first direction, the top select gate cut line is provided between each adjacent two of the semiconductor pillars in the partition.

11. The semiconductor device according to claim 8 or 10, wherein, The size of the top selection gate tangent in the first direction is smaller than the size of the gate line gap structure in the first direction, or smaller than the size of the gate line gap structure in the third direction.

12. The semiconductor device according to claim 3, wherein, a gate dielectric layer is provided between the gate layer and the semiconductor pillar, and the gate dielectric layer includes an extension portion extending in the first direction and located between the gate layer and the first dielectric layer; wherein, one side of the top selection gate tangent close to the bit line is connected to the extension portion of the gate dielectric layer corresponding to the gate layer that is farthest from the bit line and not penetrated by the top selection gate tangent.

13. The semiconductor device according to claim 1 or 2, wherein, further comprising: a connection layer, located on a side of the semiconductor pillar away from the bit line, and in the first direction or the third direction, the size of the connection layer is greater than or equal to the size of the semiconductor pillar, and the third direction intersects the first direction and the second direction.

14. The semiconductor device according to claim 13, wherein, further comprising: a capacitor structure, located on a side of the connection layer away from the semiconductor pillar.

15. A storage system, characterized in that, comprising: at least one semiconductor device according to any one of claims 1-14; and a controller, coupled to the semiconductor device.

16. A method for manufacturing a semiconductor device, characterized in that, comprising: forming a bit line, the bit line extending in a first direction; forming an initial stacked structure on one side of the bit line, the initial stacked structure including a first dielectric layer and a second dielectric layer stacked on each other in a second direction, the second direction intersecting the first direction; forming a plurality of semiconductor pillars, the plurality of semiconductor pillars penetrating the initial stacked structure in the second direction and respectively connected to the bit line; removing the second dielectric layer to form a void in the initial stacked structure, filling the void and forming a gate layer, the gate layer surrounding the semiconductor pillar; and forming a selection gate tangent between at least some adjacent two of the semiconductor pillars in the first direction, the selection gate tangent penetrating at least one layer of the gate layer.

17. The manufacturing method according to claim 16, wherein, forming the bit line includes: forming a plurality of the bit lines spaced apart in a third direction, the third direction intersecting the first direction and the second direction.

18. The manufacturing method according to claim 17, wherein, the bit line includes a plurality of bit line contact structures spaced apart in the first direction, and forming a plurality of semiconductor pillars includes: forming a plurality of first holes in the initial stacked structure, the first holes penetrating the initial stacked structure in the second direction and exposing the bit line contact structures, the plurality of first holes being spaced apart in both the first direction and the third direction; and forming the semiconductor pillars in the first holes, the semiconductor pillars being connected to the bit line contact structures.

19. The manufacturing method according to claim 18, wherein, forming the semiconductor pillars in the first holes includes: Epitaxial growth is carried out using the bit line contact structure, and the semiconductor pillar is formed in the first hole. The materials of both the bit line contact structure and the semiconductor pillar are single crystal silicon.

20. The manufacturing method according to claim 17 or 18, wherein, an isolation layer is provided between two adjacent bit line contact structures of each bit line or between two adjacent bit lines. The second dielectric layer is removed to form a void in the initial stacked structure. Filling the void and forming the gate layer includes: forming a gate line gap that penetrates the initial stacked structure along the second direction and exposes the isolation layer. The gate line gap extends along the third direction to divide the initial stacked structure into at least two partitions in the first direction, or the gate line gap extends along the first direction to divide the initial stacked structure into at least two partitions in the third direction; removing the second dielectric layer through the gate line gap to form the void; and filling the void and forming the gate layer. In the third direction, the gate layers corresponding to two adjacent semiconductor pillars in the partition are connected.

21. The manufacturing method according to claim 20, wherein, the gate layer extends from the void to the side wall and bottom surface of the gate line gap. The method further includes: removing the gate layer located on the side wall and bottom surface of the gate line gap.

22. The manufacturing method according to claim 20, wherein, the select gate tangent line includes a top select gate tangent line. Forming a select gate tangent line between at least some adjacent semiconductor pillars includes: in the first direction, forming a top select gate opening extending along the third direction between each two adjacent semiconductor pillars in the partition. The top select gate opening penetrates at least the gate layer farthest from the bit line from the side of the initial stacked structure away from the bit line; and filling the top select gate opening and forming the top select gate tangent line.

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