Semiconductor device, memory system, and method of manufacturing semiconductor device

Abstract

The embodiment of the invention provides a semiconductor device, a storage system and a manufacturing method of the semiconductor device. The semiconductor device includes: a bit line extending in a first direction; the laminated structure comprises a first dielectric layer and a first gate layer which are mutually stacked in a second direction, and the second direction intersects with the first direction; the plurality of semiconductor columns penetrate through the laminated structure in the second direction and are respectively connected with the bit lines, the first gate layers surround the semiconductor columns, and in the first direction, the first gate layers corresponding to every two adjacent semiconductor columns are arranged at intervals.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more particularly, to a semiconductor device, a storage system, and a method for manufacturing a semiconductor device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor device, which consists of many repeated memory cells. However, due to process conditions, semiconductor devices usually have problems such as weak gate control performance. Summary of the Invention

[0003] The present application provides a semiconductor device, a storage system, and a method for manufacturing a semiconductor device that can at least partially solve the above problems or other problems in the art.

[0004] In a first aspect, some embodiments of the present application provide a semiconductor device. The semiconductor device includes: bit lines extending in a first direction; a stacked structure including a first dielectric layer and a first gate layer stacked on each other in a second direction, the second direction intersecting the first direction; and a plurality of semiconductor pillars penetrating the stacked structure in the second direction and respectively connected to the bit lines, wherein the first gate layer surrounds the semiconductor pillars, and in the first direction, there is a spaced arrangement between the first gate layers corresponding to two adjacent semiconductor pillars.

[0005] In some embodiments, the number of bit lines is multiple, and the multiple bit lines are spaced in a third direction, the third direction intersecting the first direction and the second direction.

[0006] In some embodiments, the plurality of semiconductor pillars are spaced in both the first direction and the third direction, and in the third direction, the first gate layers corresponding to two adjacent semiconductor pillars are connected.

[0007] In some embodiments, the bit line includes a plurality of bit line contact structures spaced in the first direction, and the semiconductor pillar is connected to the bit line contact structure; in the first direction, the size of the bit line contact structure is larger than the size of the semiconductor pillar.

[0008] In some embodiments, a first gate dielectric layer is provided between the first gate layer and the semiconductor pillar.

[0009] In some embodiments, the first gate dielectric layer includes a first part and a second part, the first part is located between the first gate layer and the semiconductor pillar, and the second part is located between the first gate layer and the first dielectric layer.

[0010] In some embodiments, the semiconductor device further includes: an isolation layer located between two adjacent bit line contact structures of each bit line and between two adjacent bit lines.

[0011] In some embodiments, the semiconductor device further includes: a gate line gap structure that penetrates the stacked structure in the second direction, and the gate line gap structure extends in a third direction that intersects the first direction and the second direction.

[0012] In some embodiments, in the first direction, a gate line gap structure is disposed between every two adjacent semiconductor pillars.

[0013] In some embodiments, the gate line gap structure includes a second insulating layer and a second gate layer, and the second gate layer is located between the second insulating layer and the stacked structure and is connected to the first gate layer.

[0014] In some embodiments, the stacked structure includes a plurality of stacked pairs, each stacked pair being a structure formed by a first dielectric layer and a first gate layer, and the second gate layer extends in the second direction and is connected to the plurality of first gate layers.

[0015] In some embodiments, the semiconductor device further includes: a connection layer located on a side of the semiconductor pillar away from the bit line, and in the first direction or the third direction, the size of the connection layer is greater than or equal to the size of the semiconductor pillar, and the third direction intersects the first direction and the second direction.

[0016] In some embodiments, the semiconductor device further includes: a capacitor structure located on a side of the connection layer away from the semiconductor pillar.

[0017] In a second aspect, some embodiments of the present application provide a storage system. The storage system includes: a semiconductor device as described in any embodiment of the first aspect; and a controller coupled to the semiconductor device.

[0018] In a third aspect, some embodiments of the present application provide a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device includes: forming a bit line that extends in the first direction; forming an initial stacked structure on one side of the bit line, the initial stacked structure including a first dielectric layer and a second dielectric layer stacked on each other in the second direction, and the second direction intersects the first direction; forming a plurality of semiconductor pillars that penetrate the initial stacked structure in the second direction and are respectively connected to the bit line; and removing the second dielectric layer to form a void in the initial stacked structure, filling the void and forming a first gate layer that surrounds the semiconductor pillars, and in the first direction, the first gate layers corresponding to two adjacent semiconductor pillars are spaced apart.

[0019] In some embodiments, forming the bit line includes: forming a plurality of bit lines spaced apart in a third direction, and the third direction intersects the first direction and the second direction.

[0020] In some embodiments, the bit lines include a plurality of bit line contact structures spaced apart in a first direction, forming a plurality of semiconductor pillars, including: forming a plurality of first holes in an initial stacked structure, the first holes penetrating the initial stacked structure in a second direction and exposing the bit line contact structures, the plurality of first holes being spaced apart in both the first direction and a third direction; and forming semiconductor pillars in the first holes, the semiconductor pillars being connected to the bit line contact structures.

[0021] In some embodiments, forming semiconductor pillars in the first holes includes: epitaxially growing using the bit line contact structures and forming semiconductor pillars in the first holes, the materials of the bit line contact structures and the semiconductor pillars being single crystal silicon.

[0022] In some embodiments, an isolation layer is provided between two adjacent bit line contact structures of each bit line or between two adjacent bit lines. Removing the second dielectric layer to form a void in the initial stacked structure, filling the void and forming a first gate layer includes: forming a gate line gap between every two adjacent semiconductor pillars in the first direction, the gate line gap penetrating the initial stacked structure in the second direction and exposing the isolation layer, the gate line gap extending in the third direction; removing the second dielectric layer via the gate line gap to form a void; and filling the void and forming a first gate layer.

[0023] In some embodiments, the method for manufacturing the semiconductor device further includes: forming a gate line gap structure in the gate line gap, the gate line gap structure being connected to the isolation layer;

[0024] Wherein, forming a gate line gap structure in the gate line gap includes: forming a second gate layer on the sidewalls of the gate line gap, the second gate layer being connected to the first gate layer; and forming a second insulating layer in the remaining region in the gate line gap.

[0025] In some embodiments, the initial stacked structure includes a plurality of initial stacked pairs, the initial stacked pairs being structures formed by a first dielectric layer and a second dielectric layer. Forming a second gate layer on the sidewalls of the gate line gap includes: forming a second gate layer extending in the second direction on the sidewalls of the gate line gap, the second gate layer being connected to a plurality of first gate layers.

[0026] According to one or more embodiments of the present application, the semiconductor device, storage system, and method for manufacturing a semiconductor device provided by the present application, the stacked structure includes a first dielectric layer and a first gate layer stacked on each other in a second direction, a plurality of semiconductor pillars penetrate the stacked structure and are respectively connected to the bit lines, and the first gate layer surrounds the semiconductor pillars, which is beneficial to improving the gate control performance of the enhanced semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects, and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Among them:

[0028] Figure 1 is a top view schematic diagram of a semiconductor device according to the present application;

[0029] Figure 2A is a cross-sectional schematic diagram taken along line A-A’ shown in Figure 1 according to an embodiment of the present application;

[0030] Figure 2B is Figure 2A an enlarged schematic diagram of region I in

[0031] Figure 2C and Figure 2D are cross-sectional schematic diagrams taken along line C-C’ and line D-D’ shown in Figure 2A according to an embodiment of the present application, respectively;

[0032] Figure 2E is a cross-sectional schematic diagram taken along line B-B’ shown in Figure 1 according to an embodiment of the present application;

[0033] Figure 2F is a cross-sectional schematic diagram taken along line A-A’ of a semiconductor device having a capacitor structure according to an embodiment of the present application; Figure 1 shown in

[0034] Figure 3A is a cross-sectional schematic diagram taken along line A-A’ shown in Figure 1 according to another embodiment of the present application;

[0035] Figure 3B is Figure 3A an enlarged schematic diagram of region II in

[0036] Figure 3C is a cross-sectional schematic diagram taken along line C-C’ shown in Figure 3A according to an embodiment of the present application;

[0037] Figure 3D is a cross-sectional schematic diagram taken along line B-B’ shown in Figure 1 according to another embodiment of the present application;

[0038] Figure 4 is a system block diagram of a system having a storage system according to an embodiment of the present application;

[0039] Figure 5 is a flowchart of a manufacturing method of a semiconductor device according to an embodiment of the present application; and

[0040] Figures 6A to 12 is a structural schematic diagram of a semiconductor device during the manufacturing process according to an embodiment of the present application. Detailed Embodiments

[0041] To better understand the present application, various aspects of the present application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application and do not limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] It should be noted that in this specification, the expressions such as first, second, etc. are only used to distinguish one feature from another feature and do not represent any limitation on the features, especially not any order. Therefore, without departing from the teachings of the present application, the first gate layer discussed in the present application may also be referred to as the second gate layer, and vice versa.

[0043] In the drawings, for ease of illustration, the thickness, dimensions, and shapes of the components have been slightly adjusted. The drawings are only examples and are not drawn to an exact scale. As used herein, the terms "substantially", "about", and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by a person of ordinary skill in the art.

[0044] It should also be understood that expressions such as "comprises", "comprising", "has", "including", and / or "including having" are open-ended rather than closed-ended expressions in this specification, which means that the stated features, elements, and / or components exist, but do not exclude the existence of one or more other features, elements, components, and / or their combinations. In addition, when an expression such as "at least one of..." appears after a list of listed features, it modifies the entire list of features rather than just an individual element in the list. In addition, when describing the embodiments of the present application, the use of "may" means "one or more embodiments of the present application". And the term "exemplary" is intended to refer to an example or illustration.

[0045] Unless otherwise defined, all terms used herein (including engineering terms and scientific and technical terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which the present application pertains. It should also be understood that unless clearly stated in the present application, words defined in a commonly used dictionary should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted in an idealized or overly formal sense.

[0046] It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Additionally, unless explicitly defined or contradictory to the context, the specific steps included in the methods described in the present application do not have to be limited to the recorded order, but can be executed in any order or executed in parallel.

[0047] In addition, in the present application, when using "connect" or "couple", it can indicate direct contact or indirect contact between the corresponding components, unless there are other explicit limitations or can be deduced from the context.

[0048] The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0049] An embodiment of the present application provides a semiconductor device. Figure 1 It is a top view schematic diagram of the semiconductor device provided by the embodiment of the present application. Figure 2A It is along Figure 1 The cross-sectional schematic diagram taken along the line A-A' shown. Figure 2B It is Figure 2A The enlarged schematic diagram of the region I in Figure 2C And Figure 2D They are respectively the cross-sectional schematic diagrams taken along Figure 2A The lines C-C' and D-D' shown. Figure 2E It is along Figure 1 The cross-sectional schematic diagram taken along the line B-B' shown. Figure 2F It is the cross-sectional schematic diagram taken along Figure 1 The line A-A' of the semiconductor device with a capacitive structure provided by the embodiment of the present application. The semiconductor device can be a memory or a part of a memory. For example, the memory can be a DRAM memory.

[0050] It should be noted that, hereinafter, the first direction is simply referred to as the D1 direction, the second direction is simply referred to as the D2 direction, and the third direction is simply referred to as the D3 direction. The D1 direction, D2 direction, and D3 direction in each drawing show the spatial relationship of the components in the semiconductor device. For example, the D2 direction is the stacking direction of the stacked structure, and the D1 direction and D3 direction are two directions that intersect (for example, are perpendicular) to each other on a plane intersecting (for example, perpendicular) to the stacking direction. In addition, the D1 direction, D2 direction, and D3 direction in each drawing include not only the directions indicated by the arrows, but also the directions away from the arrows. In other words, the arrows in the D1 direction, D2 direction, and D3 direction do not have a limiting meaning. The same concept will be used throughout the present application to describe the spatial relationship of the components in the semiconductor device.

[0051] As Figure 1 、 Figure 2A AndFigure 2C As shown in the figure, the semiconductor device 100 includes bit lines 110, a stacked structure 120, and a plurality of semiconductor pillars 130. The bit lines 110 can extend along the D1 direction. The stacked structure 120 can include a first dielectric layer 121 and a first gate layer 122 stacked on each other in the D2 direction. The plurality of semiconductor pillars 130 can penetrate the stacked structure 120 along the D2 direction and be respectively connected (e.g., in contact) with the bit lines 110. Among them, the first gate layer 122 can surround the semiconductor pillars 130, and there is a spaced arrangement between the first gate layers 122 corresponding to two adjacent semiconductor pillars 130 in the D1 direction.

[0052] The material of the first dielectric layer 121 can include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials. The material of the first gate layer 122 can include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si) or one or more of any other suitable conductive materials. For example, the material of the first dielectric layer 121 can be silicon oxide (SiO 2 ), and the material of the first gate layer 122 can be tungsten (W). The materials of the bit lines 110 and the semiconductor pillars 130 can include but are not limited to single-crystalline silicon.

[0053] According to the semiconductor device provided by the above embodiments of the present application, the semiconductor pillars penetrate the stacked structure and are in contact with the bit lines, and the first gate layer in the stacked structure surrounds the periphery of the semiconductor pillars, that is, the first gate layer is a Gate-All-Around (GAA). The GAA structure can enable the semiconductor pillars to be wrapped by the first gate layer in their circumferential directions, greatly reducing problems such as leakage current, capacitance effect, and short-channel effect, reducing the occupied area of the first gate layer in the stacking direction, and being beneficial to enhancing the gate control performance of the semiconductor device.

[0054] To further elaborate on the spatial relationship of the components in the semiconductor device 100, the semiconductor device 100 will be exemplified below in combination with Figure 1 、 Figures 2A to 2F .

[0055] In some embodiments, such as Figure 1 、 Figure 2A and Figure 2EAs shown, the number of bit lines 110 can be multiple, and the multiple bit lines 110 are arranged at intervals in the D3 direction. For each bit line 110, each bit line 110 includes a bit line body 112 and a plurality of bit line contact structures 111. The bit line body 112 can extend along the D1 direction, and the plurality of bit line contact structures 111 can be arranged at intervals along the D1 direction on the bit line body 112. An isolation layer 113 is provided between every two adjacent bit lines 110 and between every two adjacent bit line contact structures 111. The top surface of the isolation layer 113 is substantially flush with the top surface of the bit line contact structure 111 (for example, the error is less than or equal to ±10%). The material of the isolation layer 113 can include but is not limited to one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the isolation layer 113 can be silicon nitride (Si 3 N 4 ). By providing the isolation layer 113 between two adjacent bit line contact structures 111 and between two adjacent bit lines 110, electrical isolation between adjacent bit line contact structures 111 and between adjacent bit lines 110 can be achieved. The material of the bit line body 112 and the material of the bit line contact structure 111 can be the same.

[0056] In some embodiments, as shown in Figure 1 , Figure 2A and Figure 2E , a plurality of semiconductor pillars 130 are arranged in an array. The D1 direction is defined as the row direction, and the D3 direction is defined as the column direction. The semiconductor device 100 can include, for example, m×n semiconductor pillars 130, where m is the number of rows of the semiconductor pillars 130 and n is the number of columns of the semiconductor pillars 130. The plurality of semiconductor pillars 130 are arranged at intervals in both the D1 direction and the D3 direction. For each semiconductor pillar 130, the semiconductor pillar 130 can be connected (for example, in contact) to the bit line contact structure 111. In the D1 direction and / or the D3 direction, the size of the bit line contact structure 111 can be larger than the size of the semiconductor pillar 130 so that the end of the semiconductor pillar 130 close to the bit line 110 is in full contact with the bit line contact structure 111. The number of semiconductor pillars 130 and the number of bit line contact structures 111 can be the same. The shape of the semiconductor pillar 130 can be generally cylindrical.

[0057] It should be noted that the number of semiconductor columns 130 and bit-line contact structures 111 is not specifically limited in this application. For example, the number of bit-line contact structures 111 corresponds to the number of semiconductor columns 130, and the number of semiconductor columns 130 can be designed according to actual storage requirements. Generally speaking, the more the number of semiconductor columns 130, the more the number of subsequent capacitor structures connected thereto, the higher the integration degree of the semiconductor device 100, and the higher the storage density.

[0058] In some embodiments, as Figure 2A and Figure 2C shown, the stacked structure 120 may include at least one stacked pair, and each stacked pair is a structure formed by a first dielectric layer 121 and a first gate layer 122. For each stacked pair, the first gate layer 122 is farther from the bit line 110 than the first dielectric layer 121. In the D1 direction, the first gate layers 122 corresponding to two adjacent semiconductor columns 130 are arranged at intervals, that is, the first gate layers 122 corresponding to two adjacent semiconductor columns 130 in each row are discontinuous (for example, do not extend continuously). In the D3 direction, the first gate layers 122 corresponding to two adjacent semiconductor columns 130 are connected, that is, the first gate layers 122 corresponding to two adjacent semiconductor columns 130 in each column extend continuously.

[0059] The extension dimension of the first gate layer 122 in the D1 direction may be greater than the extension dimension of the first dielectric layer 121 in the D1 direction, and the extension dimension of the first gate layer 122 in the D3 direction may be less than the extension dimension of the first dielectric layer 121 in the D3 direction ( Figure 2E shown). And, a first dielectric layer 121 covers the surface of the uppermost stacked pair (for example, the stacked pair farthest from the bit line 110) away from the bit line 110. In the D1 direction and / or the D3 direction, the extension dimension of this first dielectric layer 121 may be substantially the same as the extension dimension of the first dielectric layer 121 in the stacked pair.

[0060] It should be noted that the dimensions and numbers of the first dielectric layer 121 and the first gate layer 122 are not specifically limited in this application. For example, each first dielectric layer 121 may have the same or different dimensions, and each first gate layer 122 may also have the same or different dimensions.

[0061] In some embodiments, as Figure 2A 、 Figure 2B and Figure 2EAs shown, for each semiconductor pillar 130, a first gate dielectric layer 123 can be provided between the semiconductor pillar 130 and the first gate layer 122. In the D1 direction, the first gate dielectric layers 123 corresponding to two adjacent semiconductor pillars 130 are arranged at intervals, that is, the first gate dielectric layers 123 corresponding to two adjacent semiconductor pillars 130 in each row are discontinuous (for example, not continuously extended). In the D3 direction, the first gate dielectric layers 123 corresponding to two adjacent semiconductor pillars 130 are connected, that is, the first gate dielectric layers 123 corresponding to two adjacent semiconductor pillars 130 in each column are continuously extended. The material of the first gate dielectric layer 123 can include but is not limited to one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the first gate dielectric layer 123 can be silicon nitride (Si 3 N 4 ).

[0062] Continuing to refer to Figure 2B , the first gate dielectric layer 123 can include a first part 1231 and a second part 1232. The first part 1231 can surround the semiconductor pillar 130 and is located between the first gate layer 122 and the semiconductor pillar 130, and the first part 1231 extends along the D2 direction. The second part 1232 can extend outward (for example, continuously extend) from the two end parts of the first part 1231 in the D2 direction within the plane defined by the D1 direction and the D3 direction, and the second part 1232 is located between the first gate layer 122 and the adjacent first dielectric layer 121. In the D1 direction, the second parts 1232 corresponding to two adjacent semiconductor pillars 130 are arranged at intervals. In the D3 direction, the second parts 1232 corresponding to two adjacent semiconductor pillars 130 are connected.

[0063] Each stack pair can include the above-mentioned first gate dielectric layer 123. For each stack pair, the extension dimension of the first part 1231 in the D2 direction can be substantially the same as the extension dimension of the first gate layer 122 in the D2 direction, and, in the D1 direction and / or the D3 direction, the extension dimension of the second part 1232 can be substantially the same as the sum of the extension dimensions of the first gate layer 122 and the first part 1231.

[0064] It should be noted that the size and quantity of the first gate dielectric layer 123 are not specifically limited in this application. For example, the quantity of the first gate dielectric layer 123 corresponds to the quantity of the first gate layer 122 in the above text, and each first gate dielectric layer 123 can have the same or different sizes.

[0065] In some embodiments, such as Figure 1 , Figure 2A, Figure 2C and Figure 2D As shown, the semiconductor device 100 may further include a gate line gap structure 140. The gate line gap structure 140 may penetrate the stacked structure 120 along the D2 direction and be connected to the isolation layer 113. The gate line gap structure 140 may extend along the D3 direction (e.g., continuously extend). In the D1 direction, the size of the portion of the gate line gap structure 140 for connecting to the isolation layer 113 may be smaller than the size of the isolation layer 113. The gate line gap structure 140 may be composed of a single material or a composite material. The material of the gate line gap structure 140 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), polysilicon (poly-Si), or any other suitable material. In the D1 direction, a gate line gap structure 140 is provided between every two adjacent semiconductor pillars 130. The adjacent two gate line gap structures 140 may define a region and provide electrical isolation between two adjacent regions.

[0066] As described above, in the D1 direction, the first gate dielectric layer 123 and the first gate electrode layer 122 corresponding to two adjacent semiconductor pillars 130 are both discontinuous (e.g., not continuously extend). Referring to Figure 2B , for each semiconductor pillar 130, the first part 1231 of the first gate dielectric layer 123 surrounds the periphery of the semiconductor pillar 130 and extends outward from the outer wall surface of the semiconductor pillar 130 in the plane defined by the D1 direction and the D3 direction. The second part 1232 of the first gate dielectric layer 123 respectively takes the two ends in the D2 direction of the first part 1231 as the centers and extends outward from the two ends in the D2 direction of the first part 1231 in the plane defined by the D1 direction and the D3 direction (e.g., continuously extend). In the D1 direction, the two side portions of the second part 1232 far from the first part 1231 are respectively in contact with two adjacent gate line gap structures 140. In the D3 direction, the second parts 1232 corresponding to two adjacent semiconductor pillars 130 are in contact.

[0067] Referring to Figure 2B and Figure 2C, the first gate layer 122 surrounds the periphery of the first part 1231 and extends outward from the outer wall surface of the first part 1231 in the plane defined by the D1 direction and the D3 direction. The first gate layer 122 is located between two second parts 1232 extending from the two end portions of the first part 1231 in the D2 direction. In the D1 direction, the two side portions of the first gate layer 122 away from the first part 1231 are respectively in contact with two adjacent gate line gap structures 140. In the D3 direction, the first gate layers 122 corresponding to two adjacent semiconductor pillars 130 are in contact. The gate line gap structure 140 can be used to make the first gate layers 122 corresponding to two adjacent semiconductor pillars 130 in the D1 direction discontinuous, so as to realize the partition control of two adjacent semiconductor pillars 130 in the D1 direction.

[0068] In some embodiments, as Figure 2B shown, the gate line gap structure 140 may include a second insulating layer 141 and a second gate layer 142. The second gate layer 142 is located between the second insulating layer 141 and the stacked structure 120 and is connected (e.g., in contact) to the first gate layer 122. The second insulating layer 141 is used to achieve electrical isolation between two adjacent semiconductor pillars 130 in the D1 direction.

[0069] As an example, the gate line gap structure 140 may further include a second gate dielectric layer 143. For example, the gate line gap structure 140 includes a second gate dielectric layer 143, a second gate layer 142, and a second insulating layer 141 arranged in sequence from outside to inside. Among them, the second gate dielectric layer 143 is in contact with the second part 1232 of the first gate dielectric layer 123, and the second gate layer 142 is in contact with the first gate layer 122. The material of the second insulating layer 141 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), tetraethyl orthosilicate (TEOS), or one or more of any other suitable insulating materials. The material of the second gate layer 142 may include but is not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or one or more of any other suitable conductive materials. The material of the second gate dielectric layer 143 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y) or one or more of any other suitable insulating materials. The material of the second gate layer 142 and the material of the first gate layer 122 may be the same. The material of the second gate dielectric layer 143 and the material of the first gate dielectric layer 123 may be the same. For example, the material of the second insulating layer 141 may be silicon oxide (SiO 2 ), the material of the second gate layer 142 may be tungsten (W), and the material of the second gate dielectric layer 143 may be silicon nitride (Si 3 N 4 ).

[0070] The stacked structure 120 may include a plurality of stacked pairs. The second gate layer 142 may extend (e.g., continuously extend) in the plane defined by the D2 direction and the D3 direction. In the D2 direction, the second gate layer 142 is connected (e.g., in contact) to the first gate layer 122 in the plurality of stacked pairs. For each semiconductor pillar 130, the second gate layer 142 is connected (e.g., in contact) to the plurality of first gate layers 122 corresponding to the semiconductor pillar 130, so that the plurality of first gate layers 122 corresponding to the semiconductor pillar 130 are short-circuited, realizing single-layer control of the semiconductor pillar 130. In addition, the second gate layer 142 may also serve as an extraction structure for the plurality of first gate layers 122 corresponding to the semiconductor pillar 130.

[0071] It should be noted that the dimensions of the second gate dielectric layer 143, the second gate layer 142, and the second insulating layer 141 are not specifically limited in this application. For example, the second gate dielectric layer 143 in different gate line gap structures 140 may have the same or different dimensions, the second gate layer 142 may have the same or different dimensions, and the second insulating layer 141 may have the same or different dimensions.

[0072] In some embodiments, as Figure 2B shown, the second gate dielectric layer 143 further includes an extension portion 1431 extending onto the isolation layer 113. For example, the ends of the second gate layer 142 and the second insulating layer 141 close to the bit line 110 may be in contact with the isolation layer 113 through the extension portion 1431.

[0073] As described above, in the D1 direction, the size of the portion of the gate line gap structure 140 for connecting to the isolation layer 113 is smaller than the size of the isolation layer 113, so that only the end of the second gate layer 142 close to the bit line 110 is in contact with the isolation layer 113, ensuring that the isolation layer 113 can achieve electrical isolation between the second gate layer 142 and the bit line contact structure 111. At the same time, at least the end of the second gate layer 142 close to the bit line 110 can be in contact with the isolation layer 113 through the extension portion 1431, and the extension portion 1431 can be further used to achieve electrical isolation between the second gate layer 142 and the bit line contact structure 111.

[0074] In some embodiments, as Figure 1, Figure 2A , Figure 2E and Figure 2F As shown, the semiconductor device 100 may further include a connection layer 150 and a capacitor structure 170. The connection layer 150 may be located on a side of the semiconductor pillar 130 away from the bit line 110 and connected (e.g., in contact) to the semiconductor pillar 130. The capacitor structure 170 may be located on a side of the connection layer 150 away from the semiconductor pillar 130 and connected (e.g., in contact) to the connection layer 150. The number of the connection layer 150 and the capacitor structure 170 may be the same as the number of the semiconductor pillars 130, that is, each semiconductor pillar 130 corresponds to one connection layer 150 and one capacitor structure 170. In the D1 direction and / or the D3 direction, the size of the connection layer 150 may be greater than or equal to the size of the semiconductor pillar 130. The material of the connection layer 150 may include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), or any other suitable conductive material. For example, the material of the connection layer 150 may be tungsten (W).

[0075] The surface of the connection layer 150 away from the bit line 110 may be substantially flush with the surface of the stacked structure 120 away from the bit line 110 (e.g., the error is less than or equal to ±10%). Alternatively, the surface of the semiconductor pillar 130 away from the bit line 110 may be substantially flush with the surface of the stacked structure 120 away from the bit line 110 (e.g., the error is less than or equal to ±10%), and the surface of the connection layer 150 away from the bit line 110 is not aligned with the surface of the stacked structure 120 away from the bit line 110.

[0076] It should be noted that the present application does not specifically limit the size and number of the connection layer 150 and the capacitor structure 170. For example, each connection layer 150 may have the same or different sizes. The number of the connection layer 150 corresponds to the number of the capacitor structure 170, and the number of the capacitor structure 170 may be designed according to actual storage requirements. Generally speaking, the more the number of the capacitor structure 170, the higher the integration degree and the storage density of the semiconductor device 100.

[0077] In some embodiments, the semiconductor device 100 may include a plurality of memory cells, each memory cell including a transistor structure and a capacitor structure, and the capacitor structure is configured to store data written into the memory cell. For each transistor structure, the transistor structure includes a semiconductor pillar 130 and a gate structure. The semiconductor pillar 130 may include a channel structure, a source, and a drain, and the source and the drain are respectively located at two ends of the channel structure in the D2 direction. For example, the end of the semiconductor pillar 130 away from the bit line 110 is doped to form the source, and the end of the semiconductor pillar 130 close to the bit line 110 is doped to form the drain. The source of the semiconductor pillar 130 may be connected to the capacitor structure, and the drain of the semiconductor pillar 130 may be connected to the bit line 110. The gate structure surrounds the channel structure of the semiconductor pillar 130 and includes a first gate layer 122 and a first gate dielectric layer 123. The plurality of first gate layers 122 corresponding to the same transistor structure are connected by a second gate layer 142. Thus, the second gate layer 142 and the first gate layer 122 may form a word line.

[0078] Figure 3A is a cross-sectional schematic view taken along line A-A' provided in another embodiment of the present application. Figure 1 as shown. Figure 3B is Figure 3A an enlarged schematic view of region II in Figure 3C is a cross-sectional schematic view taken along line C-C' Figure 3A as shown. Figure 3D is a cross-sectional schematic view taken along line B-B' provided in another embodiment of the present application. It should be noted that the cross-sectional schematic view taken along line D-D' shown in Figure 1 is the same as that in the above text. For the purpose of concise description, the same content as in the previous embodiment will not be repeated in this embodiment. Figure 3A as shown. Figure 2D the above.

[0079] In some embodiments, as Figure 3A , Figure 3B and Figure 3C shown, the stacked structure 220 may include a stacked pair, and the stacked pair is a structure formed by a first dielectric layer 221 and a first gate layer 222. For this stacked pair, the first gate layer 222 is farther from the bit line 210 than the first dielectric layer 221. In the D1 direction, the first gate layers 222 corresponding to two adjacent semiconductor pillars 230 are spaced apart, that is, the first gate layers 222 corresponding to two adjacent semiconductor pillars 230 in each row are discontinuous (for example, do not extend continuously). In the D3 direction, the first gate layers 222 corresponding to two adjacent semiconductor pillars 230 are connected, that is, the first gate layers 222 corresponding to two adjacent semiconductor pillars 230 in each column extend continuously.

[0080] The first gate layer 222 may include a first conductive portion 2221 and a second conductive portion 2222. The first conductive portion 2221 surrounds the periphery of the semiconductor pillar 230 and extends along the D2 direction. The second conductive portion 2222 extends outward (e.g., continuously) from the two end portions of the first conductive portion 2221 in the D2 direction within the plane defined by the D1 direction and the D3 direction. In the D3 direction, the second conductive portions 2222 corresponding to two adjacent semiconductor pillars 230 are connected, that is, the second conductive portions 2222 corresponding to two adjacent semiconductor pillars 230 in each column extend continuously.

[0081] The extension dimension of the first conductive portion 2221 in the D1 direction may be smaller than the extension dimension of the first dielectric layer 221 in the D1 direction, and the extension dimension of the first conductive portion 2221 in the D3 direction may be smaller than the extension dimension of the first dielectric layer 221 in the D3 direction. Moreover, the first dielectric layer 221 covers the surface of the stack pair away from the bit line 210, and in the D1 direction and / or the D3 direction, the extension dimension of this first dielectric layer 221 may be substantially the same as the extension dimension of the first dielectric layer 221 in the stack pair.

[0082] In some embodiments, as Figure 3A 、 Figure 3B and Figure 3C shown, for each semiconductor pillar 230, a first gate dielectric layer 223 may be disposed between the semiconductor pillar 230 and the first gate layer 222. In the D1 direction, the first gate dielectric layers 223 corresponding to two adjacent semiconductor pillars 230 are disposed at intervals, that is, the first gate dielectric layers 223 corresponding to two adjacent semiconductor pillars 230 in each row are discontinuous (e.g., do not extend continuously). In the D3 direction, the first gate dielectric layers 223 corresponding to two adjacent semiconductor pillars 230 are connected, that is, the first gate dielectric layers 223 corresponding to two adjacent semiconductor pillars 230 in each column extend continuously.

[0083] The first gate dielectric layer 223 may include a first portion 2231 and a second portion 2232. The first portion 2231 may surround the periphery of the semiconductor pillar 230 and is located between the first conductive portion 2221 and the semiconductor pillar 230, and the first portion 2231 extends along the D2 direction. The second portion 2232 may extend outward (e.g., continuously) from the two end portions of the first portion 2231 in the D2 direction within the plane defined by the D1 direction and the D3 direction, and the second portion 2232 is located between the second conductive portion 2222 and the first dielectric layer 221. In the D1 direction, the second portions 2232 corresponding to two adjacent semiconductor pillars 230 are disposed at intervals. In the D3 direction, the second portions 2232 corresponding to two adjacent semiconductor pillars 230 are connected. The extension dimension of the first portion 2231 in the D2 direction may be substantially the same as the sum of the extension dimensions of the first conductive portion 2221 and the second conductive portion 2222 in the D2 direction.

[0084] In some embodiments, as Figures 3A to 3D shown, the extension dimension of the first conductive portion 2221 in the D2 direction is greater than that of the second conductive portion 2222 in the D2 direction. A first insulating layer 225 is provided between the two second conductive portions 2222 extending from both ends of the first conductive portion 2221 in the D2 direction. The material of the first insulating layer 225 may include but is not limited to silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or one or more of any other suitable insulating materials.

[0085] In some embodiments, as Figure 3A , Figure 3C and Figure 3D shown, the semiconductor device 200 may further include a gate line slot structure 240. The gate line slot structure 240 may penetrate the stacked structure 220 along the D2 direction and be connected to the isolation layer 213. The gate line slot structure 240 may extend along the D3 direction (e.g., continuously extend). In the D1 direction, the dimension of the portion of the gate line slot structure 240 for connecting to the isolation layer 213 may be smaller than that of the isolation layer 213. In the D1 direction, a gate line slot structure 240 is provided between every two adjacent semiconductor pillars 230, and two adjacent gate line slot structures 240 may define a region and provide electrical isolation between two adjacent regions.

[0086] As described above, in the D1 direction, the first gate dielectric layer 223 and the first gate layer 222 corresponding to two adjacent semiconductor pillars 230 are discontinuous (e.g., not continuously extend). Referring to Figure 3B , for each semiconductor pillar 230, the first portion 2231 of the first gate dielectric layer 223 surrounds the periphery of the semiconductor pillar 230 and extends outward from the outer wall surface of the semiconductor pillar 230 in the plane defined by the D1 direction and the D3 direction. The second portion 2232 of the first gate dielectric layer 223 respectively takes the two end portions of the first portion 2231 in the D2 direction as centers and extends outward from the two end portions of the first portion 2231 in the D2 direction in the plane defined by the D1 direction and the D3 direction (e.g., continuously extend). In the D1 direction, the two side portions of the second portion 2232 away from the first portion 2231 are respectively in contact with two adjacent gate line slot structures 240. In the D3 direction, the second portions 2232 corresponding to two adjacent semiconductor pillars 230 are in contact.

[0087] Referring to Figure 3B and Figure 3C, the first conductive portion 2221 of the first gate layer 222 surrounds the outer periphery of the first portion 2231 and extends outward from the outer wall surface of the first portion 2231 in the plane defined by the D1 direction and the D3 direction. The second conductive portions 2222 of the first gate layer 222 are centered on the two end portions of the first conductive portion 2221 in the D2 direction respectively, and extend outward from the two end portions of the first conductive portion 2221 in the D2 direction in the plane defined by the D1 direction and the D3 direction (for example, continuously extend). The extension dimension of the second conductive portion 2221 in the D2 direction is smaller than the extension dimension of the first conductive portion 2221 in the D2 direction. In the D1 direction, the two side portions of the second conductive portion 2222 away from the first conductive portion 2221 are respectively in contact with two adjacent gate line gap structures 240. In the D3 direction, the second conductive portions 2222 corresponding to two adjacent semiconductor pillars 230 are in contact. The gate line gap structure 240 is used to make the first gate layer 222 corresponding to two adjacent semiconductor pillars 230 in the D1 direction discontinuous, so as to realize the partition control of two adjacent semiconductor pillars 230 in the D1 direction. The first insulating layer 225 extends outward from the outer wall surface of the first conductive portion 2221 in the plane defined by the D1 direction and the D3 direction and is located between the two second conductive portions 2222.

[0088] In some embodiments, as Figure 3B shown, the gate line gap structure 240 may include a second insulating layer 241, a second gate layer 242, and a second gate dielectric layer 243. For example, the gate line gap structure 240 includes a second gate dielectric layer 243, a second gate layer 242, and a second insulating layer 241 arranged in sequence from outside to inside, wherein the second gate dielectric layer 243 is in contact with the second portion 2232 of the first gate dielectric layer 223, the second gate layer 242 is in contact with the second conductive portion 2222 of the first gate layer 222, and the second insulating layer 241 is in contact with the first insulating layer 225. The second insulating layer 241 may be an insulating structure having an air gap 2411, which is used to realize the electrical isolation of two adjacent semiconductor pillars 230 in the D1 direction.

[0089] The embodiments of the present application also provide a storage system. Figure 4 is a system block diagram of the system provided by the embodiments of the present application with a storage system.

[0090] As Figure 4 shown, the system 300 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, an in-vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has a storage system 310 located therein). As Figure 4As shown, the system 300 may include a host 320 and a storage system 310. The storage system 310 has one or more 3D memories 311 and a controller 312. The host 320 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 320 may be configured to send or receive data to / from the 3D memory 311.

[0091] The 3D memory 311 may include semiconductor devices described in any embodiment of the present application. For example, Figure 1 the semiconductor device shown or Figures 2A to 2F the semiconductor device 100 shown or Figures 3A to 3D the semiconductor device shown. According to some embodiments, the controller 312 is coupled to the 3D memory 311 and the host 320, and is configured to control operations of the 3D memory 311, such as read, erase, and program operations. The controller 312 may also manage data stored in the 3D memory 311 and communicate with the host 320. For example, the controller 312 may communicate with an external device (e.g., the host 320) according to a specific communication protocol.

[0092] Embodiments of the present application also provide a method for manufacturing a semiconductor device. Figure 5 is a flowchart of the method for manufacturing a semiconductor device provided by an embodiment of the present application. As Figure 5 shown, the method 400 for manufacturing a semiconductor device (hereinafter simply referred to as the manufacturing method 400) includes the following steps.

[0093] S410, forming bit lines that extend in a first direction.

[0094] S420, forming an initial stack structure on one side of the bit lines. The initial stack structure includes a first dielectric layer and a second dielectric layer that are stacked on each other in a second direction, and the second direction intersects the first direction.

[0095] S430, forming a plurality of semiconductor pillars that penetrate the initial stack structure in the second direction and are respectively connected to the bit lines.

[0096] S440, removing the second dielectric layer to form a void in the initial stack structure, filling the void and forming a first gate layer. The first gate layer surrounds the semiconductor pillars, and there is a spaced arrangement between the first gate layers corresponding to adjacent two semiconductor pillars in the first direction.

[0097] The manufacturing method 400 of a semiconductor device provided by an embodiment of the present application is such that a semiconductor pillar penetrates a stacked structure and contacts a bit line, and a first gate layer in the stacked structure surrounds the periphery of the semiconductor pillar, that is, the first gate layer is a Gate-All-Around (GAA). The GAA structure can ensure that the semiconductor pillar is wrapped by the first gate layer in its circumferential direction, greatly reducing problems such as leakage current, capacitance effect, and short-channel effect, reducing the occupied area of the first gate layer in the stacking direction, and being beneficial to enhancing the gate control performance of the semiconductor device.

[0098] Figures 6A to 12 It is a schematic structural diagram of a semiconductor device provided by an embodiment of the present application during the manufacturing process. For example, Figures 6A to 12 may be an intermediate structure formed according to Figure 5 the manufacturing method 400 shown, and is used to form a semiconductor device 100 as shown in Figures 2A to 2F . The following further describes the manufacturing method 400 shown in Figures 6A to 12 in conjunction with Figure 5 .

[0099] S410. Form bit lines, which extend along a first direction.

[0100] Specifically, a substrate is provided. The substrate may have multiple bit lines 510. The multiple bit lines 510 are spaced apart in the D3 direction, and each bit line 510 can extend along the D1 direction. The substrate may be a semiconductor substrate, and the semiconductor substrate may include but is not limited to being one of a silicon substrate, a germanium substrate, a germanium-silicon substrate, or a silicon carbide substrate. For example, the semiconductor substrate may be a single-crystalline silicon substrate, that is, the material of the bit line 510 may be single-crystalline silicon.

[0101] For each bit line 510, each bit line 510 includes a bit line body 512 and multiple bit line contact structures 511. The bit line body 512 can extend along the D1 direction, and the multiple bit line contact structures 511 can be spaced apart along the D1 direction on the bit line body 512. An isolation layer 513 is provided between every two adjacent bit lines 510 and between every two adjacent bit line contact structures 511. The top surface of the isolation layer 513 is substantially flush with the top surface of the bit line contact structure 511 (for example, the error is less than or equal to ±10%). The material of the isolation layer 513 may include but is not limited to being one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ) or any other suitable insulating material. For example, the material of the isolation layer 513 may be silicon nitride (Si 3 N 4) By providing an isolation layer 513 between two adjacent bit line contact structures 511 and between two adjacent bit lines 510, electrical isolation between adjacent bit line contact structures 511 and between adjacent bit lines 510 can be achieved. The material of the bit line body 512 and the material of the bit line contact structure 511 can be the same.

[0102] S420. Form an initial stacked structure on one side of the bit lines. The initial stacked structure includes a first dielectric layer and a second dielectric layer stacked on top of each other in a second direction, and the second direction intersects the first direction. Figure 6A

[0103] Figure 6B and Figure 6A FIG. shows a cross-sectional schematic view of an intermediate structure 500a after forming an initial stacked structure. Specifically, Figure 2A is a cross-sectional schematic view of the intermediate structure 500a taken along the D1 direction (reference Figure 6B ). Figure 2E is a cross-sectional schematic view of the intermediate structure 500a taken along the D3 direction (reference Figure 6A ).

[0104] In step S420, as shown in Figure 6B and S430. Form a plurality of semiconductor pillars, which penetrate the initial stacked structure along the second direction and are respectively connected to the bit lines. , an initial stacked structure 520 is formed on the surface of the substrate provided with the bit line contact structure 511. The initial stacked structure 520 includes a first dielectric layer 521 and a second dielectric layer 524 stacked relative to each other. For example, a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof can be used to alternately form the first dielectric layer 521 and the second dielectric layer 524. The material of the first dielectric layer 521 and the material of the second dielectric layer 524 can be different from each other, so that the two have different etching selectivity ratios with respect to the same etching material. The material of the first dielectric layer 521 may include silicon oxide (SiO 2 ), and the material of the second dielectric layer 524 may include silicon nitride (Si 3 N 4 ). The initial stacked structure 520 may include a plurality of initial stacked pairs, and each initial stacked pair is a structure formed by the first dielectric layer 521 and the second dielectric layer 524. The surface of the uppermost initial stacked pair (e.g., the initial stacked pair farthest from the bit line 510) away from the bit line 510 is covered with the first dielectric layer 521.

[0105] Figure 7A Figure 7B

[0106] In step S430, a plurality of first holes 561 are formed in the initial stack structure 520. The first holes 561 penetrate the initial stack structure 520 along the D2 direction and expose the bit line contact structure 511. The plurality of first holes 561 are spaced apart in both the D1 direction and the D3 direction; and semiconductor pillars 530 are formed in the first holes 561, and the semiconductor pillars 530 are connected to the bit line contact structure 511.

[0107] Figure 7A and Figure 2A FIG. shows a cross-sectional schematic view of an intermediate structure 500b after a plurality of first holes are formed in the initial stack structure. Specifically, Figure 7B is a cross-sectional schematic view of the intermediate structure 500b taken along the D1 direction (reference Figure 2E ). Figure 8A is a cross-sectional schematic view of the intermediate structure 500b taken along the D3 direction (reference Figure 8B ). Figure 8A and Figure 2A FIG. shows a cross-sectional schematic view of an intermediate structure 500c after semiconductor pillars are formed in the first holes. Specifically, Figure 8B is a cross-sectional schematic view of the intermediate structure 500c taken along the D1 direction (reference Figure 2E ). Figure 7A is a cross-sectional schematic view of the intermediate structure 500c taken along the D3 direction (reference Figure 7B ).

[0108] As Figure 8A and Figure 8B shown, a plurality of first holes 561 penetrating the initial stack structure 520 along the D2 direction are formed by an etching process (e.g., dry etching and / or wet etching). The plurality of first holes 561 are spaced apart in both the D1 direction and the D3 direction. For each first hole 561, the first hole 561 can expose the bit line contact structure 511 to facilitate the subsequent direct formation of a semiconductor pillar 530 connected thereto through the bit line contact structure 511. The shape of the first hole 561 can be generally cylindrical.

[0109] As S440. Remove the second dielectric layer to form a void in the initial stacked structure, fill the void and form a first gate layer. The first gate layer surrounds the semiconductor pillars, and there is a gap between the first gate layers corresponding to adjacent two semiconductor pillars in the first direction. and Figure 9 shown, epitaxial growth is carried out using the bit line contact structure 511, and semiconductor pillars 530 are formed in the first holes 561. The material of the semiconductor pillars 530 is the same as that of the bit line contact structure 511, both being single crystal silicon. The number of semiconductor pillars 530 can be the same as the number of bit line contact structures 511. Forming the semiconductor pillars 530 by epitaxial growth using the bit line contact structure 511 can enable the semiconductor pillars 530 to have good interface defect states, thereby improving the carrier (e.g., electron or hole) mobility.

[0110] Figure 9 Figure 2AFigure 10A

[0111] In step S440, in the D1 direction, a gate line gap 562 is formed between every two adjacent semiconductor pillars 530. The gate line gap 562 penetrates the initial stacked structure 520 in the D2 direction and exposes the isolation layer 513. The gate line gap 562 extends in the D3 direction; through the gate line gap 562, the second dielectric layer 524 is removed to form a void 563; and the void 563 is filled and a first gate layer 522 is formed.

[0112] Figure 10B A cross-sectional schematic view of the intermediate structure 500d after the formation of the gate line gap is shown. Specifically, Figure 10A is a cross-sectional schematic view of the intermediate structure 500d taken along the D1 direction (reference Figure 2A ). Figure 10B and Figure 2E show a cross-sectional schematic view of the intermediate structure 500e after the removal of the second dielectric layer to form a void. Specifically, Figure 11A is a cross-sectional schematic view of the intermediate structure 500e taken along the D1 direction (reference Figure 11B ). Figure 11A is a cross-sectional schematic view of the intermediate structure 500e taken along the D3 direction (reference Figure 2A ). Figure 11B and Figure 2E show a cross-sectional schematic view of the intermediate structure 500f after filling the void and forming the first gate layer. Specifically, Figure 9 is a cross-sectional schematic view of the intermediate structure 500f taken along the D1 direction (reference Figure 10A ). Figure 10B is a cross-sectional schematic view of the intermediate structure 500f taken along the D3 direction (reference Figure 11A ).

[0113] As Figure 11B shown, an etching process (e.g., dry etching and / or wet etching) is used to form a gate line gap 562 between every two adjacent semiconductor pillars 530 in the D1 direction. The gate line gap 562 penetrates the initial stacked structure 520 in the D2 direction and exposes the isolation layer 513. The gate line gap 562 can extend in the D3 direction.

[0114] As Figure 2A and Figure 11A shown, by using the gate line gap 562, the second dielectric layer 524 is removed to form a void 563. For example, a wet etching process is used to etch the second dielectric layer 524 from both sides in the D1 direction through the gate line gap 562, and by controlling the etching time, the second dielectric layer 524 is completely removed, and a void 563 is formed in the area where the second dielectric layer 524 is located.

[0115] AsFigure 11B and Figure 12 As shown, a first gate layer 522 is formed in the void 563 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The first gate layer 522 surrounds the periphery of the semiconductor pillar 530. In the D1 direction, the first gate layers 522 corresponding to two adjacent semiconductor pillars 530 are spaced apart. For example, a first gate dielectric layer 523 is pre-formed in the void 563 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. At this time, the first gate dielectric layer 523 does not fill the entire area of the void 563. Then, the first gate layer 522 is formed in the remaining area of the void 563 that is not filled by the first gate dielectric layer 523. The material of the first gate layer 522 may include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material. The material of the first gate dielectric layer 523 may include, but is not limited to, one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), or any other suitable insulating material. Among them, the distribution and positional relationship of the first gate layer 522 and the first gate dielectric layer 523 have been described in detail above, and will not be elaborated herein. After this step, the initial stacked structure 520 can be converted into the stacked structure described above (refer to Figure 12 ).

[0116] In some embodiments, the manufacturing method 400 may further include: forming a gate line gap structure in the gate line gap 562, and the gate line gap structure is connected to the isolation layer 513.

[0117] In this step, a second gate layer 542 is formed on the sidewall of the gate line gap 562, and the second gate layer 542 is connected to the first gate layer 522; and a second insulating layer is formed in the remaining area within the gate line gap 562.

[0118] In Figure 2A and Figure 11A , a second gate dielectric layer and a second gate layer are also formed on the sidewall and bottom of the gate line gap. Figure 11B FIG. shows a cross-sectional schematic diagram of the intermediate structure 500g after removing the second gate layer at the bottom of the gate line gap. Specifically, Figure 12 is a cross-sectional schematic diagram of the intermediate structure 500g taken along the D1 direction (refer to Figure 2B ).

[0119] As Figure 2F and Figure 3AAs shown, a second gate layer 542 is formed on the sidewalls and bottom of the gate line gap 562 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. For example, a second gate dielectric layer 543 and a second gate layer 542 are sequentially formed on the sidewalls and bottom of the gate line gap 562 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0120] As Figure 3B shown, the second gate layer 542 at the bottom of the gate line gap 562 is removed by an etching process (e.g., dry etching and / or wet etching) so that the second gate layers 542 corresponding to two adjacent semiconductor pillars 530 in the D1 direction are discontinuous.

[0121] The second gate layer 542 and the second gate dielectric layer 543 do not fill the entire area of the gate line gap 562. A second insulating layer can be formed in the remaining area within the gate line gap 562 that is not filled by the second gate layer 542 and the second gate dielectric layer 543 by a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. The second insulating layer, the second gate layer 542, and the second gate dielectric layer 543 are arranged in sequence from the inside out to form a gate line gap structure (refer to Figure 3A ).

[0122] It should be noted that the second gate layer 542 and the first gate layer 522 can be formed synchronously, and the materials of the second gate layer 542 and the first gate layer 522 can be the same. The second gate dielectric layer 543 and the first gate dielectric layer 523 can be formed synchronously, and the materials of the second gate dielectric layer 543 and the first gate dielectric layer 523 can be the same. Among them, the distribution and positional relationship of the gate line gap structure have been described in detail above, and will not be elaborated herein.

[0123] In some embodiments, the manufacturing method 400 may further include: forming a connection layer on the side of the semiconductor pillar 530 away from the bit line 510, and the connection layer is connected (e.g., in contact) with the semiconductor pillar 530; and forming a capacitor structure on the side of the connection layer away from the semiconductor pillar 530, and the capacitor structure is connected (e.g., in contact) with the connection layer. After this step, the structure as shown in Figure 3CThe semiconductor device shown. The number of connection layers and capacitor structures can be the same as the number of semiconductor columns 530, that is, each semiconductor column 530 corresponds to a connection layer and a capacitor structure. In the D1 direction and / or the D3 direction, the size of the connection layer can be greater than or equal to the size of the semiconductor column 530. The material of the connection layer can include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), or any other suitable conductive material. For example, the material of the connection layer can be tungsten (W). Among them, the distribution and positional relationship of the connection layer and the capacitor structure have been described in detail above, and will not be elaborated herein.

[0124] In another embodiment, the initial stack structure 520 can include an initial stack pair.

[0125] Specifically, using a wet etching process, etching is performed from both sides of the second dielectric layer 524 in the D1 direction through the gate line gap 562, and by controlling the etching time, the second dielectric layer 524 is completely removed, and a void 563 is formed in the area where the second dielectric layer 524 is located. A first gate dielectric layer 523 and a first gate layer 522 are sequentially formed in the void 563 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. At this time, the first gate dielectric layer 523 and the first gate layer 522 do not fill the entire area of the void 563. Then, a first insulating layer is formed in the remaining area of the void 563 that is not filled by the first gate dielectric layer 523 and the first gate layer 522. The material of the first gate layer 522 can include, but is not limited to, one or more of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), titanium nitride (TiN), polysilicon (poly-Si), or any other suitable conductive material. The material of the first gate dielectric layer 523 can include, but is not limited to, one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), or any other suitable insulating material. The material of the first insulating layer can include, but is not limited to, one or more of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiO x N y ), or any other suitable insulating material. Among them, the distribution and positional relationship of the first gate layer 522, the first gate dielectric layer 523, and the first insulating layer have been described in detail above, and will not be elaborated herein. After this step, the initial stack structure can be converted into the stack structure described above (refer to Figure 3A ).

[0126] A thin film deposition process such as CVD, PVD, ALD or any combination thereof is used to sequentially form a second gate dielectric layer 543 and a second gate layer 542 on the sidewalls and bottom of the gate line gap 562. Then, an etching process (e.g., dry etching and / or wet etching) is used to remove the second gate layer 542 at the bottom of the gate line gap 562, so that the second gate layers 542 corresponding to two adjacent semiconductor pillars 530 in the D1 direction are discontinuous. Since the second gate dielectric layer 543 and the second gate layer 542 do not fill the entire area of the gate line gap 562, a thin film deposition process such as CVD, PVD, ALD or any combination thereof can be used to form a second insulating layer in the remaining area of the gate line gap 562 that is not filled by the second gate dielectric layer 543 and the second gate layer 542. The second insulating layer, the second gate layer 542 and the second gate dielectric layer 543 are arranged in sequence from the inside out to form a gate line gap structure (refer to Figure 3D ).

[0127] It should be noted that the second gate layer 542 and the first gate layer 522 can be formed synchronously, and the materials of the second gate layer 542 and the first gate layer 522 can be the same. The second gate dielectric layer 543 and the first gate dielectric layer 523 can be formed synchronously, and the materials of the second gate dielectric layer 543 and the first gate dielectric layer 523 can be the same. The second insulating layer and the first insulating layer can be formed synchronously, and the materials of the second insulating layer and the first insulating layer can be the same. Among them, the distribution and positional relationship of the gate line gap structure have been described in detail above, and will not be elaborated herein in this application.

[0128] The above description is only for the embodiments of the present application and the description of the applied technical principles. Those skilled in the art should understand that the protection scope involved in the present application is not limited to the technical solutions formed by the specific combination of the above technical features, but also covers other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the technical solutions formed by mutually replacing the above features with the (but not limited to) technical features with similar functions disclosed in the present application.

Claims

1. A semiconductor device, characterized in that, comprising: bit lines extending in a first direction; a stacked structure including a first dielectric layer and a first gate layer stacked on each other in a second direction, the second direction intersecting the first direction; and a plurality of semiconductor pillars penetrating the stacked structure in the second direction and respectively connected to the bit lines, wherein the first gate layer surrounds the semiconductor pillars, and in the first direction, there is a spaced arrangement between the first gate layers corresponding to two adjacent semiconductor pillars.

2. The semiconductor device according to claim 1, wherein, the number of the bit lines is multiple, and the multiple bit lines are spaced apart in a third direction, the third direction intersecting the first direction and the second direction.

3. The semiconductor device according to claim 2, wherein, the plurality of semiconductor pillars are spaced apart in both the first direction and the third direction, and in the third direction, the first gate layers corresponding to two adjacent semiconductor pillars are connected.

4. The semiconductor device according to claim 2, wherein, the bit line includes a plurality of bit line contact structures spaced apart in the first direction, and the semiconductor pillar is connected to the bit line contact structure; in the first direction, the size of the bit line contact structure is larger than the size of the semiconductor pillar.

5. The semiconductor device according to claim 1, wherein, a first gate dielectric layer is provided between the first gate layer and the semiconductor pillar.

6. The semiconductor device according to claim 5, wherein, the first gate dielectric layer includes a first part and a second part, the first part is located between the first gate layer and the semiconductor pillar, and the second part is located between the first gate layer and the first dielectric layer.

7. The semiconductor device according to claim 4, wherein, further comprising: an isolation layer located between two adjacent bit line contact structures of each bit line and between two adjacent bit lines.

8. The semiconductor device according to claim 1, wherein, further comprising: a gate line gap structure penetrating the stacked structure in the second direction, the gate line gap structure extending in a third direction, the third direction intersecting the first direction and the second direction.

9. The semiconductor device according to claim 8, wherein, in the first direction, the gate line gap structure is provided between every two adjacent semiconductor pillars.

10. The semiconductor device according to claim 8, wherein, the gate line gap structure includes a second insulating layer and a second gate layer, the second gate layer is located between the second insulating layer and the stacked structure and is connected to the first gate layer.

11. The semiconductor device according to claim 10, wherein, the stacked structure includes a plurality of stacked pairs, the stacked pair is a structure formed by the first dielectric layer and the first gate layer, and the second gate layer extends in the second direction and is connected to a plurality of the first gate layers.

12. The semiconductor device according to any one of claims 1-11, wherein, further comprising: A connection layer, located on a side of the semiconductor pillar away from the bit line. In the first direction or the third direction, the size of the connection layer is greater than or equal to the size of the semiconductor pillar, and the third direction intersects the first direction and the second direction.

13. The semiconductor device according to claim 12, wherein, further comprising: a capacitor structure, located on a side of the connection layer away from the semiconductor pillar.

14. A storage system, characterized in that, comprising: at least one semiconductor device according to any one of claims 1 - 13; and a controller, coupled to the semiconductor device.

15. A manufacturing method of a semiconductor device, characterized in that, comprising: forming a bit line, the bit line extending along a first direction; forming an initial stacked structure on one side of the bit line, the initial stacked structure including a first dielectric layer and a second dielectric layer stacked on each other in a second direction, and the second direction intersects the first direction; forming a plurality of semiconductor pillars, the plurality of semiconductor pillars penetrating the initial stacked structure along the second direction and respectively connected to the bit line; and removing the second dielectric layer to form a void in the initial stacked structure, filling the void and forming a first gate layer, the first gate layer surrounding the semiconductor pillar, and being spaced between the first gate layers corresponding to two adjacent semiconductor pillars in the first direction.

16. The manufacturing method according to claim 15, wherein, forming the bit line includes: forming a plurality of the bit lines spaced in a third direction, and the third direction intersects the first direction and the second direction.

17. The manufacturing method according to claim 16, wherein, the bit line includes a plurality of bit line contact structures spaced in the first direction. Forming a plurality of semiconductor pillars includes: forming a plurality of first holes in the initial stacked structure, the first holes penetrating the initial stacked structure along the second direction and exposing the bit line contact structures, and the plurality of first holes are spaced in both the first direction and the third direction; and forming the semiconductor pillars in the first holes, and the semiconductor pillars are connected to the bit line contact structures.

18. The manufacturing method according to claim 17, wherein, forming the semiconductor pillars in the first holes includes: using the bit line contact structures for epitaxial growth and forming the semiconductor pillars in the first holes, and the materials of the bit line contact structures and the semiconductor pillars are both single - crystal silicon.

19. The manufacturing method according to claim 16 or 17, wherein, an isolation layer is provided between two adjacent bit line contact structures of each bit line or between two adjacent bit lines. Removing the second dielectric layer to form a void in the initial stacked structure, filling the void and forming a first gate layer includes: forming a gate line gap between every two adjacent semiconductor pillars in the first direction, the gate line gap penetrating the initial stacked structure along the second direction and exposing the isolation layer, and the gate line gap extending along the third direction; Removing the second dielectric layer through the gate line gap to form the void; and Filling the void and forming the first gate layer.

20. The manufacturing method according to claim 19,[[]]END]] wherein,[[]]END]] the method further includes:[[]]END]] Forming a gate line gap structure within the gate line gap, the gate line gap structure being connected to the isolation layer;[[]]END]] wherein, forming a gate line gap structure within the gate line gap includes:[[]]END]] Forming a second gate layer on the sidewalls of the gate line gap, the second gate layer being connected to the first gate layer; and[[]]END]] Forming a second insulating layer in the remaining area within the gate line gap.[[]]END]] 21. The manufacturing method according to claim 20,[[]]END]] wherein,[[]]END]] the initial stack structure includes a plurality of initial stack pairs, the initial stack pair being a structure formed by the first dielectric layer and the second dielectric layer, forming a second gate layer on the sidewalls of the gate line gap includes:[[]]END]] Forming the second gate layer extending in the second direction on the sidewalls of the gate line gap, the second gate layer being connected to a plurality of the first gate layers.[[]]END]]

Images