Semiconductor structure, forming method thereof and memory

Abstract

The invention relates to a semiconductor structure and a forming method thereof, and a memory, and the semiconductor structure comprises an active layer, a first gate dielectric layer, a first word line structure, a second gate dielectric layer, a second word line structure, a bit line structure, a common electrode, a dielectric layer, and a conductive contact layer. The active layer comprises a first channel region, a second channel region, a source region, a first drain region and a second drain region which are at least partially different lines, and the first gate dielectric layer at least covers part of the surface of the first channel region; the first word line structure covers the first gate dielectric layer and extends along the first direction; the second gate dielectric layer at least covers part of the surface of the second channel region; the second word line structure covers the second gate dielectric layer and extends along the first direction; the bit line structure is electrically connected with the source electrode region; in the second direction, the common electrode is located between the first channel region and the second channel region; the dielectric layer at least covers the periphery of the common electrode; the conductive contact layer covers the surface of the dielectric layer and is electrically connected with the second drain region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure, a method for forming the same, and a memory. Background Art

[0002] Memories are widely used in mobile devices such as mobile phones and tablet computers due to their advantages of small volume, high integration level, and fast transmission speed. However, due to the influence of the existing memory structure, the leakage phenomenon is relatively serious, resulting in poor structural reliability.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure, a method for forming the same, and a memory, which can reduce leakage and improve device reliability.

[0005] According to one aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0006] An active layer, including a first channel region, a second channel region, a source region, a first drain region, and a second drain region, wherein the first channel region and the second channel region both extend along a first direction, and the first channel region and the second channel region are spaced apart along a second direction; the first direction intersects the second direction; the first drain region is connected to one end of the first channel region, and the second drain region is connected to the end of the second channel region close to the first drain region; the source region is connected between the end of the first channel region far from the first drain region along the first direction and the end of the second channel region far from the second drain region along the first direction, and the first drain region and the second drain region are insulated from each other;

[0007] A first gate dielectric layer, covering at least a part of the surface of the first channel region;

[0008] A first word line structure, covering the first gate dielectric layer and extending along the first direction;

[0009] A second gate dielectric layer, covering at least a part of the surface of the second channel region;

[0010] A second word line structure, covering the second gate dielectric layer and extending along the first direction;

[0011] A bit line structure, electrically connected to the source region;

[0012] A common electrode, which is located between the first channel region and the second channel region in the second direction;

[0013] A dielectric layer covering at least the outer periphery of the common electrode;

[0014] A conductive contact layer covering the surface of the dielectric layer and electrically connected to the second drain region.

[0015] In an exemplary embodiment of the present disclosure, the conductive contact layer is located between the common electrode and the first channel region; or, the conductive contact layer is located between the common electrode and the second channel region.

[0016] In an exemplary embodiment of the present disclosure, when the conductive contact layer is located between the common electrode and the first channel region, the dielectric layer is further located between the conductive contact layer and the first drain region, the first channel region, and the source region; when the conductive contact layer is located between the common electrode and the second channel region, the dielectric layer is further located between the conductive contact layer and the second drain region, the second channel region, and the source region.

[0017] In an exemplary embodiment of the present disclosure, the material of the dielectric layer is a high-k material.

[0018] In an exemplary embodiment of the present disclosure, the first gate dielectric layer surrounds the first channel region for one week, and the first word line structure surrounds the first gate dielectric layer for one week;

[0019] And / or, the second gate dielectric layer surrounds the second channel region for one week, and the second word line structure surrounds the second gate dielectric layer for one week.

[0020] In an exemplary embodiment of the present disclosure, the first gate dielectric layer covers the surface of the first channel region far from the second channel region and the surfaces of two sidewalls of the first channel region that are oppositely distributed along the third direction, and the third direction is perpendicular to the first direction and the second direction;

[0021] And / or, the second gate dielectric layer covers the surface of the second channel region far from the first channel region and the surfaces of two sidewalls of the second channel region that are oppositely distributed along the third direction.

[0022] In an exemplary embodiment of the present disclosure, the materials of the first channel region and the second channel region are different.

[0023] In an exemplary embodiment of the present disclosure, the material of the first channel region includes at least one of indium gallium zinc oxide, indium gallium oxide, or indium zinc oxide.

[0024] In an exemplary embodiment of the present disclosure, the material of the second channel region includes at least one of indium tin oxide, polysilicon, silicon, or silicon germanium.

[0025] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes:

[0026] An insulating layer located between the first drain region and the second drain region.

[0027] In an exemplary embodiment of the present disclosure, the semiconductor structure further includes a ground electrode electrically connected to the first drain region to ground the first drain region.

[0028] According to one aspect of the present disclosure, there is provided a memory including a plurality of the semiconductor structures as described in any one of the above. The number of the semiconductor structures is plural, and the plural semiconductor structures form a plurality of semiconductor groups spaced apart along a first direction. Each semiconductor group includes a plurality of the semiconductor structures stacked along a third direction; each of the semiconductor structures in the same semiconductor group shares the bit line structure, and two adjacent semiconductor structures along the first direction in different semiconductor groups share the first gate dielectric layer, the second gate dielectric layer, the first word line structure, and the second word line structure.

[0029] According to one aspect of the present disclosure, there is provided a method for forming a semiconductor structure, including:

[0030] Forming an active layer including a first channel region, a second channel region, a source region, a first drain region, and a second drain region. The first channel region and the second channel region both extend along a first direction, and the first channel region and the second channel region are spaced apart along a second direction; the first direction intersects the second direction; the first drain region is connected to one end of the first channel region, and the second drain region is connected to the end of the second channel region close to the first drain region; the source region is connected between the end of the first channel region far from the first drain region along the first direction and the end of the second channel region far from the second drain region along the first direction, and the first drain region and the second drain region are insulated from each other;

[0031] Forming a first gate dielectric layer covering at least a partial surface of the first channel region;

[0032] Forming a first word line structure covering the first gate dielectric layer and extending along the first direction;

[0033] Forming a second gate dielectric layer covering at least a partial surface of the second channel region;

[0034] Forming a second word line structure covering the second gate dielectric layer and extending along the first direction;

[0035] Form a bit line structure, the bit line structure being electrically connected to the source region;

[0036] Form a common electrode, the common electrode being located between the first channel region and the second channel region in the second direction;

[0037] Form a dielectric layer at least covering the outer periphery of the common electrode;

[0038] Form a conductive contact layer covering the surface of the dielectric layer, the conductive contact layer being electrically connected to the second drain region.

[0039] In an exemplary embodiment of the present disclosure, the materials of the first channel region and the second channel region are different.

[0040] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0041] Form an insulating layer between the first drain region and the second drain region.

[0042] For the semiconductor structure and its forming method of the present disclosure, on the one hand, the common electrode, the dielectric layer and the conductive contact layer can jointly form a structure similar to a capacitor, which can be used to store charges; this structure can be read and written through current. Compared with the traditional capacitor structure, this structure is not sensitive to various parasitic effects, the leakage phenomenon is significantly weakened, the data retention time is longer, and the refresh frequency can be reduced, reducing power consumption, the structure has strong reliability, and is convenient for 3D stacking. On the other hand, the active layer, the first gate dielectric layer, the first word line structure, the second gate dielectric layer and the second word line structure jointly form a dual-transistor structure, which can effectively improve the transistor distribution density, and adjacent transistors can share the source region and the bit line structure, which helps to reduce the wiring density, save area and reduce the parasitic coupling effect; in addition, since the source region, the first drain region and the second drain region are all non-collinear with the first word line structure and / or the second word line structure, the parasitic coupling effect can be further reduced while facilitating wiring, thereby improving the device reliability.

[0043] For the memory of the present disclosure, since the source region, the first drain region and the second drain region are all non-collinear with the first word line structure and / or the second word line structure, and the bit line structures are shared in the third direction by the semiconductor structures in the same semiconductor group, and the first gate dielectric layer, the second gate dielectric layer, the first word line structure and the second word line structure are shared by two adjacent semiconductor structures in the first direction in different semiconductor groups, it is convenient to realize the 3D stacking of the first word line structure and / or the second word line structure and the bit line structure. This design will not increase the height of the single-layer transistors in the third direction, is more conducive to 3D stacking, and the manufacturing process is relatively simple, and the manufacturing cost is low.

[0044] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and do not limit the present disclosure. Brief Description of the Drawings

[0045] The drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0046] Figure 1 Schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0047] Figure 2 Top view of a semiconductor structure in an embodiment of the present disclosure.

[0048] Figure 3 Schematic diagram of a semiconductor structure in an embodiment of the present disclosure.

[0049] Figure 4 Cross-sectional view of a second channel region, a second gate dielectric layer, and a second word line structure taken along a second direction in an embodiment of the present disclosure.

[0050] Figure 5 Cross-sectional view of a second channel region, a second gate dielectric layer, and a second word line structure taken along a second direction in another embodiment of the present disclosure.

[0051] Figure 6 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0052] Figure 7 Schematic diagram of a memory in an embodiment of the present disclosure.

[0053] Figure 8 Top view of a memory in an embodiment of the present disclosure.

[0054] Description of Reference Numerals:

[0055] 100, memory; 1, active layer; 11, first channel region; 12, second channel region; 13, source region; 14, first drain region; 15, second drain region; 2, first gate dielectric layer; 3, first word line structure; 4, second gate dielectric layer; 5, second word line structure; 6, bit line structure; 7, common electrode; 8, dielectric layer; 9, conductive contact layer; 10, insulating layer; 20, ground electrode; 30, insulating protection layer; X, first direction; Y, second direction; Z, third direction. Detailed Description of the Embodiments

[0056] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0057] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another component, these terms are used in this specification only for convenience, for example, according to the directions of the examples described in the drawings. It can be understood that if the device of the icon is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" another structure, it may mean that a structure is integrally formed on another structure, or that a structure is "directly" disposed on another structure, or that a structure is "indirectly" disposed on another structure through another structure.

[0058] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "comprising" and "having" are used to mean an open inclusion and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.; the terms "first", "second", "third", etc. are used only as labels and are not a limitation on the quantity of their objects.

[0059] With the continuous development of mobile devices, mobile devices such as mobile phones, tablet computers, and wearable devices are increasingly used in life. As an essential component in mobile devices, people have put forward huge demands for the small size and integration of memories. In the manufacturing process of memories, it is becoming increasingly difficult to miniaturize transistors and capacitors due to structural limitations. Moreover, as the size of the capacitor decreases, the amount of charge stored in it continuously decreases, and the leakage phenomenon is relatively serious. At the same time, when performing 3D stacking, the 3D stacking of capacitors is difficult, and various parasitic capacitors in the 3D structure seriously erode the read / write window, resulting in low device reliability.

[0060] Based on this, the embodiments of the present disclosure provide a semiconductor structure, as Figure 1 and Figure 2 shown. The semiconductor structure includes an active layer 1, a first gate dielectric layer 2, a first word line structure 3, a second gate dielectric layer 4, a second word line structure 5, a bit line structure 6, a common electrode 7, a dielectric layer 8, and a conductive contact layer 9, wherein:

[0061] The active layer 1 includes a first channel region 11, a second channel region 12, a source region 13, a first drain region 14, and a second drain region 15. Both the first channel region 11 and the second channel region 12 extend along a first direction X, and the first channel region 11 and the second channel region 12 are spaced apart along a second direction Y; the first direction X intersects the second direction Y; the first drain region 14 is connected to one end of the first channel region 11, and the second drain region 15 is connected to the end of the second channel region 12 close to the first drain region 14; the source region 13 is connected between the end of the first channel region 11 far from the first drain region 14 along the first direction X and the end of the second channel region 12 far from the second drain region 15 along the first direction X, and the first drain region 14 and the second drain region 15 are insulated from each other;

[0062] The first gate dielectric layer 2 covers at least a partial surface of the first channel region 11;

[0063] The first word line structure 3 covers the first gate dielectric layer 2 and extends along the first direction X;

[0064] The second gate dielectric layer 4 covers at least a partial surface of the second channel region 12;

[0065] The second word line structure 5 covers the second gate dielectric layer 4 and extends along the first direction X;

[0066] The bit line structure 6 is electrically connected to the source region 13;

[0067] In the second direction Y, the common electrode 7 is located between the first channel region 11 and the second channel region 12;

[0068] The dielectric layer 8 at least coats the outer periphery of the common electrode 7;

[0069] The conductive contact layer 9 covers the surface of the dielectric layer 8 and is electrically connected to the second drain region 15.

[0070] On one hand, the semiconductor structure of the present disclosure, the common electrode 7, the dielectric layer 8, and the conductive contact layer 9 can jointly form a structure similar to a capacitor, which can be used to store charges; this structure can be read and written through current. Compared with the traditional capacitor structure, this structure is insensitive to various parasitic effects, the leakage phenomenon is significantly weakened, the data retention time is longer, and the refresh frequency can be reduced, thereby reducing power consumption. The structure has strong reliability and is convenient for 3D stacking. On the other hand, the active layer 1, the first gate dielectric layer 2, the first word line structure 3, the second gate dielectric layer 4, and the second word line structure 5 jointly form a dual-transistor structure, which can effectively increase the transistor distribution density, and adjacent transistors can share the source region 13 and the bit line structure 6, which helps to reduce the wiring density, save area and reduce the parasitic coupling effect; in addition, since the source region 13, the first drain region 14, and the second drain region 15 are all non-collinear with the first word line structure 3 and / or the second word line structure 5, the parasitic coupling effect can be further reduced while facilitating wiring, thereby improving the device reliability.

[0071] The following will detail each part of the semiconductor structure of the present disclosure and its specific details:

[0072] As Figure 1 and Figure 2 shown, the active layer 1 may include a first channel region 11, a second channel region 12, a source region 13, a first drain region 14, and a second drain region 15. Among them, the first channel region 11 and the second channel region 12 may be distributed in parallel, the first channel region 11 and the second channel region 12 may both extend along the first direction X, and the first channel region 11 may be spaced from the second channel region 12 along the second direction Y.

[0073] It should be noted that the first direction X may intersect the second direction Y. For example, the first direction X and the second direction Y may be perpendicular to each other. It should be noted that perpendicularity can be absolute perpendicularity or approximately perpendicular. There will inevitably be deviations during the manufacturing process. In the present disclosure, the angle deviation may be caused by the manufacturing process limitations, so that there is a certain deviation in the included angle between the first direction X and the second direction Y. As long as the angle deviation between the first direction X and the second direction Y is within the preset range, it can be considered that the first direction X is perpendicular to the second direction Y. For example, the preset range may be 10°, that is: when the included angle between the first direction X and the second direction Y is greater than or equal to 80° and less than or equal to 100°, it can be considered that the first direction X is perpendicular to the second direction Y.

[0074] The first drain region 14 can be connected to an end portion of the first channel region 11 distributed along the first direction X, and the first drain region 14 can be non - collinear with the first channel region 11. For example, the first drain region 14 can extend along the second direction Y. The second drain region 15 is connected to an end portion of the second channel region 12 close to the first drain region 14. For example, the second drain region 15 can be connected to the end portion of the second channel region 12 distributed along the first direction X that is close to the first drain region 14, and the second drain region 15 can be non - collinear with the second channel region 12. For example, the second drain region 15 can extend along the second direction Y. It should be noted that when both the first drain region 14 and the second drain region 15 extend along the second direction Y, the end portion of the first drain region 14 along the second direction Y away from the first channel region 11 can be distributed opposite to the end portion of the second drain region 15 along the second direction Y away from the second channel region 12, and the end portion of the first drain region 14 along the second direction Y away from the first channel region 11 can be insulated from the end portion of the second drain region 15 along the second direction Y away from the second channel region 12.

[0075] For example, an insulating layer 10 can be provided between the end portion of the first drain region 14 along the second direction Y away from the first channel region 11 and the end portion of the second drain region 15 along the second direction Y away from the second channel region 12. The material of the insulating layer 10 can be silicon nitride. In some embodiments of the present disclosure, the insulating layer 10 can be strip - shaped and can extend along the third direction Z, and the third direction Z can be perpendicular to both the first direction X and the second direction Y.

[0076] The source region 13 can be non - collinear with the first channel region 11 and / or the second channel region 12. Since the first drain region 14, the first channel region 11, and the source region 13 are non - collinear, and at the same time the second drain region 15, the second channel region 12, and the source region 13 are non - collinear, it is possible to reduce the parasitic coupling effect while facilitating wiring and improve the device reliability.

[0077] For example, the source region 13 can be connected between the end portion of the first channel region 11 along the first direction X away from the first drain region 14 and the end portion of the second channel region 12 along the first direction X away from the second drain region 15. The source region 13 can be parallel to the first drain region 14 and / or the second drain region 15. For example, the first drain region 14, the second drain region 15, and the source region 13 can all extend along the second direction Y. In some embodiments of the present disclosure, the first channel region 11, the second channel region 12, the first drain region 14, the second drain region 15, the source region 13, and the insulating layer 10 can form a ring - shaped structure similar to a rectangle.

[0078] In some embodiments of the present disclosure, the doping types of the first drain region 14, the second drain region 15, and the source region 13 are the same, the doping types of the first channel region 11 and the second channel region 12 are the same, and the doping types of the first drain region 14 and the first channel region 11 are different. For example, the doping types of the first drain region 14, the second drain region 15, and the source region 13 are all n-type, and the doping types of the first channel region 11 and the second channel region 12 are both p-type. N-type ions can be implanted into the first drain region 14, the second drain region 15, and the source region 13 through an ion implantation process.

[0079] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 1 and Figure 2 As shown, the semiconductor structure of the present disclosure may further include a ground electrode 20, and the ground electrode 20 may be electrically connected to the first drain region 14 to ground the first drain region 14. For example, the ground electrode 20 may be disposed on the surface of the first drain region 14 away from the source region 13 along the first direction X; alternatively, the ground electrode 20 may be at least partially embedded in the first drain region 14; or the ground electrode 20 may be disposed between the first drain region 14 and the insulating layer 10. The ground electrode 20 may be strip-shaped and may extend along the third direction Z. For example, both the ground electrode 20 and the insulating layer 10 may extend along the third direction Z, and the ground electrode 20 and the insulating layer 10 may be arranged side by side in the second direction Y.

[0080] Please continue to refer to Figure 1 and Figure 2 As shown, the first gate dielectric layer 2 at least covers a partial surface of the first channel region 11. For example, the first gate dielectric layer 2 may at least cover the surface of the first channel region 11 away from the second channel region 12 along the second direction Y. The first gate dielectric layer 2 may be strip-shaped and may extend along the first direction X. The material of the first gate dielectric layer 2 may be silicon oxide, and the first gate dielectric layer 2 may be formed on the surface of the first channel region 11 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or in-situ steam oxidation, etc. Of course, the first gate dielectric layer 2 may also be formed by other methods, and the formation method of the first gate dielectric layer 2 is not specially limited herein.

[0081] The first word line structure 3 may cover the surface of the first gate dielectric layer 2. The first word line structure 3 may also be strip-shaped and may extend along the first direction X. For example, the first word line structure 3 may cover the entire surface of the first gate dielectric layer 2. The first word line structure 3, the first gate dielectric layer 2, the first channel region 11, the first drain region 14, and the source region 13 may jointly form a transistor structure.

[0082] In some embodiments of the present disclosure, the first word line structure 3 may include a first conductive layer, a first barrier layer, and a second conductive layer that are sequentially distributed along the second direction Y. Among them, the first conductive layer may cover the surface of the first gate dielectric layer 2, the first barrier layer may be located between the first conductive layer and the second conductive layer, the material of the first conductive layer may be polysilicon, the material of the first barrier layer may be titanium nitride, and the material of the second conductive layer may be tungsten. The metal ions in the second conductive layer can be prevented from diffusing into the first conductive layer and / or the first gate dielectric layer 2 through the first barrier layer, which helps to improve the device reliability.

[0083] In some embodiments of the present disclosure, the first gate dielectric layer 2 may surround the periphery of the first channel region 11 for one week, that is, the first gate dielectric layer 2 may cover the first channel region 11; the first word line structure 3 may surround the first gate dielectric layer 2 for one week, that is, the first word line structure 3 may cover the first gate dielectric layer 2, thereby forming a fully surrounding gate structure, which helps to enhance the gate control ability and reduce the channel leakage.

[0084] In some other embodiments of the present disclosure, the first gate dielectric layer 2 covers the surface of the first channel region 11 that is far from the second channel region 12 along the second direction Y and the surfaces of the two sidewalls of the first channel region 11 that are oppositely distributed along the third direction Z. The first word line structure 3 may cover the entire surface of the first gate dielectric layer 2, thereby forming a fin field effect transistor structure with strong gate control ability.

[0085] The second gate dielectric layer 4 covers at least a part of the surface of the second channel region 12. For example, the second gate dielectric layer 4 may cover at least the surface of the second channel region 12 that is far from the first channel region 11 along the second direction Y. The second gate dielectric layer 4 may be strip-shaped and may extend along the first direction X. The material of the second gate dielectric layer 4 may be silicon oxide. The second gate dielectric layer 4 may be formed on the surface of the second channel region 12 by chemical vapor deposition, physical vapor deposition, atomic layer deposition, or in-situ steam oxidation, etc. Of course, the second gate dielectric layer 4 may also be formed by other methods, and the formation method of the second gate dielectric layer 4 is not particularly limited herein.

[0086] The second word line structure 5 may cover the surface of the second gate dielectric layer 4. The second word line structure 5 may be strip-shaped and may extend along the first direction X. For example, the second word line structure 5 may cover the entire surface of the second gate dielectric layer 4. The second word line structure 5 may jointly form a transistor structure with the second gate dielectric layer 4, the second channel region 12, the second drain region 15, and the source region 13. It should be noted that the transistor structure formed by the first gate dielectric layer 2, the first channel region 11, the first drain region 14, and the source region 13 and the transistor structure formed by the second gate dielectric layer 4, the second channel region 12, the second drain region 15, and the source region 13 share the same source region 13, which helps to reduce the wiring density, save area, and reduce the parasitic coupling effect.

[0087] In some embodiments of the present disclosure, the second word line structure 5 may include a third conductive layer, a second barrier layer, and a fourth conductive layer that are sequentially distributed along the second direction Y. Among them, the third conductive layer may cover the surface of the second gate dielectric layer 4, the second barrier layer is located between the third conductive layer and the fourth conductive layer, the material of the third conductive layer may be polysilicon, the material of the second barrier layer may be titanium nitride, and the material of the fourth conductive layer may be tungsten. The second barrier layer can prevent metal ions in the fourth conductive layer from diffusing into the third conductive layer and / or the second gate dielectric layer 4, which helps to further improve the device reliability.

[0088] In some embodiments of the present disclosure, as Figure 4 shown, the second gate dielectric layer 4 may surround the periphery of the second channel region 12 for one week, that is, the second gate dielectric layer 4 may cover the second channel region 12 therein; the second word line structure 5 may surround the second gate dielectric layer 4 for one week, that is, the second word line structure 5 may cover the second gate dielectric layer 4 therein, thereby forming a fully surrounding gate structure, which helps to enhance the gate control ability and reduce channel leakage.

[0089] In some other embodiments of the present disclosure, as Figure 5 shown, the second gate dielectric layer 4 covers the surface of the second channel region 12 that is far from the first channel region 11 along the second direction Y and the surfaces of the two sidewalls that are oppositely distributed along the third direction Z in the second channel region 12. The second word line structure 5 may cover the entire surface of the second gate dielectric layer 4, thereby forming a fin field effect transistor structure with a relatively strong gate control ability.

[0090] In an exemplary embodiment of the present disclosure, the material of the first channel region 11 may be different from the material of the second channel region 12. For example, the material of the first channel region 11 may be a material with a relatively low electron mobility. For example, it may be a metal oxide with a relatively large bandgap. Specifically, the material of the first channel region 11 may include at least one of indium gallium zinc oxide, indium gallium oxide, or indium zinc oxide, which helps to reduce leakage. The material of the second channel region 12 may be a material with a relatively high electron mobility to facilitate the improvement of the signal transmission speed. For example, the material of the second channel region 12 may include at least one of indium tin oxide, polysilicon, silicon, or germanium silicon. It should be noted that at this time, the transistor composed of the first channel region 11, the first drain region 14, the source region 13, the first gate dielectric layer 2, and the first word line structure 3 may be used as a read transistor, and the transistor composed of the second channel region 12, the second drain region 15, the source region 13, the second gate dielectric layer 4, and the second word line structure 5 may be used as a write transistor.

[0091] The bit line structure 6 can be electrically connected to the source region 13. For example, the bit line structure 6 can be located on the surface of the source region 13 that is away from the first drain region 14 and the second drain region 15 along the first direction X. The bit line structure 6 can be formed on the surface of the source region 13 by means such as chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the bit line structure 6 can also be formed by other means, and no special limitation is made on the formation method of the bit line structure 6 herein. Alternatively, at least part of the region of the bit line structure 6 can be embedded in the source region 13. In some embodiments of the present disclosure, the bit line structure 6 can be strip-shaped, and the bit line structure 6 can be distributed in parallel with the insulating layer 10 and / or the ground electrode 20. For example, the bit line structure 6 can extend along the third direction Z.

[0092] It should be noted that when two transistors share the same source region 13, the two transistors can also share the same bit line structure 6, which helps to reduce the wiring density, save area, reduce the size of the bit line structure, and reduce the parasitic coupling effect.

[0093] In the second direction Y, the common electrode 7 can be located between the first channel region 11 and the second channel region 12. For example, the common electrode 7 can be located within a similar rectangular ring structure surrounded by the first channel region 11, the second channel region 12, the first drain region 14, the second drain region 15, the source region 13, and the insulating layer 10. It should be noted that there are gaps between the common electrode 7 and the first channel region 11, the second channel region 12, the first drain region 14, the second drain region 15, the source region 13, and the insulating layer 10. The material of the common electrode 7 can be polysilicon and / or tungsten, etc. In some embodiments of the present disclosure, the common electrode 7 can be strip-shaped and can extend along the third direction Z, and its cross-section can be rectangular, circular, elliptical, polygonal, or irregularly shaped, and no special limitation is made herein.

[0094] The dielectric layer 8 can at least cover the surface of the common electrode 7. For example, the dielectric layer 8 can at least adhere to the outer periphery of the common electrode 7 for one week. The material of the dielectric layer 8 can be a high-k material. For example, it can be alumina, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide, or a mixture thereof. Of course, it can also be other high-k materials, which are not listed one by one herein.

[0095] The conductive contact layer 9 may cover the surface of the dielectric layer 8 and may be electrically connected to the second drain region 15. For example, the conductive contact layer 9 may be located between the common electrode 7 and the first channel region 11. For example, the conductive contact layer 9 may cover the surface of the dielectric layer 8 close to the first channel region 11 in the second direction Y, and the surface of the dielectric layer 8 close to the first drain region 14 and the second drain region 15 in the first direction X. Alternatively, the conductive contact layer 9 may be located between the common electrode 7 and the second channel region 12. For example, the conductive contact layer 9 may cover the surface of the dielectric layer 8 close to the second channel region 12 in the second direction Y, and the surface of the dielectric layer 8 close to the first drain region 14 and the second drain region 15 in the first direction X. It should be noted that when an insulating layer 10 is provided between the first drain region 14 and the second drain region 15, a partial region of the conductive contact layer 9 may be located between the common electrode 7 and the insulating layer 10.

[0096] In an exemplary embodiment of the present disclosure, when the conductive contact layer 9 is located between the common electrode 7 and the first channel region 11, a partial region of the dielectric layer 8 may also be located between the conductive contact layer 9, the first drain region 14, the first channel region 11, and the source region 13.

[0097] In an exemplary embodiment of the present disclosure, when the conductive contact layer 9 is located between the common electrode 7 and the second channel region 12, a partial region of the dielectric layer 8 may also be located between the conductive contact layer 9, the second drain region 15, the second channel region 12, and the source region 13.

[0098] The common electrode 7, the dielectric layer 8, and the conductive contact layer 9 in the embodiments of the present disclosure may jointly form a structure similar to a capacitor, which can be used to store charges; this structure can be read and written through current. Compared with the traditional capacitor structure, it is not sensitive to various parasitic effects, the leakage phenomenon is significantly weakened, the data retention time is longer, the refresh frequency can be reduced, the power consumption can be reduced, the structure reliability is strong, and it is convenient for 3D stacking.

[0099] The embodiments of the present disclosure further include a method for forming a semiconductor structure. Figure 6 The flowchart showing the method for forming the semiconductor structure of the present disclosure is as Figure 6 shown. The forming method includes steps S110 - step S190, where:

[0100] Step S110: Form an active layer, where the active layer includes a first channel region, a second channel region, a source region, a first drain region, and a second drain region. The first channel region and the second channel region both extend along a first direction, and the first channel region and the second channel region are spaced apart along a second direction; the first direction intersects the second direction; the first drain region is connected to one end of the first channel region, and the second drain region is connected to the end of the second channel region close to the first drain region; the source region is connected between the end of the first channel region far from the first drain region along the first direction and the end of the second channel region far from the second drain region along the first direction, and the first drain region and the second drain region are insulated from each other.

[0101] Step S120: Form a first gate dielectric layer that at least covers a partial surface of the first channel region.

[0102] Step S130: Form a first word line structure that covers the first gate dielectric layer and extends along the first direction.

[0103] Step S140: Form a second gate dielectric layer that at least covers a partial surface of the second channel region.

[0104] Step S150: Form a second word line structure that covers the second gate dielectric layer and extends along the first direction.

[0105] Step S160: Form a bit line structure, and the bit line structure is electrically connected to the source region.

[0106] Step S170: Form a common electrode, and in the second direction, the common electrode is located between the first channel region and the second channel region.

[0107] Step S180: Form a dielectric layer that at least coats the outer periphery of the common electrode.

[0108] Step S190: Form a conductive contact layer that covers the surface of the dielectric layer, and the conductive contact layer is electrically connected to the second drain region.

[0109] In an exemplary embodiment of the present disclosure, the material of the first channel region 11 may be different from the material of the second channel region 12. For example, the material of the first channel region 11 may be a material with a lower electron mobility. For example, it may be a metal oxide with a larger bandgap. Specifically, the material of the first channel region 11 may include at least one of indium gallium zinc oxide, indium gallium oxide, or indium zinc oxide, which helps to reduce leakage current. The material of the second channel region 12 may be a material with a higher electron mobility to facilitate the improvement of signal transmission speed. For example, the material of the second channel region 12 may include at least one of indium tin oxide, polysilicon, silicon, or silicon germanium.

[0110] In some embodiments of the present disclosure, the forming method of the present disclosure may further include:

[0111] Step S200, forming an insulating layer between the first drain region and the second drain region.

[0112] The material of the insulating layer 10 may be silicon nitride. The insulating layer 10 may be strip-shaped and may extend in the third direction Z. The first channel region 11, the second channel region 12, the first drain region 14, the second drain region 15, the source region 13, and the insulating layer 10 may enclose a ring structure similar to a rectangle.

[0113] For the forming method of the semiconductor structure of the present disclosure, on the one hand, the common electrode 7, the dielectric layer 8, and the conductive contact layer 9 may jointly form a structure similar to a capacitor, which can be used to store charges; this structure can be read and written through current. Compared with the traditional capacitor structure, this structure is insensitive to various parasitic effects, the leakage phenomenon is significantly weakened, the data retention time is longer, and the refresh frequency can be reduced, reducing power consumption. The structure has strong reliability and is convenient for 3D stacking. On the other hand, the active layer 1, the first gate dielectric layer 2, the first word line structure 3, the second gate dielectric layer 4, and the second word line structure 5 jointly form a dual-transistor structure, which can effectively improve the transistor distribution density, and adjacent transistors can share the source region 13 and the bit line structure 6, which helps to reduce the wiring density, save area and reduce the parasitic coupling effect; in addition, since the source region 13, the first drain region 14, and the second drain region 15 are not collinear with the first word line structure 3 and / or the second word line structure 5, the parasitic coupling effect can be further reduced while facilitating wiring, thereby improving the device reliability.

[0114] The specific details of the forming method of the semiconductor structure of the present disclosure have been described in detail in the corresponding embodiments of the semiconductor structure. Therefore, they will not be repeated here.

[0115] It should be noted that although the steps of the forming method of the semiconductor structure in the present disclosure are described in a specific order in the drawings, this does not require or imply that these steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0116] Embodiments of the present disclosure also provide a memory 100, such as Figure 7 and Figure 8As shown, the memory 100 includes a plurality of semiconductor structures in any of the above embodiments. The number of the semiconductor structures is plural, and the plurality of semiconductor structures form a plurality of semiconductor groups spaced apart along a first direction X. Each semiconductor group includes a plurality of semiconductor structures stacked along a third direction Z; each semiconductor structure in the same semiconductor group shares a bit line structure 6, and two adjacent semiconductor structures in different semiconductor groups along the first direction X share a first gate dielectric layer 2, a second gate dielectric layer 4, a first word line structure 3, and a second word line structure 5.

[0117] In the memory 100 of the present disclosure, since the source region 13, the first drain region 14, and the second drain region 15 are all non - collinear with the first word line structure 3 and / or the second word line structure 5, and each semiconductor structure in the same semiconductor group shares the bit line structure 6 in the third direction Z, and two adjacent semiconductor structures in different semiconductor groups along the first direction X share the first gate dielectric layer 2, the second gate dielectric layer 4, the first word line structure 3, and the second word line structure 5, it is convenient to realize the 3D stacking of the first word line structure 3 and / or the second word line structure 5 and the bit line structure 6. With this design, the height of a single - layer transistor in the third direction Z will not be increased, which is more conducive to 3D stacking, and the manufacturing process is relatively simple and the manufacturing cost is relatively low.

[0118] It should be noted that when the semiconductor structure further includes an insulating layer 10, each semiconductor structure in the same semiconductor group may share the same insulating layer 10; when the semiconductor structure further includes a grounding electrode 20, each semiconductor structure in the same semiconductor group may share the same grounding electrode 20.

[0119] In an exemplary embodiment of the present disclosure, please continue to refer to Figure 8 As shown, the memory of the present disclosure may further include an insulating protection layer 30. The insulating protection layer 30 can fill the remaining voids within the semiconductor group and the voids between adjacent semiconductor groups, and can insulate and protect each part in the memory through the insulating protection layer 30 to prevent short - circuit or coupling between each structure, which helps to further improve the device reliability.

[0120] Those skilled in the art will readily conceive of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known common knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and the embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the appended claims.

Claims

1. A semiconductor structure, characterized in that, comprising: An active layer, including a first channel region, a second channel region, a source region, a first drain region, and a second drain region. The first channel region and the second channel region both extend along a first direction, and the first channel region and the second channel region are spaced apart along a second direction; the first direction intersects the second direction; the first drain region is connected to one end of the first channel region, and the second drain region is connected to the end of the second channel region close to the first drain region; the source region is connected between the end of the first channel region far from the first drain region along the first direction and the end of the second channel region far from the second drain region along the first direction, and the first drain region and the second drain region are insulated from each other; A first gate dielectric layer, covering at least a part of the surface of the first channel region; A first word line structure, covering the first gate dielectric layer and extending along the first direction; A second gate dielectric layer, covering at least a part of the surface of the second channel region; A second word line structure, covering the second gate dielectric layer and extending along the first direction; A bit line structure, electrically connected to the source region; A common electrode, in the second direction, the common electrode is located between the first channel region and the second channel region; A dielectric layer, covering at least the outer periphery of the common electrode; A conductive contact layer, covering the surface of the dielectric layer and electrically connected to the second drain region.

2. The semiconductor structure according to claim 1, characterized in that, The conductive contact layer is located between the common electrode and the first channel region; or, the conductive contact layer is located between the common electrode and the second channel region.

3. The semiconductor structure according to claim 2, characterized in that, When the conductive contact layer is located between the common electrode and the first channel region, the dielectric layer is also located between the conductive contact layer and the first drain region, the first channel region, and the source region; when the conductive contact layer is located between the common electrode and the second channel region, the dielectric layer is also located between the conductive contact layer and the second drain region, the second channel region, and the source region.

4. The semiconductor structure according to claim 1, characterized in that, The material of the dielectric layer is a high-k material.

5. The semiconductor structure according to claim 1, characterized in that, The first gate dielectric layer surrounds the first channel region for one week, and the first word line structure surrounds the first gate dielectric layer for one week; And / or, the second gate dielectric layer surrounds the second channel region for one week, and the second word line structure surrounds the second gate dielectric layer for one week.

6. The semiconductor structure according to claim 1, characterized in that, The first gate dielectric layer covers the surface of the first channel region far from the second channel region and the surfaces of the two sidewalls of the first channel region facing each other along a third direction, and the third direction is perpendicular to the first direction and the second direction; And / or, the second gate dielectric layer covers the surface of the second channel region far from the first channel region and the surfaces of two sidewalls that are oppositely distributed along the third direction in the second channel region.

7. The semiconductor structure according to any one of claims 1-6, wherein, the materials of the first channel region and the second channel region are different.

8. The semiconductor structure according to claim 7, wherein, the material of the first channel region includes at least one of indium gallium zinc oxide, indium gallium oxide, or indium zinc oxide.

9. The semiconductor structure according to claim 7, wherein, the material of the second channel region includes at least one of indium tin oxide, polysilicon, single crystal silicon, or silicon germanium.

10. The semiconductor structure according to any one of claims 1-6, wherein, the semiconductor structure further includes: an insulating layer located between the first drain region and the second drain region.

11. The semiconductor structure according to any one of claims 1-6, wherein, the semiconductor structure further includes a ground electrode, and the ground electrode is electrically connected to the first drain region to ground the first drain region.

12. A memory, wherein, it includes a plurality of semiconductor structures according to any one of claims 1-11. The number of the semiconductor structures is multiple, and the multiple semiconductor structures form multiple semiconductor groups that are spaced apart along the first direction. Each semiconductor group includes a plurality of the semiconductor structures that are stacked along the third direction; each of the semiconductor structures in the same semiconductor group shares the bit line structure, and two adjacent semiconductor structures along the first direction in different semiconductor groups share the first gate dielectric layer, the second gate dielectric layer, the first word line structure, and the second word line structure.

13. A method for forming a semiconductor structure, wherein, it includes: forming an active layer, the active layer includes a first channel region, a second channel region, a source region, a first drain region, and a second drain region. Both the first channel region and the second channel region extend along the first direction, and the first channel region and the second channel region are spaced apart along the second direction; the first direction intersects with the second direction; the first drain region is connected to one end of the first channel region, and the second drain region is connected to the end of the second channel region close to the first drain region; the source region is connected between the end of the first channel region far from the first drain region along the first direction and the end of the second channel region far from the second drain region along the first direction, and the first drain region and the second drain region are insulated from each other; forming a first gate dielectric layer that covers at least a part of the surface of the first channel region; forming a first word line structure that covers the first gate dielectric layer and extends along the first direction; forming a second gate dielectric layer that covers at least a part of the surface of the second channel region; forming a second word line structure that covers the second gate dielectric layer and extends along the first direction; forming a bit line structure, and the bit line structure is electrically connected to the source region; Form a common electrode, which is located between the first channel region and the second channel region in the second direction; Form a dielectric layer that at least coats the outer periphery of the common electrode; Form a conductive contact layer covering the surface of the dielectric layer, and the conductive contact layer is electrically connected to the second drain region.

14. The forming method according to claim 13, wherein, the materials of the first channel region and the second channel region are different.

15. The forming method according to claim 13 or 14, wherein, the forming method further includes: Form an insulating layer between the first drain region and the second drain region.

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