Semiconductor device and manufacturing method thereof

Abstract

The invention discloses a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate, a plurality of bit lines, bit line gap walls and at least one filling layer. The plurality of bit lines extend along a first direction and are arranged on the substrate at intervals. The bit lines comprise at least one first bit line and a plurality of second bit lines, and the at least one first bit line is arranged on one side of the plurality of second bit lines. The bit line gap walls are arranged on the side walls of the second bit lines and the at least one first bit line. The at least one fill layer extends along the first direction and is disposed within the at least one first bit line, wherein the fill layer includes a material at least partially identical to the bit line spacer. Therefore, through the arrangement of the filling layer, the structural integrity of each second bit line in the unit region can be effectively maintained, so that the operation performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a semiconductor device having a bit line structure and a manufacturing method thereof. Background Art

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For a dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitive structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally speaking, a dynamic random access memory with a recessed gate structure is formed by aggregating a large number of memory cells to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the memory cell density in the array region must be continuously increased, resulting in an increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technologies or structures need to be further improved to effectively improve the performance and reliability of related memory devices. Summary of the Invention

[0003] One object of the present invention is to provide a semiconductor device. By additionally providing a filling portion in the bit line in the peripheral region, it helps to maintain the structural integrity of each bit line provided in the cell region. Thus, the semiconductor device of the present invention has a more optimized component structure and performance, thereby improving the operation performance of the semiconductor device.

[0004] One object of the present invention is to provide a manufacturing method of a semiconductor device. A filling portion is additionally formed in the bit line in the peripheral region to help maintain the structural integrity of each bit line formed in the cell region. Moreover, the formation of the filling portion can be integrated with the formation method of the bit line spacer of the semiconductor device. Thus, the manufacturing method of the present invention can manufacture a semiconductor device with an optimized component structure and performance without increasing the operation steps.

[0005] To achieve the above object, an embodiment of the present invention provides a semiconductor device, including a substrate, a plurality of bit lines, bit line spacer walls, and at least one filling layer. The plurality of bit lines extend in a first direction and are disposed on the substrate at intervals. The bit lines include at least one first bit line and a plurality of second bit lines, and the at least one first bit line is disposed on one side of the plurality of second bit lines. The bit line spacer walls are disposed on sidewalls of each of the second bit lines and the at least one first bit line. The at least one filling layer extends along the first direction and is disposed within the at least one first bit line, wherein the at least one filling layer includes a material that is at least partially the same as that of the bit line spacer walls.

[0006] To achieve the above object, an embodiment of the present invention provides a semiconductor device, including a substrate, a plurality of bit lines, and a filling layer. The plurality of bit lines are disposed on the substrate separately from each other. The bit lines include at least one first bit line and a plurality of second bit lines, the at least one first bit line is disposed on one side of the second bit lines and includes a conductive layer. A filling portion is disposed within the at least one first bit line, and a bottom surface of the filling portion is higher than a bottom surface of the conductive layer.

[0007] To achieve the above object, an embodiment of the present invention provides a method for manufacturing a semiconductor device, including the following steps. Provide a substrate, and form a plurality of bit lines on the substrate, extending in a first direction at intervals, the bit lines including at least one first bit line and a plurality of second bit lines, the at least one first bit line being disposed on one side of the second bit lines. Form bit line spacer walls on sidewalls of each of the second bit lines and the at least one first bit line. Form at least one filling layer extending in the first direction within the at least one bit line, wherein the at least one filling layer includes a material that is at least partially the same as that of the bit line spacer walls. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a deeper understanding of embodiments of the present invention and are incorporated into this specification as a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all the drawings are schematic diagrams, for the purpose of illustration and drawing convenience, and the relative sizes and proportions are adjusted. The same reference signs represent corresponding or similar features in different embodiments.

[0009] FIGS. 1 to 5 illustrate schematic diagrams of a semiconductor device according to a first embodiment of the present invention, wherein:

[0010] FIG. 1 is a top view schematic diagram of the semiconductor device;

[0011] FIG. 2 is a cross-sectional schematic diagram taken along section line A-A' in FIG. 1;

[0012] FIG. 3 is a cross-sectional schematic diagram taken along section line B-B' in FIG. 1;

[0013] FIG. 4 is a schematic cross-sectional view taken along the section line C-C' in FIG. 1;

[0014] FIG. 5 is a schematic cross-sectional view taken along the section line D-D' in FIG. 1;

[0015] FIG. 6 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention;

[0016] FIGS. 7 to 12 illustrate schematic diagrams of a method for manufacturing a semiconductor device according to a preferred embodiment of the present invention, wherein:

[0017] FIG. 7 is a top view schematic diagram of a semiconductor device after forming a mask layer structure;

[0018] FIG. 8 is a schematic cross-sectional view taken along the section line A-A' in FIG. 7;

[0019] FIG. 9 is a top view schematic diagram of a semiconductor device after performing a patterning process;

[0020] FIG. 10 is a schematic cross-sectional view taken along the section line A-A' in FIG. 9;

[0021] FIG. 11 is a top view schematic diagram of a semiconductor device after forming bit lines and trenches;

[0022] FIG. 12 is a schematic cross-sectional view taken along the section line A-A' in FIG. 11.

[0023] Description of reference numerals:

[0024] 10 Semiconductor device

[0025] 100 Substrate

[0026] 102 Unit area

[0027] 104 Peripheral area

[0028] 106 Active region

[0029] 108 Shallow trench isolation

[0030] 110 Dielectric layer

[0031] 112 Silicon oxide layer

[0032] 114 Silicon nitride layer

[0033] 116 Silicon oxide layer

[0034] 120 Bit line

[0035] 122 First bit line

[0036] 124 Second bit line

[0037] 124c Bit line contact

[0038] 126 Conductive layer

[0039] 126b Bottom surface

[0040] 128 Covering layer

[0041] 128t Top surface

[0042] 130 Filling layer

[0043] 132, 134, 136, 138 Filling parts

[0044] 142 Semiconductor layer

[0045] 144 Barrier layer

[0046] 146 Metal layer

[0047] 150 Bit line spacer

[0048] 210 Dielectric material layer

[0049] 212 Silicon oxide material layer

[0050] 214 Silicon nitride material layer

[0051] 216 Silicon oxide material layer

[0052] 226 Conductive material layer

[0053] 228 Covering material layer

[0054] 230 Groove

[0055] 232, 234, 236, 238 Groove parts

[0056] 242 Semiconductor material layer

[0057] 244 Barrier material layer

[0058] 246 Metal material layer

[0059] 252 Insulating layer

[0060] 254 Sacrificial layer

[0061] 256 Silicon-containing hard mask layer

[0062] 258 Patterned mask layer

[0063] 260 Photoresist layer

[0064] BS1, BS2, BS3, BS4 Lowest bottom surface

[0065] D1 First direction

[0066] D2 Second direction

[0067] D3 Third direction

[0068] Lengths of L1, L2, L3, and L4

[0069] OP Contact opening

[0070] RE Groove

[0071] Groove portions of RP1, RP2, RP3, and RP4

[0072] Lengths of W1 and W2

[0073] Y Vertical direction Detailed implementation manner

[0074] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the following specifically lists the preferred embodiments of the present invention and, in conjunction with the accompanying drawings, details the composition and the effects to be achieved of the present invention. It should be noted that, without departing from the spirit of the present invention, the features in several different embodiments can be replaced, recombined, and mixed to complete other embodiments.

[0075] Please refer to FIGS. 1 to 5, which show a schematic diagram of a semiconductor device 10 according to a first embodiment of the present invention. Among them, FIG. 1 is a top view schematic diagram of the semiconductor device 10, and FIGS. 2, 3, 4, and 5 are cross-sectional schematic diagrams of the semiconductor device 10, respectively. First, as shown in FIG. 1, the semiconductor device 10 includes a substrate 100, a plurality of bit lines 120, bit line spacer walls 150, and at least one filling layer 130. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, etc., and a unit region 102 with a relatively high component integration degree and a peripheral region 104 with a relatively low component integration degree are simultaneously defined on the substrate 100. Specifically, the bit lines 120 are arranged to extend along a first direction D1 at intervals on the substrate 100, and specifically include at least one first bit line 122 and a plurality of second bit lines 124. Among them, at least one first bit line 122 is arranged, for example, on one side of all the second bit lines 124 in a second direction D2 perpendicular to the first direction D1. The bit line spacer walls 150 are disposed around the side walls of each second bit line 124 and the side walls of at least one first bit line 122.

[0076] It should be specifically noted that at least one filling layer 130 also extends along the first direction D1 and is disposed within at least one first bit line 122. Among them, at least one filling layer 130, for example, includes at least partially the same material as the bit line spacer 150, such as insulating materials or combinations thereof including silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, etc., but not limited thereto. In one embodiment, at least one filling layer 130 and the bit line spacer 150, for example, respectively include the single-layer structure shown in FIG. 1 and include the same insulating material. Or, in another embodiment, the bit line spacer 150, for example, includes a composite layer structure (not shown), and at least one filling layer 130 includes a single-layer structure whose material is the same as a part of the bit line spacer 150, or includes a composite layer structure (not shown) whose material is the same as a part of the bit line spacer 150, or includes a composite layer structure (not shown) whose material is exactly the same as the bit line spacer 150, etc., but not limited thereto. With this arrangement, at least one first bit line 122 disposed within the peripheral region 104 can effectively maintain the structural integrity of each second bit line 124 disposed within the cell region 102 by means of at least one filling layer 130 additionally disposed therein, which is beneficial to improving the component structure and performance of the semiconductor device 10, thereby improving the operation performance of the semiconductor device 10.

[0077] Specifically, at least one filling layer 130 further includes a plurality of filling portions 132, 134, 136, 138, which respectively extend along a first direction D1 and have different lengths L1, L2, L3, L4 in a second direction D2. In one embodiment, at least two of the filling portions 132, 134, 138 are arranged to be connected to each other, for example, or at least two of the filling portions 136, 132 may also be selectively arranged to be separated from each other, but not limited thereto. As shown in FIG. 1 again, at least one shallow trench isolation (STI) 108 is further provided in the unit area 102 and the peripheral area 104 of the substrate 100, and a plurality of active areas (AA) 106 are defined in the substrate 100. Among them, each active area 106 extends along a third direction D3 that is not perpendicular to the first direction D1 and the second direction D2, so that each second bit line 124 provided in the unit area 102 simultaneously straddles at least two corresponding active areas 106 and directly contacts the corresponding active areas 106 through bit line contacts (BLCs) 124c provided therebelow. In this way, each second bit line 124 can be electrically connected to a transistor component (not shown) provided in the substrate 100 to receive or send signals from the transistor component. In one embodiment, each second bit line 124 has the same length W2 as each other in the second direction D2, while the length W1 of at least one first bit line 122 in the second direction D2 is greater than the length W2, preferably about 2 to 10 times the length W2, as shown in FIG. 1, but not limited thereto.

[0078] On the other hand, referring to FIGS. 2 to 5, from the perspective of the cross-sectional schematic diagram, a plurality of shallow trench isolations 108 and active areas 106 are alternately arranged in the substrate 100, and at least one first bit line 122 and each second bit line 124 are arranged to be separated from each other on the substrate 100, wherein at least one first bit line 122 simultaneously straddles at least two active areas 106 provided in the peripheral area 104 in the second direction D2, for example. Bit line spacer walls 150 are provided on the sidewalls of each second bit line 124 and at least one first bit line 122. It should be noted that at least one filling layer 130 is provided in at least one first bit line 122 to help maintain the structural integrity of the adjacent second bit lines 124. Among them, the bottom surfaces BS1, BS2, BS3, BS4 of the respective filling portions 132, 134, 136, 138 of at least one filling layer 130 are not coplanar with each other. That is to say, any two of the filling portions 132 / 134, 136 / 138 may have different extension depths in at least one first bit line 122.

[0079] Specifically, at least one first bit line 122 and each second bit line 124 each include, for example, a conductive layer 126 disposed on the dielectric layer 110, and the conductive layer 126 further includes a semiconductor layer 142 (for example, including semiconductor materials such as doped polysilicon, doped silicon, doped silicon phosphorus, etc.), a barrier layer 144 (for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), and a metal layer 146 (for example, including low-resistance metal materials such as tungsten, aluminum, or copper) stacked in sequence in the vertical direction Y. The bottom surfaces BS1, BS2, BS4 of the respective filling portions 132, 134, 138 are, for example, respectively located in the semiconductor layer 142, the metal layer 146, or the barrier layer 144 of at least one first bit line 122, as shown in FIGS. 2 to 5 respectively, but not limited thereto. A cover layer 128 is also disposed on at least one first bit line 122 and each second bit line 124, and the bottom surface BS3 of the filling portion 136 may also be located in the cover layer 128. In one embodiment, a cover layer 128 is also disposed on at least one first bit line 122 and each second bit line 124, for example, including insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride, and the dielectric layer 110 includes, for example, a silicon oxide layer 112, a silicon nitride layer 114, and a silicon oxide layer 116 stacked in sequence and having an oxide-nitride-oxide (ONO) structure.

[0080] As shown in FIGS. 2 to 5 again, the bottommost surface BS1 of the filling portion 132 is, for example, between the top surface and the bottom surface of the semiconductor layer 142 of at least one first bit line 122 in the vertical direction Y, the bottommost surface BS2 of the filling portion 134 is, for example, between the top surface and the bottom surface of the metal layer 146 of at least one first bit line 122 in the vertical direction Y, the bottommost surface BS3 of the filling portion 136 is, for example, between the top surface and the bottom surface of the covering layer 128 above at least one first bit line 122 in the vertical direction Y, and the bottommost surface BS4 of the filling portion 138 is, for example, between the top surface and the bottom surface of the barrier layer 144 of at least one first bit line 122 in the vertical direction Y, but not limited thereto. Preferably, the bottommost surfaces BS1, BS2, BS3, and BS4 of the respective filling portions 132, 134, 136, and 138 are all higher than the bottom surface 126b of the conductive layer 126 (i.e., the bottom surface of the semiconductor layer 142) and all lower than the top surface 128t of the covering layer 128. Moreover, the filling portions 132, 134, and 138 having relatively longer lengths L1, L2, and L4 in the second direction D2 have relatively deeper depths in at least one first bit line 122 in the vertical direction Y, as shown in FIGS. 1 to 5, but not limited thereto. That is to say, when the length L1 of the filling portion 132 is greater than the lengths L2, L3, and L4 of the filling portions 134, 136, and 138, the depth of the filling portion 132 in at least one first bit line 122 is also greater than the depths of the filling portions 134, 136, and 138 in at least one first bit line 122 or in the covering layer 128. In addition, when the length L4 of the filling portion 138 is greater than the length L2 of the filling portion 134 and the length L2 of the filling portion 134 is greater than the length L3 of the filling portion 136, the depth of the filling portion 138 in at least one first bit line 122 is greater than the depth of the filling portion 134 in at least one first bit line 122, and the depth of the filling portion 134 in at least one first bit line 122 is greater than the depth of the filling portion 136 in the covering layer 128.

[0081] In addition, it should be noted that at least one filling layer 130 includes at least part of the same insulating material as the bit line spacer 150 and can be fabricated by the same process. For example, in one embodiment, the bit line spacer 150 includes, for example, a single layer of insulating material as shown in FIG. 1, and at least one filling layer 130 also includes a single layer of insulating material. In another embodiment, the bit line spacer 150 can alternatively include a composite layer (not shown) of insulating material, such as a first spacer (not shown), a second spacer (not shown), and a third spacer (not shown) that are sequentially arranged and made of different stacked materials. And at least one filling layer 130 can include a single layer of insulating material identical to the first spacer, or a composite layer of insulating material identical to the first spacer and the second spacer, or a composite layer of insulating material identical to the first spacer, the second spacer, and the third spacer according to the actual device requirements, but not limited thereto.

[0082] Although other components are not specifically depicted in the drawings of this embodiment, those skilled in the art should readily understand that the semiconductor device 10 of this embodiment may further include various required components according to the actual device requirements. For example, as shown in FIG. 6, in a preferred embodiment, the semiconductor device 10 may further include a plurality of word line structures (not shown) disposed in the cell region 102, a plurality of storage node plugs 160, a plurality of storage node pads 162, and a capacitor structure 170 (including a plurality of bottom electrodes 172, a capacitor dielectric layer 174, and a top electrode layer 176 disposed in sequence). The word line structures extend in a second direction D2 perpendicular to the second bit line 124 in a mutually separated manner, and each storage node plug 160 is alternately disposed with each second bit line 124 in the second direction D2 and physically contacts the respective storage node pads 162 disposed above, so as to be electrically connected to the corresponding active region 106 and the respective bottom electrodes 172 disposed above each storage node pad 162 at the same time, and receive and transfer voltage signals from the substrate 100 (the source or drain of the transistor component in the substrate 100). Thus, the semiconductor device 10 and the capacitor structure 170 disposed above it can jointly form a dynamic random access memory (DRAM) device, and the transistor component in the substrate 100 and the capacitor structure 170 jointly constitute the smallest memory cell in the dynamic random access memory array to receive voltage information from the bit line 120 and the word line structure.

[0083] In the semiconductor device 10 according to the first embodiment of the present invention, a filling portion 130 is additionally provided in the first bit line 122 in the peripheral region 104. For example, it has a single-layer or composite-layer insulating material, and further includes filling portions 132, 134, 136, 138 that are partially connected or partially separated, thereby maintaining the structural integrity of the second bit line 124 adjacent to the first bit line 122. Thus, the semiconductor device 10 of this embodiment can have an overall optimized component structure and performance, thereby improving its operating performance.

[0084] To enable those of ordinary skill in the art to which the present invention pertains to easily understand the semiconductor device 10 of the present invention, the manufacturing method of the semiconductor device 10 of the present invention will be further described below.

[0085] Please refer to FIGS. 7 to 12, which are schematic diagrams of a method for manufacturing a semiconductor device 10 in a preferred embodiment of the present invention. First, as shown in FIGS. 7 and 8, a substrate 100 is provided, on which a cell region 102 with a relatively high component integration degree and a peripheral region 104 with a relatively low component integration degree are simultaneously defined. Moreover, at least one shallow trench isolation 108 is formed on the substrate 100, and a plurality of active regions 106 are defined within the cell region 102 of the substrate 100. Specifically, each of the active regions 106, for example, extends in parallel and separately towards the third direction D3, and as a whole, presents a specific arrangement, such as the array arrangement shown in FIG. 7 (array arrangement), etc., but is not limited thereto. In one embodiment, the formation of the active regions 106 and at least one shallow trench isolation 108 can be achieved by, but is not limited to, the following manufacturing processes. First, a bulk substrate (bulk silicon, not shown) is provided, and a mask layer (not shown) is formed on the bulk substrate. The mask layer includes a pattern that can be used to define the active regions 106. By partially covering the bulk substrate with the mask layer and performing an etching manufacturing process, a part of the bulk substrate is removed to form the active regions 106 and at least one shallow trench (shallow trench, not shown) surrounding the active regions 106. Then, an insulating material (not shown), such as silicon oxide, silicon nitride, or silicon oxynitride, etc., is filled into the shallow trench to form the substrate 100 and at least one shallow trench isolation 108. In addition, in another embodiment, a self-aligned double patterning (SADP) manufacturing process, or a self-aligned reverse patterning (SARP) manufacturing process can also be used to form a patterned mask (not shown) that defines the active regions 106, but is not limited thereto.

[0086] Next, a dielectric material layer 210 is formed on the substrate 100, and a patterning process is performed through a mask layer (not shown), partially removing the dielectric material layer 210 and the active region 106 therebelow to form a plurality of contact openings OP. In one embodiment, the dielectric material layer 210 includes, for example, a silicon oxide material layer 212, a silicon nitride material layer 214, and a silicon oxide material layer 216 stacked in sequence, as shown in FIG. 8, but not limited thereto. Then, a deposition process is performed to sequentially form a conductive material layer 226 and a capping material layer 228 (for example, including insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride) on the dielectric material layer 210. Among them, the conductive material layer 226 at least includes a semiconductor material layer 242 (for example, including semiconductor materials such as doped polysilicon, doped silicon, or doped silicon phosphorus), a barrier material layer 244 (for example, including conductive barrier materials such as titanium and / or titanium nitride, tantalum and / or tantalum oxide), and a metal material layer 246 (for example, including low-resistance metal materials such as tungsten, aluminum, or copper) as shown in FIG. 8, and a part of the semiconductor material layer 242 further fills into the contact openings OP. And then, a mask structure and a photoresist layer 260 are continuously formed above the capping material layer 228. The mask structure includes, for example, an insulating layer 252, a sacrificial layer 254 (for example, including an organic dielectric material), a silicon-containing hard mask layer 256 (SHB), and a patterned mask layer 258 stacked in sequence.

[0087] Specifically, the patterned mask layer 258 has a plurality of mask patterns for defining the bit line structure, which are formed separately in the cell region 102 and the peripheral region 104, and the photoresist layer 260 is also formed above the silicon-containing hard mask layer 256, entirely located in the peripheral region 104, covering a part of the mask patterns and exposing another part of the mask patterns. It should be noted that in this embodiment, by adjusting the layout of the photoresist layer 260, the photoresist layer 260 covers at least one mask pattern in the peripheral region 104 and exposes another mask pattern in the peripheral region 104. In this way, each mask pattern formed in the cell region 102 can have a complete pattern and layout, and will not be blocked by the photoresist layer 260 to present an incomplete pattern or contour, as shown in FIGS. 7 and 8, but not limited thereto. Among them, the photoresist layer 260 is directly adjacent to a mask pattern on the patterned mask layer 258, such that a sidewall of the photoresist layer 260 is flush with a sidewall of another mask pattern, as shown in FIGS. 7 and 8, but not limited thereto.

[0088] As shown in FIGS. 9 and 10, a patterning process is performed simultaneously through a mask pattern of another part of the patterned mask layer 258 and the photoresist layer 260, and the silicon-containing hard mask layer 256, the sacrificial layer 254, and the insulating layer 252 are partially removed to transfer the patterns of the patterned mask layer 258 and the photoresist layer 260 into the underlying silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252, and then the patterned mask layer 258 and the photoresist layer 260 are completely removed. After the patterning process is performed, the mask pattern of the patterned mask layer 258 formed in the cell region 102 is completely transferred into the underlying silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252, such that the patterned silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252 have a relatively small length W2 in the second direction D2, while the mask pattern of the patterned mask layer 258 formed in the peripheral region 104 and the pattern of the photoresist layer 260 are simultaneously transferred into the underlying silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252, such that the patterned silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252 have a relatively large length W1 in the second direction D2, as shown in FIG. 9, but not limited thereto.

[0089] It should be noted that since the formation of the photoresist layer 260 shown in FIGS. 7 and 8 is adjacent to the mask pattern of the patterned mask layer 258 in the peripheral region 104, when the patterning process is performed through the mask pattern of the patterned mask layer 258 and the photoresist layer 260 formed in the peripheral region 104, the etchant acting on the peripheral region 104 will not affect the etching of the silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252 in the cell region 102, such that the patterned silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252 in the cell region 102 can have a complete pattern and profile corresponding to the mask pattern of the patterned mask layer 258. In addition, it should be noted that when the patterning process is performed through the mask pattern of the patterned mask layer 258 and the photoresist layer 260 formed in the peripheral region 104, by controlling etching conditions such as the etching selectivity and etching direction of the etchant acting on the peripheral region 104, the silicon-containing hard mask layer 256 located below the junction of the photoresist layer 260 and a mask pattern of the patterned mask layer 258 can be further etched to form at least one trench RE in the peripheral region 104.

[0090] Specifically, at least one groove RE is formed, for example, along the side of the photoresist layer 260 in the first direction D1. By controlling etching conditions such as etching selectivity and etching direction, the at least one groove RE formed can have different lengths L1, L2, L3, L4 in the second direction D2 and / or different depths in the vertical direction Y. In one embodiment, the at least one groove RE has, for example, a plurality of groove portions RP1, RP2, RP3, RP4 with different lengths L1, L2, L3, L4 in a top view as shown in FIG. 9, and the groove portions RP1, RP2, RP3, RP4 can be selectively connected to or separated from each other. Preferably, the groove portion RP1 with a relatively larger length L1 also has a relatively larger depth in the vertical direction Y, such that the groove portion RP1 of the at least one groove RE can extend from the silicon-containing hard mask layer 256 into a part of the sacrificial layer 254 in the vertical direction Y, as shown in FIG. 10, while the groove portions RP2, RP3, RP4 with relatively smaller lengths L2, L3, L4 have relatively shallower depths in the vertical direction Y (not shown), but this is not limiting.

[0091] As shown in FIGS. 11 and 12, an etching process is performed by using the patterned silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252 as etching masks to partially remove the covering material layer 228, metal material layer 246, barrier material layer 244, semiconductor material layer 242, silicon oxide material layer 212, silicon nitride material layer 214, and silicon oxide material layer 216 formed under the insulating layer 252, and to pattern the covering material layer 228, metal material layer 246, barrier material layer 244, and semiconductor material layer 242 shown in FIG. 10 into a plurality of second bit lines 124 (including a semiconductor layer 142, a barrier layer 144, and a metal layer 146 stacked in sequence) covering layers 128 formed in the cell region 102 and at least one first bit line 122 (including a semiconductor layer 142, a barrier layer 144, and a metal layer 146 stacked in sequence) covering layer 128 formed in the peripheral region 104, and to pattern the silicon oxide material layer 212, silicon nitride material layer 214, and silicon oxide material layer 216 shown in FIG. 10 into a dielectric layer 110 (including a silicon oxide layer 112, a silicon nitride layer 114, and a silicon oxide layer 116 stacked in sequence). At the same time, after the second bit lines 124 are formed, the semiconductor material layer 242 filled in the contact opening OP simultaneously forms bit line contacts 124c located under each of the second bit lines 124.

[0092] Moreover, when the etching process is performed, the pattern of at least one trench RE is also simultaneously transferred to at least one first bit line 122, and at least one trench 230 is formed on at least one first bit line 122. Specifically, at least one trench 230 is formed along the extending direction of at least one first bit line 122 (i.e., the first direction D1), and has a pattern corresponding to at least one trench RE shown in FIG. 9, as shown in FIG. 11, but not limited thereto. In one embodiment, the at least one trench 230 formed, for example, has a plurality of groove portions 232, 234, 236, 238 with different lengths L1, L2, L3, L4 in the second direction D2, and each of the groove portions 232, 234, 236, 238 is, for example, partially connected to each other and partially separated from each other, but not limited thereto. For example, the groove portions 232, 234, 238 are connected to each other, and the groove portion 236 is separated from the groove portions 232, 234, 238, as shown in FIG. 11.

[0093] Preferably, the groove portion 232 with a relatively larger length L1 has a relatively larger depth in the vertical direction Y than the groove portions 234, 236, 238 with relatively smaller lengths L2, L3, L4. Thus, the groove portion 232, for example, extends from the cover layer 128 into the semiconductor layer 142 of at least a part of at least one first bit line 122. That is to say, the bottom surface BS1 of the groove portion 232 is, for example, formed in the semiconductor layer 142 of at least one first bit line 122, as shown in FIG. 12, but not limited thereto. On the other hand, the bottom surfaces (not shown) of the groove portions 234, 236, 238 are, for example, respectively formed at positions higher than the bottom surface BS1 of the groove portion 232, such as in the metal layer 146 or the barrier layer 144 of at least one first bit line 122, or in the cover layer 128 above at least one first bit line 122, but not limited thereto. Subsequently, at least one deposition process and at least one re-etching process are performed to form the bit line sidewall spacers 150 as shown in FIGS. 1 to 5 on the sidewalls of at least one first bit line 122 and each second bit line 124, and to form at least one filling layer 130 as shown in FIGS. 1 to 5 in at least one trench 230.

[0094] In one embodiment, the manufacturing process of at least one filling layer 130 is, for example but not limited to, the same manufacturing process as that of the bit line spacer 150, such that at least one filling layer 130 may include a film layer structure or an insulating material that is at least partially the same as that of the bit line spacer 150. For example, when the bit line spacer 150 includes a single layer of insulating material as shown in FIG. 1, the at least one filling layer 130 manufactured together also includes a single layer of insulating material; and when the bit line spacer 150 includes an insulating material of a composite layer (not shown), such as a first spacer (not shown), a second spacer (not shown), and a third spacer (not shown) that are sequentially arranged and have different stacked materials, the at least one filling layer 130 manufactured together may be selected to include a single layer of insulating material that is the same as the first spacer, or a composite layer of insulating materials that are the same as the first spacer and the second spacer, or a composite layer of insulating materials that are the same as the first spacer, the second spacer, and the third spacer according to the actual operating conditions of the deposition process, but not limited thereto. In addition, although the bottom surfaces of the grooves 234, 236, and 238 are not specifically shown in the drawings of this embodiment, those skilled in the art should be able to easily infer the formation positions of the bottom surfaces of the respective grooves 234, 236, and 238 from the bottom surfaces BS2, BS3, and BS4 of the filling portions 134, 136, and 138 shown in FIGS. 2 to 5 above.

[0095] Thus, the manufacturing method of the semiconductor device 10 in this embodiment is completed. Although the manufacturing steps of the remaining components are not shown in the drawings of this embodiment, those skilled in the art should be able to easily understand that the manufacturing method of the semiconductor device 10 in this embodiment may further include forming a plurality of word line structures (not shown) in the unit region 102 before forming the silicon oxide material layer 212, and forming a plurality of storage node plugs (not shown) in the unit region 102 after forming the bit line spacer 150 and at least one filling layer 130. In this operation, the formed word line structures extend separately in a second direction D2 perpendicular to the second bit line 124, and the formed storage node plugs are alternately arranged with the respective second bit lines 124 in the second direction D2 to be electrically connected to the corresponding active regions 106 and receive and transfer voltage signals from the substrate 100 (the source or drain of the transistor component in the substrate 100). Thus, the semiconductor device 10 formed by the manufacturing method in this embodiment and the capacitor structure (not shown) formed subsequently thereon can jointly form a dynamic random access memory device, and the transistor component formed in the substrate 100 and the capacitor structure jointly constitute the smallest storage unit in the dynamic random access memory array to receive voltage information from the bit line 120 and the word line structure.

[0096] According to the manufacturing method of the semiconductor device 10 according to an embodiment of the present invention, when manufacturing the bit line 120, by adjusting the layout of the photoresist layer 260, the formation position of the photoresist layer 260 is just adjacent to a mask pattern on the patterned mask layer 258, avoiding the etchant acting in the peripheral region 104 from affecting the manufacturing of the second bit line 124 in the cell region 102 due to the guidance of the photoresist layer 260, and at the same time forming a trench 230 on the first bit line 122 in the peripheral region 104. Moreover, when further forming the bit line spacer 150 subsequently, a single-layer or composite-layer insulating material is filled in the trench 230 at the same time to form a filling portion 130 located in the first bit line 122. Thus, without additionally increasing the photomask or the manufacturing process, a filling portion 130 is additionally formed on the first bit line 122 adjacent to the second bit line 124 in the cell region 102, which can effectively improve the structural integrity of the adjacent second bit line 124, enabling the formed semiconductor device 10 to have an overall optimized component structure and performance, thereby improving its operating performance.

[0097] Those of ordinary skill in the art to which the present invention pertains should easily understand that, to meet the requirements of actual products, there may be other aspects of the semiconductor device of the present invention and are not limited to the foregoing. For example, although a filling layer 130 (i.e., forming a trench 230 on the first bit line 122) is set on the first bit line 122 as an embodiment in the foregoing embodiment of the present invention, its specific setting and specific operation are not limited thereto. In other embodiments, multiple trenches (not shown) may also be selectively formed on the first bit line 122, and when forming the bit line spacer 150 subsequently, a single-layer or composite-layer insulating material is filled in the trenches at the same time to form multiple filling layers (not shown), wherein each filling layer may respectively have a uniform length (not shown) in the second direction D2 and a uniform depth (not shown) in the vertical direction Y, or respectively have lengths L1, L2, L3, L4 in the second direction D2 and / or have multiple filling portions 132, 134, 136, 138 with different depths in the vertical direction Y as shown in FIG. 1 above, but not limited thereto. Thus, the semiconductor devices formed in other embodiments may also have an overall optimized component structure and performance, thereby improving their operating performance.

[0098] The above are only the preferred embodiments of the present invention and are not used to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of bit lines extending along a first direction and arranged on the substrate at intervals, the bit lines comprising at least one first bit line and a plurality of second bit lines, the at least one first bit line being arranged on one side of the second bit line; A bit line spacer is disposed on the sidewalls of each of the second bit lines and the at least one first bit line; and At least one filling layer extends along the first direction and is disposed in the at least one first bit line, wherein the at least one filling layer comprises at least a portion of the same material as the bit line spacer.

2. The semiconductor device according to claim 1, wherein: The at least one filling layer further includes a plurality of filling parts, and the filling parts have different lengths in a second direction perpendicular to the first direction.

3. The semiconductor device according to claim 2, characterized in that At least two of the filling parts are arranged in connection with each other.

4. The semiconductor device according to claim 2, characterized in that At least two of the filling parts are arranged to be separated from each other.

5. The semiconductor device according to claim 2, wherein: The bottommost surfaces of at least two of the filling portions are not coplanar.

6. A semiconductor device, characterized in that: include: substrate; a plurality of bit lines, arranged on the substrate in a mutually separated manner, the bit lines comprising at least one first bit line and a plurality of second bit lines, the at least one first bit line being arranged on one side of the second bit line and comprising at least a conductive layer; and The filling portion is arranged in the at least one first bit line, and the bottom surface of the filling portion is higher than the bottom surface of the conductive layer.

7. The semiconductor device according to claim 6, characterized in that The conductive layer at least includes a semiconductor layer, a barrier layer, and a metal layer stacked in sequence.

8. The semiconductor device according to claim 7, characterized in that The bottommost surface of the filling portion is located between the top surface and the bottom surface of the metal layer in a vertical direction.

9. The semiconductor device according to claim 7, characterized in that The bottommost surface of the filling portion is located between the top surface and the bottom surface of the barrier layer in a vertical direction.

10. The semiconductor device according to claim 7, wherein: The bottommost surface of the filling portion is located between the top surface and the bottom surface of the semiconductor layer in a vertical direction.

11. The semiconductor device according to claim 6, characterized in that Also includes: A covering layer is disposed on the conductive layer of each of the bit lines, wherein the bottommost surface of the filling portion is located between a top surface and a bottom surface of the covering layer in a vertical direction.

12. The semiconductor device according to claim 6, wherein: Also includes: The bit line spacers are arranged on the sidewalls of each of the second bit lines and the at least one first bit line, wherein the filling portion comprises at least a portion of the same material as the bit line spacers.

13. The semiconductor device according to claim 6, characterized in that Also includes: A plurality of active regions and a plurality of shallow trench isolations are alternately arranged in the substrate, wherein the at least one first bit line simultaneously crosses over at least two of the active regions in a horizontal direction.

14. A method for manufacturing a semiconductor device, characterized in that: include: providing a substrate; A plurality of bit lines are formed on the substrate, extending along a first direction at intervals from each other, the bit lines comprising at least one first bit line and a plurality of second bit lines, the at least one first bit line being arranged on one side of the second bit line; forming a bit line spacer on the sidewalls of each of the second bit lines and the at least one first bit line; as well as At least one filling layer extending in the first direction is formed in the at least one bit line, wherein the at least one filling layer comprises at least a portion of the same material as the bit line spacer.

15. The method for manufacturing a semiconductor device according to claim 14, characterized in that: Forming the bit line and the at least one filling layer further includes: Performing a deposition process to sequentially form a conductive material layer, a covering material layer and a sacrificial layer on the substrate; forming a plurality of mask patterns on the sacrificial layer; forming a photoresist layer on the sacrificial layer, covering the mask pattern of the first portion and exposing the mask pattern of the second portion, wherein a sidewall of the photoresist layer is aligned with a sidewall of the mask pattern of the second portion; Performing a patterning process through the photoresist layer and the mask pattern of the second portion to simultaneously form the at least one first bit line and the second bit line; forming at least one trench extending in the first direction in the at least one first bit line; and After removing the photoresist layer, the mask pattern and the sacrificial layer, the bit line spacer is formed and the at least one filling layer is formed in the at least one trench.

16. The method for manufacturing a semiconductor device according to claim 15, characterized in that: The at least one groove further includes a plurality of groove portions, and the groove portions have different lengths in a second direction perpendicular to the first direction.

17. The method for manufacturing a semiconductor device according to claim 16, wherein: At least two of the grooves are connected to each other.

18. The method for manufacturing a semiconductor device according to claim 16, wherein: At least two of the grooves are spaced apart from each other.

19. The method for manufacturing a semiconductor device according to claim 16, wherein: At least two of the groove portions have different depths in a vertical direction perpendicular to the substrate.

20. The method for manufacturing a semiconductor device according to claim 19, characterized in that: The bottommost surface of at least one of the grooves is located in the conductive material layer or in the covering material layer.

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