Semiconductor device and method of manufacturing the same

Abstract

The present application discloses a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, a plurality of bit lines, a bit line spacer, and at least one fill layer. The plurality of bit lines extends along a first direction and is spaced apart on the substrate. The bit lines include at least one first bit line and a plurality of second bit lines, and the at least one first bit line is disposed on one side of the plurality of second bit lines. The bit line spacer is disposed on sidewalls of each of the second bit lines and the at least one first bit line. The at least one fill layer extends along the first direction and is disposed within the at least one first bit line, and the fill layer includes a material at least partially identical to the bit line spacer. Thus, by disposing the fill layer, the structural integrity of each of the second bit lines within a cell region is effectively maintained, thereby improving the operational performance of the semiconductor device.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor device and a method of fabricating the same, and more particularly, to a semiconductor device having a bit line structure and a method of fabricating the same. BACKGROUND

[0002] With the trend of miniaturization of various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, because it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced dynamic random access memory with only a planar gate structure under the current mainstream development trend. Generally, dynamic random access memory with a recessed gate structure is formed by a large number of memory cells gathered to form an array region for storing information, and each memory cell can be composed of a transistor component and a capacitor component in series to receive voltage information from the word line (WL) and the bit line (BL). In response to product demand, the density of the memory cells in the array region must continue to be improved, resulting in increasing difficulty and complexity of related manufacturing processes and designs. Therefore, the existing technology or structure still needs to be further improved to effectively improve the performance and reliability of the related memory device. SUMMARY

[0003] One object of the present application is to provide a semiconductor device, by additionally providing a filling portion in the bit line in the peripheral region, which helps to maintain the structural integrity of each bit line provided in the cell region. Thus, the semiconductor device of the present application has an optimized component structure and performance, thereby improving the operating performance of the semiconductor device.

[0004] One object of the present application is to provide a method of fabricating a semiconductor device, by additionally forming a filling portion in the bit line in the peripheral region, which helps to maintain the structural integrity of each bit line formed in the cell region. Moreover, the formation of the filling portion can be integrated with the method of forming the bit line spacer of the semiconductor device, so that the fabrication method of the present application can fabricate a semiconductor device with an optimized component structure and performance without increasing the operating steps.

[0005] To achieve the above object, one embodiment of the present application provides a semiconductor device including a substrate, a plurality of bit lines, a bit line spacer, and at least one filling layer. The plurality of bit lines extend along a first direction and are disposed on the substrate with a space between each other. The bit lines include at least one first bit line and a plurality of second bit lines, and the at least one first bit line is disposed on a side of the plurality of second bit lines. The bit line spacer is disposed on a sidewall of each of the second bit lines and the at least one first bit line. The at least one filling layer extends along the first direction and is disposed in the at least one first bit line, wherein the at least one filling layer includes a material at least partially same as the bit line spacer.

[0006] To achieve the above object, one embodiment of the present application provides a semiconductor device including a substrate, a plurality of bit lines, and a filling layer. The plurality of bit lines are disposed on the substrate with a space between each other. The bit lines include at least one first bit line and a plurality of second bit lines, and the at least one first bit line is disposed on a side of the second bit lines and includes a conductive layer. A filling portion is disposed in the at least one first bit line, and a bottom surface of the filling portion is higher than a bottom surface of the conductive layer.

[0007] To achieve the above object, one embodiment of the present application provides a method for manufacturing a semiconductor device including the following steps. A substrate is provided, and a plurality of bit lines are formed on the substrate, extending along a first direction with a space between each other. The bit lines include at least one first bit line and a plurality of second bit lines, and the at least one first bit line is disposed on a side of the second bit lines. A bit line spacer is formed on a sidewall of each of the second bit lines and the at least one first bit line. At least one filling layer extending along the first direction is formed in the at least one bit line, wherein the at least one filling layer includes a material at least partially same as the bit line spacer. BRIEF DESCRIPTION OF DRAWINGS

[0008] The accompanying drawings are included to provide a further understanding of embodiments of the application and are incorporated in and constitute a part of this specification. The drawings illustrate the principles of some embodiments. It is to be noted that all the drawings are schematic and not drawn to scale for the purpose of convenience and illustration. The same reference numerals in different drawings represent corresponding or similar features.

[0009] Figures 1 to 5 A schematic view of a semiconductor device according to a first embodiment of the present application is shown, wherein:

[0010] Figure 1 A top view of a semiconductor device is shown;

[0011] Figure 2 A cross-sectional view taken along the section line A-A’ in FIG. 4 is shown; Figure 1 A cross-sectional view taken along the section line A-A’ in FIG. 4 is shown;

[0012] Figure 3 Fig. 2 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line B-B' of Fig. 1 ; Figure 1 Fig. 3 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line C-C' of Fig. 1 ;

[0013] Figure 4 Fig. 4 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line D-D' of Fig. 1 ; Figure 1 Fig. 5 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ;

[0014] Figure 5 Fig. 6 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ; Figure 1 Fig. 7 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ;

[0015] Figure 6 Fig. 8 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ;

[0016] Figures 7 to 12 Fig. 9 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ;

[0017] Figure 7 Fig. 10 is a schematic top view of a semiconductor device after forming a mask layer structure according to a preferred embodiment of the present application;

[0018] Figure 8 Fig. 11 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ; Figure 7

[0019] Figure 9 Fig. 12 is a schematic top view of a semiconductor device after performing a patterning process according to a preferred embodiment of the present application;

[0020] Figure 10 Fig. 13 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ; Figure 9

[0021] Figure 11 Fig. 14 is a schematic top view of a semiconductor device after forming bit lines and trenches according to a preferred embodiment of the present application;

[0022] Figure 12 Fig. 15 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ; Figure 11 Fig. 16 is a schematic cross-sectional view of a semiconductor device according to a preferred embodiment of the present application, taken along section line A-A' of Fig. 1 ;

[0023] Legend of reference signs:

[0024] 10 semiconductor device

[0025] 100 substrate

[0026] 102 cell region

[0027] 104 peripheral region

[0028] 106 active area

[0029] 108 shallow trench isolation

[0030] 110 dielectric layer ​​

[0031] 112 silicon oxide layer

[0032] 114 silicon nitride layer

[0033] 116 silicon oxide layer

[0034] 120 bit line

[0035] 122 first bit line

[0036] 124 second bit line

[0037] 124c bit line contact

[0038] 126 conductive layer

[0039] 126b bottom surface

[0040] 128 cap layer

[0041] 128t top surface

[0042] 130 fill layer

[0043] 132, 134, 136, 138 fill portions

[0044] 142 semiconductor layer

[0045] 144 barrier layer

[0046] 146 metal layer

[0047] 150 bit line spacer

[0048] 210 dielectric material layer

[0049] 212 silicon oxide material layer

[0050] 214 silicon nitride material layer

[0051] 216 silicon oxide material layer

[0052] 226 conductive material layer

[0053] 228 cap material layer

[0054] 230 trench

[0055] 232, 234, 236, 238 trench portions

[0056] 242 semiconductor material layer

[0057] 244 barrier material layer

[0058] 246 metal material layer

[0059] 252 insulating layer

[0060] 254 Sacrificial layer

[0061] 256 Silicon-containing hard mask layer

[0062] 258 Patterned mask layer

[0063] 260 Photoresist layer

[0064] BS1, BS2, BS3, BS4 Bottom surface

[0065] D1 First direction

[0066] D2 Second direction

[0067] D3 Third direction

[0068] L1, L2, L3, L4 Length

[0069] OP Contact opening

[0070] RE Trench

[0071] RP1, RP2, RP3, RP4 Recess

[0072] W1, W2 Width

[0073] Y Vertical direction DETAILED DESCRIPTION

[0074] In order to enable persons having ordinary skill in the art to which this invention pertains to further understand the invention, preferred embodiments of the invention are listed below, and the constitution and effects of the invention are described in detail with reference to the accompanying drawings. It should be understood that the following embodiments can be replaced, reorganized, mixed to complete other embodiments without departing from the spirit of the invention.

[0075] Referring to FIG. 1, Figures 1 to 5 is a schematic view of a semiconductor device 10 according to a first embodiment of the present invention, wherein Figure 1 is a top view of the semiconductor device 10, Figure 2 , Figure 3 , Figure 4 and Figure 5 are cross-sectional views of the semiconductor device 10, respectively. First, as shown in FIG. 1, Figure 1As shown, the semiconductor device 10 includes a substrate 100, multiple bit lines 120, bit line spacers 150, and at least one filler layer 130. The substrate 100 includes, for example, a silicon substrate, a silicon-containing substrate, or a silicon-on-insulator (SOI) substrate, and simultaneously defines a cell region 102 with relatively high component density and a peripheral region 104 with relatively low component density on the substrate 100. Specifically, the bit lines 120 are spaced apart and extend along a first direction D1 on the substrate 100, and specifically include at least one first bit line 122 and multiple second bit lines 124. At least one first bit line 122 is disposed on one side of all the second bit lines 124, for example, in a second direction D2 perpendicular to the first direction D1. The bit line spacers 150 are disposed around the sidewalls of each second bit line 124 and the sidewalls of at least one first bit line 122.

[0076] It should be specifically noted that at least one filler layer 130 also extends along the first direction D1 and is disposed within at least one bit line 122. The at least one filler layer 130 may include, for example, at least partially the same material as the bit line spacer 150, such as insulating materials like silicon oxide, silicon oxynitride, silicon nitride, silicon carbonitride, or combinations thereof, but is not limited thereto. In one embodiment, the at least one filler layer 130 and the bit line spacer 150 may respectively include, for example, the following materials: Figure 1 The single-layer structure shown includes the same insulating material. Alternatively, in another embodiment, the bit line spacer 150 may include, for example, a composite layer structure (not shown), and at least one filler layer 130 may include a single-layer structure of the bit line spacer 150 with the same material as a portion thereof, or a composite layer structure of the bit line spacer 150 with the same material as a portion thereof (not shown), or a composite layer structure of the bit line spacer 150 with the same material as a portion thereof (not shown), etc., but is not limited thereto. Under this configuration, at least one first bit line 122 disposed within the peripheral region 104 can effectively maintain the structural integrity of each second bit line 124 disposed within the cell region 102 by means of at least one filler layer 130 additionally disposed therein, which is beneficial to improving the component structure and performance of the semiconductor device 10, thereby improving the operational performance of the semiconductor device 10.

[0077] In detail, at least one filling layer 130 further includes a plurality of filling portions 132, 134, 136, and 138, which extend along a first direction D1 and have different lengths L1, L2, L3, and L4 in a second direction D2. In one embodiment, at least two filling portions 132, 134, and 138 are arranged connected to each other, for example, or at least two filling portions 136 and 132 may be arranged separately from each other, but this is not a limitation. For example... Figure 1As shown, at least one shallow trench isolation (STI) 108 is disposed within the cell region 102 and the peripheral region 104 of the substrate 100, and a plurality of active areas (AAs) 106 are defined in the substrate 100. Each of the active areas 106, for example, extends along a third direction D3 that is not perpendicular to the first direction D1 and the second direction D2, such that each of the second bit lines 124 disposed in the cell region 102 simultaneously spans at least two corresponding active areas 106 and directly contacts the corresponding active areas 106 through the underlying bit line contacts (BLCs) 124c. In this way, each of the second bit lines 124 can be electrically connected to a transistor component (not shown) disposed in the substrate 100 to receive or send a signal from the transistor component. In an embodiment, each of the second bit lines 124, for example, has a same length W2 as each other in the second direction D2, and the length W1 of the at least one first bit line 122 in the second direction D2 is greater than the length W2, preferably about 2 to 10 times the length W2, such as Figure 1 As shown, but not limited thereto.

[0078] On the other hand, referring to Figures 2 to 5 As shown in the cross-sectional view, the plurality of STIs 108 and the plurality of active areas 106 are alternately disposed in the substrate 100, and the at least one first bit line 122 and the plurality of second bit lines 124 are disposed in the substrate 100, for example, separated from each other, wherein the at least one first bit line 122, for example, simultaneously spans at least two active areas 106 disposed in the peripheral region 104 in the second direction D2. The bit line spacers 150 are disposed on the sidewalls of the plurality of second bit lines 124 and the at least one first bit line 122. It is noted that the at least one filling layer 130 is disposed in the at least one first bit line 122 to help maintain the structural integrity of the adjacent second bit lines 124. Each of the filling portions 132, 134, 136, 138 of the at least one filling layer 130 has a bottom surface BS1, BS2, BS3, BS4 that is not coplanar with each other. That is, any two filling portions 132 / 134, 136 / 138 in the at least one first bit line 122 can have different extension depths.

[0079] In detail, the at least one first bit line 122 and each second bit line 124, for example, includes a conductive layer 126 disposed on the dielectric layer 110, and the conductive layer 126 further includes a semiconductor layer 142 (e.g., containing a doped polysilicon, a doped silicon, a doped silicon phosphor, or the like semiconductor material), a barrier layer 144 (e.g., containing titanium and / or titanium nitride, tantalum and / or tantalum oxide, or the like conductive barrier material), and a metal layer 146 (e.g., containing tungsten, aluminum, or copper, or the like low-resistance metal material) stacked in sequence in the vertical direction Y. The bottommost surfaces BS1, BS2, BS4 of the respective fill portions 132, 134, 138 are, for example, located within the semiconductor layer 142, the metal layer 146, or the barrier layer 144 of the at least one first bit line 122, respectively, as shown in Figures 2 to 5 but not limited thereto. The at least one first bit line 122 and each second bit line 124 further includes a cap layer 128 disposed thereon, and the bottommost surface BS3 of the fill portion 136 can also be located within the cap layer 128. In an embodiment, the at least one first bit line 122 and each second bit line 124 further includes a cap layer 128, for example, containing a silicon nitride, a silicon carbon nitride, or a silicon oxynitride, or the like insulating material, and the dielectric layer 110, for example, includes a silicon oxide layer 112, a silicon nitride layer 114, and a silicon oxide layer 116 stacked in sequence to have an oxide-nitride-oxide (ONO) structure.

[0080] As shown in Figures 2 to 5 for example, is bounded between a top surface and a bottom surface of the semiconductor layer 142 of the at least one first bit line 122 in the vertical direction Y, the bottommost surface BS2 of the fill portion 134 is bounded between a top surface and a bottom surface of the metal layer 146 of the at least one first bit line 122 in the vertical direction Y, the bottommost surface BS3 of the fill portion 136 is bounded between a top surface and a bottom surface of the cap layer 128 above the at least one first bit line 122 in the vertical direction Y, and the bottommost surface BS4 of the fill portion 138 is bounded between a top surface and a bottom surface of the barrier layer 144 of the at least one first bit line 122 in the vertical direction Y, but not limited thereto. Preferably, the bottommost surfaces BS1, BS2, BS3, BS4 of the respective fill portions 132, 134, 136, 138 are all higher than a bottom surface 126b (i.e., a bottom surface of the semiconductor layer 142) of the conductive layer 126 and all lower than a top surface 128t of the cap layer 128, and the fill portions 132, 134, 138 having a relatively longer length L1, L2, L4 in the second direction D2 have a relatively deeper depth within the at least one first bit line 122 in the vertical direction Y, as shown in Figures 1 to 5As shown, but not limited to. That is, when the length L1 of the filling portion 132 is greater than the lengths L2, L3, and L4 of the filling portions 134, 136, and 138, the depth of the filling portion 132 within at least one first line 122 is also greater than the depth of the filling portions 134, 136, and 138 within at least one first line 122 or within the cover layer 128; furthermore, when the length L4 of the filling portion 138 is greater than the length L2 of the filling portion 134, and the length L2 of the filling portion 134 is greater than the length L3 of the filling portion 136, the depth of the filling portion 138 within at least one first line 122 is greater than the depth of the filling portion 134 within at least one first line 122, and the depth of the filling portion 134 within at least one first line 122 is greater than the depth of the filling portion 136 within the cover layer 128.

[0081] Furthermore, it should be noted that at least one filler layer 130 includes at least a portion of the insulating material identical to that of the bit line spacer wall 150, and can be fabricated together using the same process. For example, in one embodiment, the bit line spacer wall 150 includes, for example, an insulating material such as... Figure 1 The single-layer insulating material shown is used, and at least one filler layer 130 also includes a single-layer insulating material; in another embodiment, the bit line gap wall 150 may also be selected to include a composite layer (not shown) of insulating material, such as a first gap wall (not shown), a second gap wall (not shown), and a third gap wall (not shown) arranged sequentially and with different stacked materials, etc., and the at least one filler layer 130 may include a single-layer insulating material that is the same as the first gap wall, or a composite layer insulating material that is the same as the first gap wall and the second gap wall, or a composite layer insulating material that is the same as the first gap wall, the second gap wall, and the third gap wall, depending on the actual device requirements, but is not limited thereto.

[0082] Although other components are not specifically depicted in the accompanying drawings of this embodiment, those skilled in the art should readily understand that the semiconductor device 10 of this embodiment may also include various required components depending on actual device requirements. For example, such as Figure 6As shown, in a preferred embodiment, the semiconductor device 10 can further include a plurality of word line structures (not shown), a plurality of storage node plugs 160, a plurality of storage node pads 162 and a capacitor structure 170 (including a plurality of bottom electrode layers 172, a capacitor dielectric layer 174 and a top electrode layer 176 disposed in sequence) disposed within the cell region 102. The word line structures extend in a second direction D2 perpendicular to the second bit lines 124, while each of the storage node plugs 160 is disposed in the second direction D2 alternately with each of the second bit lines 124 and physically contacts each of the storage node pads 162 disposed thereabove to be electrically connected to the corresponding active region 106 and each of the bottom electrode layers 172 disposed thereabove simultaneously to receive and transfer a voltage signal from the substrate 100 (a source or a drain of a transistor element within the substrate 100). Thus, the semiconductor device 10 and the capacitor structure 170 disposed thereabove can collectively constitute a dynamic random access memory (DRAM) device, and the transistor element within the substrate 100 and the capacitor structure 170 collectively constitute a minimum constituent memory cell in a dynamic random access memory array to receive voltage information from the bit lines 120 and the word line structures.

[0083] According to the semiconductor device 10 of the first embodiment of the present application, the filling portion 130, for example, having an insulating material of a single layer or a composite layer and further including the filling portions 132, 134, 136, 138 disposed partially in connection or partially in separation, is disposed within the first bit line 122 in the peripheral region 104 to maintain the structural integrity of the second bit line 124 disposed adjacent to the first bit line 122. Thus, the semiconductor device 10 of the present embodiment has an overall optimized component structure and performance to improve its operational performance.

[0084] To enable a person of ordinary skill in the art to which the semiconductor device 10 of the present application pertains to easily understand the semiconductor device 10 of the present application, the method for manufacturing the semiconductor device 10 of the present application will be further described below.

[0085] Referring to Figures 7 to 12 As shown, the method for manufacturing the semiconductor device 10 of a preferred embodiment of the present application is illustrated. First, as shown in FIG. 1A, a substrate 100 is provided. The substrate 100 can be a silicon substrate, for example. Figure 7 and Figure 8As shown, a substrate 100 is provided, on which a cell region 102 with relatively high component density and a peripheral region 104 with relatively low component density are defined simultaneously. At least one shallow trench isolation 108 is formed on the substrate 100, and a plurality of active regions 106 are defined within the cell region 102 of the substrate 100. Specifically, each active region 106 extends parallel to each other and spaced apart in a third direction D3, presenting a specific arrangement overall, for example... Figure 7 The array arrangement shown is an example, but not limited to it. In one embodiment, the active region 106 and at least one shallow trench isolation 108 can be formed by, but is not limited to, the following fabrication process. First, a bulk silicon substrate (not shown) is provided, a mask layer (not shown) is formed on the bulk substrate, the mask layer includes a pattern that can be used to define the active region 106, the bulk substrate is partially covered by the mask layer and an etching process is performed, the bulk substrate is partially removed to form the active region 106 and at least one shallow trench (not shown) surrounding the active region 106, and then an insulating material (not shown) such as silicon oxide, silicon nitride, or silicon oxynitride is filled into the shallow trench, thereby forming the substrate 100 and at least one shallow trench isolation 108. In another embodiment, a patterned mask (not shown) defining the active region 106 can be formed using a self-aligned double patterning (SADP) fabrication process or a self-aligned reverse patterning (SARP) fabrication process, but is not limited thereto.

[0086] Next, a dielectric material layer 210 is formed on the substrate 100, and a patterning process is performed through a mask layer (not shown) to partially remove the dielectric material layer 210 and the underlying active region 106 to form a plurality of contact openings OP. In one embodiment, the dielectric material layer 210 includes, for example, a silicon oxide material layer 212, a silicon nitride material layer 214, and a silicon oxide material layer 216 stacked in sequence, such as... Figure 8 As shown, but not limited to. Then, a deposition process is performed to sequentially form a conductive material layer 226 and a cover material layer 228 (e.g., including insulating materials such as silicon nitride, silicon carbonitride, or silicon oxynitride) on the dielectric material layer 210, wherein the conductive material layer 226 includes at least the following: Figure 8The semiconductor material layer 242 (e.g., containing a doped polysilicon, a doped silicon, a doped silicon phosphor, etc.), the barrier material layer 244 (e.g., containing a conductive barrier material such as titanium and / or titanium nitride, tantalum and / or tantalum oxide, etc.), and the metal material layer 246 (e.g., containing a low-resistance metal material such as tungsten, aluminum, or copper, etc.) are shown, and part of the semiconductor material layer 242 is further filled into the contact opening OP. And then, a mask structure and a photoresist layer 260 are formed successively over the covering material layer 228. The mask structure, for example, contains an insulating layer 252, a sacrificial layer 254 (e.g., containing an organic dielectric material), a silicon-containing hard mask (SHB) layer 256, and a patterned mask layer 258, which are sequentially stacked.

[0087] In detail, the patterned mask layer 258 has a plurality of mask patterns that can be used to define bit line structures, which are formed in the cell region 102 and the peripheral region 104, respectively, and the photoresist layer 260 is also formed over the silicon-containing hard mask layer 256, which is entirely located in the peripheral region 104, covers part of the mask patterns, and exposes another part of the mask patterns. It should be noted that, in this embodiment, the layout of the photoresist layer 260 is adjusted so that the photoresist layer 260 covers at least one mask pattern in the peripheral region 104 and exposes another mask pattern in the peripheral region 104, so that each mask pattern formed in the cell region 102 has a complete pattern and layout, and is not blocked by the photoresist layer 260 to present an incomplete pattern or profile, as shown, but not limited thereto. Figure 7 Figure 8 As shown, but not limited thereto, the photoresist layer 260 is directly adjacent to one mask pattern on the patterned mask layer 258, so that one sidewall of the photoresist layer 260 is cut to the other sidewall of the mask pattern, as shown, but not limited thereto. Figure 7 Figure 8 As shown, but not limited thereto, the photoresist layer 260 is directly adjacent to one mask pattern on the patterned mask layer 258, so that one sidewall of the photoresist layer 260 is cut to the other sidewall of the mask pattern, as shown, but not limited thereto.

[0088] As shown, but not limited thereto, the photoresist layer 260 is directly adjacent to one mask pattern on the patterned mask layer 258, so that one sidewall of the photoresist layer 260 is cut to the other sidewall of the mask pattern, as shown, but not limited thereto. Figure 9 Figure 10 ​​​As shown, a patterning process is performed simultaneously through another part of the patterned mask layer 258 and the photoresist layer 260, partially removing the silicon-containing hard mask layer 256, the sacrificial layer 254, and the insulating layer 252, so as to transfer the patterns of the patterned mask layer 258 and the photoresist layer 260 to the underlying silicon-containing hard mask layer 256, the sacrificial layer 254, and the insulating layer 252, and then completely removing the patterned mask layer 258 and the photoresist layer 260. After the patterning process is performed, the mask pattern of the patterned mask layer 258 formed in the unit region 102 is completely transferred to the underlying silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252, resulting in a relatively small length W2 of the patterned silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252 in the second direction D2. Meanwhile, the mask pattern of the patterned mask layer 258 formed in the peripheral region 104 is transferred simultaneously with the pattern of the photoresist layer 260 to the underlying silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252, resulting in a relatively large length W1 of the patterned silicon-containing hard mask layer 256, sacrificial layer 254, and insulating layer 252 in the second direction D2. Figure 9 As shown, but not limited to.

[0089] It should be noted that, due to Figure 7 and Figure 8 The photoresist layer 260 shown is formed by the mask pattern of the patterned mask layer 258 in the peripheral region 104. When the patterning process is performed by the mask pattern of the patterned mask layer 258 and the photoresist layer 260 formed in the peripheral region 104, the etchant acting in the peripheral region 104 will not affect the etching of the silicon-containing hard mask layer 256, the sacrificial layer 254 and the insulating layer 252 in the unit region 102, so that the patterned silicon-containing hard mask layer 256, the sacrificial layer 254 and the insulating layer 252 in the unit region 102 can have a complete pattern and outline corresponding to the mask pattern of the patterned mask layer 258. Furthermore, it should be noted that when a patterning process is performed using the mask pattern of the patterned mask layer 258 formed in the peripheral region 104 and the photoresist layer 260, by controlling the etching conditions such as the etch selection and etching direction of the etchant acting in the peripheral region 104, the silicon-containing hard mask layer 256 located below the junction of a mask pattern of the photoresist layer 260 and the patterned mask layer 258 can be further etched, thereby forming at least one trench RE in the peripheral region 104.

[0090] In detail, the at least one trench RE is formed, for example, along the side of the photoresist layer 260 in the first direction D1, and by controlling the etching selection, etching direction, and the like, the etching conditions are controlled so that the at least one trench RE formed in the second direction D2 can have different lengths L1, L2, L3, L4 and / or different depths in the vertical direction Y. In an embodiment, the at least one trench RE has, for example, a plurality of groove portions RP1, RP2, RP3, RP4 with different lengths L1, L2, L3, L4 in the top view as shown in Figure 9 , and the groove portions RP1, RP2, RP3, RP4 can be selected to be connected to each other or separated from each other. Preferably, the groove portion RP1 with a relatively large length L1 also has a relatively large depth in the vertical direction Y, so that the groove portion RP1 of the at least one trench RE can extend from the silicon-containing hard mask layer 256 to the sacrificial layer 254 in the vertical direction Y as shown in Figure 10 , and the groove portions RP2, RP3, RP4 with relatively small lengths L2, L3, L4 have relatively shallow depths in the vertical direction Y (not shown), but are not limited thereto.

[0091] As shown in Figure 11 and Figure 12 , by performing an etching process with the patterned silicon-containing hard mask layer 256, the sacrificial layer 254, and the insulating layer 252 as etching masks, the cover material layer 228, the metal material layer 246, the barrier material layer 244, the semiconductor material layer 242, the silicon oxide material layer 212, the silicon nitride material layer 214, and the silicon oxide material layer 216 formed under the insulating layer 252 are partially removed, and the cover material layer 228, the metal material layer 246, the barrier material layer 244, and the semiconductor material layer 242 are patterned into a plurality of second bit lines 124 (including the semiconductor layer 142, the barrier layer 144, and the metal layer 146 sequentially stacked) cover layers 128 formed in the cell region 102 and at least one first bit line 122 (including the semiconductor layer 142, the barrier layer 144, and the metal layer 146 sequentially stacked) cover layer 128 formed in the peripheral region 104 as shown in Figure 10 , and the silicon oxide material layer 212, the silicon nitride material layer 214, and the silicon oxide material layer 216 are patterned into the dielectric layer 110 (including the silicon oxide layer 112, the silicon nitride layer 114, and the silicon oxide layer 116 sequentially stacked) as shown in Figure 10 . At the same time, after the second bit lines 124 are formed, the semiconductor material layer 242 filling the contact opening OP is simultaneously formed into the bit line contact 124c located below each second bit line 124.

[0092] Furthermore, during the etching process, the pattern of at least one trench RE is simultaneously transferred to at least one first line 122, and at least one trench 230 is formed on the at least one first line 122. Specifically, the at least one trench 230 is formed along the extension direction of the at least one first line 122 (i.e., the first direction D1) and has a corresponding... Figure 9 The pattern shown has at least one groove RE, such as Figure 11 As shown, but not limited thereto. In one embodiment, the formed at least one trench 230 may have, for example, a plurality of trenches 232, 234, 236, 238 with different lengths L1, L2, L3, L4 in the second direction D2, and the trenches 232, 234, 236, 238 may be partially connected to each other and partially separated from each other, but not limited thereto. For example, the trenches 232, 234, 238 may be interconnected, while the trenches 236 and 232, 234, 238 may be separated from each other, such as... Figure 11 As shown.

[0093] Preferably, the trench 232 with a relatively larger length L1 has a relatively larger depth in the vertical direction Y compared to the trenches 234, 236, and 238 with relatively smaller lengths L2, L3, and L4. Thus, the trench 232 extends, for example, from the capping layer 128 into a portion of the semiconductor layer 142 containing at least one first line 122. That is, the bottom surface BS1 of the trench 232 is formed, for example, within the semiconductor layer 142 containing at least one first line 122. Figure 12 As shown, but not limited to. On the other hand, the bottom surfaces (not shown) of trenches 234, 236, and 238 are formed, for example, at a position higher than the bottom surface BS1 of trench 232, for example, within the metal layer 146 or barrier layer 144 of at least one first bit line 122, or within the capping layer 128 above at least one first bit line 122, but not limited to. Subsequently, at least one deposition process and at least one etching process are performed to form the aforementioned on the sidewalls of at least one first bit line 122 and each of the second bit lines 124. Figures 1 to 5 The bit line gap wall 150 shown is formed in at least one groove 230 as described above. Figures 1 to 5 At least one filling layer 130 is shown.

[0094] In one embodiment, the fabrication process of at least one filler layer 130 is, for example but not limited to, the same as that of the bit line spacer wall 150, such that the at least one filler layer 130 may include at least a portion of a film structure or insulating material identical to that of the bit line spacer wall 150. For example, when the bit line spacer wall 150 includes, as Figure 1The single-layered insulating material of the shown at least one fill layer 130 also includes a single-layered insulating material. When the bit line spacer 150 includes a composite-layered (not shown) insulating material, such as a first spacer (not shown), a second spacer (not shown), and a third spacer (not shown) sequentially arranged and stacked with different materials, the at least one fill layer 130 can include a single-layered insulating material identical to the first spacer, or a composite-layered insulating material identical to the first and second spacers, or a composite-layered insulating material identical to the first, second, and third spacers, according to the actual operation conditions of the deposition process, but not limited thereto. In addition, although the bottom surfaces of the trenches 234, 236, and 238 are not specifically shown in the drawings of the present embodiment, those skilled in the art can easily understand the formation positions of the bottom surfaces of the trenches 234, 236, and 238 from the above description of the formation of the fill portions 134, 136, and 138. Figures 2 to 5 The bottom surfaces BS2, BS3, and BS4 of the shown fill portions 134, 136, and 138 indicate the formation positions of the bottom surfaces of the respective trenches 234, 236, and 238.

[0095] Thus, the manufacturing method of the semiconductor device 10 in the present embodiment is completed. Although the manufacturing steps of the remaining components are not shown in the drawings of the present embodiment, those skilled in the art can easily understand that the manufacturing method of the semiconductor device 10 in the present embodiment can further include forming a plurality of word line structures (not shown) in the cell region 102 before forming the silicon oxide material layer 212, and forming a plurality of storage node plugs (not shown) in the cell region 102 after forming the bit line spacer 150 and the at least one fill layer 130. Under this operation, the formed word line structures extend in the second direction D2 perpendicular to the second bit line 124, and the formed storage node plugs are alternately arranged with the respective second bit lines 124 in the second direction D2 to electrically connect to the corresponding active regions 106 and receive and transmit voltage signals from the substrate 100 (the source or drain of the transistor components in the substrate 100). Thus, the semiconductor device 10 formed by the manufacturing method in the present embodiment and the subsequently formed capacitor structure (not shown) can collectively form a dynamic random access memory device, and the transistor components formed in the substrate 100 and the capacitor structure collectively constitute the smallest storage unit in the dynamic random access memory array to receive voltage information from the bit line 120 and the word line structure.

[0096] According to the method for manufacturing the semiconductor device 10, when the bit line 120 is manufactured, the layout of the photoresist layer 260 is adjusted so that the photoresist layer 260 is formed at a position adjacent to one mask pattern on the patterned mask layer 258, thereby avoiding the etchant in the peripheral region 104 from affecting the manufacturing of the second bit line 124 in the unit region 102 due to the guidance of the photoresist layer 260, and meanwhile forming the trench 230 on the first bit line 122 in the peripheral region 104. Furthermore, when the bit line spacer 150 is subsequently formed, the insulating material is filled into the trench 230 to form the filling part 130 on the first bit line 122. In this way, without adding extra masks or manufacturing processes, the filling part 130 is additionally formed on the first bit line 122 adjacent to the second bit line 124, which can effectively improve the structural integrity of the second bit line 124, so that the semiconductor device 10 has an overall optimized component structure and performance, thereby improving the operation performance.

[0097] Those skilled in the art of the present application should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device of the present application can also have other forms without being limited to the foregoing. For example, although the foregoing embodiments of the present application take the example of forming one filling layer 130 (i.e., forming one trench 230 on the first bit line 122) on the first bit line 122 as an implementation form, the specific arrangement and specific operation are not limited thereto. In other embodiments, a plurality of trenches (not shown) can also be formed on the first bit line 122, and when the bit line spacer 150 is subsequently formed, the insulating material is filled into the trenches to form a plurality of filling layers (not shown), wherein each filling layer can have a uniform length (not shown) in the second direction D2 and a uniform depth (not shown) in the vertical direction Y, or each filling layer can have a plurality of filling parts 132, 134, 136, 138 with different lengths L1, L2, L3, L4 in the second direction D2 and / or different depths in the vertical direction Y, etc., but not limited thereto. In this way, the semiconductor device formed by other embodiments can also have an overall optimized component structure and performance, thereby improving the operation performance. Figure 1

[0098] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.​

Claims

1. A semiconductor device, characterized by, The method comprises: providing a substrate; forming a plurality of bit lines on the substrate, the bit lines being spaced apart from each other and extending along a first direction, the bit lines including at least one first bit line and a plurality of second bit lines, the at least one first bit line being disposed on one side of the second bit lines; forming a bit line spacer on sidewalls of each of the second bit lines and the at least one first bit line; and forming at least one fill layer in the at least one first bit line, the at least one fill layer extending along the first direction, the at least one fill layer including a material at least partially the same as the bit line spacer.

2. The semiconductor device according to claim 1, wherein The at least one fill layer further includes a plurality of fill portions, the fill portions having different lengths in a second direction perpendicular to the first direction.

3. The semiconductor device of claim 2, wherein, At least two of the fill portions are disposed adjacent to each other.

4. The semiconductor device of claim 2, wherein At least two of the fill portions are disposed apart from each other.

5. The semiconductor device of claim 2, wherein Bottom surfaces of at least two of the fill portions are not coplanar.

6. A semiconductor device, characterized by The method comprises: providing a substrate; forming a plurality of bit lines on the substrate, the bit lines being spaced apart from each other and extending along a first direction, the bit lines including at least one first bit line and a plurality of second bit lines, the at least one first bit line being disposed on one side of the second bit lines; forming a fill portion in the at least one first bit line, a bottom surface of the fill portion being higher than a bottom surface of a conductive layer of the at least one first bit line.

7. The semiconductor device of claim 6, wherein, The conductive layer includes at least a semiconductor layer, a barrier layer, and a metal layer stacked in sequence.

8. The semiconductor device of claim 7, wherein, The bottom surface of the fill portion is bounded between a top surface and a bottom surface of the metal layer in a vertical direction.

9. The semiconductor device of claim 7, wherein, The bottom surface of the fill portion is bounded between a top surface and a bottom surface of the barrier layer in the vertical direction.

10. The semiconductor device of claim 7, wherein, The bottom surface of the fill portion is bounded between a top surface and a bottom surface of the semiconductor layer in the vertical direction.

11. The semiconductor device of claim 6, wherein, The method further comprises: forming a cap layer on the conductive layer of each of the bit lines, wherein the bottom surface of the fill portion is bounded between a top surface and a bottom surface of the cap layer in the vertical direction.

12. The semiconductor device of claim 6, wherein The method further comprises: forming a bit line spacer on sidewalls of each of the second bit lines and the at least one first bit line, wherein the fill portion includes a material at least partially the same as the bit line spacer.

13. The semiconductor device of claim 6, wherein The method further comprises: forming a plurality of active regions and a plurality of shallow trench isolations in the substrate, the active regions and the shallow trench isolations being alternately disposed in the substrate, wherein the at least one first bit line simultaneously straddles at least two of the active regions in a horizontal direction.

14. A method of fabricating a semiconductor device, characterized by, The method comprises: providing a substrate; forming a plurality of bit lines on the substrate, the bit lines being spaced apart from each other and extending along a first direction, the bit lines including at least one first bit line and a plurality of second bit lines, the at least one first bit line being disposed on one side of the second bit lines; forming a bit line spacer on sidewalls of each of the second bit lines and the at least one first bit line; and forming at least one fill layer in the at least one first bit line, the at least one fill layer extending along the first direction, the at least one fill layer including a material at least partially the same as the bit line spacer. The method of forming the bit lines and the at least one fill layer further comprises:

15. The method of fabricating a semiconductor device according to Claim 14, wherein performing a deposition process to sequentially form a conductive material layer, a cap material layer, and a sacrificial layer on the substrate; forming a plurality of mask patterns on the sacrificial layer; and performing an etching process to form the bit lines and the at least one fill layer. forming a photoresist layer on the sacrificial layer, covering the first part of the mask pattern and exposing the second part of the mask pattern, wherein a sidewall of the photoresist layer is trimmed to a sidewall of one of the second part of the mask pattern; performing a patterning process through the photoresist layer and the second part of the mask pattern, simultaneously forming the at least one first bit line and the second bit line; forming at least one trench within the at least one first bit line, extending in the first direction; and after removing the photoresist layer, the mask pattern and the sacrificial layer, forming the bit line spacer and the at least one fill layer within the at least one trench.

16. The method of fabricating a semiconductor device according to Claim 15, wherein The at least one trench further comprises a plurality of trench sections, the trench sections having different lengths in a second direction perpendicular to the first direction.

17. The method of fabricating a semiconductor device according to Claim 16, wherein At least two of the trench sections are arranged in connection with each other.

18. The method of fabricating a semiconductor device according to Claim 16, wherein At least two of the trench sections are arranged in separation from each other.

19. The method of fabricating a semiconductor device according to Claim 16, wherein At least two of the trench sections have different depths in a vertical direction perpendicular to the substrate.

20. The method of fabricating a semiconductor device according to Claim 19, wherein A bottommost surface of at least one of the trench sections is located within the conductive material layer or the cap material layer.

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