A bipolar transistor having high magnetic field resistance

Abstract

The application discloses a novel bipolar transistor with strong magnetic resistance, a control chip and a transistor manufacturing method. The transistor comprises a P-type substrate, an N-type buried layer, three first STI regions, a second STI region, an active region and an N-type deep well. The three first STI regions are arranged side by side on the side of the N-type buried layer away from the P-type substrate. The active region and the N-type deep well are arranged along the horizontal direction and are separated from the three first STI regions, and two first STI regions are respectively located at the periphery of all the active regions and the N-type deep well. The active region comprises a collector, a base arranged in sequence, a second STI region located on the side of the base away from the collector and an emitter. The second STI region is located between the emitter and the peripheral first STI region. The interface between the emitter and the base forms a BE junction. The stability of the amplification factor and the anti-magnetic interference ability of the transistor in a strong magnetic field environment at different frequencies are effectively improved.

Description

Technical Field

[0001] This application relates to the field of transistor design, and more particularly to a novel bipolar transistor with strong magnetic resistance, a control chip, and a method for manufacturing the transistor. Background Technology

[0002] With the rapid development of integrated circuit technology, chip feature sizes are constantly shrinking, integration density is significantly improving, and the performance and adaptability requirements of devices are also increasing. Besides pursuing more efficient computing power, electronic devices also need to adapt to various complex and harsh working environments, such as aerospace radiation, electromagnetic interference, and special conditions like high temperature and high humidity. In these harsh environments, strong magnetic field interference, especially pulsed strong magnetic fields, has become a key challenge.

[0003] Pulsed strong magnetic fields are a crucial physical environment generated during the operation of high-power equipment such as electromagnetic railguns. During the firing process of an electromagnetic railgun, a large current instantaneously flows through the coil, generating a strong pulsed magnetic field. Control chips need to maintain stable operation in this environment; therefore, improving the reliability of electronic components in strong magnetic environments has become a research topic of great practical value.

[0004] Current research on improving the resistance of electronic devices to strong magnetic fields focuses primarily on magnetic shielding technology, which minimizes magnetic field interference through physical isolation. These solutions typically involve magnetic shielding materials and structures. High-permeability materials (such as iron-nickel alloys or soft magnetic materials) are used to coat the device's exterior, absorbing or deflecting magnetic fields to protect internal circuitry. Specialized packaging is also employed to completely enclose the device within the magnetic shielding enclosure, isolating it from external magnetic fields. For example, Renesas Electronics Corporation proposed an improved magnetic shielding packaging technology that effectively enhances the device's shielding capability against external magnetic fields by embedding multiple layers of magnetic shielding material within the chip packaging layer. However, these methods primarily address the problem through physical isolation and do not address the internal structure of semiconductor devices. In summary, existing technologies mainly rely on external shielding methods and lack optimized solutions for the internal structure of semiconductor devices. Summary of the Invention

[0005] The main objective of this application is to provide a novel bipolar transistor, control chip, and transistor manufacturing method with strong magnetic field resistance, aiming to effectively improve their amplification stability and anti-magnetic interference capability in strong magnetic field environments at different frequencies.

[0006] To achieve the above objectives, a first aspect of this application provides a novel bipolar transistor with strong magnetic resistance, comprising: a P-type substrate and an N-type buried layer stacked sequentially, and three first STI regions, a second STI region, an active region, and an N-type deep well stacked on the side of the N-type buried layer away from the P-type substrate; the three first STI regions are all arranged side-by-side on the side of the N-type buried layer away from the P-type substrate; the active region and the N-type deep well are arranged horizontally with a gap between them and the three first STI regions, and two of the first STI regions are respectively located on the active region. The active region includes the periphery of the active region and the N-type deep well, wherein the horizontal direction is perpendicular to the stacking direction; the active region includes: a collector and a base stacked sequentially, and a second STI region and an emitter located on the side of the base away from the collector, the second STI region being located between the emitter and the peripheral first STI region, and the interface between the emitter and the base forming a BE junction; wherein the depth of the three first STI regions is greater than the depth of the active region and the N-type deep well; the depth of the second STI region is greater than the depth of the BE junction.

[0007] To achieve the above objectives, a second aspect of this application also provides a method for manufacturing a novel bipolar transistor with strong magnetic resistance as described in the first aspect, comprising: fabricating a P-type substrate and performing N-type heavy doping on one side of the P-type substrate to obtain an N-type buried layer; growing a silicon layer on the side of the N-type buried layer away from the P-type substrate; forming three spaced-apart first STI regions as described in claim 1 on the side of the silicon layer away from the N-type buried layer to change the trajectory of the emitter electrons and redistribute the base electric field distribution; and forming two adjacent first STI regions respectively. A second STI region is formed between the first STI regions to correct the carrier motion trajectory, thereby reducing the interference of the magnetic field on the device. The bottoms of the three first STI regions all extend into the N-type buried layer. The deep well between the two first STI regions that do not have the second STI region in the middle is heavily N-type doped to obtain an N-type deep well. The collector region around the second STI region is N-type doped to obtain a collector. The region of the collector away from the N-type buried layer is P-type doped to obtain a base. The region of the base away from the N-type buried layer is N+ type doped to obtain an emitter.

[0008] Optionally, the depth of the N-type deep trap is less than the depth of the first STI.

[0009] Optionally, the depth of the second STI region is lower than the depth of the first STI region.

[0010] Optionally, the depth of the collector region is lower than that of the first STI region.

[0011] Optionally, it has a novel bipolar transistor with strong magnetic resistance as described in claim 1;

[0012] In addition, to achieve the above objectives, this application also provides a control chip, and the third aspect of this application further includes the novel bipolar transistor with strong magnetic resistance described in the first aspect.

[0013] This application provides a novel bipolar transistor (BPT) with strong magnetic field resistance, a control chip, and a transistor manufacturing method. The BPT comprises a P-type substrate, an N-type buried layer, and three first STI regions, a second STI region, an active region, and an N-type deep well stacked sequentially on the side of the N-type buried layer away from the P-type substrate. The three first STI regions are arranged side-by-side on the side of the N-type buried layer away from the P-type substrate. The active region and the N-type deep well are arranged horizontally with intervals between them and the three first STI regions, with two of the first STI regions located on the periphery of all the active regions and the N-type deep well, respectively. The horizontal direction is perpendicular to the stacking direction. The active region includes a collector and a base stacked sequentially, a second STI region located on the side of the base away from the collector, and an emitter. The second STI region is located between the emitter and the peripheral first STI region, and the interface between the emitter and the base forms a BE junction. The depth of the three first STI regions is greater than the depth of the active region and the N-type deep well. The depth of the second STI region is greater than the depth of the BE junction, which effectively improves the amplification stability and anti-magnetic interference capability of the transistor in strong magnetic field environments at different frequencies. Attached Figure Description

[0014] Figure 1 A vertical cross-sectional structural schematic diagram of an embodiment of the novel bipolar transistor with strong magnetic resistance provided in this application;

[0015] Figure 2 This is a schematic cross-sectional view of a novel bipolar transistor with strong magnetic resistance according to an embodiment of this application.

[0016] Figure 3 This is a performance comparison diagram of an improved transistor provided for an embodiment of the novel bipolar transistor with strong magnetic resistance according to this application.

[0017] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0018] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0019] Traditional bipolar junction transistors (BJTs) experience significant disturbances in carrier motion under strong magnetic fields, especially those in specific sensitive directions. This alters the electric field distribution within the BJT device, severely impacting its amplification performance and stability. Current magnetic shielding is the primary protection method for semiconductor devices, but it is expensive, has low integration density, and mainly provides protection against high-frequency magnetic fields. It is ineffective against strong magnetic fields in low-frequency and static magnetic field environments.

[0020] This application aims to optimize the device structure, reduce the impact of magnetic fields on BJT performance, and effectively improve its amplification stability and anti-magnetic interference capability in strong magnetic field environments at different frequencies.

[0021] This application provides a novel bipolar transistor with strong magnetic field resistance, comprising:

[0022] A P-type substrate 1 and an N-type buried layer 2 are stacked sequentially, and three first STI regions 3, second STI regions 4, active regions 5 and N-type deep traps 6 are stacked on the side of the N-type buried layer away from the P-type substrate.

[0023] The three first STI regions 3 are all arranged side by side on the side of the N-type buried layer 2 away from the P-type substrate 1;

[0024] The active region 5 and the N-type deep well 6 are arranged horizontally with the three first STI regions 3 at intervals, and the two first STI regions 3 are located on the periphery of the active region 5 and the N-type deep well 6, respectively, wherein the horizontal direction is perpendicular to the stacking direction.

[0025] The active region 5 includes:

[0026] A collector 51 and a base 52 are stacked in sequence, and a second STI region 4 and an emitter 53 are located on the side of the base 52 away from the collector 51. The second STI region 4 is located between the emitter 53 and the first STI region 3 on the periphery. The interface between the emitter 53 and the base 52 forms a BE junction, and the interface between the base 52 and the collector 51 forms a BC junction.

[0027] Among them, the depth of the three first STI regions 3 is greater than the depth of the active region 5 and the N-type deep well 6;

[0028] The depth of the second STI region 4 is greater than the depth of the BE junction.

[0029] The purpose of this application is to provide a BJT device structure and its fabrication method to solve the problem of BJT amplification factor reduction under strong magnetic conditions. The BJT device structure is as follows: Figure 1 and Figure 2 As shown, where Figure 1 The diagram shown is a cross-sectional schematic of the BJT device structure of this application; Figure 2 The diagram shown is a longitudinal cross-sectional view of the BJT device structure of this application. The BJT device structure of this application includes at least: a P-type substrate 1 (PSUB), an N-type buried layer 2 (DNW) located on the P-type substrate 1, an N-type deep well 6 (NW) located to the upper right of the N-type buried layer, and a first STI region 3; Figure 2 It is Figure 1 The cross-section shows that the central region has an N-region forming a collector 51; the collector 51 in the central region has a P-region as a base, the P-region in the central region has an N+ region as an emitter 53, and the base 52 has a second STI region 4.

[0030] This application has the following advantages:

[0031] 1. Design of Dual-Depth STI. Based on the traditional STI structure for isolation, a shallower STI structure was designed. By placing the dual-depth STI on the left and right sides of the base region, the trajectory of electrons in the emitter region is altered, and the electric field distribution in the base region is redefined, thereby optimizing device performance.

[0032] 2. Compatibility with mainstream BCD processes. The shallow trench isolation technology and ion implantation process used in this application are fully compatible with mainstream BCD processes, enabling efficient integration of BJT, MOS, and DMOS devices to meet the needs of high-performance analog and power drive circuits.

[0033] 3. Performance optimization under strong magnetic field environments. Through specific structural design, the impact of strong magnetic fields on BJT devices is effectively reduced, significantly minimizing the decrease in amplification factor under high magnetic fields, thus enhancing device reliability and environmental adaptability.

[0034] Previous technologies for designing against strong magnetic fields have relied on magnetic shielding to protect the chip's periphery, increasing costs, reducing integration density, and proving ineffective at shielding low-frequency magnetic fields. This application aims to improve the device structure by inventing a new structure using existing BJT technology to address the magnetic field problem at the device level. This eliminates the need for additional packaging, reduces costs, increases integration density, and effectively reduces the impact of low-frequency and static magnetic fields.

[0035] refer to Figure 3 The dual-depth STI structure designed in this application exhibits higher reliability when operating in strong magnetic environments. Compared to a single-depth STI BJT with a similar structure, the BJT in this application shows suppressed collector current attenuation under strong magnetic fields, reducing the degree of BJT amplification factor attenuation by 75%.

[0036] Based on the above embodiments, a method for manufacturing a novel bipolar transistor with strong magnetic resistance includes:

[0037] S10. Fabricate a P-type substrate 1 and perform N-type heavy doping on one side of the P-type substrate to obtain an N-type buried layer 2.

[0038] S20. A silicon layer is grown on the side of the N-type buried layer 2 away from the P-type substrate 1;

[0039] S30. Three first STI regions 3 are formed at intervals on the side of the silicon layer away from the N-type buried layer 2 to change the movement trajectory of the emitter electrons and redefine the base electric field distribution. A second STI region 4 is formed between two adjacent first STI regions 3 to correct the movement trajectory of charge carriers, thereby reducing the interference of the magnetic field on the device. The bottom of the three first STI regions 3 extends into the N-type buried layer, and the depth of the second STI region is lower than the depth of the first STI region.

[0040] S40. The deep well between the two first STIs 3 that does not have the second STI region 4 is subjected to N-type heavy doping to obtain an N-type deep well 6, wherein the depth of the N-type deep well is less than the depth of the first STI.

[0041] S50. N-type doping is performed on the collector region surrounding the second STI region 4 to obtain collector 51, wherein the depth of collector 51 is lower than that of the first STI region 3.

[0042] S60. P-type doping is performed on the region of the collector 51 away from the N-type buried layer to obtain the base 52.

[0043] S70. N+ type doping is performed on a portion of the base 52 on the side away from the N-type buried layer 2 to obtain the emitter 53.

[0044] Based on the above embodiments, this application also provides a control chip, including a novel bipolar transistor with strong magnetic resistance provided in any of the preceding embodiments.

[0045] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A bipolar transistor with strong magnetic resistance, characterized in that, include: A P-type substrate and an N-type buried layer are stacked sequentially, and three first STI regions, a second STI region, an active region, and an N-type deep well are stacked on the side of the N-type buried layer away from the P-type substrate. The three first STI regions are arranged side by side on the side of the N-type buried layer away from the P-type substrate; The active region and the N-type deep well are arranged horizontally with the three first STI regions spaced apart, and the two outermost first STI regions are located around the active region and the N-type deep well, respectively, wherein the horizontal direction is perpendicular to the stacking direction. The active region includes: A collector and a base are stacked sequentially, along with a second STI region and an emitter located on the side of the base away from the collector. The second STI region is located between the emitter and the first STI region surrounding the active region. The interface between the emitter and the base forms a BE junction. The depth of the three first STI regions is greater than the depth of the active region and the N-type deep well; The depth of the second STI region is greater than the depth of the BE junction.

2. A method for manufacturing a bipolar transistor with strong magnetic resistance as described in claim 1, characterized in that, include: A P-type substrate is fabricated, and N-type heavy doping is performed on one side of the P-type substrate to obtain the N-type buried layer. A silicon layer is grown on the side of the N-type buried layer away from the P-type substrate; Three first STI regions are formed at intervals on the side of the silicon layer away from the N-type buried layer to change the trajectory of the emitter electrons and redefine the base electric field distribution. Second STI regions are formed between two adjacent first STI regions to correct the trajectory of the charge carriers. The bottom of each of the three first STI regions extends into the N-type buried layer. N-type heavy doping is performed on the deep well between two first STIs that do not have the second STI region in the middle to obtain an N-type deep well; The collector region surrounding the second STI region is N-type doped to obtain the collector. The base electrode is obtained by P-type doping of the region of the collector electrode away from the N-type buried layer. An emitter is obtained by performing N+ type doping on a portion of the base electrode away from the N-type buried layer.

3. The method for manufacturing a bipolar transistor with strong magnetic resistance as described in claim 2, characterized in that, The depth of the N-type deep well is less than the depth of the first STI.

4. The method for manufacturing a bipolar transistor with strong magnetic resistance as described in claim 2, characterized in that, The depth of the second STI region is less than the depth of the first STI region.

5. The method for manufacturing a bipolar transistor with strong magnetic resistance as described in claim 2, characterized in that, The depth of the collector region is less than that of the first STI region.

6. A control chip, characterized in that, It has a bipolar transistor with strong magnetic resistance as described in claim 1.

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