Display device

Abstract

The purpose of the present invention is to provide a display device capable of reducing parasitic capacitance between wires, a display device having high display quality, and a display device capable of reducing power consumption. A display device of the present invention includes: a signal line; a scan line; a first electrode; a second electrode; a third electrode; a first pixel electrode; a second pixel electrode; and a semiconductor film in which the signal line crosses the scan line, the first electrode is electrically connected to the signal line, the first electrode includes a region overlapping the scan line, the second electrode faces the first electrode, the third electrode faces the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, and the first electrode faces the second electrode. The semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is provided between the scanning line and the first to third electrodes.

Description

[0001] This divisional application is a divisional application of the invention patent application with the application number 201680009371.3, the application date of February 3, 2016, and the title of "Display Device". More specifically, this divisional application is a further divisional application based on the divisional application with the application number 202210029583.5, the application date of February 3, 2016, and the invention title of "Display Device". Technical Field

[0002] One aspect of the present invention relates to a display device. Note that one aspect of the present invention is not limited to the above technical field. The technical field of one aspect of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, as an example of the technical field of one aspect of the invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, driving methods of these devices, or manufacturing methods of these devices can be cited. Background Art

[0003] In recent years, as a liquid crystal display device with improved viewing angle characteristics and display quality, a vertically aligned (VA) type liquid crystal display device has been proposed. In addition, as a VA type liquid crystal display device, a liquid crystal display device with a multi-domain structure has been proposed, in which a single pixel includes a plurality of pixel electrodes and transistors connected to each pixel electrode and controlling the potential of the pixel electrode. By providing a plurality of pixel electrodes in a single pixel, the orientation of the liquid crystal can be made different for each pixel electrode. Therefore, the viewing angle of the multi-domain structure liquid crystal display device can be larger than that of the existing VA type liquid crystal display device (see Patent Document 1).

[0004] In addition, the screen size of liquid crystal display devices has a tendency to increase, such as a diagonal of 60 inches or more. Furthermore, development aiming at a screen size with a diagonal of 120 inches or more is underway. Also, the screen has a tendency to be high-definition, such as full high-definition picture quality (FHD, 1920×1080) or 4K picture quality (3840×2160). And currently, the development of a liquid crystal display device with a high resolution of so-called 8K with a pixel number of 7680×4320 is accelerating.

[0005] In addition, in order to reduce afterimages and improve display quality, high-speed driving development that doubles the driving speed (also known as double-speed driving) has been carried out. Furthermore, research on high-speed driving that triples the driving speed or more has also been carried out. In addition, for a liquid crystal display device that realizes three-dimensional (3D) display, it is necessary to alternately display the right-eye image and the left-eye image, so the liquid crystal display device needs to operate at a speed of double speed or more.

[0006] [References]

[0007] [Patent Documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-317867 Summary of the Invention

[0009] However, with the increase in size and high definition of liquid crystal display devices, the number of required pixels has increased significantly, so the writing time for each pixel has become shorter. As a result, the transistors that control the potential of the pixel electrodes are required to operate at high speed and have a high on-state current, etc.

[0010] In addition, the increase in parasitic capacitance generated between wirings causes a delay in signal transmission to the ends of the signal lines. As a result, it is possible to occur a reduction in display quality such as display unevenness or poor gradation, and an increase in power consumption.

[0011] Then, one of the purposes of one aspect of the present invention is to provide a display device that can reduce the parasitic capacitance between wirings. In addition, one of the purposes of one aspect of the present invention is to provide a display device with high display quality. In addition, one of the purposes of one aspect of the present invention is to provide a display device that can reduce power consumption. In addition, one of the purposes of one aspect of the present invention is to provide a novel semiconductor device or a novel display device, etc.

[0012] Note that the description of these purposes does not prevent the existence of other purposes. One aspect of the present invention does not necessarily need to achieve all of the above purposes. In addition, there are clearly other purposes in the descriptions of the specification, drawings, claims, etc., and other purposes can be obtained from the descriptions of the specification, drawings, claims, etc.

[0013] One aspect of the present invention is a display device including a signal line, a scanning line intersecting the signal line, a first electrode electrically connected to the signal line, a second electrode opposed to the first electrode, a third electrode opposed to the first electrode, a first pixel electrode electrically connected to the second electrode, a second pixel electrode electrically connected to the third electrode, and a semiconductor film in contact with the first electrode to the third electrode and provided between the scanning line and the first electrode to the third electrode, wherein the first electrode includes a region overlapping the scanning line.

[0014] Further, one aspect of the present invention is the above-described display device, which includes a gate insulating film between the scanning line and the semiconductor film, wherein a first transistor is constituted by the scanning line, the gate insulating film, the semiconductor film, the first electrode, and the second electrode, and a second transistor is constituted by the scanning line, the gate insulating film, the semiconductor film, the first electrode, and the third electrode.

[0015] Further, one aspect of the present invention is the above-described display device, which includes a first capacitor wiring electrically connected to the first pixel electrode and a second capacitor wiring electrically connected to the second pixel electrode, wherein the signal line includes a region overlapping between the first pixel electrode and the second pixel electrode, and the signal line does not include a region overlapping the first capacitor wiring and the second capacitor wiring.

[0016] Further, one aspect of the present invention is the above-described display device, wherein the first electrode is disposed between the second electrode and the third electrode in the top surface shape.

[0017] Further, one aspect of the present invention is the above-described display device, wherein the semiconductor film contains an oxide having In, M (M is aluminum, gallium, yttrium, or tin), and Zn.

[0018] Further, one aspect of the present invention is the above-described display device, wherein the semiconductor film includes a first semiconductor film and a second semiconductor film including a region overlapping the first semiconductor film, and the first semiconductor film contains an oxide having a higher atomic ratio of In to the atomic ratio of M than the second semiconductor film.

[0019] Thus, by adopting one aspect of the present invention, the parasitic capacitance between wirings of the display device can be reduced. In addition, by adopting one aspect of the present invention, the display quality of the display device can be improved. In addition, by adopting one aspect of the present invention, the power consumption of the display device can be reduced. In addition, by adopting one aspect of the present invention, a novel semiconductor device or a novel display device, etc. can be provided. Note that the description of these effects does not preclude the existence of other effects.

[0020] In addition, one aspect of the present invention does not necessarily have all of the above effects. Effects other than the above effects are obvious from the descriptions in the specification, the drawings, the claims, etc., and effects other than the above effects can be extracted from the said descriptions. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figures 1A to 1C are a plan view and a circuit diagram of one aspect of a pixel;

[0022] Figure 2A and Figure 2B are a plan view and a circuit diagram of a pixel illustrating one aspect of the present invention;

[0023] Figure 3A and Figure 3B are a plan view and a circuit diagram of one aspect of a pixel;

[0024] Figure 4 is a cross-sectional view of one aspect of a pixel;

[0025] Figure 5 is a plan view of one aspect of a pixel;

[0026] Figure 6 is a plan view of one aspect of a pixel;

[0027] Figures 7A to 7D are a plan view and a circuit diagram of one aspect of a pixel;

[0028] Figure 8A and Figure 8B are a plan view and a circuit diagram of one aspect of a pixel;

[0029] Figure 9 is a cross-sectional view of one aspect of a pixel;

[0030] Figures 10A to 10C is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0031] Figures 11A to 11C is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0032] Figures 12A to 12C is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0033] Figure 13A and Figure 13B is a cross-sectional view showing an example of a manufacturing process of a semiconductor device;

[0034] Figures 14A to 14C are a cross-sectional view showing an example of a manufacturing process of a semiconductor device, a plan view and a cross-sectional view showing one aspect of the semiconductor device;

[0035] Figures 15A to 15C is a cross-sectional view showing one mode of a semiconductor device;

[0036] Figure 16A and Figure 16B is a plan view and a cross-sectional view showing one mode of a semiconductor device;

[0037] Figures 17A to 17C is a cross-sectional view showing one mode of a semiconductor device;

[0038] Figure 18 is a diagram illustrating a band structure;

[0039] Figures 19A to 19D is a Cs-corrected high-resolution TEM image of a cross-section of CAAC-OS and a schematic diagram of a cross-section of CAAC-OS;

[0040] Figures 20A to 20D is a Cs-corrected high-resolution TEM image of a plane of CAAC-OS;

[0041] Figures 21A to 21C is a diagram illustrating structural analysis of CAAC-OS and single-crystalline oxide semiconductors obtained by XRD;

[0042] Figure 22 A and Figure 22 B are diagrams showing electron diffraction patterns of CAAC-OS;

[0043] Figure 23 is a diagram showing changes in a crystallized portion of In-Ga-Zn oxide due to electron irradiation;

[0044] Figure 24 is a plan view showing one mode of a display device;

[0045] Figure 25 is a cross-sectional view showing one mode of a display device;

[0046] Figure 26 is a cross-sectional view showing one mode of a display device;

[0047] Figure 27 is a diagram illustrating a display module;

[0048] Figures 28A to 28G is a diagram illustrating an electronic device. Detailed Description of the Invention

[0049] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following description. It is easily understandable for those of ordinary skill in the art that the manner and details thereof can be changed into various forms without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited only to the content described in the embodiments shown below. Note that when describing the structure of the present invention with reference to the drawings, the same reference numerals are commonly used in different drawings to represent the same components.

[0050] In addition, the terms such as first, second, third to nth (n is a natural number) used in this specification are attached to avoid confusion of components, rather than being attached to limit the number.

[0051] In addition, depending on the situation or condition, the terms "film" and "layer" can be interchanged with each other. For example, sometimes the "conductive layer" can be referred to as the "conductive film". In addition, sometimes the "insulating film" can be referred to as the "insulating layer".

[0052] Embodiment 1

[0053] In this embodiment, with reference to FIGS. 1 to Figure 9 the structure of one pixel of the liquid crystal display device will be described.

[0054] Figure 1A is a top view of one pixel 100 of the liquid crystal display device having a multi-domain structure shown in this embodiment, Figure 1B showing Figure 1A the circuit diagram of the pixel 100 shown. Figure 2A is a top view of one pixel 200 of the existing liquid crystal display device having a multi-domain structure, Figure 2B showing Figure 2A the circuit diagram of the pixel shown.

[0055] As Figure 1A and Figure 1B shown, the pixel 100 includes a scan line 103 and a signal line 121 intersecting the scan line 103. The pixel 100 further includes a capacitor wiring 105a and a capacitor wiring 105b extending in the same direction as the scan line 103. The scan line 103 is disposed between the capacitor wiring 105a and the capacitor wiring 105b.

[0056] Near the intersection of the scanning line 103 and the signal line 121, a transistor 136 and a transistor 137 are provided. The transistor 136 includes a semiconductor film 135 overlapping the scanning line 103, a first electrode 123 overlapping the semiconductor film 135, and a second electrode 125a. The first electrode 123 is electrically connected to the signal line 121. The first electrode 123 is used as one of the source electrode and the drain electrode in the transistor 136. The second electrode 125a is used as the other of the source electrode and the drain electrode in the transistor 136.

[0057] The transistor 137 includes a semiconductor film 135 overlapping the scanning line 103, a first electrode 123 overlapping the semiconductor film 135, and a third electrode 125b. The first electrode 123 is used as one of the source electrode and the drain electrode in the transistor 137. The third electrode 125b is used as the other of the source electrode and the drain electrode in the transistor 137.

[0058] In Figure 1A , in the top surface shape, a part of the end of the semiconductor film 135 of the transistor 136 and the transistor 137 is located outside the scanning line 103 used as the gate electrode, but it is not limited to this. As Figure 1C shown, in the transistor 136 and the transistor 137 included in the pixel 100, the end of the semiconductor film 135 may also be located inside the end of the scanning line 103.

[0059] The second electrode 125a included in the transistor 136 is electrically connected to the pixel electrode 139a through the opening 144a. In other words, the transistor 136 is connected to the liquid crystal element 142 including the pixel electrode 139a through the second electrode 125a. In addition, one electrode of the capacitor element 140 is electrically connected to the pixel electrode 139a and the second electrode 125a of the transistor 136, and the other electrode is electrically connected to the capacitor wiring 105a (refer to Figure 1B ).

[0060] The third electrode 125b included in the transistor 137 is electrically connected to the pixel electrode 139b through the opening 144b. In other words, the transistor 137 is connected to the liquid crystal element 143 including the pixel electrode 139b through the third electrode 125b. In addition, one electrode of the capacitor element 141 is electrically connected to the pixel electrode 139b and the third electrode 125b of the transistor 137, and the other electrode is electrically connected to the capacitor wiring 105b (refer to Figure 1B ).

[0061] The openings 144a and 144b are provided in the insulating film 116 described later. In addition, in order to avoid complicating the drawing, in Figure 1A and Figure 2A , no hatching is added to the pixel electrode 139a and the pixel electrode 139b, and only the outline of the top surface shape is shown by a dotted line.

[0062] The transistors 136 and 137 are located at a position approximately in the center of the pixel 100 in the top surface shape, and are formed between the pixel electrodes 139a and 139b of each sub-pixel in the pixel 100.

[0063] One embodiment of the present invention is a display device including a signal line 121, a scan line 103, a first electrode 123, a second electrode 125a, a third electrode 125b, a first pixel electrode 139a, a second pixel electrode 139b, and a semiconductor film 135. The signal line 121 intersects with the scan line 103. The first electrode 123 is electrically connected to the signal line 121. The first electrode 125a includes a region overlapping with the scan line 103. The second electrode 125a faces the first electrode 123. The third electrode 125b faces the first electrode 123. The first pixel electrode 139a is electrically connected to the second electrode 125a. The second pixel electrode 139b is electrically connected to the third electrode 125b. The semiconductor film 135 is in contact with the first electrode 123, the second electrode 125a, and the third electrode 125b, and the semiconductor film 135 is disposed between the scan line 103, the first electrode 123 to the third electrode 125b.

[0064] In addition, the following display device is also one embodiment of the present invention: the display device includes a gate insulating film 107, a transistor 136, and a transistor 137. The gate insulating film 107 is disposed between the scan line 103 and the semiconductor film 135. The transistor 136 includes the scan line 103, the gate insulating film 107, the semiconductor film 135, the first electrode 123, and the second electrode 125a. The transistor 137 includes the scan line 103, the gate insulating film 107, the semiconductor film 135, the first electrode 123, and the third electrode 125b.

[0065] The transistors 136 and 137 commonly use the first electrode 123 as one of the source electrode and the drain electrode, and the first electrode 123 overlaps with the scan line 103. By adopting such a structure, in one pixel 100 constituting the display device, the parasitic capacitance generated between one electrode of the transistors 136 and 137 and the scan line 103 can be reduced.

[0066] In addition, as Figure 1B shown, in the transistor 136, a parasitic capacitance C1 is generated at the overlapping portion of the scan line 103 and the second electrode 125a. In addition, in the transistor 137, a parasitic capacitance C2 is generated at the overlapping portion of the scan line 103 and the third electrode 125b. In addition, parasitic capacitances C5, C6, and C7 are respectively generated at the overlapping portions of the signal line 121 and the scan line 103, the signal line 121 and the capacitance wiring 105a, and the signal line 121 and the capacitance wiring 105b.

[0067] Here, as a comparative example, Figure 2A FIG. 3 shows a top view of pixel 200, in which, among the two transistors included in one pixel, electrodes different from each other are electrically connected to the signal line and the electrode does not overlap with the scan line. Figure 2B FIG. 4 shows a circuit diagram of pixel 200. In the description of pixel 200, the same reference numerals are assigned to the same components as those in pixel 100, and the description of these components is omitted.

[0068] As Figure 2B shown, pixel 200 includes scan line 203 and signal line 212 that intersects scan line 203. Pixel 200 further includes capacitor wirings 105a and 105b that extend in the same direction as scan line 203. Scan line 203 is provided between capacitor wiring 105a and capacitor wiring 105b.

[0069] In addition, transistors 236 and 237 are provided near the intersection of scan line 203 and signal line 221. Transistor 236 includes a gate electrode protruding from scan line 203, a fourth electrode 223a protruding from signal line 221, and a second electrode 125a connected to liquid crystal element 142. One electrode of capacitor element 140 is electrically connected to pixel electrode 139a included in liquid crystal element 142 and the second electrode 125a of transistor 236, and the other electrode of capacitor element 140 is electrically connected to capacitor wiring 105a (see Figure 2B ).

[0070] Transistor 237 includes a gate electrode protruding from scan line 203, a fifth electrode 223b protruding from signal line 121, and a third electrode 125b connected to liquid crystal element 143. One electrode of capacitor element 141 is electrically connected to pixel electrode 139b included in liquid crystal element 143 and the third electrode 125b of transistor 237, and the other electrode of capacitor element 141 is electrically connected to capacitor wiring 105b (see Figure 2B ).

[0071] The differences between transistors 236 and 237 and transistors 136 and 137 in pixel 100 are that they respectively include a fourth electrode 223a and a fifth electrode 223b as one of the source electrode and the drain electrode. In addition, the fourth electrode 223a and the fifth electrode 223b protruding from signal line 221 do not overlap with scan line 203.

[0072] In addition, in the transistor 236, a parasitic capacitance C11 is generated at the overlapping portion of the scanning line 203 and the second electrode 125a. In addition, a parasitic capacitance C13 is generated at the overlapping portion of the scanning line 203 and the fourth electrode 223a. In the transistor 237, a parasitic capacitance C12 is generated at the overlapping portion of the scanning line 203 and the third electrode 125b. In addition, a parasitic capacitance C14 is generated at the overlapping portion of the scanning line 203 and the fifth electrode 223b. In addition, parasitic capacitances C15, C16, and C17 are respectively generated at the overlapping portion of the signal line 221 and the scanning line 203, the overlapping portion of the signal line 221 and the capacitor wiring 105a, and the overlapping portion of the signal line 221 and the capacitor wiring 105b.

[0073] In the transistors 136 and 236, if the areas of the overlapping portions of the scanning line 103 and the second electrode 125a and the scanning line 203 and the second electrode 125a are substantially the same, the parasitic capacitances C1 and C11 are substantially the same. In the transistors 137 and 237, if the areas of the overlapping portions of the scanning line 103 and the third electrode 125b and the scanning line 203 and the third electrode 125b are substantially the same, the parasitic capacitances C2 and C12 are substantially the same. In addition, if the areas of the overlapping portions of the signal line 121 and the scanning line 103 and the signal line 221 and the scanning line 203 are substantially the same, the parasitic capacitances C5 and C15 are substantially the same. In addition, if the areas of the overlapping portions of the signal line 121 and the capacitor wiring 105a and the signal line 221 and the capacitor wiring 105a are substantially the same, the parasitic capacitances C6 and C16 are substantially the same. In addition, if the areas of the overlapping portions of the signal line 121 and the capacitor wiring 105b and the signal line 221 and the capacitor wiring 105b are substantially the same, the parasitic capacitances C7 and C17 are substantially the same.

[0074] In the pixel 200 as a comparative example, the electrodes used as one of the source electrode and the drain electrode in the transistors 236 and 237 are different electrodes (in the transistor 236, it is the fourth electrode 223a, and in the transistor 237, it is the fifth electrode 223b). Therefore, a parasitic capacitance C13 is generated between the scanning line 203 and the fourth electrode 223a, and a parasitic capacitance C14 is generated between the scanning line 203 and the fifth electrode 223b.

[0075] However, in the pixel 100 shown in this embodiment, the electrode (the first electrode 123) that serves as one of the source electrode and the drain electrode in the transistor 136 and the transistor 137 is common, and this electrode overlaps the scanning line 103 at the overlapping portion of the signal line 121 and the scanning line 103. Therefore, in the transistor 136 and the transistor 137, the parasitic capacitance generated at the overlapping portion of this electrode and the scanning line 103 is included in the above-mentioned parasitic capacitance C5. The parasitic capacitance C5 is substantially the same as the parasitic capacitance C15. Therefore, the parasitic capacitance in the pixel 100 is less than that in the pixel 200, and the difference is equal to the parasitic capacitance C13 and the parasitic capacitance C14. As described above, the display device according to one aspect of the present invention can reduce the parasitic capacitance generated between the wirings of one pixel 100.

[0076] In addition, in the pixel 100 shown in this embodiment, the transistor 136 and the transistor 137 include a common semiconductor film. Therefore, the transistor 136 and the transistor 137 can commonly use the region where the first electrode 123 contacts the semiconductor film 135. As a result, the occupied area of the transistor 136 and the transistor 137 in the pixel 100 can be reduced.

[0077] In addition, as Figure 3A and Figure 3B shown, in the pixel 100, a structure in which adjacent pixels commonly use the capacitor wirings 105a and 105b can also be adopted. By adopting this structure, the number of capacitor wirings included in the display device can be reduced. In addition, as Figure 3A shown, by increasing the area of the overlapping portion of the pixel electrode 139a and the capacitor wiring 105a, the capacitance of the capacitor element 140 can be increased. Similarly, by increasing the area of the overlapping portion of the pixel electrode 139b and the capacitor wiring 105b, the capacitance of the capacitor element 141 can be increased.

[0078] Next, with reference to Figure 4 the structure of the transistors and capacitor elements included in the pixel 100 will be described.

[0079] Figure 4 Shown is Figure 1A the cross-sectional structure of the transistor 136 and the capacitor element 140 between the dotted lines A - B shown.

[0080] The transistor 136 includes a scanning line 103, a semiconductor film 135, a gate insulating film 107 provided between the scanning line 103 and the semiconductor film 135, a first electrode 123 in contact with the semiconductor film 135, and a second electrode 125a in contact with the semiconductor film 135 on the substrate 101.

[0081] The capacitive element 140 includes a capacitive wiring 105a, a second electrode 125a, and a gate insulating film 107 provided between the capacitive wiring 105a and the second electrode 125a on the substrate 101.

[0082] An insulating film 116 is provided on the gate insulating film 107, the semiconductor film 135, the first electrode 123, and the second electrode 125a. Further, a pixel electrode 139a electrically connected to the second electrode 125a through an opening 144a provided in the insulating film 116 is provided on the insulating film 116.

[0083] Although not shown, the transistor 137 has the same structure as the transistor 136. Further, the capacitive element 141 and the capacitive element 140 are composed of the same constituent elements.

[0084] As the substrate 101, in addition to a glass substrate and a ceramic substrate, a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process or the like can be used. Further, when the substrate does not need to have translucency, a substrate in which an insulating film is provided on the surface of a metal substrate such as stainless steel can also be used. As the glass substrate, for example, an alkali-free glass substrate such as barium borosilicate glass, aluminoborosilicate glass, or aluminosilicate glass can be used. Note that there is no limitation on the size of the substrate 101. For example, the third to tenth generation glass substrates commonly used in liquid crystal display devices can be used. Further, as the material for the substrate 101, the material for the substrate 502 described in Embodiment 2 can be referred to.

[0085] A part of the scanning line 103 serves as the gate electrode of the transistor 136. The scanning line 103 can be formed in a single layer or a stack using a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium, or nickel, or an alloy material mainly composed of these materials. Further, a semiconductor typified by polysilicon doped with an impurity element such as phosphorus, an Ag - Pd - Cu alloy, an Al - Nd alloy, an Al - Ni alloy, or the like can also be used.

[0086] For example, as the two-layer structure of the scanning line 103, the following structures are preferably adopted: a two-layer structure in which a molybdenum film is laminated on an aluminum film; a two-layer structure in which a molybdenum film is laminated on a copper film; a two-layer structure in which a titanium nitride film or a tantalum nitride film is laminated on a copper film; a two-layer structure in which a titanium nitride film and a molybdenum film are laminated; a two-layer structure in which a copper-magnesium alloy film containing oxygen and a copper film are laminated; a two-layer structure in which a copper-manganese alloy film containing oxygen and a copper film are laminated; a two-layer structure in which a copper-manganese alloy film and a copper film are laminated, etc. As the three-layer structure, a three-layer structure in which a tungsten film or a tungsten nitride film, an alloy film of aluminum and silicon or an alloy film of aluminum and titanium, and a titanium nitride film or a titanium film are laminated is preferably adopted. By laminating a metal film serving as a barrier film on a low-resistance film, the resistance can be reduced, and the diffusion of metal elements from the metal film into the semiconductor film can be prevented. In addition, as the material for the scanning line 103, the material of the conductive film 504 described in Embodiment 2 can be referred to.

[0087] In addition, the capacitor wirings 105a and 105b have the same material and laminated structure as the scanning line 103.

[0088] The gate insulating film 107 can be formed of a single layer or a laminate of a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum nitride film, an aluminum oxynitride film, or an aluminum nitride oxide film. In the present embodiment, the gate insulating film 107 has a laminated structure of a gate insulating film 107a and a gate insulating film 107b. In addition, as the material for the gate insulating film 107a and the gate insulating film 107b, the materials of the insulating films 506 and 507 described in Embodiment 2 can be referred to.

[0089] As the semiconductor film 135, a silicon film or an oxide semiconductor film can be used. The semiconductor film 135 can appropriately have an amorphous structure, a polycrystalline structure, a single crystal structure, or other crystal structures.

[0090] In particular, as the semiconductor film 135, an oxide semiconductor film is preferably used. Specifically, In-M (M is aluminum, gallium, yttrium, or tin) oxide or In-M-Zn oxide can be used. Particularly preferably, as the semiconductor film 135, oxide semiconductor films 135a and 135b having different compositions from each other are used. As the materials for the oxide semiconductor films 135a and 135b, the materials of the oxide semiconductor films 508a and 508b described in Embodiment 2 can be referred to.

[0091] The first electrode 123 and the second electrode 125a can be formed of aluminum, copper, titanium, neodymium, scandium, molybdenum, chromium, tantalum, tungsten, etc. in a single layer or a stacked layer. Alternatively, the first electrode 123 and the second electrode 125a can be formed of an aluminum alloy (such as an Al-Nd alloy that can be used for the scanning line 103) added with an element for preventing hillocks. In addition, crystalline silicon added with an impurity element serving as a donor can also be used. Further, a stacked structure can also be adopted, that is, a film in contact with the crystalline silicon added with the impurity element serving as a donor is formed of titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, and aluminum or an aluminum alloy is formed thereon. Moreover, a stacked structure can also be adopted in which the top and bottom surfaces of aluminum or an aluminum alloy are clamped by titanium, tantalum, molybdenum, tungsten, or a nitride of these elements. Additionally, as the materials for the first electrode 123 and the second electrode 125a, reference can be made to the materials of the conductive film 512a and the conductive film 512b described in Embodiment 2.

[0092] The signal line 121 and the third electrode 125b have the same material and stacked structure as the first electrode 123.

[0093] In this embodiment, the insulating film 116 has a stacked structure of an insulating film 116a, an insulating film 116b, and an insulating film 116c. As the materials and formation methods for the insulating film 116a, the insulating film 116b, and the insulating film 116c, reference can be made to the descriptions of the insulating film 514, the insulating film 516, and the insulating film 518 described in Embodiment 2. Additionally, the insulating film 116 can be formed of a single layer or a stacked layer using the same material as the gate insulating film 107.

[0094] The pixel electrode 139a can be formed of a metal film such as molybdenum, titanium, tantalum, tungsten, aluminum, silver, copper, chromium, neodymium, scandium, etc. or an alloy film containing these metals in a single layer or a stacked layer. Examples of alloys containing aluminum include an aluminum-nickel-lanthanum alloy, an aluminum-titanium alloy, an aluminum-neodymium alloy, etc. Examples of alloys containing silver include a silver-neodymium alloy, a magnesium-silver alloy, etc. In addition, an alloy containing gold and copper can also be used. Further, a metal nitride film containing titanium nitride, molybdenum nitride, tungsten nitride, etc. can also be used. Additionally, as the material for the pixel electrode 139a, reference can be made to the material of the conductive film 520 described in Embodiment 2. The pixel electrode 139b has the same material and stacked structure as the pixel electrode 139a.

[0095] Additionally, an oxide semiconductor film can also be used as the pixel electrode. Figure 5 A top view of the pixel 100 including the pixel electrodes 148 and 149 using an oxide semiconductor film is shown. Figure 6 is Figure 5 the cross-sectional structure of the transistor 136 and the capacitor element 145 between the dotted lines C-D shown.

[0096] In this specification and the like, the oxide conductor film may be alternatively referred to as an oxide semiconductor film having a high carrier density and low resistance, a conductive oxide semiconductor film, or a highly conductive oxide semiconductor film, etc.

[0097] If an oxide semiconductor film is used as the pixel electrode 148 and an oxide semiconductor film is used as the semiconductor film 135, then the semiconductor film 135 and the pixel electrode 148 can be formed in the same process, so it is preferable. In the oxide semiconductor film, the resistivity can be controlled according to the oxygen defects in the film and / or the concentration of impurities such as hydrogen and water in the film. Therefore, by selecting a process for increasing the oxygen defects and / or impurity concentration or reducing the oxygen defects and / or impurity concentration of the oxide semiconductor film processed into an island shape, the resistivity of the semiconductor film 135 and the pixel electrode 148 formed in the same process can be controlled.

[0098] Specifically, by performing plasma treatment on the island-shaped oxide semiconductor film that will become the oxide conductor films 148a and 148b used as the pixel electrode 148, the oxygen defects in the oxide semiconductor film and / or impurities such as hydrogen and water in the oxide semiconductor film are increased, whereby an oxide semiconductor film having a high carrier density and low resistance can be realized. On the other hand, insulating films 116a and 116b are provided on the transistor 136 so that the oxide semiconductor films 135a and 135b are not exposed to the above-mentioned plasma treatment. In Figure 6 this, the insulating films 116a and 116b are provided in such a manner as to selectively remove the regions overlapping with the oxide conductor films 148a and 148b.

[0099] As the plasma treatment performed on the oxide conductor films 148a and 148b, typically, a plasma treatment using a gas containing one or more selected from noble gases (He, Ne, Ar, Kr, Xe), phosphorus, boron, hydrogen, and nitrogen can be cited. More specifically, a plasma treatment in an Ar atmosphere, a plasma treatment in a mixed atmosphere of Ar and hydrogen, a plasma treatment in an ammonia atmosphere, a plasma treatment in a mixed atmosphere of Ar and ammonia, or a plasma treatment in a nitrogen atmosphere, etc. can be cited.

[0100] In addition, the pixel electrode 149 and the pixel electrode 148 have the same material and laminated structure. In addition, in Figure 5 and Figure 6 the pixel 100 shown, the capacitive element 145 includes a capacitive wiring 105a, a pixel electrode 148, and a gate insulating film 107 provided between the capacitive wiring 105a and the pixel electrode 148. In addition, the capacitive element 146 includes a capacitive wiring 105b, a pixel electrode 149, and a gate insulating film 107 provided between the capacitive wiring 105b and the pixel electrode 149.

[0101] A more detailed structure and manufacturing method of the transistor 136 will be described in Embodiment 2. By using the transistor described in Embodiment 2 in the pixel 100 described in this embodiment, the power consumption of a display device according to one aspect of the present invention can be reduced.

[0102] [Modification Examples of Pixel Structure]

[0103] Hereinafter, with reference to FIGS. 7 to Figure 9 The structure of a pixel having a structure different from that of the above-described pixel 100 in a liquid crystal display device will be described.

[0104] Figure 7A is a top view of a pixel 300 of a multi-domain structure liquid crystal display device shown in this embodiment, Figure 7B showing Figure 7A the circuit diagram of the pixel 300 shown.

[0105] As Figure 7A and Figure 7B shown, the pixel 300 includes a scanning line 303 and a signal line 321 intersecting the scanning line 303. The signal line 321 includes a region overlapping between the pixel electrode 339a and the pixel electrode 339b. The pixel 300 further includes a capacitor wiring 305a and a capacitor wiring 305b extending in the same direction as the signal line 321. In other words, the signal line 321 does not include a region overlapping with the capacitor wiring 305a and the capacitor wiring 305b. In addition, the capacitor wiring 305a and the capacitor wiring 305b are electrically connected to the pixel electrode 339a and the pixel electrode 339b, respectively. The signal line 321 is provided between the capacitor wiring 305a and the capacitor wiring 305b.

[0106] Near the intersection of the scanning line 303 and the signal line 321, a transistor 336 and a transistor 337 are provided. The transistor 336 includes a semiconductor film 335 overlapping the scanning line 303, a sixth electrode 323a, and a seventh electrode 325a overlapping the semiconductor film 335. The sixth electrode 323a is electrically connected to the signal line 321. The sixth electrode 323a is used as one of the source electrode and the drain electrode in the transistor 336. The seventh electrode 325a is used as the other of the source electrode and the drain electrode in the transistor 336.

[0107] The transistor 337 includes a semiconductor film 335 overlapping the scanning line 303, an eighth electrode 323b, and a ninth electrode 325b overlapping the semiconductor film 335. The eighth electrode 323b is electrically connected to the signal line 321. The eighth electrode 323b is used as one of the source electrode and the drain electrode in the transistor 337. The ninth electrode 325b is used as the other of the source electrode and the drain electrode in the transistor 337.

[0108] The seventh electrode 325a included in the transistor 336 is electrically connected to the pixel electrode 339a through the opening 344a. In other words, the transistor 336 is connected to the liquid crystal element 342 including the pixel electrode 339a through the seventh electrode 325a. Further, one electrode of the capacitor element 340 is electrically connected to the pixel electrode 339a and the seventh electrode 325a of the transistor 336, and the other electrode 345a is electrically connected to the capacitor wiring 305a through the opening 346a.

[0109] The ninth electrode 325b included in the transistor 337 is electrically connected to the pixel electrode 339b through the opening 344b. In other words, the transistor 337 is connected to the liquid crystal element 343 including the pixel electrode 339b through the ninth electrode 325b. Further, one electrode of the capacitor element 341 is electrically connected to the pixel electrode 339b and the ninth electrode 325b of the transistor 337, and the other electrode 345b is electrically connected to the capacitor wiring 305b through the opening 346b.

[0110] The opening 344a and the opening 344b are provided in an insulating film 316 described later. The opening 346a and the opening 346b are provided in a gate insulating film 307 described later. Further, in order to avoid complication of the drawing, in Figure 7A no hatching is added to the pixel electrode 339a and the pixel electrode 339b, and only the outline of the top surface shape is shown by a dotted line.

[0111] The transistors 336 and 337 are located at a position substantially in the center of the pixel 300 in the top surface shape, and are formed between the pixel electrodes 339a and 339b of the respective sub-pixels in the pixel 300.

[0112] The sixth electrode 323a and the eighth electrode 323b, which are one of the source electrode and the drain electrode of the transistors 336 and 337, overlap the scanning line 303 at the overlapping portion of the signal line 321 and the scanning line 303. By adopting such a structure, in one pixel 300 constituting the display element, the parasitic capacitance generated between one electrode of the transistors 336 and 337 and the scanning line 303 can be reduced. Further, in the transistors 336 and 337, the seventh electrode 325a and the ninth electrode 325b, which are respectively used as the other of the source electrode and the drain electrode, overlap the scanning line 303.

[0113] Further, as Figure 7BAs shown, in transistor 336, parasitic capacitance C21 is generated at the overlapping portion of scan line 303 and seventh electrode 325a. Additionally, in transistor 337, parasitic capacitance C22 is generated at the overlapping portion of scan line 303 and ninth electrode 325b. Moreover, parasitic capacitance C25 is generated at the overlapping portion of signal line 321 and scan line 303. Sixth electrode 323a and eighth electrode 323b overlap with scan line 303 at the overlapping portion of signal line 321 and scan line 303. Thus, the parasitic capacitances generated at the overlapping portion of sixth electrode 323a and scan line 303 and at the overlapping portion of eighth electrode 323b and scan line 303 are included in the above-mentioned parasitic capacitance C25.

[0114] Here, pixel 300 including transistor 336 and transistor 337 is compared with pixel 100 including transistor 136 and transistor 137. Since the area of the overlapping portion of seventh electrode 325a and scan line 303 is larger than the area of the overlapping portion of second electrode 125a and scan line 103, parasitic capacitance C21 is larger than parasitic capacitance C1. Additionally, since the area of the overlapping portion of ninth electrode 325b and scan line 303 is larger than the area of the overlapping portion of third electrode 125b and scan line 103, parasitic capacitance C22 is larger than parasitic capacitance C2. Moreover, if the areas of the overlapping portion of scan line 303 and signal line 321 and the overlapping portion of scan line 103 and signal line 121 are substantially the same, parasitic capacitance C25 and parasitic capacitance C5 are substantially the same.

[0115] Furthermore, in pixel 100, parasitic capacitances C6 and C7 are respectively generated at the overlapping portion of signal line 121 and capacitance wiring 105a and at the overlapping portion of signal line 121 and capacitance wiring 105b. On the other hand, in pixel 300, signal line 321 does not include regions overlapping with capacitance wiring 305a and capacitance wiring 305b. Thus, no parasitic capacitances are generated between signal line 321 and capacitance wiring 305a and between signal line 321 and capacitance wiring 305b.

[0116] In a liquid crystal display device including a plurality of pixels, the parasitic capacitance that causes signal transmission delay in a signal line has less influence on the signal transmission delay when it is generated in a portion closer to the end of the transistor in the signal transmission path. For example, in pixel 100, compared with the parasitic capacitance C6 generated at the overlapping portion of the signal line 121 and the capacitance wiring 105a, the parasitic capacitance C1 generated at the overlapping portion of the scanning line 103 and the second electrode 125a has less influence on the signal transmission delay of the signal line 121. This is because: in a liquid crystal display device, if it is the parasitic capacitance C6, the parasitic capacitances C6 of the same number as the capacitance wirings overlapping one signal line 121 affect signal transmission, however, if it is the parasitic capacitance C1, it affects signal transmission when one transistor 136 connected to one signal line 121 is in the on state. Therefore, although the parasitic capacitance of pixel 300 is larger than that of pixel 100, the difference is equal to the difference between the parasitic capacitance C21 and the parasitic capacitance C1 and the difference between the parasitic capacitance C22 and the parasitic capacitance C2, but in pixel 300, the parasitic capacitances C6 and C7 generated in pixel 100 are not generated, so the parasitic capacitance that causes signal transmission delay in the signal lines included in the liquid crystal display device can be reduced.

[0117] In addition, as Figure 7C shown, the end of the semiconductor film 335 can also be extended in the extending direction of the signal line 321, and the seventh electrode 325a and the ninth electrode 325b can be arranged such that the areas of the overlapping portions of the seventh electrode 325a and the ninth electrode 325b with the scanning line 303 are small. By adopting such a structure, the above-mentioned parasitic capacitances C21 and C22 can be reduced. In addition, as Figure 7D shown, the semiconductor film 335 can also be arranged such that in a top view, the end of the semiconductor film 335 is located outside the overlapping portion of the signal line 321 and the scanning line 303. By forming the semiconductor film 335 between the signal line 321 and the scanning line 303 in addition to the gate insulating film 307, sometimes the parasitic capacitance generated at the overlapping portion of the signal line 321 and the scanning line 303 can be reduced.

[0118] In addition, as Figure 8A and Figure 8B shown, in pixel 300, a structure in which adjacent pixels share the capacitance wirings 305a and 305b can also be adopted. By adopting such a structure, the number of capacitance wirings included in the display device can be reduced. In addition, as Figure 8A shown, by increasing the area of the overlapping portion of the pixel electrode 339a and the capacitance wiring 305a, the capacitance of the capacitive element 340 can be increased. Similarly, by increasing the area of the overlapping portion of the pixel electrode 339b and the capacitance wiring 305b, the capacitance of the capacitive element 341 can be increased.

[0119] Next, with reference to Figure 9 the structures of the transistor and the capacitor element included in pixel 300 will be described.

[0120] Figure 9 Shown is Figure 7A the cross-sectional structures of transistor 336 and capacitor element 340 between the dotted lines C-D shown.

[0121] Transistor 336 includes a scan line 303, a semiconductor film 335, a gate insulating film 307 provided between the scan line 303 and the semiconductor film 335, a sixth electrode 323a in contact with the semiconductor film 335, and a seventh electrode 325a in contact with the semiconductor film 335 on a substrate 301.

[0122] Capacitor element 340 includes an electrode 345a, a seventh electrode 325a, and a gate insulating film 307 provided between the electrode 345a and the seventh electrode 325a on a substrate 301.

[0123] In addition, a capacitor wiring 305a electrically connected to the electrode 345a through an opening 346a provided in the gate insulating film 307 is provided on the gate insulating film 307. An insulating film 316 is provided on the gate insulating film 307, the semiconductor film 335, the sixth electrode 323a, the seventh electrode 325a, and the capacitor wiring 305a. A pixel electrode 339a electrically connected to the seventh electrode 325a through an opening 344a provided in the insulating film 316 is provided on the insulating film 316.

[0124] Although not shown, transistor 337 has the same structure as transistor 336. In addition, capacitor element 341 and capacitor element 340 are composed of the same constituent elements.

[0125] Each layer constituting transistor 336 and capacitor element 340 has the same material and laminated structure as each layer constituting transistor 136 and capacitor element 140. In addition, as the insulating film 316 and the pixel electrode 339a, the same materials as the insulating film 116 and the pixel electrode 139a can be used respectively. In addition, as the electrode 345a and the capacitor wiring 305a, the same materials as the scan line 303 and the sixth electrode 323a are used respectively.

[0126] A more detailed structure and manufacturing method of transistor 336 will be described in Embodiment 2. By using the transistor described in Embodiment 2 for pixel 300 described in this embodiment, the power consumption of a display device according to one aspect of the present invention can be reduced.

[0127] When including the pixel 100 or the pixel 300 described in this embodiment, the multi-domain structure liquid crystal display device can reduce the parasitic capacitance generated between the scan line and the signal line (in other words, between the scan line used as the gate electrode of the transistor and the signal line used as one of the source electrode and the drain electrode of the transistor). In addition, when including the pixel 300 described in this embodiment, the multi-domain structure liquid crystal display device can reduce the parasitic capacitance generated between the signal line and the capacitance wiring. Therefore, in particular, the display quality of a large liquid crystal display device, a liquid crystal display device capable of high-speed driving, and a liquid crystal display device with high resolution can be improved. In addition, the power consumption of the liquid crystal display device can be reduced.

[0128] In addition, although a structure in which two transistors are provided in one pixel is shown in this embodiment, it is not limited thereto. One pixel may also include three or more transistors and a plurality of pixel electrodes connected to the transistors.

[0129] The structure shown in this embodiment can be implemented by appropriately combining with the structures shown in other embodiments.

[0130] Embodiment 2

[0131] In this embodiment, with reference to FIGS. 10 to Figure 18 a semiconductor device and a method of manufacturing the semiconductor device according to one aspect of the present invention will be described.

[0132] <Structural Example 1 of Semiconductor Device>

[0133] Figure 14C is a top view of a transistor 500 of a semiconductor device according to one aspect of the present invention, Figure 14B corresponding to a cross-sectional view along the cut surface of the dotted line X1-X2 shown in Figure 14C and a cross-sectional view of the cut surface of the dotted line Y1-Y2. In addition, Figures 10A to 14A is to illustrate Figure 14B a cross-sectional view of the manufacturing process of the transistor 500 shown.

[0134] In addition, in Figure 14C , for convenience, a part of the components of the transistor 500 (such as the insulating film used as the gate insulating film) is omitted. In addition, the direction of the dotted line X1-X2 is sometimes referred to as the channel length direction, and the direction of the dotted line Y1-Y2 is sometimes referred to as the channel width direction. Note that sometimes a part of the components may also be omitted in the same manner as in Figure 14C the top view of the transistor later.

[0135] The transistor 500 includes: a conductive film 504 serving as a gate electrode on a substrate 502; an insulating film 506 on the substrate 502 and the conductive film 504; an insulating film 507 on the insulating film 506; an oxide semiconductor film 508 on the insulating film 507; a conductive film 512a serving as a source electrode electrically connected to the oxide semiconductor film 508; and a conductive film 512b serving as a drain electrode electrically connected to the oxide semiconductor film 508. Additionally, on the transistor 500, specifically, insulating films 514, 516, and 518 are provided on the conductive films 512a, 512b, and the oxide semiconductor film 508. The insulating films 514, 516, and 518 function as protective insulating films of the transistor 500. Note that the insulating film 514 is sometimes referred to as the first protective insulating film, and the insulating film 516 is sometimes referred to as the second protective insulating film.

[0136] Furthermore, the oxide semiconductor film 508 includes a first oxide semiconductor film 508a on the side of the conductive film 504 serving as a gate electrode and a second oxide semiconductor film 508b on the first oxide semiconductor film 508a. Additionally, the insulating film 506 and the insulating film 507 function as the gate insulating film of the transistor 500.

[0137] As the oxide semiconductor film 508, In-M (where M is aluminum, gallium, yttrium, or tin) oxide or In-M-Zn oxide can be used. In particular, In-M-Zn oxide is preferably used as the oxide semiconductor film 508.

[0138] Additionally, the first oxide semiconductor film 508a preferably contains an oxide with a higher atomic ratio of In to the atomic ratio of M compared to the second oxide semiconductor film 508b.

[0139] By making the first oxide semiconductor film 508a have a composition with an atomic ratio of In greater than the atomic ratio of M, the field-effect mobility (sometimes simply referred to as mobility or μFE) of the transistor 500 can be increased. Specifically, the field-effect mobility of the transistor 500 can exceed 10 cm 2 / Vs, and preferably, it exceeds 30 cm 2 / Vs.

[0140] For example, by using the transistor with the above high field-effect mobility for a gate driver that generates a gate signal (specifically, a demultiplexer connected to the output terminal of a shift register included in the gate driver), a semiconductor device or a display device with a narrow border width (also referred to as a narrow border) can be provided.

[0141] On the other hand, by making the composition of the first oxide semiconductor film 508a such that the atomic ratio of In is greater than the atomic ratio of M, the electrical characteristics of the transistor 500 during light irradiation are likely to change. However, in a semiconductor device according to one embodiment of the present invention, a second oxide semiconductor film 508b is formed on the first oxide semiconductor film 508a. Since the second oxide semiconductor film 508b has a composition with an atomic ratio of In less than that of the first oxide semiconductor film 508a, its bandgap Eg is greater than that of the first oxide semiconductor film 508a. Therefore, the resistance of the oxide semiconductor film 508 having a stacked structure of the first oxide semiconductor film 508a and the second oxide semiconductor film 508b to the light negative bias stress test becomes higher.

[0142] By using the oxide semiconductor film having the above structure, the light absorption amount of the oxide semiconductor film 508 during light irradiation can be reduced. Therefore, it is possible to suppress the change in the electrical characteristics of the transistor 500 during light irradiation.

[0143] In addition, when oxygen defects are formed in the oxide semiconductor film 508 included in the transistor 500, electrons are generated as carriers, and thus it easily becomes a normally-on characteristic. Note that the normally-on characteristic of a transistor means a characteristic in which a current (for example, a current between the drain and the source (Ids)) flows when the gate voltage Vg = 0V. Thus, in order to obtain stable transistor characteristics, it is important to reduce the oxygen defects in the oxide semiconductor film 508, particularly to reduce the oxygen defects in the first oxide semiconductor film 508a. Then, in the structure of a transistor according to one embodiment of the present invention, by introducing excess oxygen into the insulating film on the oxide semiconductor film 508, here, into the insulating film 514 and / or the insulating film 516 on the oxide semiconductor film 508, oxygen is moved from the insulating film 514 and / or the insulating film 516 into the oxide semiconductor film 508, thereby filling the oxygen defects in the oxide semiconductor film 508, particularly the oxygen defects in the first oxide semiconductor film 508a. Alternatively, when the first barrier film 531 is formed on the insulating film 516, excess oxygen is introduced into the insulating film 516, and oxygen is moved from the insulating film 516 into the oxide semiconductor film 508, thereby filling the oxygen defects in the oxide semiconductor film 508, particularly the oxygen defects in the first oxide semiconductor film 508a.

[0144] In addition, the insulating films 514 and 516 more preferably have regions (oxygen-excess regions) containing oxygen in excess of the stoichiometric composition. In other words, the insulating films 514 and 516 are insulating films capable of releasing oxygen. Further, in order to provide oxygen-excess regions in the insulating films 514 and 516, for example, oxygen is introduced into the formed insulating films 514 and 516 to form oxygen-excess regions. As a method for introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

[0145] In addition, in order to fill oxygen defects in the first oxide semiconductor film 508a, it is preferable to form the vicinity of the channel region of the second oxide semiconductor film 508b thinly. For example, the thickness of the vicinity of the channel region of the second oxide semiconductor film 508b is preferably 1 nm or more and 20 nm or less, more preferably 3 nm or more and 10 nm or less.

[0146] In addition, in order to fill oxygen defects in the first oxide semiconductor film 508a, it is preferable that the second oxide semiconductor film 508b has high oxygen permeability. By making the second oxide semiconductor film 508b have high oxygen permeability, excess oxygen in the insulating film 514 and the insulating film 516 can be effectively permeated into the first oxide semiconductor film 508a.

[0147] Thus, in the semiconductor device according to one embodiment of the present invention, by making the oxide semiconductor film have a stacked structure and making the insulating film in contact with the oxide semiconductor film contain excess oxygen, a semiconductor device with high reliability can be provided. And, in one embodiment of the present invention, the temperature in the manufacturing process of the semiconductor device having the above structure can be reduced (typically below 400°C or below 375°C (preferably 340°C or more and 360°C or less)). In addition, the manufacturing process of the semiconductor device will be described later.

[0148] Next, other components included in the semiconductor device of the present embodiment will be described in detail.

[0149] <Substrate>

[0150] Although there is no particular limitation on the material of the substrate 502, etc., it is at least necessary to have heat resistance capable of withstanding subsequent heat treatment. For example, as the substrate 502, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. can be used. In addition, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate made of silicon germanium, etc., an SOI (Silicon On Insulator) substrate, etc. can also be used, and a substrate on which semiconductor elements are provided can also be used as the substrate 502. When a glass substrate is used as the substrate 502, a large display device can be manufactured by using a large area substrate such as the 6th generation, 7th generation, 8th generation, 9th generation, 10th generation, etc. By using such a large area substrate, the manufacturing cost can be reduced, so it is preferable.

[0151] As the substrate 502, a flexible substrate can also be used, and the transistor 500 can be directly formed on the flexible substrate. Alternatively, a release layer can be provided between the substrate 502 and the transistor 500. The release layer can be used in the following cases, that is, when a part or all of the semiconductor device is manufactured on the release layer and then separated from the substrate 502 and transposed to another substrate. At this time, the transistor 500 can also be transposed to a substrate with low heat resistance or a flexible substrate.

[0152] <Conductive films used as gate electrodes, source electrodes, and drain electrodes>

[0153] As the conductive film 504 used as the gate electrode, the conductive film 512a used as the source electrode, and the conductive film 512b used as the drain electrode, metal elements selected from chromium (Cr), copper (Cu), aluminum (Al), gold (Au), silver (Ag), zinc (Zn), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), manganese (Mn), nickel (Ni), iron (Fe), cobalt (Co), alloys composed of the above metal elements, or alloys combining the above metal elements can be used to form them.

[0154] In addition, the conductive films 504, 512a, and 512b can also have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked on an aluminum film, a two-layer structure in which a titanium film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a titanium nitride film, a two-layer structure in which a tungsten film is stacked on a tantalum nitride film or a tungsten nitride film, and a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in sequence can be cited. In addition, an alloy film or a nitride film formed by combining aluminum with one or more selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium can also be used.

[0155] As the conductive films 504, 512a, and 512b, transparent conductive materials such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon oxide can also be used.

[0156] In addition, as the conductive films 504, 512a, and 512b, a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti) can also be applied. By using the Cu-X alloy film, it can be processed through a wet etching process, thereby suppressing the manufacturing cost.

[0157] <Insulating film used as a gate insulating film>

[0158] As the insulating films 506 and 507 serving as the gate insulating film of the transistor 500, insulating films including one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film formed by a plasma enhanced chemical vapor deposition (PECVD) method, a sputtering method, or the like can be used, respectively. Note that a single-layer or three-layer or more insulating film selected from the above materials can also be used instead of the stacked structure of the insulating films 506 and 507.

[0159] The insulating film 506 has a function of a barrier film that inhibits oxygen permeation. For example, when excessive oxygen is supplied to the insulating films 507, 114, 516, and / or the oxide semiconductor film 508, the insulating film 506 can inhibit oxygen permeation.

[0160] The insulating film 507 in contact with the oxide semiconductor film 508 serving as the channel region of the transistor 500 is preferably an oxide insulating film, and more preferably includes a region (oxygen-excess region) containing oxygen in excess of the stoichiometric composition. In other words, the insulating film 507 is an insulating film capable of releasing oxygen. In order to provide an oxygen-excess region in the insulating film 507, for example, the insulating film 507 can be formed in an oxygen atmosphere. Alternatively, oxygen can be introduced into the formed insulating film 507 to form an oxygen-excess region. As a method of introducing oxygen, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, or the like can be used.

[0161] In addition, when hafnium oxide is used as the insulating film 507, the following effects are exhibited. The relative dielectric constant of hafnium oxide is higher than that of silicon oxide or silicon oxynitride. Therefore, the thickness of the insulating film 507 can be made larger than in the case of using silicon oxide or silicon oxynitride, and thus, leakage current caused by tunneling current can be reduced. That is, a transistor with a small off-state current can be realized. Furthermore, the relative dielectric constant of hafnium oxide having a crystalline structure is higher than that of hafnium oxide having an amorphous structure. Therefore, in order to form a transistor with a small off-state current, it is preferable to use hafnium oxide including a crystalline structure. Examples of the crystalline structure include a monoclinic system or a cubic system. Note that one embodiment of the present invention is not limited thereto.

[0162] Note that, in the present embodiment, a silicon nitride film is formed as the insulating film 506, and a silicon oxide film is formed as the insulating film 507. Compared with the silicon oxide film, the silicon nitride film has a relatively high relative dielectric constant and requires a larger thickness to obtain the same capacitance as the silicon oxide film. Therefore, by including the silicon nitride film in the gate insulating film of the transistor 500, the physical thickness of the insulating film can be increased. Therefore, the electrostatic breakdown of the transistor 500 can be suppressed by suppressing the decrease in the withstand voltage of the insulation of the transistor 500 and improving the withstand voltage of the insulation.

[0163] <Oxide semiconductor film>

[0164] The above materials can be used as the oxide semiconductor film 508. When the oxide semiconductor film 508 is In-M-Zn oxide, the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In≥M and Zn≥M. The atomic ratio of the metal elements of such a sputtering target is preferably In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1. In addition, when the oxide semiconductor film 508 is In-M-Zn oxide, a target containing polycrystalline In-M-Zn oxide is preferably used as the sputtering target. By using a target containing polycrystalline In-M-Zn oxide, it is easy to form the oxide semiconductor film 508 having crystallinity. Note that the atomic ratio of the formed oxide semiconductor film 508 includes an error within the range of ±40% of the atomic ratio of the metal elements in the above sputtering target. For example, when the atomic ratio of the sputtering target is In:Ga:Zn = 4:2:4.1, the atomic ratio of the formed oxide semiconductor film 508 may be around In:Ga:Zn = 4:2:3.

[0165] For example, the first oxide semiconductor film 508a can be formed using the above sputtering targets such as In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:4.1. The atomic ratio of the first oxide semiconductor film 508a is preferably In:M:Zn = 4:α1(1.5≤α1≤2.5):α2(2.5≤α2≤3.5).

[0166] In addition, the second oxide semiconductor film 508b can be formed using the above-mentioned sputtering targets such as In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, etc. The atomic ratio of the second oxide semiconductor film 508b is preferably In:M:Zn = 1:β1 (0.8 ≤ β1 ≤ 1.2):β2 (0.8 ≤ β2 ≤ 1.2). Additionally, as the atomic ratio of the metal elements of the sputtering target for the second oxide semiconductor film 508b, it is not necessarily required to satisfy both In ≥ M and Zn ≥ M simultaneously, and it can also satisfy In < M and / or Zn < M. Specifically, examples include In:M:Zn = 1:3:2, In:M:Zn = 1:3:4, In:M:Zn = 1:3:6, etc.

[0167] The energy gap of the oxide semiconductor film 508 is 2 eV or more, preferably 2.5 eV or more, and more preferably 3 eV or more. Thus, by using an oxide semiconductor with a relatively wide energy gap, the off-state current of the transistor 500 can be reduced. In particular, an oxide semiconductor film with an energy gap of 2.0 eV or more, preferably 2.0 eV or more and 3.0 eV or less, is used as the first oxide semiconductor film 508a, and an oxide semiconductor film with an energy gap of 2.5 eV or more and 3.5 eV or less is used as the second oxide semiconductor film 508b. In addition, it is preferable that the energy gap of the second oxide semiconductor film 508b is greater than the energy gap of the first oxide semiconductor film 508a.

[0168] In addition, the thicknesses of the first oxide semiconductor film 508a and the second oxide semiconductor film 508b are each 3 nm or more and 200 nm or less, preferably each 3 nm or more and 100 nm or less, and more preferably each 3 nm or more and 50 nm or less.

[0169] In addition, an oxide semiconductor film with a low carrier density is used as the first oxide semiconductor film 508a. For example, the carrier density of the first oxide semiconductor film 508a can be less than 8×10 11 / cm 3 , preferably less than 1×10 11 / cm 3 , more preferably less than 1×10 10 / cm 3 , and 1×10 -9 / cm 3 or more. In addition, an oxide semiconductor film with a relatively low carrier density is used as the second oxide semiconductor film 508b. For example, the carrier density of the second oxide semiconductor film 508b can be 1×10 17 / cm 3 or less, preferably 1×10 15 / cm 3 or less, more preferably 1×10 13 / cm3 Hereinafter, it is further preferably 1×10 11 / cm 3 Hereinafter.

[0170] The present invention is not limited to the above description, and materials having an appropriate composition can be used according to the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the required transistors. In addition, it is preferable to appropriately set the carrier density, impurity concentration, defect density, atomic number ratio of metal element to oxygen, interatomic distance, density, etc. of the first oxide semiconductor film 508a and the second oxide semiconductor film 508b to obtain the semiconductor characteristics of the required transistors.

[0171] By using an oxide semiconductor film with a low impurity concentration and a low defect state density as the first oxide semiconductor film 508a and the second oxide semiconductor film 508b, a transistor with more excellent electrical characteristics can be manufactured, so it is preferable. Here, a state with a low impurity concentration and a low defect state density (few oxygen defects) is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic". Since the carrier generation sources of the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film are few, the carrier density can be reduced. Therefore, a transistor having a channel region formed in the oxide semiconductor film rarely has an electrical characteristic of a negative threshold voltage (also referred to as a normally-on characteristic). Since the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film has a low defect state density, it is possible to have a low trap state density. The off-state current of the high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film is significantly low. Even for an element with a channel width of 1×10 6 μm and a channel length L of 10 μm, when the voltage (drain voltage) between the source electrode and the drain electrode is in the range of 1 V to 10 V, the off-state current can also be below the measurement limit of the semiconductor parameter analyzer, that is, 1×10 -13 A or less.

[0172] Therefore, a transistor having a channel region formed in the above high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor film can be a transistor with small electrical characteristic variations and high reliability. In addition, it takes a long time for the charge trapped in the trap energy level of the oxide semiconductor film to disappear, and sometimes it behaves like a fixed charge. Therefore, sometimes the electrical characteristics of a transistor having a channel region formed in an oxide semiconductor film with a high trap state density are unstable. Examples of impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals.

[0173] Hydrogen contained in the oxide semiconductor film reacts with oxygen bonded to metal atoms to generate water, and at the same time, oxygen defects are formed in the lattice (or the oxygen-depleted part) where oxygen detachment occurs. When hydrogen enters the oxygen defect, electrons serving as carriers are sometimes generated. In addition, sometimes electrons serving as carriers are generated because a part of hydrogen bonds with oxygen bonded to metal atoms. Therefore, a transistor using an oxide semiconductor film containing hydrogen easily has normally-on characteristics. Thus, it is preferable to minimize hydrogen in the oxide semiconductor film 508 as much as possible. Specifically, in the oxide semiconductor film 508, the hydrogen concentration measured by SIMS (Secondary Ion Mass Spectrometry) is 2×10 20 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or less, more preferably 1×10 19 atoms / cm 3 or less, more preferably 5×10 18 atoms / cm 3 or less, more preferably 1×10 18 atoms / cm 3 or less, more preferably 5×10 17 atoms / cm 3 or less, more preferably 1×10 16 atoms / cm 3 or less.

[0174] In addition, the first oxide semiconductor film 508a preferably includes a portion having a hydrogen concentration lower than that of the second oxide semiconductor film 508b. By making the first oxide semiconductor film 508a include a portion having a hydrogen concentration lower than that of the second oxide semiconductor film 508b, a semiconductor device with high reliability can be provided.

[0175] In addition, when the first oxide semiconductor film 508a contains silicon or carbon, which is one of the Group 14 elements, oxygen defects increase in the first oxide semiconductor film 508a, resulting in n-type conversion of the first oxide semiconductor film 508a. Therefore, the concentration of silicon or carbon in the first oxide semiconductor film 508a and the concentration of silicon or carbon near the interface with the first oxide semiconductor film 508a (the concentration measured by SIMS analysis) are 2×10 18 atoms / cm 3 or less, preferably 2×10 17 atoms / cm 3 or less.

[0176] In addition, in the first oxide semiconductor film 508a, the concentration of alkali metal or alkaline earth metal measured by SIMS analysis is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. When an alkali metal or an alkaline earth metal bonds to an oxide semiconductor, carriers are sometimes generated, increasing the off-state current of the transistor. Therefore, it is preferable to reduce the concentration of alkali metal or alkaline earth metal in the first oxide semiconductor film 508a.

[0177] When nitrogen is contained in the first oxide semiconductor film 508a, electrons as carriers are generated, and the carrier density increases, resulting in n-type conversion of the first oxide semiconductor film 508a. As a result, a transistor using an oxide semiconductor film containing nitrogen easily has normally-on characteristics. Therefore, it is preferable to minimize nitrogen in the oxide semiconductor film as much as possible. For example, the nitrogen concentration measured by SIMS analysis is preferably 5×10 18 atoms / cm 3 or less.

[0178] The first oxide semiconductor film 508a and the second oxide semiconductor film 508b may each have a non-single crystal structure. The non-single crystal structure includes, for example, the following CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor), polycrystalline structure, microcrystalline structure, or amorphous structure. Among the non-single crystal structures, the amorphous structure has the highest density of defect states, and the CAAC-OS has the lowest density of defect states.

[0179] Here, with reference to Figure 18 the energy band structure of the oxide semiconductor film 508 and the insulating film in contact with the oxide semiconductor film 508 will be described.

[0180] Figure 18 is an example of the energy band structure in the film thickness direction of a stacked structure, and the stacked structure has an insulating film 507, a first oxide semiconductor film 508a, a second oxide semiconductor film 508b, and an insulating film 514. In the energy band structure, for easy understanding, the bottom energy levels (Ec) of the conduction bands of the insulating film 507, the first oxide semiconductor film 508a, the second oxide semiconductor film 508b, and the insulating film 514 are shown.

[0181] In Figure 18In the energy band diagram shown, a silicon oxide film is used as the insulating film 507 and the insulating film 514, and an oxide semiconductor film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 4:2:4.1 is used as the first oxide semiconductor film 508a, and a metal oxide film formed using a metal oxide target with an atomic ratio of metal elements of In:Ga:Zn = 1:1:1.2 is used as the second oxide semiconductor film 508b.

[0182] As Figure 18 shown, in the first oxide semiconductor film 508a and the second oxide semiconductor film 508b, the bottom energy level of the conduction band changes gently. In other words, the bottom energy level of the conduction band changes continuously or is continuously joined. In order to achieve such an energy band structure, impurities that form defect energy levels such as trap centers or recombination centers do not exist at the interface between the first oxide semiconductor film 508a and the second oxide semiconductor film 508b.

[0183] In order to form a continuous junction between the first oxide semiconductor film 508a and the second oxide semiconductor film 508b, a multi-chamber film formation apparatus (sputtering apparatus) equipped with a loading lock chamber can be used to continuously stack the films in such a way that each film is not exposed to the atmosphere.

[0184] It can be seen that by adopting Figure 18 the structure shown, the first oxide semiconductor film 508a serves as a well, and in a transistor using the above-mentioned stacked structure, a channel region is formed in the first oxide semiconductor film 508a.

[0185] In addition, when the second oxide semiconductor film 508b is not formed, trap energy levels may be formed in the first oxide semiconductor film 508a. On the other hand, by adopting the above-mentioned stacked structure, the trap energy levels may be formed in the second oxide semiconductor film 508b. Therefore, the trap energy levels can be made far from the first oxide semiconductor film 508a.

[0186] In addition, sometimes the trap energy level is farther from the vacuum energy level than the bottom energy level (Ec) of the conduction band of the first oxide semiconductor film 508a used as the channel region, and electrons are likely to accumulate in the trap energy level. When electrons accumulate in the trap energy level, they become negative fixed charges, causing the threshold voltage of the transistor to drift in the positive direction. Therefore, a structure in which the trap energy level is closer to the vacuum energy level than the bottom energy level (Ec) of the first oxide semiconductor film 508a is preferably adopted. By adopting the above structure, electrons are not easily accumulated in the trap energy level, so the on-state current of the transistor can be increased, and the field effect mobility can also be improved.

[0187] In Figure 18In this case, the bottom energy level of the conduction band of the second oxide semiconductor film 508b is closer to the vacuum energy level than that of the first oxide semiconductor film 508a. Typically, the difference between the bottom energy level of the conduction band of the first oxide semiconductor film 508a and that of the second oxide semiconductor film 508b is 0.15 eV or more, or 0.5 eV or more, and is 2 eV or less, or 1 eV or less. In other words, the difference between the electron affinity of the second oxide semiconductor film 508b and that of the first oxide semiconductor film 508a is 0.15 eV or more, or 0.5 eV or more, and is 2 eV or less, or 1 eV or less.

[0188] By adopting the above structure, the first oxide semiconductor film 508a becomes the main path of the current and is used as the channel region. Since the second oxide semiconductor film 508b contains one or more of the metal elements included in the first oxide semiconductor film 508a in which the channel region is formed, it is not easy to generate interface scattering at the interface between the first oxide semiconductor film 508a and the second oxide semiconductor film 508b. Thus, since the movement of carriers is not hindered at this interface, the field-effect mobility of the transistor is improved.

[0189] In order to prevent the second oxide semiconductor film 508b from being used as a part of the channel region, a material with a sufficiently low conductivity is used for the second oxide semiconductor film 508b. Alternatively, a material is used for the second oxide semiconductor film 508b whose electron affinity (the difference between the vacuum energy level and the bottom energy level of the conduction band) is lower than that of the first oxide semiconductor film 508a and whose bottom energy level of the conduction band is different (energy band offset) from that of the first oxide semiconductor film 508a. In addition, in order to suppress the generation of the difference between the threshold voltages due to the drain voltage value, it is preferable to use a material in which the bottom energy level of the conduction band of the second oxide semiconductor film 508b is closer to the vacuum energy level by 0.2 eV or more, preferably 0.5 eV or more, than that of the first oxide semiconductor film 508a.

[0190] It is preferable that the second oxide semiconductor film 508b does not contain a spinel-type crystal structure. When the second oxide semiconductor film 508b contains a spinel-type crystal structure, the constituent elements of the conductive films 512a and 512b may diffuse into the first oxide semiconductor film 508a at the interface between the spinel-type crystal structure and other regions. Note that when the second oxide semiconductor film 508b is CAAC-OS described later, the property of blocking the constituent elements such as copper elements of the conductive films 512a and 512b is improved, so it is preferable.

[0191] The thickness of the second oxide semiconductor film 508b is greater than or equal to the thickness that can inhibit the diffusion of the constituent elements of the conductive films 512a and 512b into the oxide semiconductor film 508b and less than the thickness at which the supply of oxygen from the insulating film 514 to the oxide semiconductor film 508b is inhibited. For example, when the thickness of the second oxide semiconductor film 508b is 10 nm or more, the diffusion of the constituent elements of the conductive films 512a and 512b into the first oxide semiconductor film 508a can be inhibited. In addition, when the thickness of the second oxide semiconductor film 508b is 100 nm or less, oxygen can be effectively supplied from the insulating films 514 and 516 to the first oxide semiconductor film 508a.

[0192] <An insulating film serving as a protective insulating film of a transistor>

[0193] The insulating films 514 and 516 have a function of supplying oxygen to the oxide semiconductor film 508. The insulating film 518 has a function of a protective insulating film of the transistor 500. The insulating films 514 and 516 contain oxygen. The insulating film 514 is an insulating film that can allow oxygen to permeate. Note that the insulating film 514 also serves as a film that alleviates damage to the oxide semiconductor film 508 when the insulating film 516 is formed later.

[0194] As the insulating film 514, silicon oxide, silicon oxynitride, etc. with a thickness of 5 nm or more and 150 nm or less, preferably 5 nm or more and 50 nm or less can be used.

[0195] In addition, it is preferable that the amount of defects in the insulating film 514 is small. Typically, the spin density of the signal presented at g = 2.001 due to silicon dangling bonds measured by ESR (Electron Spin Resonance) is preferably 3×10 17 spins / cm 3 or less. This is because if the defect density of the insulating film 514 is high, oxygen bonds to the defects, reducing the amount of oxygen permeating through the insulating film 514.

[0196] In the insulating film 514, sometimes not all of the oxygen that enters the insulating film 514 from the outside moves to the outside of the insulating film 514, but a part of it remains inside the insulating film 514. In addition, sometimes while oxygen enters the insulating film 514, the oxygen contained in the insulating film 514 moves to the outside of the insulating film 514, and oxygen movement occurs in the insulating film 514. When forming an oxide insulating film that can allow oxygen to permeate as the insulating film 514, the oxygen detached from the insulating film 516 provided on the insulating film 514 can move through the insulating film 514 into the oxide semiconductor film 508.

[0197] In addition, the insulating film 514 can be formed using an oxide insulating film having a low state density of nitride oxide. Note that the state density of the nitride oxide may be formed at an energy level (E ) at the top of the valence band of the oxide semiconductor film. V_OS ) and the energy of the conduction band bottom of the oxide semiconductor film (E C_OS ). As E v_os and E c_os As an oxide insulating film having a low state density of nitride oxides, a silicon oxynitride film having a small amount of nitride oxides released or an aluminum oxynitride film having a small amount of nitride oxides released can be used.

[0199] In addition, in thermal desorption spectrum analysis, the silicon oxynitride film with a small amount of nitrogen oxide release is a film that releases more ammonia than nitrogen oxide. Typically, the amount of ammonia molecules released is 1×10 18 Molecules / cm 3 Above and 5×10 19 Molecules / cm 3 Note that the amount of ammonia released is the amount released when the film surface temperature is heated to a temperature of 50° C. to 650° C., preferably 50° C. to 550° C.

[0200] Nitrogen oxides (NO x , x is greater than or equal to 0 and less than or equal to 2, preferably greater than or equal to 1 and less than or equal to 2), typically NO 2 Or NO forms an energy level in the insulating film 514 or the like. This energy level is located in the energy gap of the oxide semiconductor film 508. Therefore, when the nitrogen oxide diffuses to the interface between the insulating film 514 and the oxide semiconductor film 508, this energy level sometimes captures electrons on the insulating film 514 side. As a result, the captured electrons remain near the interface between the insulating film 514 and the oxide semiconductor film 508, thereby causing the threshold voltage of the transistor to drift in the positive direction.

[0201] In addition, when heat treatment is performed, nitrogen oxide reacts with ammonia and oxygen. When heat treatment is performed, nitrogen oxide contained in the insulating film 514 reacts with ammonia contained in the insulating film 516, thereby reducing nitrogen oxide contained in the insulating film 514. Therefore, electrons are not easily captured at the interface between the insulating film 514 and the oxide semiconductor film 508.

[0202] By using E as the insulating film 514 v os and E c os The state density of nitrogen oxides between

[0203] --The oxide insulating film can reduce the drift of the threshold voltage of the transistor, thereby reducing the variation of the electrical characteristics of the transistor.

[0204] By performing a heat treatment in the manufacturing process of a transistor, typically a heat treatment at a temperature below 400 °C or below 375 °C (preferably 340 °C or higher and 360 °C or lower), in the spectrum of the insulating film 514 measured by ESR at 100 K or lower, a first signal with a g-value of 2.037 or higher and 2.039 or lower, a second signal with a g-value of 2.001 or higher and 2.003 or lower, and a third signal with a g-value of 1.964 or higher and 1.966 or lower are observed. In the X-band ESR measurement, the split width between the first signal and the second signal and the split width between the second signal and the third signal are approximately 5 mT. Additionally, the total spin density of the first signal with a g-value of 2.037 or higher and 2.039 or lower, the second signal with a g-value of 2.001 or higher and 2.003 or lower, and the third signal with a g-value of 1.964 or higher and 1.966 or lower is lower than 1×10 18 spins / cm 3 , typically 1×10 17 spins / cm 3 or higher and lower than 1×10 18 spins / cm 3 .

[0205] In the ESR spectrum at 100 K or lower, the first signal with a g-value of 2.037 or higher and 2.039 or lower, the second signal with a g-value of 2.001 or higher and 2.003 or lower, and the third signal with a g-value of 1.964 or higher and 1.966 or lower correspond to signals caused by nitrogen oxides (NO x , where x is 0 or higher and 2 or lower, preferably 1 or higher and 2 or lower). Typical examples of nitrogen oxides include nitric oxide, nitrogen dioxide, etc. That is, the lower the total spin density of the first signal with a g-value of 2.037 or higher and 2.039 or lower, the second signal with a g-value of 2.001 or higher and 2.003 or lower, and the third signal with a g-value of 1.964 or higher and 1.966 or lower, the lower the content of nitrogen oxides in the oxide insulating film.

[0206] Additionally, for the oxide insulating film with a low density of states of nitrogen oxides between E v_os and E c_os , the nitrogen concentration measured by SIMS is 6×10

[0208] atoms / cm 20 or less. 3

[0209] By forming E v_os and E c_os using the PECVD method with silane and nitrous oxide at a substrate temperature of 220 °C or higher and 350 °C or lowerAn oxide insulating film with a low density of states of nitrogen oxides between them can form a dense and hard film.

[0211] The insulating film 516 is formed using an oxide insulating film whose oxygen content exceeds the stoichiometric composition. Due to heating, a part of the oxygen in the oxide insulating film whose oxygen content exceeds the stoichiometric composition is released. By TDS analysis, the oxygen release amount of the oxide insulating film whose oxygen content exceeds the stoichiometric composition, converted to oxygen atoms, is 1.0×10 19 atoms / cm 3 or more, preferably 3.0×10 20 atoms / cm 3 or more. Note that the surface temperature of the film during the above TDS analysis is preferably 100°C or more and 700°C or less, or 100°C or more and 500°C or less.

[0212] As the insulating film 516, a silicon oxide film, a silicon oxynitride film, etc. with a thickness of 30 nm or more and 500 nm or less, preferably 50 nm or more and 400 nm or less can be used.

[0213] In addition, it is preferable that the amount of defects in the insulating film 516 is small. Typically, the spin density of the signal presented at g = 2.001 due to silicon dangling bonds measured by ESR is less than 1.5×10 18 spins / cm 3 , more preferably 1×10 18 spins / cm 3 or less. Since the insulating film 516 is farther from the oxide semiconductor film 508 than the insulating film 514, the defect density of the insulating film 516 can also be higher than that of the insulating film 514.

[0214] In addition, since the insulating films 514 and 516 can be formed using the same type of material, it is sometimes impossible to clearly confirm the interface between the insulating film 514 and the insulating film 516. Therefore, in this embodiment, the interface between the insulating film 514 and the insulating film 516 is shown by a dotted line. Note that in this embodiment, although a two-layer structure of the insulating film 514 and the insulating film 516 is described, it is not limited thereto. For example, a single-layer structure of the insulating film 514 or the insulating film 516 can also be adopted.

[0215] The insulating film 518 has the function of being able to block oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. By providing the insulating film 518, it is possible to prevent oxygen from diffusing from the oxide semiconductor film 508 to the outside, and it is also possible to prevent the oxygen contained in the insulating films 514 and 516 from diffusing to the outside. Moreover, it is possible to prevent hydrogen, water, etc. from invading the oxide semiconductor film 508 from the outside. As the insulating film 518, for example, a nitride insulating film can be used. As this nitride insulating film, there are silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. In particular, when a silicon oxynitride or silicon nitride film is used as the insulating film 518, oxygen diffusion to the outside can be suppressed, so it is preferred.

[0216] In addition, as the insulating film 518, an oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc. can be provided instead of the nitride insulating film having a blocking effect on oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. As the oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc., there are aluminum oxide film, aluminum oxynitride film, gallium oxide film, gallium oxynitride film, yttrium oxide film, yttrium oxynitride film, hafnium oxide film, hafnium oxynitride film, etc. In addition, as the oxide insulating film having a blocking effect on oxygen, hydrogen, water, etc., it is particularly preferred to use aluminum oxide, hafnium oxide or yttrium oxide.

[0217] Although various films such as the above-described conductive film, insulating film, and oxide semiconductor film can be formed by a sputtering method or a PECVD method, they can also be formed by, for example, a thermal CVD (Chemical Vapor Deposition: metalorganic chemical vapor deposition) method or an ALD (Atomic Layer Deposition: atomic layer deposition) method. As an example of the thermal CVD method, an MOCVD (Metal Organic Chemical Vapor Deposition: metalorganic chemical vapor deposition) method can be cited.

[0218] Since the thermal CVD method is a film-forming method that does not use plasma, it has the advantage of not generating defects caused by plasma damage.

[0219] Film formation using the thermal CVD method can be performed as follows: The source gas and the oxidant are simultaneously supplied into the chamber, the pressure in the chamber is set to atmospheric pressure or reduced pressure, and a reaction occurs near the substrate or on the substrate to deposit on the substrate.

[0220] In addition, film formation using the ALD method can also be carried out as follows: Set the pressure in the chamber to atmospheric pressure or reduced pressure, introduce the source gases for reaction into the chamber in sequence, and repeatedly introduce the gases in this order. For example, by switching each switching valve (also called a high-speed valve), two or more source gases are sequentially supplied into the chamber. To prevent the mixing of multiple source gases, an inert gas (such as argon or nitrogen) is introduced simultaneously with or after the introduction of the first source gas, and then the second source gas is introduced. Note that when the first source gas and the inert gas are introduced simultaneously, the inert gas is used as a carrier gas. In addition, an inert gas can be introduced simultaneously with the introduction of the second source gas. Alternatively, the first source gas can be exhausted by vacuum pumping without introducing an inert gas, and then the second source gas is introduced. The first source gas adheres to the substrate surface to form the first layer, and the second source gas introduced later reacts with this first layer, whereby the second layer is stacked on the first layer to form a thin film. By repeatedly introducing the gases in this order multiple times until the desired thickness is obtained, a thin film with good step coverage can be formed. Since the thickness of the thin film can be adjusted according to the number of times of repeatedly introducing the gases in sequence, the ALD method can accurately adjust the thickness and is suitable for manufacturing micro-FETs.

[0221] Various films such as the conductive film, insulating film, oxide semiconductor film, and metal oxide film described in the above embodiments can be formed by thermal CVD methods such as the MOCVD method. For example, when forming an In-Ga-ZnO film, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In(CH 3 ) 3 . The chemical formula of trimethylgallium is Ga(CH 3 ) 3 . In addition, the chemical formula of dimethylzinc is Zn(CH 3 ) 2 . In addition, not limited to the above combination, triethylgallium (chemical formula: Ga(C 2 H 5 ) 3 ) can be used instead of trimethylgallium, and diethylzinc (chemical formula: Zn(C 2 H 5 ) 2 ) can be used instead of dimethylzinc.

[0222] For example, when forming a hafnium oxide film using a film formation apparatus using the ALD method, the following two gases are used: a source gas obtained by vaporizing a liquid containing a solvent and a hafnium precursor compound (hafnium alkoxide, hafnium amide such as tetrakis(dimethylamido)hafnium (TDMAH), etc.); and ozone (O 3 ) used as an oxidant. In addition, the chemical formula of tetrakis(dimethylamido)hafnium is Hf[N(CH 3 ) 2 4 ​In addition, as other material liquids, there are hafnium tetra(ethylmethylamide) and the like.

[0223] For example, when forming an alumina film using a film formation apparatus employing the ALD method, the following two gases are used: a source gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA)) containing a solvent and an aluminum precursor compound; and H 2 O used as an oxidant. In addition, the chemical formula of trimethylaluminum is Al(CH 3 ) 3 In addition, as other material liquids, there are aluminum tris(dimethylamide), triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), etc.

[0224] For example, when forming a silicon oxide film using a film formation apparatus employing the ALD method, hexachloroethyldisilane is attached to the film formation surface, chlorine contained in the attachment is removed, and radicals of an oxidizing gas (O 2 , nitrous oxide) are supplied to react with the attachment.

[0225] For example, when forming a tungsten film using a film formation apparatus employing the ALD method, WF 6 gas and B 2 H 6 gas are alternately introduced repeatedly to form an initial tungsten film, and then WF 6 gas and H 2 gas are alternately introduced repeatedly to form a tungsten film. Note that SiH 4 gas can also be used instead of B 2 H 6 gas.

[0226] For example, when forming an oxide semiconductor film such as an In-Ga-ZnO film using a film formation apparatus employing the ALD method, In(CH 3 ) 3 gas and O 3 gas are alternately introduced repeatedly to form an In-O layer, then Ga(CH 3 ) 3 gas and O 3 gas are alternately introduced repeatedly to form a GaO layer, and then Zn(CH 3 ) 2 gas and O 3 gas are alternately introduced repeatedly to form a ZnO layer. Note that the order of these layers is not limited to the above example. In addition, these gases can also be mixed to form mixed compound layers such as In-Ga-O layers, In-Zn-O layers, Ga-Zn-O layers, etc. Note that although H 2 O gas obtained by bubbling with an inert gas such as Ar can also be used instead of O 3 gas, it is preferable to use O 3 that does not contain HGas. Additionally, In(C 2 H 5 ) 3 gas can also be used instead of In(CH 3 ) 3 gas. Ga(C 2 H 5 ) 3 gas can also be used instead of Ga(CH 3 ) 3 gas. Zn(CH 3 ) 2 gas can also be used.

[0227] <Structural Example 2 of Semiconductor Device>

[0228] Next, with reference to Figure 16A and Figure 16B we will describe structural examples different from the transistor 500 shown in Figure 14B and Figure 14C . Additionally, when indicating parts having the same functions as those described above, the same hatching is sometimes used without particularly attaching reference numerals.

[0229] Figure 16A is a top view of the transistor 570 of the semiconductor device as one aspect of the present invention, Figure 16B which is equivalent to a cross-sectional view along the dotted line X3 - X4 shown in Figure 16A and a cross-sectional view along the dotted line Y3 - Y4 shown in Figure 16A .

[0230] The transistor 570 includes: a conductive film 504 serving as a first gate electrode on a substrate 502; an insulating film 506 on the substrate 502 and the conductive film 504; an insulating film 507 on the insulating film 506; an oxide semiconductor film 508 on the insulating film 507; an insulating film 514 on the oxide semiconductor film 508; an insulating film 516 on the insulating film 514; a conductive film 512a serving as a source electrode electrically connected to the oxide semiconductor film 508; a conductive film 512b serving as a drain electrode electrically connected to the oxide semiconductor film 508; an insulating film 514 on the oxide semiconductor film 508; an insulating film 516 on the insulating film 514; an insulating film 518 on the insulating film 516; a conductive film 520a on the insulating film 518; and a conductive film 520b on the insulating film 518. The insulating films 514, 516, and 518 function as a second gate insulating film of the transistor 570. In addition, the conductive film 520a is electrically connected to the conductive film 512b through an opening 542c provided in the insulating films 514, 516, and 518. In the transistor 570, the conductive film 520a functions as, for example, a pixel electrode of a display device. In the transistor 570, the conductive film 520b serves as a second gate electrode (also referred to as a back gate electrode).

[0231] As Figure 16B shown, the conductive film 520b is connected to the conductive film 504 serving as the first gate electrode in openings 542a and 542b provided in the insulating films 506, 507, 514, 516, and 518. Therefore, the same potential is applied to the conductive film 520b and the conductive film 504.

[0232] In addition, in this embodiment, a structure in which the openings 542a and 542b are provided to connect the conductive film 520b and the conductive film 504 is illustrated, but it is not limited thereto. For example, a structure in which only one of the openings 542a and 542b is formed to connect the conductive film 520b and the conductive film 504 may be employed, or a structure in which the openings 542a and 542b are not provided and the conductive film 520b is not connected to the conductive film 504 may be employed. When a structure in which the conductive film 520b is not connected to the conductive film 504 is adopted, different potentials may be applied to the conductive film 520b and the conductive film 504, respectively.

[0233] As Figure 16BAs shown, the oxide semiconductor film 508 is located opposite to the conductive film 504 serving as a gate electrode and the conductive film 520b serving as a second gate electrode, and is sandwiched between the two conductive films serving as gate electrodes. The lengths in the channel length direction and the channel width direction of the conductive film 520b serving as a second gate electrode are both greater than the lengths in the channel length direction and the channel width direction of the oxide semiconductor film 508, and the conductive film 520b covers the entire oxide semiconductor film 508 with the insulating films 514, 516, and 518 interposed therebetween. In addition, since the conductive film 520b serving as a second gate electrode is connected to the conductive film 504 serving as a gate electrode in the openings 542a and 542b provided in the insulating films 506, 507, 514, 516, and 518, the sides in the channel width direction of the oxide semiconductor film 508 face the conductive film 520b serving as a second gate electrode with the insulating films 514, 516, and 518 interposed therebetween.

[0234] In other words, in the channel width direction of the transistor 570, the conductive film 504 serving as a gate electrode and the conductive film 520b serving as a second gate electrode are connected in the openings provided in the insulating films 506 and 507 serving as gate insulating films and the insulating films 514, 516, and 518 serving as second gate insulating films, and at the same time, the conductive film 504 and the conductive film 520b surround the oxide semiconductor film 508 with the insulating films 506 and 507 serving as gate insulating films and the insulating films 514, 516, and 518 serving as second gate insulating films interposed therebetween.

[0235] By adopting the above structure, the oxide semiconductor film 508 included in the transistor 570 is surrounded by the electric fields of the conductive film 504 serving as a gate electrode and the conductive film 520b serving as a second gate electrode. As shown in the transistor 570, a device structure of a transistor in which the oxide semiconductor film forming a channel region is surrounded by the electric fields of the gate electrode and the second gate electrode can be referred to as a surrounded channel (s-channel) structure.

[0236] Since the transistor 570 has an s-channel structure, the conductive film 504 serving as a gate electrode can effectively apply an electric field for inducing a channel to the oxide semiconductor film 508. As a result, the current driving ability of the transistor 570 is improved, and thus high on-state current characteristics can be obtained. In addition, since the on-state current can be increased, the transistor 570 can be miniaturized. Further, since the transistor 570 has a structure surrounded by the conductive film 504 serving as a gate electrode and the conductive film 520b serving as a second gate electrode, the mechanical strength of the transistor 570 can be improved.

[0237] Note that the other structures of the transistor 570 are the same as those of the above transistor 500 and exhibit the same effects.

[0238] In addition, the transistors of the present embodiment can freely combine the above structures. For example, the transistors shown in Figure 14A and Figure 14B can be used as the transistors for the pixels of the display device, while the transistors shown in Figure 16A and Figure 16B can be used as the transistors for the gate driver of the display device.

[0239] <Method of manufacturing a semiconductor device 1>

[0240] Next, a method of manufacturing the transistor 500 of the semiconductor device according to one embodiment of the present invention will be described in detail with reference to Figures 10A to 14A FIG. Figures 10A to 14A is a cross-sectional view for explaining the method of manufacturing the semiconductor device.

[0241] First, a conductive film is formed on the substrate 502, and the conductive film is processed by a photolithography process and an etching process to form a conductive film 504 serving as a gate electrode. Next, an insulating film 506, 507 (see Figure 10A ) serving as a gate insulating film is formed on the conductive film 504.

[0242] In the present embodiment, a glass substrate is used as the substrate 502. As the conductive film 504 serving as the gate electrode, a tungsten film having a thickness of 100 nm is formed by a sputtering method. In addition, a silicon nitride film having a thickness of 400 nm is formed as the insulating film 506 by PECVD, and a silicon oxynitride film having a thickness of 50 nm is formed as the insulating film 507 by PECVD.

[0243] As the insulating film 506, a stacked structure of silicon nitride films can be employed. Specifically, as the insulating film 506, a three-layer structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film can be employed. An example of the three-layer structure can be formed by the following steps.

[0244] A first silicon nitride film having a thickness of 50 nm can be formed under the following conditions: for example, silane having a flow rate of 200 sccm, nitrogen having a flow rate of 2000 sccm, and ammonia gas having a flow rate of 100 sccm are used as source gases, the source gases are supplied into the reaction chamber of the PECVD apparatus, the pressure in the reaction chamber is controlled to 100 Pa, and a power of 2000 W is supplied using a 27.12 MHz high-frequency power supply.

[0245] A second silicon nitride film with a thickness of 300 nm can be formed under the following conditions: silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 2000 sccm are used as source gases, and these source gases are supplied into the reaction chamber of the PECVD apparatus. The pressure in the reaction chamber is controlled to be 100 Pa, and a power of 2000 W is supplied using a high-frequency power supply of 27.12 MHz.

[0246] A third silicon nitride film with a thickness of 50 nm can be formed under the following conditions: silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm are used as source gases, and these source gases are supplied into the reaction chamber of the PECVD apparatus. The pressure in the reaction chamber is controlled to be 100 Pa, and a power of 2000 W is supplied using a high-frequency power supply of 27.12 MHz.

[0247] In addition, the substrate temperature when forming the above-mentioned first silicon nitride film, second silicon nitride film, and third silicon nitride film can be set to 350 °C or lower.

[0248] For example, in the case where a conductive film containing copper (Cu) is used as the conductive film 504, by adopting a three-layer structure with a silicon nitride film as the insulating film 506, the following effects are achieved.

[0249] The first silicon nitride film can inhibit the diffusion of copper (Cu) elements from the conductive film 504. The second silicon nitride film has a function of releasing hydrogen and can improve the breakdown voltage of the insulating film used as the gate insulating film. The third silicon nitride film has a small amount of hydrogen release and can inhibit the diffusion of hydrogen released from the second silicon nitride film.

[0250] As the insulating film 507, in order to improve the interface characteristics between the insulating film 507 and the oxide semiconductor film 508 (more specifically, the first oxide semiconductor film 508a) formed later, it is preferable to use an insulating film containing oxygen for formation.

[0251] Next, an oxide semiconductor film 509 is formed on the insulating film 507 at a first temperature. In addition, as the oxide semiconductor film 509, a first oxide semiconductor film 509a is formed, and then a second oxide semiconductor film 509b is formed (refer to Figure 10B ).

[0252] The first temperature for forming the oxide semiconductor film 509 is above room temperature and below 340°C, preferably above room temperature and below 300°C, more preferably above 100°C and below 250°C, and still more preferably above 100°C and below 200°C. By heating to form the oxide semiconductor film 509, the crystallinity of the oxide semiconductor film 509 can be improved. On the other hand, when using a large glass substrate (for example, Generation 6 to Generation 10) as the substrate 502, the substrate 502 sometimes deforms when the first temperature is above 150°C and below 340°C. Therefore, when using a large glass substrate, by setting the first temperature to be above 100°C and below 150°C, deformation of the glass substrate can be suppressed.

[0253] The substrate temperatures during the film formation of the first oxide semiconductor film 509a and the second oxide semiconductor film 509b can be the same or different. However, by making the substrate temperatures of the first oxide semiconductor film 509a and the second oxide semiconductor film 509b the same, the manufacturing cost can be reduced, so it is preferred.

[0254] In this embodiment, the first oxide semiconductor film 509a is formed by sputtering using an In-Ga-Zn metal oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1, and then the second oxide semiconductor film 509b is continuously formed by sputtering using an In-Ga-Zn metal oxide target with an atomic ratio of In:Ga:Zn = 1:1:1.2 in a vacuum. In addition, the substrate temperature during the formation of the first oxide semiconductor film 509a and the second oxide semiconductor film 509b is set to 170°C.

[0255] In addition, when forming the oxide semiconductor film 509 by sputtering, as the sputtering gas, noble gases (typically argon), oxygen, or a mixed gas of noble gas and oxygen is appropriately used. Further, when using a mixed gas, it is preferred to increase the proportion of oxygen gas relative to the noble gas. In addition, high purity of the sputtering gas is required. For example, as the oxygen gas or argon gas for the sputtering gas, a high purity gas with a dew point of -40°C or lower, preferably -80°C or lower, more preferably -100°C or lower, and still more preferably -120°C or lower is used, thereby being able to prevent moisture and the like from mixing into the oxide semiconductor film 509 as much as possible.

[0256] In addition, when forming the oxide semiconductor film 509 by sputtering, in the processing chamber of the sputtering apparatus, it is preferred to perform high-vacuum pumping (pumping down to 5×10 -7 Pa or more and 1×10 -4(at a pressure of Pa or less) to remove water and the like, which are impurities for the oxide semiconductor film 509, as much as possible. Alternatively, it is preferable to combine a turbo molecular pump and a cold trap to prevent gas, particularly gas containing carbon or hydrogen, from flowing back from the pumping system into the processing chamber.

[0257] Next, the oxide semiconductor film 509 is processed to form island-shaped oxide semiconductor films 508. Note that the first oxide semiconductor film 509a becomes the island-shaped first oxide semiconductor film 508a, and the second oxide semiconductor film 509b becomes the island-shaped second oxide semiconductor film 508b (see Figure 10C ).

[0258] Next, in such a manner that a process at a temperature higher than the above-described first temperature is not performed, a conductive film 512 that will become source and drain electrodes is formed on the insulating film 507 and the oxide semiconductor film 508 by sputtering (see Figure 11A ).

[0259] In the present embodiment, as the conductive film 512, a laminated film in which a tungsten film with a thickness of 50 nm and an aluminum film with a thickness of 400 nm are laminated in sequence is formed by sputtering. Although the conductive film 512 has a two-layer laminated structure in the present embodiment, it is not limited thereto. For example, the conductive film 512 may also have a three-layer structure in which a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 100 nm are laminated in sequence.

[0260] Next, masks 536a and 536b are formed in desired regions on the conductive film 512 (see Figure 11B ).

[0261] In the present embodiment, the masks 536a and 536b are formed by coating a photosensitive resin film on the conductive film 512 and patterning the photosensitive resin film by a photolithography process.

[0262] Next, the conductive film 512 is processed from the conductive film 512 and the masks 536a and 536b using an etchant 538, thereby forming separated conductive films 512a and 512b (see Figure 11C ).

[0263] In this embodiment, a dry etching apparatus is used to process the conductive film 512. However, the method for processing the conductive film 512 is not limited thereto. For example, a chemical solution can be used as the etchant 538 and a wet etching apparatus can be used to process the conductive film 512 and the second oxide semiconductor film 508b. Note that, compared with the case of processing the conductive film 512 using a wet etching apparatus, processing the conductive film 512 using a dry etching apparatus can form a finer pattern. On the other hand, compared with the case of processing the conductive film 512 using a dry etching apparatus, processing the conductive film 512 using a wet etching apparatus can reduce the manufacturing cost.

[0264] Next, the surface of the second oxide semiconductor film 508b is washed from the second oxide semiconductor film 508b, the conductive films 512a and 512b, and the masks 536a and 536b using the etchant 539 (see Figure 12A ).

[0265] As the above washing method, for example, washing using a chemical solution such as phosphoric acid can be cited. By washing using a chemical solution such as phosphoric acid, impurities (for example, elements contained in the conductive films 512a and 512b, etc.) attached to the surface of the second oxide semiconductor film 508b can be removed. Note that it is not necessarily required to perform this washing. Depending on the situation, this washing can be omitted.

[0266] In addition, when forming the conductive films 512a and 512b and / or in the above washing process, the region of the second oxide semiconductor film 508b exposed from the conductive films 512a and 512b sometimes becomes thinner than the first oxide semiconductor film 508a.

[0267] Furthermore, when forming the conductive films 512a and 512b and / or in the above washing process, the region of the second oxide semiconductor film 508b exposed from the conductive films 512a and 512b sometimes does not become thinner. Figure 15A And Figure 15B An example at this time is shown. Figure 15A And Figure 15B is a cross-sectional view showing an example of a semiconductor device. Figure 15A is Figure 14B An example of the case where the second oxide semiconductor film 508b of the transistor 500 shown does not become thinner. In addition, as shown in Figure 15B , the second oxide semiconductor film 508b can also be formed thinner than the first oxide semiconductor film 508a in advance, and the thickness of the region exposed from the conductive films 512a and 512b can be made equal to that of the transistor 500 shown in Figure 14B . In addition, as shown in Figure 15CAs shown, the second oxide semiconductor film 508b may also be formed thinner than the first oxide semiconductor film 508a in advance, and an insulating film 519 is formed on the second oxide semiconductor film 508b and the insulating film 507. At this time, an opening for bringing the second oxide semiconductor film 508b into contact with the conductive film 512a and the conductive film 512b is formed in the insulating film 519. The insulating film 519 can be formed using the same material and the same formation method as the insulating film 514.

[0268] Next, by removing the masks 536a and 536b, the conductive film 512a serving as a source electrode on the second oxide semiconductor film 508b and the conductive film 512b serving as a drain electrode on the oxide semiconductor film 508 are formed. In addition, the oxide semiconductor film 508 has a stacked structure of a first oxide semiconductor film 508a and a second oxide semiconductor film 508b (see Figure 12B ).

[0269] Next, an insulating film 514 serving as a first protective insulating film and an insulating film 516 serving as a second protective insulating film are formed on the oxide semiconductor film 508 and the conductive films 512a and 512b, and then a first barrier film 531 is formed (see Figure 12C ).

[0270] In addition, preferably, after the insulating film 514 is formed, the insulating film 516 is continuously formed without being exposed to the atmosphere. After the insulating film 514 is formed, without being exposed to the atmosphere, by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, the insulating film 516 is continuously formed, whereby the impurity concentration derived from the atmospheric components at the interface between the insulating film 514 and the insulating film 516 can be reduced while oxygen contained in the insulating films 514 and 516 can be moved into the oxide semiconductor film 508, and the amount of oxygen defects in the oxide semiconductor film 508 can be reduced.

[0271] For example, as the insulating film 514, a silicon oxynitride film can be formed by the PECVD method. At this time, as the source gas, a deposition gas containing silicon and an oxidizing gas are preferably used. Typical examples of the deposition gas containing silicon are silane, disilane, trisilane, silane fluoride, etc. As the oxidizing gas, there are nitrous oxide, nitrogen dioxide, etc. In addition, the insulating film 514 containing nitrogen and having a small amount of defects can be formed by the PECVD method under the following conditions: the flow rate of the oxidizing gas is more than 20 times and less than 100 times, preferably 40 times or more and 80 times or less, the flow rate of the above deposition gas; and the pressure in the processing chamber is less than 100 Pa, preferably 50 Pa or less.

[0272] In this embodiment, as the insulating film 514, a silicon oxynitride film is formed by PECVD under the following conditions: the temperature of the substrate 502 is maintained at 220 °C; silane with a flow rate of 50 sccm and nitrous oxide with a flow rate of 2000 sccm are used as source gases; the pressure in the processing chamber is 20 Pa; and the high-frequency power supplied to the parallel plate electrode is 13.56 MHz and 100 W (the power density is 1.6×10 -2 W / cm 2 ).

[0273] As the insulating film 516, a silicon oxide film or a silicon oxynitride film is formed under the following conditions: the temperature of the substrate in the processing chamber evacuated in the PECVD apparatus is maintained at 180 °C or higher and 350 °C or lower, the source gas is introduced into the processing chamber, and the pressure in the processing chamber is set to 100 Pa or higher and 250 Pa or lower, preferably 100 Pa or higher and 200 Pa or lower, and a high-frequency power of 0.17 W / cm 2 or higher and 0.5 W / cm 2 or lower, more preferably 0.25 W / cm 2 or higher and 0.35 W / cm 2 or lower is supplied to the electrode provided in the processing chamber.

[0274] In the film formation conditions of the insulating film 516, a high-frequency power with the above power density is supplied in the reaction chamber having the above pressure, whereby the decomposition efficiency of the source gas in the plasma is improved, oxygen radicals increase, and the oxidation of the source gas is promoted, so that the oxygen content in the insulating film 516 exceeds the stoichiometric composition. On the other hand, in the film formed at the above substrate temperature, since the bonding force between silicon and oxygen is weak, a part of the oxygen in the film is released due to the heat treatment in the subsequent process. As a result, an oxide insulating film can be formed in which the oxygen content exceeds the stoichiometric composition and a part of the oxygen is released due to heating.

[0275] In the film formation process of the insulating film 516, the insulating film 514 is used as a protective film for the oxide semiconductor film 508. Therefore, the insulating film 516 can be formed using a high-power density high-frequency power while reducing the damage to the oxide semiconductor film 508.

[0276] In addition, in the film formation conditions of the insulating film 516, by increasing the flow rate of the silicon-containing deposition gas relative to the oxidizing gas, the amount of defects in the insulating film 516 can be reduced. Typically, an oxide insulating film with a small amount of defects can be formed, in which the spin density of the signal presented at g = 2.001 due to the dangling bonds of silicon measured by ESR is lower than 6×10 17 spins / cm 3 , preferably 3×10 17spins / cm 3 Below, more preferably 1.5×10 17 spins / cm 3 As follows. This can improve the reliability of the transistor.

[0277] Alternatively, heat treatment may be performed after the insulating films 514 and 516 are formed (in other words, after the insulating film 516 is formed and before the first barrier film 531 is formed). By this heat treatment, nitrogen oxides contained in the insulating films 514 and 516 can be reduced. Also, by this heat treatment, part of the oxygen contained in the insulating films 514 and 516 can be moved to the oxide semiconductor film 508 to reduce the amount of oxygen vacancies in the oxide semiconductor film 508.

[0278] The temperature of the heat treatment performed on the insulating films 514 and 516 is typically set to be lower than 400°C, preferably lower than 375°C, more preferably higher than 340°C and lower than 360°C, and further preferably higher than 150°C and lower than 350°C. The heat treatment can be performed in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, preferably lower than 1 ppm, and more preferably lower than 10 ppb) or a rare gas (argon, helium, etc.). The above-mentioned nitrogen, oxygen, ultra-dry air or rare gas preferably does not contain hydrogen, water, etc. The heat treatment can be performed using an electric furnace, an RTA device, etc.

[0279] The first barrier film 531 contains oxygen and a metal (at least one selected from indium, zinc, titanium, aluminum, tungsten, tantalum, molybdenum, hafnium, and yttrium). When indium tin oxide (also referred to as ITO (Indium Tin Oxide)), indium tin silicon oxide (hereinafter referred to as ITSO), or indium oxide is used as the first barrier film 531, since the coverage of the uneven surface is good, it is preferable.

[0280] In addition, the first barrier film 531 can be formed by a sputtering method. When the first barrier film 531 is very thin, it is sometimes difficult to suppress oxygen that may be released from the insulating film 516 to the outside. On the other hand, when the first barrier film 531 is very thick, oxygen may not be properly added to the insulating film 516. Therefore, the thickness of the first barrier film 531 is preferably not less than 1 nm and not more than 20 nm, and more preferably not less than 2 nm and not more than 10 nm. In this embodiment, ITSO with a thickness of 5 nm is formed as the first barrier film 531.

[0281] Next, oxygen 540 is added to the insulating film 516 serving as the second protective insulating film via the first barrier film 531. Note that in the drawings, oxygen added to the insulating film 516 is schematically indicated as oxygen 540a (see FIG. 5A ). Figure 13A ). In addition, oxygen 540 is sometimes added to the insulating film 514.

[0282] As a method of adding oxygen 540 to the insulating film 516 via the first barrier film 531, there are ion doping, ion implantation, plasma treatment, etc. In addition, as oxygen 540, excess oxygen or oxygen radicals can be cited. In addition, when adding oxygen 540, oxygen 540 can be effectively added to the insulating film 516 by applying a bias voltage to the substrate side. As the above-mentioned bias voltage, for example, the power density is set to 1 W / cm 2 Above and 5W / cm 2 By providing the first barrier film 531 over the insulating film 516 to add oxygen, the first barrier film 531 can be used as a protective film for suppressing the release of oxygen from the insulating film 516. Therefore, more oxygen can be added to the insulating film 516.

[0283] Next, the first barrier film 531 or a portion of the first barrier film 531 and a portion of the insulating film 516 serving as the second protective insulating film are removed using an etchant 542 (see Figure 13B ).

[0284] As a method for removing the first barrier film 531 and a portion of the insulating film 516 serving as the second protective insulating film, dry etching, wet etching, or a method combining dry etching and wet etching can be cited. Note that when dry etching is used, the etchant 542 is an etching gas, and when wet etching is used, the etchant 542 is a chemical solution. In this embodiment, the first barrier film 531 is removed by wet etching. As a method for removing the first barrier film 531, wet etching is preferably used because it can reduce manufacturing costs.

[0285] Next, an insulating film 518 serving as a second barrier film is formed on the insulating film 516 (see Figure 14A ).

[0286] When the insulating film 518 is formed by the PECVD method, the substrate temperature is lower than 400° C., preferably lower than 375° C., and more preferably 340° C. to 360° C. When the substrate temperature is set to the above range when the insulating film 518 is formed, the excess oxygen or the oxygen radicals can be diffused into the oxide semiconductor film 508. When the substrate temperature is set to the above range when the insulating film 518 is formed, a dense film can be formed, which is preferred.

[0287] For example, when forming a silicon nitride film as the insulating film 518 using the PECVD method, a silicon-containing deposition gas, nitrogen, and ammonia are preferably used as the source gases. By using a small amount of ammonia compared to nitrogen, ammonia dissociates in the plasma to generate active species. These active species break the bonds between silicon and hydrogen and the triple bond of nitrogen contained in the silicon-containing deposition gas. As a result, the bonding between silicon and nitrogen can be promoted, and a silicon nitride film with fewer silicon-hydrogen bonds, fewer defects, and high density can be formed. On the other hand, when the amount of ammonia relative to nitrogen is large, the decomposition of the silicon-containing deposition gas and nitrogen does not proceed, and the silicon-hydrogen bond remains, resulting in the formation of a silicon nitride film with more defects and low density. Therefore, in the source gases, the flow rate ratio of nitrogen to ammonia is set to be 5 times or more and 50 times or less, preferably 10 times or more and 50 times or less.

[0288] In the present embodiment, as the insulating film 518, a silicon nitride film with a thickness of 50 nm is formed by using a PECVD apparatus and using silane, nitrogen, and ammonia as the source gases. The flow rate of silane is 50 sccm, the flow rate of nitrogen is 5000 sccm, and the flow rate of ammonia is 100 sccm. The pressure in the processing chamber is set to 100 Pa, the substrate temperature is set to 350 °C, and 1000 W of high-frequency power is supplied to the parallel plate electrodes using a 27.12 MHz high-frequency power supply. The PECVD apparatus is a parallel plate type PECVD apparatus with an electrode area of 6000 cm 2 When the supplied electric power is converted to the power per unit area (power density), it is 1.7×10 -1 W / cm 2 .

[0289] In addition, a heat treatment may be performed after forming the insulating film 518 used as the second barrier film. Further, by performing the heat treatment after forming the insulating film 518, excess oxygen or oxygen radicals in the insulating film 516 can be diffused into the oxide semiconductor film 508, thereby filling oxygen defects in the oxide semiconductor film 508. Alternatively, by heating to form the insulating film 518, excess oxygen or oxygen radicals in the insulating film 516 can be diffused into the oxide semiconductor film 508, thereby filling oxygen defects in the oxide semiconductor film 508.

[0290] Through the above processes, the transistor 500 shown in Figure 14B can be formed.

[0291] <Manufacturing Method 2 of Semiconductor Device>

[0292] Next, a manufacturing method different from the manufacturing method of the transistor 500 shown in Figures 10A to 14A will be described.

[0293] First, similar to <Manufacturing Method 1 of Semiconductor Device>, Figures 10A to 12CThe process shown. Then, do not perform Figure 13A , Figure 13B , Figure 14A The process shown. That is, Figure 12C The structure shown has the same function as Figure 14B and Figure 14C The transistor 500 shown.

[0294] At this time, a metal oxide film is used as the first barrier film 531, and as this metal oxide film, alumina, hafnium oxide, or yttrium oxide is preferably formed.

[0295] In addition, when alumina, hafnium oxide, or yttrium oxide is formed as the first barrier film 531 by sputtering, the sputtering gas preferably contains at least oxygen. When forming the first barrier film 531, by using oxygen as the sputtering gas, this oxygen becomes oxygen radicals in the plasma, and sometimes one or both of this oxygen and these oxygen radicals are added to the insulating film 516. Therefore, it is also possible not to perform Figure 13A The process of adding oxygen 540 shown. In other words, when forming the first barrier film 531, the oxygen addition treatment and the formation of the first barrier film 531 can be performed simultaneously. In addition, when forming the first barrier film 531 (especially in the initial stage of formation), the first barrier film 531 has the function of adding oxygen, and after forming the first barrier film 531, the first barrier film 531 has the function of blocking oxygen.

[0296] In addition, as the first barrier film 531, for example, when alumina is formed by sputtering, a mixed layer is sometimes formed near the interface between the insulating film 516 and the first barrier film 531. When the insulating film 516 is an oxynitride film, it is possible to form Al x Si y O z .

[0297] In addition, when alumina, hafnium oxide, or yttrium oxide is used as the first barrier film 531, alumina, hafnium oxide, and yttrium oxide have high insulation and high oxygen barrier properties. Therefore, it is not necessary to perform Figure 13B The process of removing the first barrier film 531 shown and Figure 14A The process of forming the insulating film 518 shown. Therefore, the first barrier film 531 has the same function as the insulating film 518.

[0298] In addition, by forming the first barrier film 531 by heating at a substrate temperature during film formation of less than 400°C, preferably less than 375°C, and more preferably 340°C or higher and 360°C or lower, excess oxygen or oxygen radicals added to the insulating film 516 can be diffused into the oxide semiconductor film 508. Alternatively, when a heat treatment of less than 400°C, preferably less than 375°C, and more preferably 340°C or higher and 360°C or lower is performed after forming the first barrier film 531, excess oxygen or oxygen radicals added to the insulating film 516 can be diffused into the oxide semiconductor film 508.

[0299] Thus, by using alumina, hafnium oxide, or yttrium oxide as the first barrier film 531, the manufacturing process of the semiconductor device can be shortened, and thus the manufacturing cost can be suppressed.

[0300] <Manufacturing Method 3 of Semiconductor Device>

[0301] Next, with reference to Figures 17A to 17C a method for manufacturing the transistor 570 according to one embodiment of the present invention will be described in detail. Figures 17A to 17C It is a cross-sectional view for explaining the manufacturing method of the semiconductor device.

[0302] First, the same processes as those of the manufacturing method of the transistor 500 shown above are performed (up to the processes shown in Figures 10A to 14A ).

[0303] Next, a mask is formed on the insulating film 518 by a photolithography process, and openings 542c are formed in desired regions of the insulating films 514, 516, and 518. In addition, a mask is formed on the insulating film 518 by a photolithography process, and openings 542a and 542b are formed in desired regions of the insulating films 506, 507, 514, 516, and 518. The opening 542c is formed so as to reach the conductive film 512b. In addition, the openings 542a and 542b are formed so as to both reach the conductive film 504 (refer to Figure 17A ).

[0304] In addition, the openings 542a, 542b, and the opening 542c may be formed by the same process or different processes. When the openings 542a, 542b, and the opening 542c are formed in the same process, for example, a gray-tone mask or a halftone mask can be used for formation. In addition, the openings 542a and 542b may be formed in multiple steps. For example, the insulating films 506 and 507 may be processed first, and then the insulating films 514, 516, and 518 may be processed.

[0305] Next, a conductive film 520 is formed on the insulating film 518 so as to cover the openings 542a, 542b, and 542c (refer to Figure 17B ).

[0306] As the conductive film 520, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) can be used. In particular, as the conductive film 520, a transparent conductive material such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (ITO), indium zinc oxide, indium tin silicon oxide (ITSO), etc. can be used. In addition, for example, the conductive film 520 can be formed by a sputtering method. In this embodiment, ITSO with a thickness of 110 nm is formed by a sputtering method.

[0307] Next, a mask is formed on the conductive film 520 through a photolithography process, and the conductive film 520 is processed into a desired shape to form the conductive films 520a and 520b (refer to Figure 17C ).

[0308] As a method for forming the conductive films 520a and 520b, a dry etching method, a wet etching method, or a method combining a dry etching method and a wet etching method, etc. can be cited. In this embodiment, the conductive film 520 is processed into the conductive films 520a and 520b using a wet etching method.

[0309] Through the above steps, the transistor 570 shown in Figure 16A and Figure 16B can be manufactured.

[0310] The structure and method shown in this embodiment can be used in appropriate combination with the structure and method shown in other embodiments.

[0311] Embodiment 3

[0312] In this embodiment, the structure of the oxide semiconductor included in a semiconductor device according to one aspect of the present invention will be described in detail.

[0313] <Structure of Oxide Semiconductor>

[0314] Oxide semiconductors are classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. As non-single-crystalline oxide semiconductors, there are CAAC-OS (C-Axis Aligned Crystalline Oxide Semiconductor), polycrystalline oxide semiconductors, nc-OS (nanocrystalline Oxide Semiconductor), a-like OS (amorphous like Oxide Semiconductor), and amorphous oxide semiconductors, etc.

[0315] From other viewpoints, oxide semiconductors are classified into amorphous oxide semiconductors and crystalline oxide semiconductors. Examples of crystalline oxide semiconductors include single crystal oxide semiconductors, CAAC-OS, polycrystalline oxide semiconductors, and nc-OS, etc.

[0316] As a definition of an amorphous structure, generally, it is known that: it is in a metastable state and not immobilized, is isotropic and does not have a non-uniform structure, etc. In other words, the bond angles of the amorphous structure are not fixed, and it has short-range order but not long-range order.

[0317] From the opposite viewpoint, an oxide semiconductor that is substantially stable cannot be called a completely amorphous oxide semiconductor. Additionally, an oxide semiconductor that does not have isotropy (for example, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. Note that a-like OS has a periodic structure in a minute region, but at the same time has voids (also called voids) and has an unstable structure. Therefore, a-like OS is physically similar to an amorphous oxide semiconductor.

[0318] <caac-os>

[0319] First, the CAAC-OS will be described.

[0320] CAAC-OS is one of the oxide semiconductors containing a plurality of c-axis oriented crystalline parts (also referred to as grains).

[0321] In the composite analysis image (also referred to as a high-resolution TEM image) of the bright-field image and the diffraction pattern of the obtained CAAC-OS observed by a transmission electron microscope (TEM: Transmission Electron Microscope), a plurality of grains are observed. However, in the high-resolution TEM image, a clear boundary, that is, a grain boundary, between the grains cannot be observed. Therefore, it can be said that in CAAC-OS, a decrease in electron mobility due to grain boundaries does not easily occur.

[0322] Next, the CAAC-OS observed by TEM will be described. Figure 19A A high-resolution TEM image showing a cross-section of CAAC-OS observed from a direction substantially parallel to the sample surface is shown. The high-resolution TEM image is obtained using the spherical aberration corrector function. The high-resolution TEM image obtained using the spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. For example, a Cs-corrected high-resolution TEM image can be obtained using an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

[0323] Figure 19B Shows Figure 19A The Cs-corrected high-resolution TEM image obtained by magnifying the region (1) in Figure 19B It can be confirmed that metal atoms are arranged in layers in the grain. Each metal atom layer has a configuration reflecting the unevenness of the surface on which the CAAC-OS film is formed (also referred to as the formed surface) or the top surface of the CAAC-OS and is arranged parallel to the formed surface or the top surface of the CAAC-OS.

[0324] As Figure 19B shown, CAAC-OS has a unique atomic arrangement. Figure 19C is a diagram showing the unique atomic arrangement with auxiliary lines. From Figure 19B and Figure 19C It is known that the size of a single grain is 1 nm or more, or 3 nm or more, and the size of the voids generated by the inclination between grains is about 0.8 nm. Therefore, the grains can also be referred to as nanocrystals (nc: nanocrystal). Note that CAAC-OS can also be referred to as an oxide semiconductor having CANC (C-Axis Aligned nanocrystals: c-axis oriented nanocrystals).

[0325] Here, based on the Cs-corrected high-resolution TEM image, the arrangement of the grains 5100 of CAAC-OS on the substrate 5120 is schematically shown as a structure of stacked bricks or blocks (see Figure 19D ). The portion where inclination is generated between grains, as observed in Figure 19C , corresponds to the region 5161 shown in Figure 19D .

[0326] In addition, Figure 20A shows a Cs-corrected high-resolution TEM image of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface. Figure 20B , Figure 20C and Figure 20D respectively show Cs-corrected high-resolution TEM images obtained by magnifying the regions (1), (2), and (3) in Figure 20A . It can be seen from Figure 20B , Figure 20C and Figure 20D that the metal atoms are arranged in a triangular, square, or hexagonal shape in the grains. However, there is no regularity in the arrangement of metal atoms between different grains.

[0327] Next, CAAC-OS analyzed using X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when analyzing the structure of CAAC-OS containing InGaZnO 4 crystals by the out-of-plane method, as shown in Figure 21A , peaks often appear around a diffraction angle (2θ) of 31°. Since this peak originates from the (009) plane of InGaZnO 4 crystals, it can be seen that the crystals in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the top surface.

[0328] Note that when analyzing the structure of CAAC-OS using the out-of-plane method, in addition to the peak near 2θ = 31°, a peak sometimes appears near 2θ = 36°. The peak near 2θ = 36° indicates that a part of CAAC-OS contains crystals without c-axis orientation. Preferably, in the structure of CAAC-OS analyzed by the out-of-plane method, a peak appears near 2θ = 31° and no peak appears near 2θ = 36°.

[0329] On the other hand, when analyzing the structure of CAAC-OS using the in-plane method in which X-rays are incident on the sample from a direction substantially perpendicular to the c-axis, a peak appears near 2θ = 56°. This peak originates from the (110) plane of the InGaZnO 4 crystal. In CAAC-OS, even when analyzing (φ scan) under the condition of fixing 2θ near 56° and rotating the sample about the normal vector of the sample surface (θ axis), no distinct peak is observed as Figure 21B shown. In contrast, in a single crystal oxide semiconductor of InGaZnO 4 , when performing φ scan with 2θ fixed near 56°, six peaks originating from the crystal plane equivalent to the (110) plane are observed as Figure 21C shown. Therefore, it can be confirmed from the structural analysis using XRD that the orientations of the a-axis and b-axis in CAAC-OS have no regularity.

[0330] Next, CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a beam diameter of 300 nm is incident on CAAC-OS containing InGaZnO 4 crystals in a direction parallel to the sample surface, a diffraction pattern (also called a selected area transmission electron diffraction pattern) as shown in Figure 22 A may be obtained. In this diffraction pattern, spots due to the (009) plane of the InGaZnO 4 crystal are included. Therefore, it can also be known from electron diffraction that the particles contained in CAAC-OS have c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the top surface. On the other hand, Figure 22 B shows the diffraction pattern when an electron beam with a beam diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. A ring-shaped diffraction pattern is observed from Figure 22 B. Therefore, it can also be known from electron diffraction that the a-axis and b-axis of the particles contained in CAAC-OS have no orientation. It is considered that the first ring in Figure 22 B originates from the (010) plane and (100) plane of the InGaZnO 4 crystal, etc. In addition, it is considered that Figure 22 The second ring in B is caused by the (110) plane or the like.

[0331] As described above, CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor sometimes decreases due to the incorporation of impurities or the generation of defects, etc., from the opposite point of view, it can be said that CAAC-OS is an oxide semiconductor with few impurities or defects (such as oxygen defects).

[0332] In addition, impurities refer to elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements, etc. For example, elements such as silicon, whose bonding force with oxygen is stronger than that of the metal elements constituting the oxide semiconductor, will capture oxygen in the oxide semiconductor, thereby disrupting the atomic arrangement of the oxide semiconductor and resulting in a decrease in crystallinity. In addition, since heavy metals such as iron or nickel, and argon, carbon dioxide, etc. have large atomic radii (or molecular radii), they will disrupt the atomic arrangement of the oxide semiconductor and result in a decrease in crystallinity.

[0333] When an oxide semiconductor contains impurities or defects, its properties sometimes change due to light, heat, etc. For example, impurities contained in the oxide semiconductor sometimes become carrier traps or carrier generation sources. In addition, oxygen defects in the oxide semiconductor sometimes become carrier traps or become carrier generation sources due to the capture of hydrogen.

[0334] CAAC-OS with few impurities and oxygen defects is an oxide semiconductor with a low carrier density. Such an oxide semiconductor is called a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor. The impurity concentration and defect state density of CAAC-OS are low. That is, it can be said that CAAC-OS is an oxide semiconductor with stable properties.

[0335] <nc-os>

[0336] Next, nc-OS will be described.

[0337] In the high-resolution TEM image of nc-OS, there are regions where a crystalline part can be observed and regions where no distinct crystalline part can be observed. Most of the sizes of the crystalline parts included in nc-OS are 1 nm or more and 10 nm or less, or 1 nm or more. Note that an oxide semiconductor having a crystalline part with a size greater than 10 nm and 100 nm or less is sometimes referred to as a microcrystalline oxide semiconductor. For example, in the high-resolution TEM image of nc-OS, grain boundaries may not be clearly observed sometimes. Note that the source of the nanocrystals may be the same as the particles in CAAC-OS. Therefore, the crystalline part of nc-OS is sometimes referred to as a particle below.

[0338] In nc-OS, the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less) has periodicity. In addition, no regularity in the crystal orientation is observed among different particles in nc-OS. Therefore, no orientation is observed in the entire film. Thus, in some analysis methods, nc-OS may be indistinguishable from a-like OS or an amorphous oxide semiconductor sometimes. For example, when the structure of nc-OS is analyzed by an out-of-plane method using X-rays having a beam diameter larger than the particles, peaks indicating crystal planes cannot be detected. When electron diffraction is performed on nc-OS using an electron beam having a beam diameter larger than the particles (for example, 50 nm or more), a diffraction pattern similar to a halo pattern is observed. On the other hand, when nano-beam electron diffraction is performed on nc-OS using an electron beam having a beam diameter close to or smaller than the particles, spots are observed. In addition, in the nano-beam electron diffraction pattern of nc-OS, a region with high brightness (ring-shaped) such as a circle is sometimes observed. Moreover, in the nano-beam electron diffraction pattern of nc-OS, multiple spots are sometimes observed within the ring-shaped region.

[0339] As described above, since there is no regularity in the crystal orientation among the particles (nanocrystals), nc-OS can also be referred to as an oxide semiconductor containing RANC (Random Aligned nanocrystals) or an oxide semiconductor containing NANC (Non-Aligned nanocrystals).

[0340] nc-OS is an oxide semiconductor having higher regularity than an amorphous oxide semiconductor. Therefore, the density of defect states in nc-OS is lower than that in a-like OS or an amorphous oxide semiconductor. However, no regularity in the crystal orientation is observed among different particles in nc-OS. Therefore, the density of defect states in nc-OS is higher than that in CAAC-OS.

[0341] <a-like OS>

[0342] The a-like OS is an oxide semiconductor having a structure intermediate between nc-OS and amorphous oxide semiconductors.

[0343] Voids are sometimes observed in the high-resolution TEM images of a-like OS. In addition, in the high-resolution TEM images, there are regions where the crystalline part can be clearly observed and regions where the crystalline part cannot be observed.

[0344] Since the a-like OS contains voids, its structure is unstable. To demonstrate that the a-like OS has an unstable structure compared to CAAC-OS and nc-OS, the structural changes caused by electron irradiation are shown below.

[0345] As samples for electron irradiation, a-like OS (designated as sample A), nc-OS (designated as sample B), and CAAC-OS (designated as sample C) were prepared. Each sample is an In-Ga-Zn oxide.

[0346] First, high-resolution cross-sectional TEM images of each sample were obtained. From the high-resolution cross-sectional TEM images, it can be seen that each sample has a crystalline part.

[0347] Note that it is determined as follows which part is taken as one crystalline part. For example, it is known that InGaZnO 4 The unit lattice of the crystal has a structure in which nine layers including three In-O layers and six Ga-Zn-O layers are stacked in layers in the c-axis direction. The intervals between these adjacent layers are almost equal to the lattice surface interval (also called the d value) of the (009) plane, and its value obtained by crystal structure analysis is 0.29 nm. Thus, a part with a lattice fringe interval of 0.28 nm or more and 0.30 nm or less can be taken as the InGaZnO 4 crystalline part. Each lattice fringe corresponds to the a-b plane of the InGaZnO 4 crystal.

[0348] Figure 23 Examples showing the average size (Average crystal size) of the crystalline parts (22 to 45 parts) of each sample are shown. Note that the crystalline part size corresponds to the length of the above lattice fringe. From Figure 23 it can be seen that in the a-like OS, the crystalline part gradually becomes larger according to the cumulative electron dose. Specifically, as Figure 23 As shown in (1) therein, it can be seen that during the initial stage of observation using TEM, the crystal part (also called the initial crystal nucleus) with an initial size of about 1.2 nm grows to about 2.6 nm when the cumulative irradiation dose is 4.2×10 8 e - / nm 2 . On the other hand, it can be seen that in nc-OS and CAAC-OS, from the start of electron irradiation to the cumulative irradiation dose of electrons reaching 4.2×10 8 e - / nm 2 , the size of the crystal part does not change. Specifically, as shown in (2) and (3) of Figure 23 , it can be seen that regardless of the cumulative irradiation dose of electrons, the average crystal part sizes of nc-OS and CAAC-OS are about 1.4 nm and about 2.1 nm respectively.

[0349] Thus, sometimes electron irradiation causes the growth of the crystal part in a-like OS. On the other hand, it can be seen that in nc-OS and CAAC-OS, there is almost no growth of the crystal part caused by electron irradiation. That is to say, a-like OS has an unstable structure compared with CAAC-OS and nc-OS.

[0350] In addition, since a-like OS contains voids, its density is lower than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is more than 78.6% and less than 92.3% of that of a single-crystalline oxide semiconductor with the same composition. The densities of nc-OS and CAAC-OS are more than 92.3% and less than 100% of that of a single-crystalline oxide semiconductor with the same composition. Note that it is difficult to form an oxide semiconductor with a density less than 78% of the density of a single-crystalline oxide semiconductor.

[0351] For example, in an oxide semiconductor with an atomic ratio satisfying In:Ga:Zn = 1:1:1, the density of single-crystalline InGaZnO with a rhombohedral crystal structure 4 is 6.357 g / cm 3 . Therefore, for example, in an oxide semiconductor with an atomic ratio satisfying In:Ga:Zn = 1:1:1, the density of a-like OS is 5.0 g / cm 3 or more and less than 5.9 g / cm 3 . In addition, for example, in an oxide semiconductor with an atomic ratio satisfying In:Ga:Zn = 1:1:1, the densities of nc-OS and CAAC-OS are 5.9 g / cm 3 or more and less than 6.3 g / cm 3 .

[0352] Note that there are sometimes no single-crystalline oxide semiconductors with the same composition. In this case, by combining single-crystalline oxide semiconductors with different compositions in any ratio, the density of a single-crystalline oxide semiconductor equivalent to the desired composition can be estimated. The density of a single-crystalline oxide semiconductor equivalent to the desired composition can be calculated using a weighted average according to the combination ratio of single-crystalline oxide semiconductors with different compositions. Note that it is preferable to calculate the density by minimizing the types of single-crystalline oxide semiconductors to be combined as much as possible.

[0353] As described above, the oxide semiconductor has various structures and various characteristics. Note that the oxide semiconductor can be, for example, a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

[0354] Embodiment 4

[0355] In this embodiment, Figures 24 to 26 An example of a display device including the transistors exemplified in the previous embodiments will be described.

[0356] Figure 24 is a top view showing an example of the display device. Figure 24 The display device 700 shown includes: a pixel portion 702 provided on a first substrate 701; a source driver circuit portion 704 and a gate driver circuit portion 706 provided on the first substrate 701; a sealant 712 provided so as to surround the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706; and a second substrate 705 provided so as to face the first substrate 701. Note that the first substrate 701 and the second substrate 705 are sealed by the sealant 712. That is, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 are sealed by the first substrate 701, the sealant 712, and the second substrate 705. Note that although not shown in Figure 24 a display element is provided between the first substrate 701 and the second substrate 705.

[0357] In addition, in the display device 700, FPC (Flexible Printed Circuit) terminal portions 708 that are electrically connected to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706, respectively, are provided in regions on the first substrate 701 that are not surrounded by the sealant 712. In addition, the FPC terminal portions 708 are connected to the FPC 716, and various signals and the like are supplied to the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 through the FPC 716. In addition, the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portions 708 are each connected to the wiring 710. The various signals and the like supplied by the FPC 716 are supplied to the pixel portion 702, the source driver circuit portion 704, the gate driver circuit portion 706, and the FPC terminal portions 708 through the wiring 710.

[0358] In addition, a plurality of gate driver circuit portions 706 may be provided in the display device 700. In addition, as the display device 700, although an example in which the source driver circuit portion 704 and the gate driver circuit portion 706 are formed on the same first substrate 701 as the pixel portion 702 is shown, the structure is not limited thereto. For example, only the gate driver circuit portion 706 may be formed on the first substrate 701, or only the source driver circuit portion 704 may be formed on the first substrate 701. At this time, a structure in which a substrate (for example, a driver circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) on which a source driver circuit or a gate driver circuit or the like is formed is mounted on the first substrate 701 may also be employed. In addition, there is no particular limitation on the connection method for the separately formed driver circuit substrate, and a COG (Chip On Glass) method, a wire bonding method, or the like may be employed.

[0359] In addition, the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 included in the display device 700 include a plurality of transistors, and the transistors described in Embodiment 2 may be applied as the transistors.

[0360] In addition, the display device 700 can adopt various methods or have various display elements. As the display element, for example, a liquid crystal element, an EL (electroluminescence) element including LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) (including EL elements of organic and inorganic materials, organic EL elements or inorganic EL elements), a transistor (a transistor that emits light according to current), an electron emission element, an electrophoretic element, a display element using microelectromechanical systems (MEMS) such as a grating light valve (GLV), a digital micromirror device (DMD), a digital microshutter (DMS) element, a MIRASOL (registered trademark) display, an interference modulation (IMOD) element, a piezoelectric ceramic display, an electrowetting element, etc. In addition to this, it can also include a display medium whose contrast, brightness, reflectivity, transmittance, etc. change due to an electric or magnetic action. In addition, quantum dots can also be used as the display element. As an example of a display device using a liquid crystal element, there are liquid crystal displays (transmissive liquid crystal displays, transflective liquid crystal displays, reflective liquid crystal displays, direct-view liquid crystal displays, projection liquid crystal displays), etc. As an example of a display device using an EL element, there is an EL display, etc. As an example of a display device using an electron emission element, there is a field emission display (FED) or a SED type flat panel display (SED: Surface-conduction Electron-emitter Display: surface conduction electron emission display), etc. As an example of a display device using quantum dots, there is a quantum dot display, etc. As an example of a display device using electronic ink or an electrophoretic element, there is an electronic paper, etc. Note that when implementing a transflective liquid crystal display or a reflective liquid crystal display, it is only necessary to make a part or all of the pixel electrodes have the function of a reflective electrode. For example, it is only necessary to make a part or all of the pixel electrodes contain aluminum, silver, etc. And at this time, a storage circuit such as an SRAM can also be provided under the reflective electrode. Thereby, the power consumption can be further reduced.

[0361] As the display method of the display device 700, a progressive scanning method, an interlaced scanning method, etc. can be adopted. In addition, as the color elements controlled in the pixels during color display, they are not limited to the three colors of RGB (R represents red, G represents green, and B represents blue). For example, it can be composed of four pixels of R pixels, G pixels, B pixels, and W (white) pixels. Or, like the PenTile arrangement, it can also be composed of two colors in RGB to form one color element, and different two colors are selected according to the color element to form. Or one or more colors such as yellow, cyan, and magenta can be added to RGB. In addition, the display area sizes of the dots of each color element can be different. However, the disclosed invention is not limited to display devices for color display, but can also be applied to display devices for black-and-white display.

[0362] In addition, in order to use white light (W) for the backlight (organic EL element, inorganic EL element, LED, fluorescent lamp, etc.) to enable the display device to perform full-color display, a coloring layer (also called a color filter) can also be used. As the coloring layer, for example, red (R), green (G), blue (B), yellow (Y), etc. can be appropriately combined and used. By using the coloring layer, the color reproducibility can be further improved compared with the case of not using the coloring layer. At this time, by providing an area including the coloring layer and an area not including the coloring layer, the white light in the area not including the coloring layer can be directly used for display. By partially providing an area not including the coloring layer, when displaying a bright image, sometimes the brightness reduction caused by the coloring layer can be reduced, and the power consumption can be reduced by about two to three tenths. However, when using a self-luminous element such as an organic EL element or an inorganic EL element for full-color display, R, G, B, Y, and white (W) can also be emitted from elements having respective light-emitting colors. By using the self-luminous element, sometimes the power consumption can be further reduced compared with the case of using the coloring layer.

[0363] In this embodiment, use Figure 25 and Figure 26 to illustrate the structure of a display device using a VA (vertical alignment) type liquid crystal element as a display element. The VA type refers to a type of method for controlling the alignment of liquid crystal molecules of a display device. A VA type liquid crystal display device is a normally black type display device in which the liquid crystal molecules are oriented in a direction perpendicular to the panel surface when no voltage is applied. In the display device shown in this embodiment, one pixel is divided into several regions (sub-pixels), and the liquid crystal molecules are respectively tilted in different directions. This is called multi-domain or multi-domain design.

[0364] Figure 25 is Figure 24 a cross-sectional view between the dotted lines Q-R shown. Figure 25 The display device 700 shown includes: a winding wiring portion 711; a pixel portion 702; a source driver circuit portion 704; and an FPC terminal portion 708. Further, the winding wiring portion 711 includes a wiring 710. Further, the pixel portion 702 includes a transistor 750 and a capacitor element 790. Further, the source driver circuit portion 704 includes a transistor 752.

[0365] The transistor 750 and the transistor 752 may use the transistors described in Embodiment 2.

[0366] The transistor used in this embodiment includes an oxide semiconductor film that is highly purified and has suppressed formation of oxygen defects. This transistor can reduce the current value in the off state (off-state current value). Therefore, the holding time of an electrical signal such as an image signal can be extended, and the writing interval can also be extended in the state where the power is on. Therefore, the frequency of the refresh operation can be reduced, and thus the effect of suppressing power consumption can be exhibited.

[0367] Further, the transistor used in this embodiment can achieve a high field-effect mobility, and thus can perform high-speed driving. For example, by using such a transistor capable of high-speed driving in a liquid crystal display device, a switching transistor of the pixel portion and a driving transistor for the driver circuit portion can be formed on the same substrate. That is, since a semiconductor device formed of a silicon wafer or the like does not need to be separately used as the driver circuit, the number of components of the semiconductor device can be reduced. Further, in the pixel portion, a high-quality image can also be provided by using a transistor capable of high-speed driving.

[0368] The capacitor element 790 has a structure having a dielectric between a pair of electrodes. More specifically, one electrode of the capacitor element 790 uses a conductive film formed by the same process as the conductive film used as the gate electrode of the transistor 750, and the other electrode of the capacitor element 790 uses the conductive film used as the source electrode and the drain electrode of the transistor 750. Further, the dielectric sandwiched between the pair of electrodes uses the insulating film used as the gate insulating film of the transistor 750.

[0369] Further, in Figure 25 there are provided insulating films 764, 766, 768, and a planarizing insulating film 770 on the transistor 750, the transistor 752, and the capacitor element 790.

[0370] The insulating films 764, 766, and 768 can be formed using the same materials and manufacturing methods as the insulating films 514, 516, and 518 described in Embodiment 2. As the planarization insulating film 770, an organic material having heat resistance such as polyimide resin, acrylic resin, polyimide amide resin, benzocyclobutene resin, polyamide resin, epoxy resin, etc. can be used. Also, the planarization insulating film 770 can be formed by laminating a plurality of insulating films formed from these materials. Additionally, a structure without the planarization insulating film 770 can also be adopted.

[0371] The wiring 710 is formed in the same process as the conductive films serving as the source electrodes and drain electrodes of the transistors 750 and 752. The wiring 710 can also use a conductive film formed in a process different from the conductive films serving as the source electrodes and drain electrodes of the transistors 750 and 752, such as using the conductive film serving as the gate electrode. As the wiring 710, for example, when a material containing copper element is used, signal delay due to wiring resistance is less, and a large-screen display can be achieved.

[0372] In addition, the FPC terminal portion 708 includes a connection electrode 760, an anisotropic conductive film 780, and an FPC 716. The connection electrode 760 is formed in the same process as the conductive films serving as the source electrodes and drain electrodes of the transistors 750 and 752. Additionally, the connection electrode 760 and the terminals included in the FPC 716 are electrically connected through the anisotropic conductive film 780.

[0373] In addition, as the first substrate 701 and the second substrate 705, for example, a glass substrate can be used. Additionally, the first substrate 701 and the second substrate 705 can use the same materials as the substrate 502 described in Embodiment 2.

[0374] On the side of the second substrate 705, a light-shielding film 738 serving as a black matrix, a colored layer 736 serving as a color filter, and an insulating film 734 in contact with the light-shielding film 738 and the colored layer 736 are provided.

[0375] In addition, a structure body 778 is provided between the first substrate 701 and the second substrate 705. The structure body 778 is a columnar spacer obtained by selectively etching the insulating film, and is used to control the distance between the first substrate 701 and the second substrate 705 (cell gap). Additionally, as the structure body 778, a spherical spacer can also be used.

[0376] In addition, as Figure 26 shown, a stack of a plurality of colored layers 736 can also be used as a spacer instead of the structure body 778. For example, Figure 26 The display device 700 shown includes a red color layer 736R, a green color layer 736G, and a blue color layer 736B. The color layers 736G and 736B are provided at positions overlapping with the light-shielding film 738 on the color layer 736R. By adopting this structure, the process of forming the structure 778 can be omitted. In addition, Figure 26 The display device 700 shown does not include the insulating film 734. In addition, as the above-described spacer, a laminate of any two of the color layer 736R, the color layer 736G, and the color layer 736B can also be used.

[0377] In the present embodiment, a structure in which the structure 778 is provided on one side of the first substrate 701 is shown, but it is not limited thereto. For example, a structure in which the structure 778 is provided on one side of the second substrate 705 or a structure in which the structure 778 is provided on both the first substrate 701 and the second substrate 705 can also be adopted.

[0378] The display device 700 includes a liquid crystal element 775. The liquid crystal element 775 includes a conductive film 772, a conductive film 774, and a liquid crystal layer 776. The conductive film 774 is provided on one side of the second substrate 705 and is used as a counter electrode. The display device 700 can display an image by changing the alignment state of the liquid crystal layer 776 by the voltage applied to the conductive film 772 and the conductive film 774, thereby controlling the transmission and non-transmission of light. Protrusions 744 are provided on the conductive film 774.

[0379] The conductive film 772 is connected to the conductive films used as the source electrode and the drain electrode of the transistor 750. The conductive film 772 is formed on the planarization insulating film 770 and is used as a pixel electrode, that is, one electrode of the display element. In addition, the conductive film 772 has the function of a reflective electrode. The display device 700 is a so-called reflective color liquid crystal display device that reflects external light by the conductive film 772 and performs display through the color layer 736.

[0380] In addition, as the conductive film 772, a conductive film having translucency to visible light or a conductive film having reflectivity to visible light can be used. As the conductive film having translucency to visible light, for example, a material containing one selected from indium (In), zinc (Zn), and tin (Sn) is preferably used. As the conductive film having reflectivity to visible light, for example, a material containing aluminum or silver is preferably used. In the present embodiment, a conductive film having reflectivity to visible light is used as the conductive film 772.

[0381] In addition, when a conductive film having reflectivity to visible light is used, the conductive film 772 can also adopt a laminated structure. For example, an aluminum film having a thickness of 100 nm is formed as the lower layer, and a silver alloy film (for example, an alloy film containing silver, palladium, and copper) having a thickness of 30 nm is formed as the upper layer. By adopting the above structure, the following excellent effects are exhibited.

[0382] The above excellent effects are as follows: (1) The adhesion between the base film and the conductive film 772 can be improved; (2) The aluminum film and the silver alloy film can be etched together using a chemical solution; (3) The cross-sectional shape of the conductive film 772 can be made into a good shape (for example, a tapered shape). The reason for (3) can be considered as follows: When etching with a chemical solution, the etching rate of the aluminum film is slower than that of the silver alloy film, or when the lower aluminum film is exposed after etching the upper silver alloy film, electrons are extracted from the metal that is less noble than the silver alloy film, in other words, aluminum with a high ionization tendency, whereby the etching of the silver alloy film is suppressed, and the etching rate of the lower aluminum film is fast.

[0383] In addition, as Figures 25 to 27 An example of the display device 700 shown is a reflective color liquid crystal display device, but the mode of the display device 700 is not limited to this. For example, a transmissive color liquid crystal display device using a conductive film having light transmittance to visible light as the conductive film 772 can also be adopted. In the case where the display device 700 is a transmissive liquid crystal display device, a pair of electrodes included in the capacitive element 790 are provided at positions that do not overlap with the conductive film 772. In addition, each layer provided in the path of light incident from the substrate 701 and exiting through the liquid crystal element 775 and the coloring layer 736 is preferably a layer having light transmittance to visible light.

[0384] The conductive film 772 includes a slit 725. The slit 725 is provided to control the alignment of liquid crystal molecules. An alignment film 746 is provided on the conductive film 772, the planarization insulating film 770, and the structure 778, and similarly, an alignment film 748 is provided on the conductive film 774.

[0385] When a voltage is applied to the conductive film 772 formed with the slit 725, an electric field strain (tilted electric field) is generated near the slit 725. By arranging the slit 725 and the protrusion 744 on the substrate 705 side in an interlocking manner, a tilted electric field is effectively generated and the alignment of the liquid crystal is controlled, and the direction of the liquid crystal alignment is made different according to each position. That is, by making the liquid crystal molecules tilt in different directions in each sub-pixel included in one pixel to perform multi-domainization, the viewing angle of the liquid crystal display panel is expanded.

[0386] In addition, although not shown in Figure 25 , optical members (optical substrates) such as a polarization member, a retardation member, and an antireflection member can also be appropriately provided. For example, circular polarization using a polarization substrate and a retardation substrate can also be used. In addition, as a light source, a backlight, a side light, etc. can also be used.

[0387] The structure shown in this embodiment can be implemented by appropriately combining with the structures shown in other embodiments.

[0388] Embodiment 5

[0389] In this embodiment, a display module and an electronic device having one aspect of the present invention will be described with reference to Figure 27 FIGs. 28 to 28.

[0390] Figure 27 The illustrated display module 8000 includes, between an upper cover 8001 and a lower cover 8002, a touch panel 8004 connected to an FPC 8003, a display panel 8006 connected to an FPC 8005, a backlight 8007, a frame 8009, a printed circuit board 8010, and a battery 8011.

[0391] One aspect of the display device of the present invention can be used, for example, for the display panel 8006.

[0392] The upper cover 8001 and the lower cover 8002 can appropriately change their shapes or sizes according to the sizes of the touch panel 8004 and the display panel 8006.

[0393] The touch panel 8004 can be a resistive film type touch panel or a capacitive touch panel, and can be formed so as to overlap with the display panel 8006. In addition, the counter substrate (sealing substrate) of the display panel 8006 can also have the function of a touch panel. Further, a light sensor can be provided in each pixel of the display panel 8006 to form an optical touch panel.

[0394] The backlight 8007 includes a light source 8008. Note that, although a structure in which the light source 8008 is disposed on the backlight 8007 is illustrated in Figure 27 , it is not limited thereto. For example, the light source 8008 can be provided at an end of the backlight 8007, and a light diffusion plate can be used. When a self-luminous type light-emitting element such as an organic EL element is used, or when a reflective panel is used, a structure in which the backlight 8007 is not provided can be adopted.

[0395] In addition to the function of protecting the display panel 8006, the frame 8009 also has an electromagnetic shielding function for blocking electromagnetic waves generated by the operation of the printed circuit board 8010. Further, the frame 8009 can also have the function of a heat dissipation plate.

[0396] The printed circuit board 8010 includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power supply for supplying power to the power supply circuit, either an external commercial power supply or the power of a separately provided battery 8011 can be used. When a commercial power supply is used, the battery 8011 can be omitted.

[0397] In addition, members such as a polarizing plate, a retardation plate, and a prism sheet can also be provided in the display module 8000.

[0398] Figures 28A to 28G This is a diagram showing electronic devices. These electronic devices may include a housing 5000, a display unit 5001, a speaker 5003, an LED lamp 5004, operation keys 5005 (including a power switch or an operation switch), connection terminals 5006, a sensor 5007 (having the function of measuring factors such as force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, inclination, vibration, odor, or infrared rays), a microphone 5008, etc.

[0399] Figure 28A This shows a mobile computer, which may further include a switch 5009, an infrared port 5010, etc. in addition to the above. Figure 28B This shows a portable image reproduction device (such as a DVD reproduction device) having a recording medium, which may further include a second display unit 5002, a recording medium reading unit 5011, etc. in addition to the above. Figure 28C This shows a goggle-type display, which may further include a second display unit 5002, a support unit 5012, earphones 5013, etc. in addition to the above. Figure 28D This shows a portable game console, which may further include a recording medium reading unit 5011, etc. in addition to the above. Figure 28E This shows a digital camera having a television receiving function, which may further include an antenna 5014, a shutter button 5015, an image receiving unit 5016, etc. in addition to the above. Figure 28F This shows a portable game console, which may further include a second display unit 5002, a recording medium reading unit 5011, etc. in addition to the above. Figure 28G This shows a portable television receiver, which may further include a charger 5017 capable of transmitting and receiving signals, etc. in addition to the above.

[0400] Figures 28A to 28G The electronic device shown can have various functions. For example, it can have the following functions: displaying various data (such as static images, dynamic images, text images, etc.) on the display unit; a touch panel; displaying a calendar, date, time, etc.; controlling processing by using various software (programs); performing wireless communication; connecting to various computer networks by using the wireless communication function; sending or receiving various data by using the wireless communication function; reading out programs or data stored in a recording medium and displaying them on the display unit, etc. Furthermore, in an electronic device having multiple display units, it can have the following functions: one display unit mainly displays image data, while the other display unit mainly displays text data; or, displaying images considering parallax on multiple display units to display a stereoscopic image, etc. Furthermore, in an electronic device having an image receiving unit, it can have the following functions: taking a static image; taking a dynamic image; automatically or manually correcting the taken image; storing the taken image in a recording medium (external or built into the camera); displaying the taken image on the display unit, etc. Note that Figures 28A to 28G The functions that the electronic device shown can have are not limited to the above functions, but can have various functions.

[0401] The electronic device according to this embodiment is characterized by having a display unit for displaying certain information. In addition, the display device shown in Embodiment 4 can be appropriately applied to this display unit.

[0402] The structure shown in this embodiment can be implemented by appropriately combining with the structures shown in other embodiments.

[0403] Symbol Explanation

[0404] 100 pixels

[0405] 101 substrate

[0406] 103 scanning line

[0407] 105a capacitive wiring

[0408] 105b capacitive wiring

[0409] 107 gate insulating film

[0410] 107a gate insulating film

[0411] 107b gate insulating film

[0412] 114 insulating film

[0413] 116 insulating film

[0414] 116a insulating film

[0415] 116b insulating film

[0416] 116c Insulating Film

[0417] 121 Signal Line

[0418] 123 Electrode

[0419] 125a Electrode

[0420] 125b Electrode

[0421] 135 Semiconductor Film

[0422] 135a Oxide Semiconductor Film

[0423] 135b Oxide Semiconductor Film

[0424] 136 Transistor

[0425] 137 Transistor

[0426] 139a Pixel Electrode

[0427] 139b Pixel Electrode

[0428] 140 Capacitor Element

[0429] 141 Capacitor Element

[0430] 142 Liquid Crystal Element

[0431] 143 Liquid Crystal Element

[0432] 144a Opening

[0433] 144b Opening

[0434] 145 Capacitor Element

[0435] 146 Capacitor Element

[0436] 148 Pixel Electrode

[0437] 148a Oxide Conductor Film

[0438] 148b Oxide Conductor Film

[0439] 149 Pixel Electrode

[0440] 200 Pixel

[0441] 203 Scanning Line

[0442] 221 Signal Line

[0443] 223a Electrode

[0444] 223b Electrode

[0445] 236 Transistor

[0446] 237 Transistor

[0447] 300 Pixels

[0448] 301 Substrate

[0449] 303 Scanning Line

[0450] 305a Capacitor Wiring

[0451] 305b Capacitor Wiring

[0452] 307 Gate Insulating Film

[0453] 316 Insulating Film

[0454] 321 Signal Line

[0455] 323a Electrode

[0456] 323b Electrode

[0457] 325a Electrode

[0458] 325b Electrode

[0459] 335 Semiconductor Film

[0460] 336 Transistor

[0461] 337 Transistor

[0462] 339a Pixel Electrode

[0463] 339b Pixel Electrode

[0464] 340 Capacitor Element

[0465] 341 Capacitor Element

[0466] 342 Liquid Crystal Element

[0467] 343 Liquid Crystal Element

[0468] 344a Opening

[0469] 344b Opening

[0470] 345a Electrode

[0471] 345b Electrode

[0472] 346a Opening

[0473] 346b Opening

[0474] 500 Transistor

[0475] 502 Substrate

[0476] 504 Conductive Film

[0477] 506 Insulating Film

[0478] 507 Insulating Film

[0479] 508 Oxide Semiconductor Film

[0480] 508a Oxide Semiconductor Film

[0481] 508b Oxide Semiconductor Film

[0482] 509 Oxide Semiconductor Film

[0483] 509a Oxide Semiconductor Film

[0484] 509b Oxide Semiconductor Film

[0485] 512 Conductive Film

[0486] 512a Conductive Film

[0487] 512b Conductive Film

[0488] 514 Insulating Film

[0489] 516 Insulating Film

[0490] 518 Insulating Film

[0491] 519 Insulating Film

[0492] 520 Conductive Film

[0493] 520a Conductive Film

[0494] 520b Conductive Film

[0495] 531 Barrier Film

[0496] 536a Mask

[0497] 536b Mask

[0498] 538 Etchant

[0499] 539 Etchant

[0500] 540 Oxygen

[0501] 540a Oxygen

[0502] 542 Etchant

[0503] 542a Opening

[0504] 542b Opening

[0505] 542c Opening

[0506] 570 Transistor

[0507] 700 Display device

[0508] 701 Substrate

[0509] 702 Pixel section

[0510] 704 Source driver circuit section

[0511] 705 Substrate

[0512] 706 Gate driver circuit section

[0513] 708 FPC terminal section

[0514] 710 Wiring

[0515] 711 Wiring section

[0516] 712 Sealant

[0517] 716 FPC

[0518] 725 Slit

[0519] 734 Insulating film

[0520] 736 Coloring layer

[0521] 736B Coloring layer

[0522] 736G Coloring layer

[0523] 736R Coloring layer

[0524] 738 Light-shielding film

[0525] 744 Protrusion

[0526] 746 Alignment film

[0527] 748 Alignment film

[0528] 750 Transistor

[0529] 752 Transistor

[0530] 760 Connection electrode

[0531] 764 Insulating film

[0532] 766 Insulating film

[0533] 768 Insulating film

[0534] 770 Planarization insulating film

[0535] 772 Conductive film

[0536] 774 Conductive film

[0537] 775 Liquid crystal element

[0538] 776 Liquid crystal layer

[0539] 778 Structure

[0540] 780 Anisotropic conductive film

[0541] 790 Capacitor element

[0542] 5000 Housing

[0543] 5001 Display unit

[0544] 5002 Display unit

[0545] 5003 Speaker

[0546] 5004 LED lamp

[0547] 5005 Operation key

[0548] 5006 Connection terminal

[0549] 5007 Sensor

[0550] 5008 Microphone

[0551] 5009 Switch

[0552] 5010 Infrared port

[0553] 5011 Recording medium reading unit

[0554] 5012 Support part

[0555] 5013 Earphone

[0556] 5014 Antenna

[0557] 5015 Shutter button

[0558] 5016 Image receiving unit

[0559] 5017 Charger

[0560] 5100 Particle

[0561] 5120 Substrate

[0562] 5161 Area

[0563] 8000 Display module

[0564] 8001 Upper cover

[0565] 8002 Lower cover

[0566] 8003 FPC

[0567] 8004 Touch panel

[0568] 8005 FPC

[0569] 8006 Display Panel

[0570] 8007 Backlight

[0571] 8008 Light Source

[0572] 8009 Frame

[0573] 8010 Printed Circuit Board

[0574] 8011 Battery

Claims

1. A semiconductor device, comprising: a pixel, the pixel comprising: a first transistor; a second transistor; a first pixel electrode electrically connected to the first transistor; and a second pixel electrode electrically connected to the second transistor, wherein a first conductive layer is in contact with the substrate and has a first region serving as a gate electrode of the first transistor and a second region serving as a gate electrode of the second transistor, wherein a second conductive layer is in contact with the substrate and contains the same material as the first conductive layer, wherein a gate insulating layer is provided on the first conductive layer and the second conductive layer, and wherein a semiconductor layer is provided on the gate insulating layer and includes a channel formation region of the first transistor and a channel formation region of the second transistor, wherein a third conductive layer is provided on the semiconductor layer and includes a first region serving as one of a source electrode and a drain electrode of the first transistor and a second region serving as one of a source electrode and a drain electrode of the second transistor, wherein a fourth conductive layer is provided on the semiconductor layer and includes a region serving as the other of the source electrode and the drain electrode of the first transistor, wherein a first insulating layer is provided on the third conductive layer and the fourth conductive layer, and wherein the second conductive layer includes a first region overlapping with a first contact hole provided in the first insulating layer and a second region overlapping with a second contact hole provided in the gate insulating layer, wherein the fourth conductive layer includes a region overlapping with the first contact hole and not overlapping with the second contact hole, wherein the first pixel electrode includes a region overlapping with the second contact hole, and wherein the first pixel electrode and the second pixel electrode are provided on the first insulating layer, wherein, in a top view, an area of the first contact hole is larger than an area of the second contact hole, and wherein the third conductive layer does not overlap with the first pixel electrode and the second pixel electrode.

Images