Solar cell and manufacturing method thereof

Abstract

The invention discloses a solar cell and a manufacturing method thereof, relates to the field of photovoltaic technology, and aims to increase the surface area of one side, deviating from a semiconductor substrate, of a first semiconductor layer and facilitate the increase of the contact area between the first semiconductor layer and a transparent conductive layer or an electrode and other conductive materials. Therefore, the transmission loss of carriers collected in the first semiconductor layer transmitted to the conductive material is reduced, and the working efficiency of the solar cell is improved. The solar cell includes a semiconductor substrate and a first semiconductor layer. The semiconductor substrate has a first surface and a second surface opposite to each other. At least one of the first surface and the second surface is a target surface. The surface of at least part of the area of the target surface is a suede, and the suede comprises a plurality of pyramid-like parts. The first semiconductor layer is disposed on the textured surface. A hole structure is arranged in the first semiconductor layer, and the hole structure is distributed in the part, covering at least part of the pyramid-like top, of the first semiconductor layer. The material of the first semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

Description

[0001] This application claims the priority of a Chinese patent with an application number of 202411132114.1 and an invention title of "A Solar Cell and Its Manufacturing Method" filed with the Chinese Patent Office on August 16, 2024. The entire content thereof is incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of photovoltaic technology, and particularly to a solar cell and its manufacturing method. Background Art

[0003] A solar cell is a device that can convert solar light energy into electrical energy. Specifically, when the solar cell is in a working state, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After connecting the circuit, an electric current can be generated. Among them, setting the surface where the semiconductor substrate included in the solar cell is in contact with the semiconductor layer of at least one conductive type as a matte surface is not only conducive to making more light refract into the semiconductor substrate through the matte surface, improving the working efficiency of the solar cell; but also conducive to increasing the contact area between the semiconductor layer and conductive materials (such as a transparent conductive layer or an electrode, etc.), reducing the transmission loss.

[0004] However, the reduction in the transmission loss between the semiconductor layer included in the existing solar cell and the conductive material is relatively small, which is not conducive to further improving the working efficiency of the solar cell. Summary of the Invention

[0005] The purpose of the present invention is to provide a solar cell and its manufacturing method, which is used to increase the surface area on the side of the first semiconductor layer facing away from the semiconductor substrate, conducive to increasing the contact area between the first semiconductor layer and conductive materials such as a transparent conductive layer or an electrode, thereby conducive to reducing the transmission loss of the carriers collected in the first semiconductor layer to the conductive material, and improving the working efficiency of the solar cell.

[0006] To achieve the above purpose, in a first aspect, the present invention provides a solar cell, which includes: a semiconductor substrate and a first semiconductor layer. The semiconductor substrate has opposite first and second surfaces. At least one of the first surface and the second surface is a target surface. At least a partial area of the surface of the target surface is a matte surface, and the matte surface includes a plurality of pyramid-like shapes. The first semiconductor layer is disposed on the matte surface. A hole structure is disposed in the first semiconductor layer, and the hole structure is distributed in the portion of the first semiconductor layer covering at least a part of the tops of the pyramid-like shapes. The material of the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0007] In the case of adopting the above technical solution, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon materials contain hydrogen, which can hydrogenate the dangling bonds on the surface of the semiconductor substrate, reduce surface defects, and thus have a high passivation effect on the semiconductor substrate. Therefore, when the material of the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, the part of the semiconductor substrate corresponding to the textured surface has a low carrier recombination rate, which is beneficial to improving the working efficiency of the solar cell. In addition, compared with the case where the surface of the first semiconductor layer facing away from the semiconductor substrate is a flat surface, when the first semiconductor layer is disposed on the textured surface, the surface of the first semiconductor layer facing away from the semiconductor substrate has a rough morphology substantially the same as that of the textured surface. At this time, the first semiconductor layer has a larger specific surface area, which can increase the contact area between the first semiconductor layer and the conductive material (such as a transparent conductive layer or an electrode). Secondly, a hole structure is provided in the first semiconductor layer. The provision of this hole structure makes the part of the first semiconductor layer covering at least part of the top of the pseudo-pyramids further have an inwardly concave rough morphology, further increasing the specific surface area of the side of the first semiconductor layer facing away from the semiconductor substrate, which is beneficial to further increasing the contact area between the first semiconductor layer and the conductive material, and further reducing the transmission loss of carriers from the first semiconductor layer to the conductive material. However, the hole structure will cause the passivation effect to weaken and reduce the current collection efficiency of the solar cell. Therefore, in the present invention, the hole structure is only provided at the top of at least part of the pseudo-pyramids, and a similar hole structure is not provided at the base of the pseudo-pyramids, which can improve the contact performance of the first semiconductor layer while ensuring the passivation effect of the first semiconductor layer.

[0008] As a possible implementation solution, at least one hole included in the above hole structure is a blind hole that does not penetrate the first semiconductor layer.

[0009] In the case of adopting the above technical solution, it can be understood that when at least one hole included in the hole structure is a through hole penetrating the first semiconductor layer, the part of the first semiconductor layer corresponding to the through hole cannot passivate the surface of the semiconductor substrate corresponding to the bottom of the through hole, affecting the passivation effect of the first semiconductor layer on the semiconductor substrate. Moreover, when the conductive material is in direct contact with the semiconductor substrate through the through hole, a relatively high carrier recombination will also occur at the bottom of the through hole. Based on this, compared with the above through hole, when at least one hole included in the hole structure is a blind hole that does not penetrate the first semiconductor layer, along the direction away from the textured surface, a part of the first semiconductor layer corresponding to the blind hole still retains a certain thickness, and this part of the first semiconductor layer can passivate a part of the surface of the semiconductor substrate corresponding to the blind hole, ensuring that while reducing the transmission loss of carriers from the first semiconductor layer to the conductive material, the first semiconductor layer has a relatively high passivation effect on the semiconductor substrate, further improving the working efficiency of the solar cell. In addition, it can be understood that in the actual manufacturing process, when the thickness of the first semiconductor layer is the same, compared with forming a through hole in the first semiconductor layer, the processing time for forming a blind hole with a smaller hole depth in the first semiconductor layer is shorter, and it is easier to reduce the influence degree of the processing process on the part of the first semiconductor layer where the hole structure is not opened, ensuring that the first semiconductor layer has a relatively high passivation effect.

[0010] As a possible implementation solution, the aperture of at least one hole included in the above hole structure is less than 100 nm. In this case, it can be understood that the thickness of the part of the first semiconductor layer where the hole structure is formed is relatively small, resulting in a poor passivation effect on the textured surface. Based on this, when the aperture of at least one hole included in the hole structure is less than 100 nm, it can be prevented that due to the relatively large aperture of the holes included in the hole structure, ensuring that the first semiconductor layer has a relatively high passivation effect on the textured surface.

[0011] As a possible implementation solution, the above-mentioned pseudo-pyramid is a pyramid with a sharp apex; or, the pseudo-pyramid is a pseudo-pyramid with a rounded chamfer; or, the pseudo-pyramid is a pseudo-pyramid with a flattened apex. However, no matter which pyramid structure it is, its shape still tends to be more pyramid-shaped rather than the tower base shape of a polished surface. Such a design can make the pseudo-pyramid have a relatively obvious apex or tip, so that when laser processing is carried out, light can form a hole structure at the top of some pseudo-pyramids. In addition, there is no need to strictly control the manufacturing accuracy in order to obtain a single-morphology pseudo-pyramid, reducing the process difficulty and being beneficial to improving the yield of the solar cell.

[0012] As a possible implementation solution, the crystallization degree of the part of the above first semiconductor layer covering at least part of the top of the pseudo-pyramid is greater than the crystallization degree of the part of the first semiconductor layer covering the base of the pseudo-pyramid.

[0013] In the case of adopting the above technical solution, as described above, setting the above hole structure can increase the contact area between the first semiconductor layer and the conductive material, and reduce the transmission loss of carriers between the two. Moreover, the hole structure is distributed in the part of the first semiconductor layer covering at least part of the top of the pseudo-pyramid. Based on this, when the crystallization degree of the part of the first semiconductor layer covering at least part of the top of the pseudo-pyramid is greater than the crystallization degree of the part of the first semiconductor layer covering the base of the pseudo-pyramid, it is beneficial to make the part of the first semiconductor layer covering at least part of the top of the pseudo-pyramid have a relatively large crystallization degree while increasing its own surface area by setting the hole structure, thereby reducing its own transmission resistance, further reducing the transmission loss of carriers through the first semiconductor layer to the conductive material, and further improving the working efficiency of the solar cell. In addition, in the actual manufacturing process, laser irradiation or high-temperature annealing, etc. are required to achieve the crystallization modification of part of the first semiconductor layer, and the heating rate of the top of the pseudo-pyramid is faster than that of its own substrate, and it is easier to achieve crystallization modification; based on this, when the crystallization degree of the part of the first semiconductor layer covering at least part of the top of the pseudo-pyramid is greater than the crystallization degree of the part of the first semiconductor layer covering the base of the pseudo-pyramid, there is no need to make the part of the first semiconductor layer covering the base of the pseudo-pyramid also have a large crystallization degree, which may cause dehydrogenation due to the long heating time of each part of the first semiconductor layer, ensuring that the first semiconductor layer has a high passivation effect. Secondly, for the part of the first semiconductor layer covering at least part of the top of the pseudo-pyramid and having a large crystallization degree, it can reduce the contact resistance between the first semiconductor layer and the conductive material layer (such as a transparent conductive layer or a metal electrode layer, etc.), increase the current transmission efficiency, and at the same time, for the part of the first semiconductor layer covering the base of the pseudo-pyramid with a small crystallization degree, it ensures the passivation effect, generally achieving the purpose of improving the battery efficiency. And this manufacturing method is simple, and the local crystallization degree of the first semiconductor layer covering at least part of the top of the pseudo-pyramid can be directly increased through processes such as laser or high-temperature annealing, so that it is greater than the crystallization degree of the first semiconductor layer arranged at the base of the pseudo-pyramid.

[0014] As a possible implementation solution, among all the pseudo-pyramids formed on the textured surface, the pseudo-pyramids located below the hole structure are the first type of pseudo-pyramids, and the remaining pseudo-pyramids are the second type of pseudo-pyramids. Among them, along the direction away from the textured surface, the height of the first type of pseudo-pyramid is greater than the height of at least part of the other adjacent pseudo-pyramids; and / or, among all the pseudo-pyramids formed on the textured surface, the number of the second type of pseudo-pyramids adjacent to a single first type of pseudo-pyramid is greater than the number of the other first type of pseudo-pyramids adjacent to this first type of pseudo-pyramid.

[0015] In the case of adopting the above technical solution, it can be understood that the distance between the top and the base of a class pyramid with a greater height is larger. The contact area between the base of the class pyramid and the semiconductor substrate is relatively large, and the semiconductor substrate has a good heat dissipation effect. Therefore, during the process of forming the hole structure, the heat dissipated by the top of a class pyramid with a greater height after being heated may be less, and it is easier to accumulate more heat to melt itself and make the hydrogen in it escape to obtain the hole structure. In addition, when using the laser irradiation process to form the hole structure, since the class pyramid has a reflecting effect on the laser, the reflected laser is more likely to be concentrated on the top of the class pyramid with a greater height, so that the top of the class pyramid with a greater height is heated to a higher degree. Based on this, when in the direction away from the textured surface, the height of the first type of pyramid located below the hole structure is greater than the height of at least some of the other adjacent class pyramids, the process difficulty can be reduced, and at the same time, it can be prevented that the part of the first semiconductor layer above the top of the class pyramid with a greater height is overheated due to the formation of the hole structure above the top of the class pyramid with a smaller height, resulting in a poor passivation effect, thereby further improving the working efficiency of the solar cell.

[0016] In addition, when the number of other class pyramids adjacent to a single class pyramid (adjacent means adjacent and the bases of the two class pyramids are in contact with each other) is relatively large, that is, the distribution density of the other class pyramids around the single class pyramid is relatively large, at this time, the laser reflected by the other class pyramids is more likely to be concentrated on the top of the corresponding class pyramid adjacent to it, making the heat at the top of the corresponding class pyramid relatively high, and thus it is easier to form the hole structure. Based on this, when among all the class pyramids formed on the textured surface, the number of the second type of pyramids adjacent to a single first type of pyramid is greater than the number of other first type of pyramids adjacent to the first type of pyramid, it is easier to reduce the process difficulty and is beneficial to improving the yield of the solar cell. At the same time, it can also prevent the distribution density of the hole structure in the first semiconductor layer from being relatively large and ensure that the first semiconductor layer has a relatively high passivation effect on the textured surface.

[0017] As a possible implementation solution, along the inclined direction of the side surface of the class pyramid, the ratio of the maximum extension length of the hole structure on the side surface of the class pyramid below it to the length of the side surface of the class pyramid is less than or equal to 0.5.

[0018] In the case of adopting the above technical solution, as described above, although the part with the hole structure in the first semiconductor layer can reduce the transmission loss between the first semiconductor layer and the conductive material, the thickness of the part with the hole structure in the first semiconductor layer is relatively small, so that the passivation effect of this part on the semiconductor substrate is relatively weak (compared with the part without the hole structure); based on this, when the ratio of the maximum extension length of the hole structure on the side surface of the class pyramid below itself to the length of the side surface of the class pyramid is less than or equal to 0.5 along the inclined direction of the side surface of the class pyramid, the part with a higher passivation effect in the first semiconductor layer can have a larger coverage range for the textured surface, and the number of surface defects of the textured surface can be further reduced. In addition, in the actual manufacturing process, the heating rate of the top of the class pyramid is faster than that of its own substrate, and it is easier to accumulate more heat at its own top to melt itself and make the hydrogen in itself escape to obtain the hole structure. Based on this, when the ratio of the maximum extension length of the hole structure on the side surface of the class pyramid below itself to the length of the side surface of the class pyramid is less than or equal to 0.5 along the inclined direction of the side surface of the class pyramid, it can prevent the part of the first semiconductor layer at the top of the class pyramid from overheating due to the large extension length of the hole structure above the class pyramid, affecting its own passivation effect, and ensure that the part of the first semiconductor layer at the top of the class pyramid also has a certain passivation effect, further improving the working efficiency of the solar cell.

[0019] As a possible implementation solution, the thickness of the part of the first semiconductor layer without the hole structure is greater than or equal to 10 nm, and / or the thickness of the part of the first semiconductor layer without the hole structure is less than or equal to 45 nm. In this case, the lower limit and / or the upper limit of the thickness of the first semiconductor layer including at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon are larger, which is beneficial to reducing the thermal influence of heat on the semiconductor substrate through a thicker first semiconductor layer, preventing thermal damage to the semiconductor substrate during the process of forming the hole structure in the first semiconductor layer, and ensuring that the solar cell has a high yield. Moreover, the thicker first semiconductor layer has a higher passivation effect, which can further reduce the carrier recombination rate at the textured surface and further improve the working efficiency of the solar cell.

[0020] As a possible implementation solution, the above solar cell further includes a transparent conductive layer, and the transparent conductive layer covers at least the side of the first semiconductor layer facing away from the semiconductor substrate and fills into the hole structure.

[0021] In the case of adopting the above technical solution, the transparent conductive layer has a high conductivity, can timely export the carriers collected by the first semiconductor layer, and can reduce the carrier recombination rate. Moreover, the transparent conductive layer not only covers the side of the first semiconductor layer facing away from the semiconductor substrate, but also fills into the hole structure. At this time, there is a large contact area between the transparent conductive layer and the first semiconductor layer, which can reduce the transmission loss and improve the working efficiency of the solar cell.

[0022] As a possible implementation solution, the surface of the above-mentioned quasi-pyramid is a plane. In this case, compared with the surface of the quasi-pyramid being uneven, when the surface of the quasi-pyramid is a plane, the undulation degree of the quasi-pyramid is relatively low, which is conducive to making the first semiconductor layer deposited on the textured surface have a larger thickness and further improving the passivation effect of the first semiconductor layer.

[0023] As a possible implementation solution, the above-mentioned first semiconductor layer includes: a first intrinsic semiconductor layer and a first doped semiconductor layer. The first doped semiconductor layer is disposed on the side of the first intrinsic semiconductor layer facing away from the semiconductor substrate. The hole structure at least does not penetrate the first intrinsic semiconductor layer.

[0024] In the case of adopting the above technical solution, the first intrinsic semiconductor layer and the first doped semiconductor layer can form a selective contact structure, which has an excellent interface passivation effect, can realize the selective collection of carriers, reduce the carrier recombination rate in the region of the semiconductor substrate where the first semiconductor layer is formed, and further improve the photoelectric conversion efficiency of the solar cell. Secondly, the hole structure at least does not penetrate the first intrinsic semiconductor layer. At this time, the part of the first intrinsic semiconductor layer corresponding to the hole structure still has a passivation effect on the semiconductor substrate, which can further reduce the carrier recombination rate.

[0025] As a possible implementation solution, the above-mentioned solar cell further includes a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer. Among them, the second semiconductor layer and the first semiconductor layer are disposed on the same side of the semiconductor substrate, and the first semiconductor layer extends to cover a part of the side of the second semiconductor layer facing away from the semiconductor substrate; and / or, the second semiconductor layer is disposed on the second side of the semiconductor substrate, and the material of the second semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0026] In the case of adopting the above technical solution, when the second semiconductor layer and the first semiconductor layer are disposed on the same side of the semiconductor substrate, the solar cell provided by the present invention is a back contact cell, which can reduce the influence of the light shielding electrode structure on the light utilization rate on the light-facing side, and further improve the photoelectric conversion efficiency of the solar cell. In addition, when the material of the second semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, there are various possible examples of the material of the second semiconductor layer, which is beneficial to improving the applicability of the solar cell provided by the present invention in different application scenarios.

[0027] In a second aspect, the present invention provides a method for manufacturing a solar cell. The method for manufacturing the solar cell includes: providing a semiconductor substrate. The semiconductor substrate has opposite first and second sides. At least one of the first side and the second side is a target side. At least a partial region of the surface of the target side is a textured surface. The textured surface includes a plurality of pyramidal-like structures. Next, a first semiconductor layer is formed on the textured surface. Next, the first semiconductor layer is processed to form a pore structure within the first semiconductor layer. The pore structure is distributed within a portion of the first semiconductor layer covering at least a part of the tops of the pyramidal-like structures. The material of the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0028] As a possible implementation, a laser irradiation process is adopted to modify at least a part of the first semiconductor layer to form a pore structure disposed within the first semiconductor layer.

[0029] For the beneficial effects of the second aspect and its various implementation manners of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, which will not be elaborated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0031] Figure 1 is a longitudinal sectional schematic view of the first structure of the solar cell provided by the embodiment of the present invention;

[0032] Figure 2 is a partial SEM of the solar cell provided by the embodiment of the present invention at the pore structure Figure 1 ;

[0033] Figure 3 is a longitudinal sectional schematic view of the second structure of the solar cell provided by the embodiment of the present invention;

[0034] Figure 4 is a longitudinal sectional schematic view of the third structure of the solar cell provided by the embodiment of the present invention;

[0035] Figure 5 Longitudinal sectional view schematic diagram of the fourth structure of the solar cell provided by the embodiment of the present invention;

[0036] Figure 6 Longitudinal sectional view schematic diagram of the fifth structure of the solar cell provided by the embodiment of the present invention;

[0037] Figure 7 Longitudinal sectional view schematic diagram of the sixth structure of the solar cell provided by the embodiment of the present invention;

[0038] Figure 8 Longitudinal sectional view schematic diagram of the structure of the pyramidal-like in the solar cell provided by the embodiment of the present invention Figure 1 ;

[0039] Figure 9 Longitudinal sectional view schematic diagram of the structure of the pyramidal-like in the solar cell provided by the embodiment of the present invention Figure 2 ;

[0040] Figure 10 Longitudinal sectional view schematic diagram of the seventh structure of the solar cell provided by the embodiment of the present invention;

[0041] Figure 11 Local SEM at the hole structure in the solar cell provided by the embodiment of the present invention Figure 2 ;

[0042] Figure 12 is Figure 11 Local SEM image of the framed area in;

[0043] Figure 13 is Figure 12 Local SEM image of the framed area in;

[0044] Figure 14 Longitudinal sectional view schematic diagram of the local part at the hole structure in the solar cell provided by the embodiment of the present invention;

[0045] Figure 15 Longitudinal sectional view schematic diagram of the eighth structure of the solar cell provided by the embodiment of the present invention;

[0046] Figure 16 Longitudinal sectional view schematic diagram of the ninth structure of the solar cell provided by the embodiment of the present invention;

[0047] Figure 17 Longitudinal sectional view schematic diagram of the tenth structure of the solar cell provided by the embodiment of the present invention;

[0048] Figure 18 Longitudinal sectional view schematic diagram of the eleventh structure of the solar cell provided by the embodiment of the present invention.

[0049] Reference numerals: 11 is a semiconductor substrate, 12 is a target surface, 13 is a pyramid-like structure, 14 is a first semiconductor layer, 15 is a hole structure, 16 is a first type of pyramid, 17 is a second type of pyramid, 18 is a transparent conductive layer, 19 is a first intrinsic semiconductor layer, 20 is a first doped semiconductor layer, 21 is a second semiconductor layer, 22 is an insulating layer, 23 is an interface passivation layer, and 24 is a second doped semiconductor layer. Detailed implementation manners

[0050] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present invention. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present invention.

[0051] Various schematic structural diagrams according to embodiments of the present invention are shown in the accompanying drawings. These figures are not drawn to scale, where in order to express more clearly, some details are enlarged and some details may be omitted. The shapes of various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary. In practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art can design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0052] In the context of the present invention, when a layer / component is referred to as being "on" another layer / component, the layer / component can be directly on the other layer / component, or there can be an intermediate layer / component between them. Additionally, if a layer / component is "on" another layer / component in one orientation, then when the orientation is reversed, the layer / component can be "under" the other layer / component. In order to make the technical problems, technical solutions, and beneficial effects to be solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain the present invention and are not used to limit the present invention.

[0053] Furthermore, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0054] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0055] A solar cell is a device that can convert the light energy of the sun into electrical energy. Specifically, when the solar cell is in a working state, sunlight shines on the semiconductor p-n junction of the solar cell, forming new hole-electron pairs. Under the action of the built-in electric field in the p-n junction, the photo-generated holes flow to the p region, and the photo-generated electrons flow to the n region. After the circuit is connected, an electric current can be generated. Among them, the surface where the semiconductor substrate included in the solar cell is in contact with the semiconductor layer of at least one type of conductivity type is set as a matte surface, which not only helps to make more light rays refract into the semiconductor substrate through the matte surface, improving the working efficiency of the solar cell; but also helps to increase the contact area between the semiconductor layer and the conductive material (such as a transparent conductive layer or an electrode, etc.), reducing the transmission loss.

[0056] However, the reduction in the transmission loss between the semiconductor layer included in the existing solar cell and the conductive material is relatively small, which is not conducive to further improving the working efficiency of the solar cell.

[0057] To solve the above technical problems, in a first aspect, an embodiment of the present invention provides a solar cell. Specifically, the solar cell provided by the embodiment of the present invention can be a double-sided contact cell or a back contact cell.

[0058] Among them, as Figure 1 and Figure 2 shown, the solar cell provided by the embodiment of the present invention includes: a semiconductor substrate 11 and a first semiconductor layer 14. The semiconductor substrate 11 has opposite first and second surfaces. At least one of the first surface and the second surface is a target surface 12. At least a partial region of the surface of the target surface 12 is a matte surface, and the matte surface includes a plurality of pyramid-like structures 13. The first semiconductor layer 14 is disposed on the matte surface. The first semiconductor layer 14 is processed to form a hole structure 15 therein, and the hole structure 15 is distributed in a portion of the first semiconductor layer 14 covering at least a part of the tops of the pyramid-like structures 13. The material of the first semiconductor layer 14 includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0059] Among them, as Figure 1 and Figure 2As shown, the above-mentioned first semiconductor layer 14 can undulate along with the surface morphology of the matte surface. At this time, the side of the first semiconductor layer 14 facing away from the semiconductor substrate 11 has an undulating morphology substantially the same as that of the matte surface. However, due to the influence of the deposition process, the thickness of the first semiconductor layer 14 at the top of the pseudo-pyramid 13 may be different from the thickness of the first semiconductor layer 14 at the base of the pseudo-pyramid 13.

[0060] In the case of adopting the above technical solution, amorphous silicon, nano-crystalline silicon, and micro-crystalline silicon materials contain hydrogen, which can hydrogenate the dangling bonds on the surface of the semiconductor substrate and reduce surface defects, so as to have a high passivation effect on the semiconductor substrate. Therefore, when the material of the first semiconductor layer includes at least one of amorphous silicon, nano-crystalline silicon, and micro-crystalline silicon, the part of the semiconductor substrate corresponding to the matte surface has a lower carrier recombination rate, which is beneficial to improving the working efficiency of the solar cell. In addition, compared with the case where the surface of the side of the first semiconductor layer facing away from the semiconductor substrate is a plane, as Figure 1 shown, when the first semiconductor layer 14 is disposed on the matte surface, the side of the first semiconductor layer 14 facing away from the semiconductor substrate 11 has an undulating morphology substantially the same as that of the matte surface. At this time, the first semiconductor layer 14 has a larger specific surface area, which can increase the contact area between the first semiconductor layer 14 and the conductive material (such as a transparent conductive layer or an electrode, etc.). Secondly, as Figure 1 and Figure 2 shown, a pore structure 15 is provided in the first semiconductor layer 14. The provision of the pore structure 15 makes the part of the first semiconductor layer 14 covering at least part of the top of the pseudo-pyramid 13 further have an inwardly concave undulating morphology, further increasing the specific surface area of the side of the first semiconductor layer 14 facing away from the semiconductor substrate 11, which is beneficial to further increasing the contact area between the first semiconductor layer 14 and the conductive material and further reducing the transmission loss of carriers transmitted from the first semiconductor layer 14 to the conductive material. However, the pore structure 15 will cause the passivation effect to weaken and reduce the current collection efficiency of the solar cell. Therefore, in the embodiment of the present invention, the pore structure 15 is only provided at the top of at least part of the pseudo-pyramid 13, and a similar pore structure 15 is not provided at the base of the pseudo-pyramid 13, which can improve the contact performance of the first semiconductor layer 14 while ensuring the passivation effect of the first semiconductor layer 14.

[0061] In the actual application process, the embodiment of the present invention does not specifically limit the material and conduction type of the semiconductor substrate. Exemplarily, the above-mentioned semiconductor substrate can be a silicon substrate. Alternatively, the above-mentioned semiconductor substrate can also be a substrate of any semiconductor material such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate.

[0062] Secondly, the semiconductor substrate has opposite first and second surfaces. Among them, the first surface of the semiconductor substrate can correspond to the light-facing surface of the solar cell, and in this case, the second surface of the semiconductor substrate corresponds to the backlight surface of the solar cell; or, the first surface of the semiconductor substrate can also correspond to the backlight surface of the solar cell, and in this case, the second surface of the semiconductor substrate corresponds to the light-facing surface of the solar cell. Additionally, since the first semiconductor layer with a hole structure is formed on the textured surface of the target surface, the first and second surfaces of the semiconductor substrate can be determined as the target surface according to the requirements for the formation position of the first semiconductor layer in the actual application scenario, and specific limitations are not made here.

[0063] Exemplarily, as Figure 1 , Figure 3 and Figure 4 shown, when the solar cell provided by the embodiment of the present invention is a double-sided contact cell, among the first surface and the second surface, only the first surface can be the target surface 12, or only the second surface can be the target surface 12, or both the first surface and the second surface can be the target surface 12. It should be noted that, as Figure 4 shown, when both the first surface and the second surface are the target surfaces, the conduction types of the two first semiconductor layers 14 formed on the first surface and the second surface are opposite.

[0064] Exemplarily, as Figure 5 shown, when the solar cell provided by the embodiment of the present invention is a back contact cell, among the first surface and the second surface, the one corresponding to the backlight surface of the solar cell is the target surface 12. For example: in this case, when the first surface of the semiconductor substrate 11 corresponds to the backlight surface of the solar cell, the first surface is the target surface 12. And when the second surface of the semiconductor substrate 11 corresponds to the backlight surface of the solar cell, the second surface is the target surface 12.

[0065] In addition, as Figure 5 shown, in the target surface 12, only the surface of a local area can be a textured surface, and the surfaces of the remaining areas can be a polished surface or a curved surface with unevenness, etc. Or, as Figure 3 and Figure 4 shown, it can also be that the entire area surface of the target surface 12 is a textured surface. Specifically, the distribution range of the textured surface on the target surface 12 can be determined according to the type of the solar cell and the actual application scenario, and specific limitations are not made here.

[0066] Exemplarily, as Figure 3 and Figure 4 shown, in the case where the solar cell is a double-sided contact cell, the entire area surface of the target surface 12 can be a textured surface. Or, as Figure 6 shown, it can also be that only a local area of the target surface 12 is a textured surface, and the surfaces of the remaining areas of the target surface 12 can be a polished surface or a curved surface with unevenness, etc.

[0067] Exemplarily, such as Figure 5 As shown, in the case where the solar cell is a back contact cell, only the surface of the region corresponding to the first semiconductor layer 14 in the target surface 12 can be a matte surface, and the surfaces of the remaining regions of the target surface 12 can be in topographies such as a polished surface. Or, as Figure 7 shown, it is also possible that the entire region of the target surface 12 is a matte surface.

[0068] In terms of the setting of the pseudo-pyramids, the present invention embodiment does not specifically limit the morphology, size, and distribution of the pseudo-pyramids formed on the matte surface, as long as they can be applied to the solar cells provided by the present invention embodiment.

[0069] Exemplarily, such as Figure 6 and Figure 7 shown, the above-mentioned pseudo-pyramid 13 can be a pyramid with a sharp apex angle; or, as Figure 8 shown, the above-mentioned pseudo-pyramid 13 can also be a pseudo-pyramid 13 with a smooth chamfer; or, as Figure 9 shown, the pseudo-pyramid 13 can also be a pseudo-pyramid 13 with a flattened apex angle. However, regardless of which pyramid structure it is, its shape still tends to be more pyramid-shaped rather than the tower base shape of a polished surface. Such a design can make the pseudo-pyramid have a relatively obvious apex or tip, so that when laser processing, holes can be formed at the tops of some pseudo-pyramids. In addition, there is no need to strictly control the manufacturing accuracy to obtain a single-morphology pseudo-pyramid 13, which reduces the process difficulty and is beneficial to improving the yield of solar cells.

[0070] Exemplarily, such as Figure 2 shown, the surface of the above-mentioned pseudo-pyramid 13 can also be a flat surface. In this case, compared with the surface of the pseudo-pyramid being uneven, when the surface of the pseudo-pyramid 13 is a flat surface, the surface of the pseudo-pyramid 13 is relatively flat, and the undulation degree of the pseudo-pyramid 13 on the matte surface is relatively low, which is beneficial to making the first semiconductor layer 14 deposited on the matte surface have a larger thickness and further improving the passivation effect of the first semiconductor layer 14. Or, the surface of the above-mentioned pseudo-pyramid can also have uneven microstructures, and the positions of these microstructures can correspond to the positions of the hole structures.

[0071] Exemplarily, the one-dimensional dimension of the above-mentioned pyramid-like structure (which can be the side length, diagonal length, height, etc. of the base of the pyramid-like structure) can be greater than or equal to 2 μm and less than or equal to 4 μm. For example, the one-dimensional dimension of the pyramid-like structure can be 2 μm, 2.2 μm, 2.4 μm, 2.6 μm, 2.8 μm, 3 μm, 3.2 μm, 3.6 μm, 3.8 μm, or 4 μm, etc. In this case, not only can the contact area between the first semiconductor layer and the conductive material be increased due to the presence of the pyramid-like structure, but also the velvet surface can have a certain light-trapping effect, improving the utilization rate of light by the semiconductor substrate. Additionally, it can prevent the processing temperature from being too high due to the small one-dimensional dimension of the pyramid-like structure, which may affect the passivation effect of the first semiconductor layer when forming a pore structure with a fixed range above the top of at least some of the pyramid-like structures; or prevent the extension range of the pore structure above the top of the pyramid-like structure from being too large or the number of through holes in the pore structure from being too many under the same processing conditions due to the large one-dimensional dimension of the pyramid-like structure, ensuring that the first semiconductor layer has a high passivation effect.

[0072] Regarding the distribution of different pyramid-like structures on the velvet surface, it can be understood that the distance between the top and the base of the pyramid-like structure with a greater height is larger. The base of the pyramid-like structure has a large contact area with the semiconductor substrate, and the semiconductor substrate has a good heat dissipation effect. Therefore, during the formation of the pore structure, the heat dissipated by the top of the pyramid-like structure with a greater height may be less after being heated, and it is easier to accumulate more heat to melt itself and release the hydrogen inside to obtain the pore structure. Additionally, when using a laser irradiation process to form the pore structure, since the pyramid-like structure has a reflection effect on the laser, the reflected laser is more likely to be concentrated on the top of the pyramid-like structure with a greater height, resulting in a higher heating degree of the top of the pyramid-like structure with a greater height and making it easier to form a pore structure at the part of the first semiconductor layer corresponding to the top of the pyramid-like structure with a greater height. Based on this, the distribution of different pyramid-like structures on the velvet surface can be determined according to the requirements for the distribution of the part with the pore structure in the first semiconductor layer in the actual application scenario.

[0073] Exemplarily, such as Figure 2As shown, among all the pyramid-like structures formed on the velvet surface, the pyramid-like structures located below the hole structure 15 are defined as the first type of pyramid-like structures 16, and the remaining pyramid-like structures are defined as the second type of pyramid-like structures 17. In the above case, along the direction away from the velvet surface, the height of the first type of pyramid-like structures 16 can be greater than the height of at least some of the other adjacent pyramid-like structures 13. With such a setting, while reducing the process difficulty, it can also prevent the part of the first semiconductor layer above the top of the pyramid-like structures with a smaller height from being overheated due to the formation of the hole structure 15 above the top of the pyramid-like structures with a smaller height, resulting in a poor passivation effect of itself, and further improving the working efficiency of the solar cell. Specifically, the difference between the height of the first type of pyramid-like structures 16 and the height of the second type of pyramid-like structures 17 can be randomly set, as long as it can be applied to the solar cell provided by the embodiment of the present invention. And, preferably, a single first type of pyramid-like structure 16 is not the lowest among the pyramid-like structures adjacent to it, that is, the height of a single first type of pyramid-like structure 16 is greater than the height of at least one of the adjacent pyramid-like structures. With such a setting, the surrounding pyramid-like structures can reflect light and concentrate it on the first type of pyramid-like structure 16, achieving the energy for forming the hole structure 15.

[0074] Exemplarily, as Figure 2 shown, among all the pyramid-like structures formed on the velvet surface, the number of the second type of pyramid-like structures adjacent to a single first type of pyramid-like structure 16 can be greater than the number of the other first type of pyramid-like structures 16 adjacent to this first type of pyramid-like structure 16. With such a setting, that is, the distribution density of the other pyramid-like structures around this single pyramid-like structure is relatively large. At this time, the laser reflected by the other pyramid-like structures is more likely to be concentrated on the top of the corresponding adjacent pyramid-like structure, making the heat at the top of the corresponding pyramid-like structure higher, and thus it is easier to form the hole structure 15. Based on this, when, among all the pyramid-like structures formed on the velvet surface, the number of the second type of pyramid-like structures 17 adjacent to a single first type of pyramid-like structure 16 is greater than the number of the second type of pyramid-like structures 17 adjacent to this first type of pyramid-like structure 16, it is easier to reduce the process difficulty and is beneficial to improving the yield of the solar cell. At the same time, it can also prevent the distribution density of the hole structures 15 in the first semiconductor layer 14 from being relatively large, ensuring that the first semiconductor layer 14 has a relatively high passivation effect on the velvet surface. Specifically, the distribution of the first type of pyramid-like structures 16 and the second type of pyramid-like structures 17 in different regions of the velvet surface can be randomly set, which is beneficial to making the specific surface areas of the regions on the side of the first semiconductor layer away from the semiconductor substrate be approximately the same, and is beneficial to making the contact areas between different regions of the first semiconductor layer in contact with the conductive material be relatively high.

[0075] For the above-mentioned first semiconductor layer, in terms of the film layer structure, as Figure 7As shown, the first semiconductor layer 14 can be a single-layer structure; in this case, the first semiconductor layer 14 can only include a first doped semiconductor layer. Alternatively, the first semiconductor layer can also be a stack composed of at least two film layers. Exemplarily, as Figure 10 shown, the first semiconductor layer 14 can include: a first intrinsic semiconductor layer 19 and a first doped semiconductor layer 20. The first doped semiconductor layer 20 is disposed on a side of the first intrinsic semiconductor layer 19 facing away from the semiconductor substrate 11. In this case, the first intrinsic semiconductor layer 19 and the first doped semiconductor layer 20 can form a selective contact structure, having an excellent interface passivation effect, and capable of realizing selective collection of carriers, reducing the carrier recombination rate in the region of the semiconductor substrate 11 where the first semiconductor layer 14 is formed, and further improving the photoelectric conversion efficiency of the solar cell.

[0076] In terms of materials, the material of the first semiconductor layer 14 can only include any one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, or can include any two of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon at the same time, or can include amorphous silicon, nanocrystalline silicon, and microcrystalline silicon at the same time. When the material of the first semiconductor layer 14 includes at least two types, the distribution of different materials in the first semiconductor layer 14 can be determined according to the distribution of the pore structure in the first semiconductor layer 14 and the actual manufacturing process, and no specific limitation is made here.

[0077] Exemplarily, when the material of the first semiconductor layer 14 includes amorphous silicon, the part containing nanocrystalline silicon generated by laser treatment in the first semiconductor layer 14 is distributed at the top of some class pyramids.

[0078] Exemplarily, as Figures 11 to 13As shown, the crystallization degree of the first semiconductor layer 14 covering at least a part of the top of the quasi-pyramid 13 can be greater than that of the first semiconductor layer 14 covering the base of the quasi-pyramid 13. In this case, as described above, setting the hole structure 15 can increase the contact area between the first semiconductor layer 14 and the conductive material and reduce the transmission loss of carriers between the two. Moreover, the hole structure 15 is distributed in the part of the first semiconductor layer 14 covering at least a part of the top of the quasi-pyramid 13. Based on this, when the crystallization degree of the part of the first semiconductor layer 14 covering at least a part of the top of the quasi-pyramid 13 is greater than that of the part of the first semiconductor layer 14 covering the base of the quasi-pyramid 13, it is beneficial to make the part of the first semiconductor layer 14 covering at least a part of the top of the quasi-pyramid 13 have a relatively large crystallization degree while increasing its surface area by setting the hole structure 15, thereby reducing its transmission resistance and further reducing the transmission loss of carriers through the first semiconductor layer 14 to the conductive material, and further improving the working efficiency of the solar cell. In addition, in the actual manufacturing process, laser irradiation or high-temperature annealing, etc. are required to achieve the crystallization modification of part of the first semiconductor layer 14, and the heating rate of the top of the quasi-pyramid 13 is faster than that of its own substrate, making it easier to achieve crystallization modification; based on this, when the crystallization degree of the part of the first semiconductor layer 14 covering at least a part of the top of the quasi-pyramid 13 is greater than that of the part of the first semiconductor layer 14 covering the base of the quasi-pyramid 13, there is no need to make the part of the first semiconductor layer 14 covering the base of the quasi-pyramid 13 also have a large crystallization degree, which may cause dehydrogenation due to the long heating time of each part of the first semiconductor layer 14, ensuring that the first semiconductor layer 14 has a high passivation effect. Secondly, for the part of the first semiconductor layer 14 covering at least a part of the top of the quasi-pyramid 13 and having a large crystallization degree, it can reduce the contact resistance between the first semiconductor layer 14 and the conductive material layer (such as a transparent conductive layer or a metal electrode layer, etc.), increase the current transmission efficiency, and at the same time, for the part of the first semiconductor layer 14 covering the base of the quasi-pyramid 13 with a small crystallization degree, it ensures the passivation effect, generally achieving the purpose of improving the battery efficiency. And this manufacturing method is simple and can directly increase the local crystallization degree of the first semiconductor layer 14 covering at least a part of the top of the quasi-pyramid 13 through processes such as laser or high-temperature annealing, so that it is greater than the crystallization degree of the first semiconductor layer 14 provided at the base of the quasi-pyramid 13.

[0079] The greater degree of crystallization referred to in the embodiments of the present invention may mean a greater crystallization rate, larger grain size, and / or more grain number. For example, when the first semiconductor layer is a nano-crystalline silicon layer (which generally still contains a part of amorphous silicon inside, which is inevitable and the content of the amorphous silicon part is small, as is known in the art), the first part with a greater degree of crystallization has a greater crystallization rate and grain size than the second part. When the first semiconductor layer is amorphous silicon (which may contain a small amount of nano-crystalline silicon part inside, but the content of the nano-crystalline silicon part is very small, for example, less than 5%, as is known in the art), grains with an ordered lattice will be generated inside the first part with a greater degree of crystallization, and its degree of crystallization increases, while the second part with a smaller degree of crystallization remains an amorphous silicon material and does not have grains generated after being treated with laser or the like.

[0080] In terms of the setting method of the hole structure, as Figure 11 shown, at least one hole included in the hole structure 15 may be a through hole penetrating the first semiconductor layer 14. At this time, under the same other factors, the relatively large depth of the through hole can further increase the contact area between the first semiconductor layer 14 and the conductive material, and further reduce the transmission loss. Figure 13 It shows that the first semiconductor layer 14 is an amorphous silicon material. After crystallization treatment, a grain structure, that is, an ordered lattice sequence, has been formed inside the first semiconductor layer 14 at the top of at least part of the class pyramid, which means that the degree of crystallization of the first semiconductor layer 14 at the top position is greater.

[0081] Or, as Figure 14As shown, at least one of the holes included in the hole structure 15 may also be a blind hole that does not penetrate the first semiconductor layer 14. In this case, it can be understood that when at least one of the holes included in the hole structure 15 is a through hole that penetrates the first semiconductor layer 14, the portion of the first semiconductor layer 14 corresponding to the through hole cannot passivate the surface of the semiconductor substrate corresponding to the bottom of the through hole, affecting the passivation effect of the first semiconductor layer 14 on the semiconductor substrate. Moreover, when the conductive material is in direct contact with the semiconductor substrate through the through hole, a relatively high carrier recombination will also occur at the bottom of the through hole. Based on this, compared with the above-mentioned through hole, when at least one of the holes included in the hole structure 15 is a blind hole that does not penetrate the first semiconductor layer 14, along the direction away from the textured surface, a part of the first semiconductor layer 14 corresponding to the blind hole still retains a certain thickness, and this part of the first semiconductor layer 14 can passivate the partial surface of the semiconductor substrate corresponding to the blind hole, ensuring that while reducing the transmission loss of carriers from the first semiconductor layer 14 to the conductive material, the first semiconductor layer 14 has a relatively high passivation effect on the semiconductor substrate, further improving the working efficiency of the solar cell. In addition, it can be understood that in the actual manufacturing process, when the thickness of the first semiconductor layer 14 is the same, compared with forming a through hole in the first semiconductor layer 14, the processing time for forming a blind hole with a smaller hole depth in the first semiconductor layer 14 is shorter, and it is easier to reduce the influence of the processing process on the part of the first semiconductor layer 14 where the hole structure 15 is not formed, ensuring that the first semiconductor layer 14 has a relatively high passivation effect.

[0082] It can be seen that when the holes included in the hole structure are arranged differently in the first semiconductor layer, they respectively correspond to different beneficial effects. The appropriate hole depth can be obtained by adjusting the manufacturing parameters according to the requirements of the actual application scenario, improving the applicability of the solar cell provided by the embodiments of the present invention in different application scenarios. In addition, when the first semiconductor layer includes the first intrinsic passivation layer and the first doped semiconductor layer as described above, and the hole structure is not a blind hole, the hole structure may at least not penetrate the first intrinsic semiconductor layer (it may be that the hole structure only penetrates the first doped semiconductor layer and does not penetrate the first intrinsic semiconductor layer; or it may be that the hole structure does not penetrate the first doped semiconductor layer). At this time, the portion of the first intrinsic semiconductor layer corresponding to the hole structure still has a passivation effect on the semiconductor substrate, which can further reduce the carrier recombination rate.

[0083] Secondly, each pore structure may include only one pore or multiple pores. When at least one pore structure includes multiple pores, the different pores in the same pore structure may be randomly distributed. The morphologies and sizes of the different pores included in the same pore structure may be the same or different. Since the pore structure can reduce the carrier transport loss, but to a certain extent will reduce the semiconductor passivation effect, the pore diameter of the pores in the pore structure needs to be relatively small. In the embodiments of the invention, the pore diameter of the pores is less than 100 nm, and more preferably, less than or equal to 50 nm. The embodiments of the invention do not specifically limit the size and morphology of the pores included in the pore structure, which can be determined according to the actual manufacturing process.

[0084] In addition, in the actual application process, the pore structure in the first semiconductor layer may be provided only above the tops of some of the pyramids included in the textured surface, or may be provided above the tops of all the pyramids included in the textured surface. The number of pyramids corresponding to the pore structure can be determined according to the distribution and height of different pyramids in the actual manufacturing process. Additionally, as described above, although the part of the first semiconductor layer provided with the pore structure can reduce the transport loss between the first semiconductor layer and the conductive material, the thickness of the part of the first semiconductor layer provided with the pore structure is relatively small, such that the passivation effect of this part on the semiconductor substrate is relatively weak (compared with the part not provided with the pore structure). Based on this, the setting range of the pore structure at the tops of the pyramids can be determined according to the requirements for the passivation effect and transport loss corresponding to the first semiconductor layer in the actual application scenario, and no specific limitation is made here.

[0085] Exemplarily, such as Figure 2As shown, along the inclined direction of the side surface of the pyramid-like structure, the ratio between the maximum extension length L1 of the hole structure 15 on the side surface of the pyramid-like structure below itself and the length L2 of the side surface of the pyramid-like structure can be less than or equal to 0.5. For example: along the inclined direction of the side surface of the pyramid-like structure, the ratio between the maximum extension length L1 of the hole structure 15 on the side surface of the pyramid-like structure below itself and the length L2 of the side surface of the pyramid-like structure can be 0.1, 0.2, 0.3, 0.4, or 0.5, etc. In this case, when along the inclined direction of the side surface of the pyramid-like structure, the ratio between the maximum extension length L1 of the hole structure 15 on the side surface of the pyramid-like structure below itself and the length L2 of the side surface of the pyramid-like structure is less than or equal to 0.5, it can make the part with a higher passivation effect in the first semiconductor layer have a larger coverage range for the textured surface, and can further reduce the number of surface defects of the textured surface. In addition, during the actual manufacturing process, the heating rate at the top of the pyramid-like structure is faster than that of its own substrate, and it is easier to accumulate more heat at its own top to melt itself and make the hydrogen in itself escape to obtain the hole structure. Based on this, when the ratio between the maximum extension length L1 of the hole structure 15 on the side surface of the pyramid-like structure below itself and the length L2 of the side surface of the pyramid-like structure is less than or equal to 0.5 along the inclined direction of the side surface of the pyramid-like structure, it can prevent the part of the first semiconductor layer at the top of the pyramid-like structure from overheating due to the larger extension length L1 of the hole structure 15 above the pyramid-like structure, which affects its own passivation effect, and ensure that the part of the first semiconductor layer at the top of the pyramid-like structure also has a certain passivation effect, further improving the working efficiency of the solar cell.

[0086] In terms of the conduction type, the conduction type of the first doped semiconductor layer included in the first semiconductor layer in the embodiments of the present invention is not limited. Specifically, the conduction type of the first doped semiconductor layer included in the first semiconductor layer can be opposite to or the same as the conduction type of the semiconductor substrate.

[0087] In addition, when the first surface and the second surface of the semiconductor substrate are not both target surfaces, as Figure 5 、 Figure 7 and Figure 15 shown, the above solar cell may further include a second semiconductor layer 21 with a conduction type opposite to that of the first semiconductor layer 14. The setting position of the second semiconductor layer 21 on the semiconductor substrate 11 can be set according to the type of the solar cell and actual requirements, and no specific limitation is made here.

[0088] Specifically, as Figure 15 shown, in the case where the solar cell is a double-sided contact cell, the first semiconductor layer 14 and the second semiconductor layer 21 are respectively disposed on opposite sides of the semiconductor substrate 11.

[0089] Or, as Figure 5 andFigure 7 As shown, in the case where the solar cell is a back-contact cell, the second semiconductor layer 21 and the first semiconductor layer 14 are disposed on the same side of the semiconductor substrate 11. In this case, the solar cell provided by the embodiment of the present invention is a back-contact cell, which can reduce the influence of the light-shielding electrode structure on the light utilization rate on the light-facing side, and further improve the photoelectric conversion efficiency of the solar cell. At this time, as Figure 15 shown, the first semiconductor layer 14 and the second semiconductor layer 21 may be spaced apart in a direction parallel to the target surface 12; or, as Figure 5 and Figure 7 shown, the first semiconductor layer 14 may also extend to cover a part of the second semiconductor layer 21 on the side facing away from the semiconductor substrate 11. At this time, when forming the first semiconductor layer 14, the etching amount of the first semiconductor material used for manufacturing the first semiconductor layer 14 and provided as a whole layer can be beneficial to improving the manufacturing efficiency of the solar cell.

[0090] Among them, as Figure 16 and Figure 17 shown, when the first semiconductor layer 14 extends to cover a part of the second semiconductor layer 21 on the side facing away from the semiconductor substrate 11, the part of the first semiconductor layer 14 extending onto the second semiconductor layer 21 can be isolated by an insulating layer 22 such as silicon oxide or silicon nitride, or the first doped semiconductor layer 20 included in the first semiconductor layer 14 can also be isolated by the first intrinsic semiconductor layer 19. Specifically, in the case where the first doped semiconductor layer 20 included in the first semiconductor layer 14 is isolated by the first intrinsic semiconductor layer 19, it can be understood that the thickness of the first intrinsic semiconductor layer 19 not only affects the transmission loss of carriers through the first intrinsic semiconductor layer 19 to the first doped semiconductor layer 20, but also affects the passivation effect of the first intrinsic semiconductor layer 19, and also affects its own leakage isolation effect on the first doped semiconductor layer 20 and the second semiconductor layer 21. Based on this, on the premise that the pore structure 15 is provided in the first semiconductor layer 14 to increase the contact area between the first semiconductor layer 14 and the conductive material and reduce the transmission loss therebetween, while not reducing the working efficiency of the solar cell provided by the embodiment of the present invention compared with the working efficiency of the existing solar cell, the setting of the pore structure 15 can reserve an adjustable space for thickening the thickness of the first intrinsic semiconductor layer 19. It can not only further suppress the leakage between the first doped semiconductor layer 20 and the second semiconductor layer 21 through the first intrinsic semiconductor layer 19 with a larger thickness, but also improve the passivation effect of the first intrinsic semiconductor layer 19 on the semiconductor substrate 11 and reduce the carrier recombination rate.

[0091] Specifically, as Figure 7As shown, the second semiconductor layer 21 described above may be a single-layer structure. In this case, the second semiconductor layer 21 may only include a second doped semiconductor layer. Alternatively, the second semiconductor layer 21 may also be a stack composed of at least two film layers. Exemplarily, as Figure 17 shown, the second semiconductor layer 21 described above may include: an interface passivation layer 23 and a second doped semiconductor layer 24. The second doped semiconductor layer 24 is disposed on a side of the interface passivation layer 23 away from the semiconductor substrate 11. In this case, the interface passivation layer 23 and the second doped semiconductor layer 24 may form a selective contact structure, having an excellent interface passivation effect, and capable of achieving selective carrier collection, reducing the carrier recombination rate in the region of the semiconductor substrate 11 where the second semiconductor layer 21 is formed, and further improving the photoelectric conversion efficiency of the solar cell.

[0092] In terms of materials, the material of the second semiconductor layer may be the same as or different from the material of the first semiconductor layer. When the material of the second semiconductor layer is different from that of the first semiconductor layer, the material of the second semiconductor layer may include any semiconductor material different from the first semiconductor layer. Exemplarily, the material of the second semiconductor layer may include at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon, and microcrystalline silicon. In this case, there are multiple possible examples of the material of the second semiconductor layer, which is beneficial to improving the applicability of the solar cell provided by the present invention in different application scenarios.

[0093] Preferably, when the solar cell provided by the embodiment of the present invention is a back-contact cell, the first semiconductor layer includes a first intrinsic semiconductor layer and a first doped semiconductor layer, and the second semiconductor layer includes an interface passivation layer and a second doped semiconductor layer. Among them, the interface passivation layer includes a tunneling passivation layer, and the second doped semiconductor layer includes a doped polycrystalline silicon layer.

[0094] Regarding the surface morphology of the semiconductor substrate where the second semiconductor layer is formed, the embodiment of the present invention does not specifically limit the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer. Exemplarily, the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer may be a polished surface, a textured surface, or an uneven curved surface, etc. Among them, when the surface morphology corresponding to the semiconductor substrate and the second semiconductor layer is a textured surface, and the material of the second semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon, a pore structure may or may not be provided in the second semiconductor layer. Specifically, when a pore structure is provided in the second semiconductor layer, the distribution of the pore structure in the second semiconductor layer, and the morphology of the pseudo-pyramids in the textured surface corresponding to the semiconductor substrate and the second semiconductor layer, etc., may refer to the distribution of the pore structure in the first semiconductor layer described above, and the morphology of the pseudo-pyramids in the textured surface corresponding to the semiconductor substrate and the first semiconductor layer, etc., and will not be elaborated here.

[0095] It should be noted that when the conductivity type of the first doped semiconductor layer included in the first semiconductor layer is the same as the conductivity type of the semiconductor substrate, the solar cell includes the second semiconductor layer. When the conductivity type of the first doped semiconductor layer included in the first semiconductor layer is opposite to the conductivity type of the semiconductor substrate, the solar cell may include the second semiconductor layer or may not include the second semiconductor layer.

[0096] As for the thickness of the first semiconductor layer, the embodiment of the present invention does not specifically limit the thickness of the first semiconductor layer, and can be determined based on the type of solar cell in the actual application scenario, and requirements for the passivation effect and transmission loss of the first semiconductor layer.

[0097] Exemplarily, the thickness of the portion of the first semiconductor layer without a pore structure may be greater than or equal to 10 nm, and / or the thickness of the portion of the first semiconductor layer without a pore structure may be less than or equal to 45 nm. For example, the thickness of the portion of the first semiconductor layer without a pore structure may be 10 nm, 12 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm or 45 nm, etc. In this case, the lower limit and / or upper limit of the thickness of the first semiconductor layer, whose material includes at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon, is greater, which is conducive to reducing the thermal effect of heat on the semiconductor substrate through the thicker first semiconductor layer, preventing thermal damage to the semiconductor substrate during the formation of the pore structure in the first semiconductor layer, and ensuring that the solar cell has a higher yield. In addition, the thicker first semiconductor layer has a higher passivation effect, which can further reduce the carrier recombination rate at the velvet surface and further improve the working efficiency of the solar cell. In addition, when the first semiconductor layer includes a first intrinsic semiconductor layer and a first doped semiconductor layer, and the first semiconductor layer extends to cover a portion of the second semiconductor layer that is away from the semiconductor substrate, it is also beneficial to increase the thickness of the first intrinsic semiconductor layer, improve the anti-leakage effect between the first doped semiconductor layer and the second semiconductor layer, and further reduce the carrier recombination rate.

[0098] As a possible implementation, Figure 18 As shown, the solar cell may further include a transparent conductive layer 18, which covers at least one side of the first semiconductor layer 14 away from the semiconductor substrate 11 and fills into the hole structure 15. In this case, the transparent conductive layer 18 has a high conductivity, and can timely guide the carriers collected by the first semiconductor layer 14, which can reduce the carrier recombination rate. In addition, the transparent conductive layer 18 not only covers the side of the first semiconductor layer 14 away from the semiconductor substrate 11, but also fills into the hole structure 15. At this time, the transparent conductive layer 18 has a large contact area with the first semiconductor layer 14, which can reduce transmission loss and improve the working efficiency of the solar cell.

[0099] In the actual application process, the embodiments of the present invention do not specifically limit the material and thickness of the transparent conductive layer, as long as it can be applied to the solar cell provided by the embodiments of the present invention. It should be noted that when the solar cell provided by the embodiments of the present invention is a back-contact cell, the transparent conductive layer may only cover the side of the first semiconductor layer facing away from the semiconductor substrate. Or, as Figure 18 shown, the transparent conductive layer 18 not only covers the side of the first semiconductor layer 14 facing away from the semiconductor substrate 11, but also covers the side of the second semiconductor layer 21 facing away from the semiconductor substrate 11, and an insulating groove is provided in the transparent conductive layer 18 to separate the portions of the transparent conductive layer 18 covering the first semiconductor layer 14 and the second semiconductor layer 21 respectively, preventing short circuit.

[0100] In a second aspect, the embodiments of the present invention provide a method for manufacturing a solar cell. The method for manufacturing the solar cell includes the steps of: First, providing a semiconductor substrate. The semiconductor substrate has opposite first and second surfaces. At least one of the first surface and the second surface is a target surface. At least a partial area of the surface of the target surface is a matte surface. The matte surface includes a plurality of pyramid-like structures. Next, forming a first semiconductor layer on the matte surface. Next, processing the first semiconductor layer to form a pore structure in the first semiconductor layer, and the pore structure is distributed in the portion of the first semiconductor layer covering at least a part of the tops of the pyramid-like structures. The material of the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon, and microcrystalline silicon.

[0101] Specifically, information such as the structure and material of the solar cell manufactured by using the manufacturing method provided by the embodiments of the present invention can refer to the description of the structure and material of the solar cell provided in the first aspect above, and will not be elaborated here.

[0102] Among them, the specific process of forming the first semiconductor layer can be determined according to the type of the manufactured solar cell.

[0103] Exemplarily, in the case where the manufactured solar cell is a double-sided contact cell, after forming a textured surface on at least a partial area of the target surface of the semiconductor substrate, a first semiconductor material layer that is integrally disposed on the target surface can be formed by processes such as chemical vapor deposition. When only a partial area of the target surface is textured, after forming the first semiconductor material layer, processes such as laser or wet etching can be used to selectively etch the first semiconductor material layer to remove the portion of the first semiconductor material layer that does not correspond to the textured surface. If the entire area of the target surface is textured, the integrally disposed first semiconductor material layer described above is the first semiconductor layer. Then, after obtaining the first semiconductor layer, a laser irradiation process can be used to modify at least a part of the first semiconductor layer to form a pore structure disposed within the first semiconductor layer. Specifically, when the first semiconductor layer absorbs light, it generates heat, causing its own temperature to rise. When the temperature rises to a certain level, the first semiconductor layer will assume a molten state, and hydrogen in the first semiconductor layer will escape, thereby forming a pore structure at the position where the hydrogen escapes. Moreover, due to the reflection of the laser on the surface of the quasi-pyramid and the difference in the heat dissipation rate at different positions of the quasi-pyramid (the heat dissipation rate at the top of the quasi-pyramid is slower, and the heat dissipation rate at the base of the quasi-pyramid is faster), the temperature of the part of the first semiconductor layer covering at least a part of the top of the quasi-pyramid is higher than that of the parts at other positions. Therefore, the pore structure is distributed within the part of the first semiconductor layer covering at least a part of the top of the quasi-pyramid.

[0104] Specifically, parameters such as the processing wavelength, pulse width, laser energy density, and processing time of the laser irradiation process can be determined according to requirements such as the formation range of the pore structure in the actual application scenario, and no specific limitations are made here. It can be understood that when the processing wavelength of the laser irradiation process is smaller, the pulse width is larger, the laser energy density is higher, and the processing time is longer, when using the laser irradiation process to process the first semiconductor layer, the degree of temperature rise of the first semiconductor layer is greater, which is more conducive to forming more pore structures with greater pore depth.

[0105] Exemplarily, the processing wavelength of the laser irradiation process can be greater than or equal to 325 nm and less than or equal to 532 nm. For example: the processing wavelength can be 325 nm, 330 nm, 350 nm, 80 nm, 400 nm, 430 nm, 450 nm, 480 nm, 500 nm, or 532 nm, etc.

[0106] Exemplarily, the pulse width of the laser irradiation process can be on the order of picoseconds to nanoseconds. For example: the pulse width can be 10 ps, 50 ps, 100 ps, 300 ps, 500 ps, 800 ps, 1 ns, or 5 ns, etc.

[0107] Exemplarily, the laser energy density of the laser irradiation process can be greater than or equal to 200 mJ / cm 2and less than or equal to 6000 mJ / cm 2 . For example, the laser energy density can be 200 mJ / cm 2 , 240 mJ / cm 2 , 280 mJ / cm 2 , 300 mJ / cm 2 , 400 mJ / cm 2 , 500 mJ / cm 2 , 1000 mJ / cm 2 , 2000 mJ / cm 2 , 3000 mJ / cm 2 , 4000 mJ / cm 2 , 5000 mJ / cm 2 or 6000 mJ / cm 2 etc.

[0108] In addition, in the case where the manufactured solar cell is a double-sided contact cell, if the solar cell further includes a second semiconductor layer, the second semiconductor layer can be formed on the side of the semiconductor substrate facing away from the first semiconductor layer by at least using a doping process before or after the formation of the first semiconductor layer. The second semiconductor layer can be locally provided, for example, it can be a local polysilicon layer of poly finger (polycrystalline silicon finger).

[0109] Exemplarily, in the case where the manufactured solar cell is a back contact cell, if the first semiconductor layer and the second semiconductor layer are spaced apart in a direction parallel to the first surface, the first semiconductor layer and the second semiconductor layer can be formed respectively by the method of forming the first semiconductor layer in a local area of the target surface described above. Then, a laser irradiation process can be used to modify at least part of the first semiconductor layer to form a pore structure provided in the first semiconductor layer. If the first semiconductor layer extends to cover part of the second semiconductor layer, a deposition process and a doping process can be used to form a second semiconductor material layer provided as a whole layer on the target surface, and then a process such as laser or wet etching can be used to selectively remove part of the second semiconductor layer material layer to expose the area of the semiconductor substrate for manufacturing the first semiconductor layer. Then, under the masking action of the corresponding mask layer, at least the area of the semiconductor substrate for manufacturing the first semiconductor layer is subjected to texturing treatment so that the surface of part of the area of the target surface forms a textured surface. Then, the first semiconductor layer can be formed in the manner described above, and a pore structure can be formed in the first semiconductor layer. In this case, the parameter settings of the laser irradiation process can refer to the above, and will not be elaborated here.

[0110] For the beneficial effects of the second aspect and its various implementation manners in the embodiments of the present invention, reference can be made to the analysis of the beneficial effects in the first aspect and its various implementation manners, and will not be elaborated here.

[0111] In the above description, technical details such as the composition and etching of each layer are not elaborated in detail. However, those skilled in the art should understand that various technical means can be used to form layers, regions, etc. of the desired shape. Additionally, in order to form the same structure, those skilled in the art can also design methods that are not exactly the same as the methods described above. Moreover, although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination.

[0112] The embodiments of the present invention have been described above. However, these embodiments are merely for clearer illustration and not for limiting the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present invention.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; At least a part of the target surface is a velvet surface, and the velvet surface includes a plurality of pyramid-like surfaces; And a first semiconductor layer is arranged on the velvet surface; a hole structure is arranged in the first semiconductor layer, and the hole structure is distributed in the part of the first semiconductor layer covering at least part of the top of the pyramid-like layer; the material of the first semiconductor layer includes amorphous silicon, nanocrystalline silicon and / or microcrystalline silicon.

2. The solar cell according to claim 1, characterized in that: At least one hole included in the hole structure is a blind hole that does not penetrate the first semiconductor layer, and / or at least one hole included in the hole structure has a pore diameter less than 100 nm.

3. The solar cell according to claim 1, characterized in that The crystallization degree of a portion of the first semiconductor layer covering at least a portion of the top of the pyramid-like layer is greater than the crystallization degree of a portion of the first semiconductor layer covering the base of the pyramid-like layer.

4. The solar cell according to claim 1, characterized in that Among all the quasi-pyramids formed on the suede surface, the quasi-pyramids located below the hole structure are first-type pyramids, and the remaining quasi-pyramids are second-type pyramids; In which, along the direction away from the velvet surface, the height of the first type of pyramid is greater than the height of at least part of the other types of pyramids adjacent to it; and / or the number of the second type of pyramids adjacent to a single first type of pyramid is greater than the number of other first type pyramids adjacent to the first type of pyramid.

5. The solar cell according to claim 1, characterized in that: Along the inclination direction of the side surface of the pyramid-like structure, the ratio between the maximum extension length of the hole structure on the side surface of the pyramid-like structure located below the hole structure and the length of the side surface of the pyramid-like structure is less than or equal to 0.

5.

6. The solar cell according to claim 1, characterized in that The thickness of the portion of the first semiconductor layer where the hole structure is not provided is greater than or equal to 10 nm, and / or the thickness of the portion of the first semiconductor layer where the hole structure is not provided is less than or equal to 45 nm.

7. The solar cell according to claim 1, characterized in that The solar cell further includes a transparent conductive layer, which covers at least a side of the first semiconductor layer away from the semiconductor substrate and fills the hole structure.

8. The solar cell according to claim 1, characterized in that The quasi-pyramid is a pyramid with a sharp vertex angle; Or, the quasi-pyramid is a quasi-pyramid with rounded chamfers; Alternatively, the quasi-pyramid is a quasi-pyramid with flattened top corners.

9. The solar cell according to claim 1, characterized in that: The surface of the pyramid-like structure is a plane.

10. The solar cell according to any one of claims 1 to 9, characterized in that: The first semiconductor layer includes: a first intrinsic semiconductor layer and a first doped semiconductor layer; the first doped semiconductor layer is arranged on a side of the first intrinsic semiconductor layer away from the semiconductor substrate; and the hole structure at least does not penetrate the first intrinsic semiconductor layer.

11. The solar cell according to claim 10, characterized in that The solar cell further comprises a second semiconductor layer of opposite conductivity type to the first semiconductor layer; The second semiconductor layer and the first semiconductor layer are arranged on the same surface of the semiconductor substrate; the first semiconductor layer extends to cover a portion of the second semiconductor layer facing away from the semiconductor substrate; and / or the second semiconductor layer is arranged on the second surface of the semiconductor substrate, and the material of the second semiconductor layer includes at least one of polycrystalline silicon, amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

12. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate; The semiconductor substrate has a first surface and a second surface opposite to each other; at least one of the first surface and the second surface is a target surface; At least a portion of the target surface is a velvet surface; the velvet surface includes a plurality of pyramid-like surfaces; forming a first semiconductor layer on the velvet surface; The first semiconductor layer is processed to form a hole structure in the first semiconductor layer, wherein the hole structure is distributed in a portion of the first semiconductor layer covering at least a portion of the top of the pyramid-like layer; the material of the first semiconductor layer includes at least one of amorphous silicon, nanocrystalline silicon and microcrystalline silicon.

13. The method for manufacturing a solar cell according to claim 12, characterized in that: A laser irradiation process is used to modify at least a portion of the first semiconductor layer to form the hole structure disposed in the first semiconductor layer.

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