Solar cells and photovoltaic modules

Abstract

The present application provides a solar cell and photovoltaic module, wherein the solar cell includes a crystalline silicon substrate, the back surface of the crystalline silicon substrate including alternating P-type doped regions and N-type doped regions, the P-type doped regions corresponding to the P-type doped layers, and the N-type doped regions corresponding to the N-type doped layers. An isolation trench is provided between adjacent P-type doped regions and N-type doped regions, and the sidewalls of the isolation trench adjacent to the P-type doped regions have a first boss structure, and at least one second boss structure is provided on a side of the first boss structure facing away from the sidewall. The first and second boss structures of the present application can reduce the hot spot temperature of the photovoltaic module.

Description

Technical Field

[0001] The present invention relates to the field of solar cells, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] Solar cells are devices that convert solar energy into electrical energy. They are clean and pollution-free and have been widely used in the power generation industry.

[0003] BC solar cells, for example, have no metal grid lines on the front, with the metal grid lines in the P / N region arranged in an interdigitated pattern on the back. While BC solar cells offer high photoelectric conversion efficiency, they are limited by the risk of hot spots after the cells are manufactured into modules, which can easily cause module power loss. Summary of the Invention

[0004] In order to solve the above technical problems, the present application discloses a solar cell and a photovoltaic module to reduce the risk of hot spots of BC solar cells at the end of the photovoltaic module.

[0005] In the first aspect, the present application provides a solar cell, comprising: a crystalline silicon substrate, the back side of which comprises alternatingly arranged P-type doped regions and N-type doped regions, the P-type doped regions corresponding to P-type doped layers, the N-type doped regions corresponding to N-type doped layers, and an isolation trench provided between adjacent P-type doped regions and N-type doped regions; wherein: the sidewall of the isolation trench adjacent to the P-type doped region has a first boss structure, and at least one second boss structure is provided on a side of the first boss structure facing away from the sidewall.

[0006] In some embodiments of the present application, a plurality of the second boss structures are distributed along an extension direction of the isolation trench.

[0007] In some embodiments of the present application, the number of the first boss structure is at least one, and within the target length L3 along the extension direction of the isolation channel, there are N second boss structures, and the sum of the lengths of the N second boss structures is L2, 0.01≤L2 / L3≤0.8, and N≥1.

[0008] In some embodiments of the present application, along the extension direction of the sidewall, the width of the first boss structure is W1, the width of the second boss structure is W2, and 1.05≤W1 / W2≤2.

[0009] In some embodiments of the present application, the widest width of the second boss structure is Wmax, and 0.5 μm≤Wmax≤5 μm.

[0010] In some embodiments of the present application, the surface of the isolation channel has a first velvet structure, the height difference between the second boss structure and the P-type doped layer is H1, the height difference between the second boss structure and the first velvet structure is H2, 0.3μm≤H1≤3μm, and / or, 2μm≤H2≤8μm.

[0011] In some embodiments of the present application, 0.2≤H1 / H2≤1.

[0012] In some embodiments of the present application, the sidewall of the isolation trench adjacent to the P-type doping region further has a reflective arm.

[0013] In a second aspect, the present application provides a photovoltaic module, which includes the solar cell as described in the first aspect.

[0014] Compared with the prior art, this application has at least the following beneficial effects:

[0015] The present application provides a solar cell and a photovoltaic module, wherein the solar cell includes a crystalline silicon substrate, the back side of the crystalline silicon substrate includes alternatingly arranged P-type doped regions and N-type doped regions, the P-type doped regions correspond to the P-type doped layers, and the N-type doped regions correspond to the N-type doped layers, an isolation trench is provided between adjacent P-type doped regions and N-type doped regions, the sidewalls of the isolation trench adjacent to the P-type doped regions have a first boss structure, and at least one second boss structure is provided on a side of the first boss structure facing away from the sidewall, so that the solar cell forms a dispersed leakage current region between the second boss structure including the N-type doped conductivity type and the P-type doped layer, thereby reducing the hot spot temperature of the photovoltaic module. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 This is a schematic structural diagram of a crystalline silicon substrate according to an embodiment of the present application;

[0018] Figure 2 A schematic structural diagram of a solar cell according to an embodiment of the present application;

[0019] Figure 3 A scanning electron microscope (SEM) image of the back side of a solar cell according to one embodiment of the present application;

[0020] Figure 4 This is a schematic structural diagram of a semi-finished solar cell product according to another embodiment of the present application;

[0021] Figure 5 This is a SEM image of the back side of a solar cell according to another embodiment of the present application;

[0022] Figure 6 is a schematic diagram when observing along the orthographic projection direction of the second boss structure relative to the side wall;

[0023] Figure 7 This is a schematic structural diagram of a semi-finished solar cell product according to another embodiment of the present application;

[0024] Figure 8 This is a schematic structural diagram of a solar cell according to another embodiment of the present application;

[0025] Figure 9 This is a schematic structural diagram of a semi-finished solar cell after the first coating process of this application;

[0026] Figure 10 This is a schematic structural diagram of a semi-finished solar cell after the first graphic processing of this application;

[0027] Figure 11 This is a schematic structural diagram of a semi-finished solar cell after the second coating process of this application;

[0028] Figure 12 This is a schematic structural diagram of a semi-finished solar cell product after the second patterning process of this application;

[0029] Figure 13 This is a schematic diagram of the flow direction of the texturing solution in this application;

[0030] Figure 14 This is a schematic structural diagram of the semi-finished solar cell after texturing in this application.

[0031] Explanation of the accompanying drawings: crystalline silicon substrate-1, P-type doped layer-2, N-type doped layer-3, isolation channel-4, first boss structure-5, second boss structure-6, first tunneling oxide layer-7, second tunneling oxide layer-8, sidewall-9, first velvet structure-10, first passivation layer-11, first anti-reflection layer-12, second passivation layer-13, second anti-reflection layer-14, electrode grid line-15, reflective support arm-16, first mask oxide layer-21, second mask oxide layer-22, second velvet structure-23, first patterned area-31, second patterned area-32, etching blind area-312. DETAILED DESCRIPTION

[0032] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0033] In this application, terms such as "upper," "lower," "left," "right," "front," "back," "top," "bottom," "inner," "outer," "vertical," "horizontal," "transverse," and "longitudinal" indicate positions or locations based on the positions or locations shown in the accompanying drawings. These terms are primarily intended to better describe this application and its embodiments and are not intended to limit the devices, elements, or components indicated to having a specific orientation, or to being constructed or operated in a specific orientation.

[0034] Furthermore, some of the above terms may be used to express other meanings besides indicating a position or location. For example, the term "on" may also be used to indicate a dependency or connection in certain circumstances. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0035] Furthermore, the terms "installed," "disposed," "provided with," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed connections, removable connections, or integral structures; mechanical connections or electrical connections; direct connections, indirect connections through an intermediary, or internal communication between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in this application based on the specific circumstances.

[0036] Furthermore, the terms "first," "second," and the like are primarily used to distinguish different devices, elements, or components (which may or may not be the same in type and configuration) and are not intended to indicate or imply the relative importance or quantity of the devices, elements, or components indicated. Unless otherwise specified, "plurality" means two or more.

[0037] The technical solution of the present application will be further described below with reference to the embodiments and drawings.

[0038] In this application, if Figure 1 As shown, the extension direction along the main gate electrode is defined as the x direction, the extension direction along the auxiliary gate electrode is defined as the y direction, that is, the extension direction along the isolation channel is defined as the y direction, and the height direction of the crystalline silicon substrate 1 is defined as the z direction.

[0039] The present application provides a solar cell. Figure 2This is a schematic diagram of the structure of a solar cell according to an embodiment of the present application. Figure 2 As shown, the solar cell includes a crystalline silicon substrate 1. The backside of the crystalline silicon substrate 1 includes alternating P-type and N-type doped regions. The P-type doped regions correspond to a P-type doped layer 2, and the N-type doped regions correspond to an N-type doped layer 3. An isolation trench 4 is provided between adjacent P-type and N-type doped regions. The sidewall 9 of the isolation trench 4 adjacent to the P-type doped region includes a first platform structure 5. The side of the first platform structure 5 facing away from the sidewall 9 is provided with at least one second platform structure 6. The first and second platforms are conductive. Furthermore, a first tunneling oxide layer 7 is provided on the backside of the crystalline silicon substrate 1 in the P-type doped region, with the P-type doped layer 2 disposed on the surface of the first tunneling oxide layer 7. A second tunneling oxide layer 8 is provided on the backside of the crystalline silicon substrate 1 in the N-type doped region, with the N-type doped layer 3 disposed on the surface of the second tunneling oxide layer 8. The second platform structure 6 comprises a doped layer of N-type conductivity.

[0040] In the present application, the first boss structure 5 and at least one second boss structure 6 can disperse the leakage current in the hot spot effect. This is because: when the second boss structure 6 and the P-type doped layer 2 form a connection path in the local area of ​​the side wall 9, and when the photovoltaic component has conditions that can trigger the hot spot effect, the N-type doped layer in the second boss structure 6 just forms a leakage conduction structure with the P-type doped layer 2, thereby achieving the effect of reducing the hot spot temperature of the photovoltaic component.

[0041] The material of the first tunnel oxide layer and / or the second tunnel oxide layer of the present application may include a variety of dielectric materials, for example: at least one of silicon oxide, magnesium fluoride, amorphous silicon, polycrystalline silicon, silicon carbide, silicon nitride, silicon oxynitride, aluminum oxide or titanium oxide. Specifically, the first tunnel oxide layer and / or the second tunnel oxide layer may be composed of a silicon oxide layer containing silicon oxide. This is because the silicon oxide layer has excellent passivation properties, which can minimize the recombination loss of minority carriers on the surface of the semiconductor substrate and is a thin film with excellent durability for subsequent high-temperature processes. In order to better provide interface passivation for the substrate, the thickness of the first tunnel oxide layer and / or the second tunnel oxide layer may be 0.1nm~5nm. For example, the thickness of the first tunnel oxide layer and / or the second tunnel oxide layer may be 0.1nm, 0.5nm, 1nm, 1.5nm, 2nm, 3nm, 4nm, 5nm, etc. However, the present application is not limited thereto, and the thickness of the first tunnel oxide layer and / or the second tunnel oxide layer may have various values. The first tunneling oxide layer and / or the second tunneling oxide layer serve as a barrier to electrons and holes and can be combined with the polysilicon layer to prevent minority carriers from passing through. The first tunneling oxide layer and / or the second tunneling oxide layer can also function as pinhole channels, allowing carriers within the solar cell to move freely. The heavily doped polysilicon generates selective passage for majority carriers, which helps reduce minority carrier recombination losses. In addition, the first tunneling oxide layer and / or the second tunneling oxide layer can serve as a diffusion barrier to prevent dopants from the doped polysilicon layer from diffusing into the semiconductor substrate.

[0042] The thickness of the crystalline silicon substrate of the present application is 100 μm to 200 μm, which is not specifically limited in the present application.

[0043] In some embodiments of the present application, reference is made to Figure 3 As shown in the dotted box areas, multiple second boss structures 6 are distributed along the extension direction of the auxiliary gate electrode, which is the y-direction. In the present application, multiple second boss structures 6 can be arranged at intervals along the y-direction on the side of the first boss structure 5 facing away from the sidewall 9. In this way, when the second boss structure 6 and the P-type doped layer 2 form a connection path in a local area of ​​the sidewall 9, and when the photovoltaic module experiences a hot spot effect, the N-type doped layer in the second boss structure 6 just forms a leakage conduction structure with the P-type doped layer 2. In addition, along the y-direction, the first boss structure 5 can be continuously distributed on the surface of the sidewall 9.

[0044] In some embodiments of the present application, the number of the first boss structure is at least one. Figure 4, a plurality of first boss structures 5 and a plurality of second boss structures 6 are provided on the sidewall 9. Within the target length L3 along the extension direction of the auxiliary gate electrode, that is, within the target length L3 along the y direction, there are N second boss structures 6, the length of the first second boss structure is L21, the length of the second second boss structure is L22, and so on, the length of the N-1th second boss structure is L2 （N-1） , the length of the Nth second boss structure is L2 N , then the sum of the lengths of these N second boss structures is L2, where 0.01≤L2 / L3≤0.8, and N≥1. By regulating L2 / L3 within the above range, it is beneficial to achieve a uniform leakage distribution. When there is an obstruction that causes a hot spot effect on the photovoltaic module, the heat generated by the hot spot can be evenly dispersed, thereby avoiding the phenomenon of local heat concentration, reducing the thermal stress caused by heat concentration and the risk of related component reliability; in addition, the hot spot temperature of the photovoltaic module can also be reduced. The value of L3 in this application can be, for example, 1μm, 2μm, 5μm or 20μm. In this application, the target length L3 refers to the length of the crystalline silicon substrate of the solar cell along the y direction within the field of view in the SEM image of the solar cell.

[0045] In some embodiments of the present application, reference is made to Figure 5 , along the extension direction of the side wall 9, the width of the first boss structure is W1, the width of the second boss structure is W2, and 1.05≤W1 / W2≤2.0. For example, W1 / W2 is 1.05, 1.2, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9 or 2.0. By controlling W1 / W2 within the above range, a leakage conduction structure is formed between the second boss structure 6 containing N-type doping atoms and the P-type doping layer 2 in a direction away from the crystalline silicon substrate 1, thereby forming a leakage current region with a suitable area range. The conversion efficiency of the solar cell will not be reduced due to the excessive size of the leakage current dispersion region, nor will the technical effect of effectively reducing the hot spot temperature of the photovoltaic module be achieved due to the excessive size of the leakage current dispersion region.

[0046] In some embodiments of the present application, reference is made to Figure 6 , as viewed along the orthographic projection direction of the second boss structure relative to the sidewall 9, the widest width of the second boss structure 6 is Wmax, where 0.5μm ≤ Wmax ≤ 5μm. For example, Wmax is 0.5μm, 1μm, 1.5μm, 2μm, 2.5μm, 3μm, 3.5μm, 4μm, or 5μm. In this application, the widest width of the second boss structure refers to the dimension at the widest point of the second boss structure as viewed along the projection direction of the second boss structure relative to the vertical sidewall.

[0047] In some embodiments of the present application, reference is made to Figure 7, the surface of the isolation trench 4 has a first velvet structure 10, the height difference between the second boss structure 6 and the P-type doped layer is H1, the height difference between the second boss structure 6 and the first velvet structure 10 is H2, 0.3μm≤H1≤3μm, 2μm≤H2≤8μm. For example, H1 is 0.3μm, 0.5μm, 1μm, 1.5μm, 2μm or 3μm; H2 is 2μm, 4μm, 5μm, 6μm or 8μm. In this application, the height difference between the second boss structure and the P-type doped layer refers to: along the z direction, selecting any cross-sectional view of the isolation trench, the distance between the center of the second boss structure and the bottom of the P-type doped layer; the height difference between the second boss structure and the first velvet structure refers to: along the z direction, the distance between the center of the second boss structure and the bottom of the first velvet structure. It should be noted that the center of the second boss refers to: reference Figure 7 , along the center point of the second boss structure in the extension direction of the sidewall 9. When H1 and H2 are too small, a larger conductive area is formed between the second boss structure and the P-type doped region, and the solar cell is prone to leakage. When H1 and H2 are too large, it indicates that the alkali solution treatment time during the first patterning process is too long, resulting in the first mask oxide layer being completely reacted and unable to provide mask protection for the film structure covered and protected by the first mask oxide layer. Alternatively, when the alkali solution treatment time during the first patterning process is too long, the depth of the crystalline silicon substrate being corroded is too deep, which is not conducive to improving the overall mechanical strength of the solar cell and increases the defective rate in subsequent process treatments, especially the fragmentation rate of the solar cell. By controlling H1 and H2 within the above range, a leakage current region is formed between the second boss structure 6 comprising an N-type doped conductive type and the P-type doped layer 2 in the solar cell, thereby reducing the hot spot temperature of the photovoltaic module; secondly, sufficient mask protection can be retained for the film layer structure covered and protected by the first mask oxide layer; and, the duration of the alkaline solution treatment during the first patterning process is controlled to avoid excessive corrosion depth of the crystalline silicon substrate, thereby reducing the process defect rate of the solar cell.

[0048] In some embodiments of the present application, 0.2 ≤ H1 / H2 ≤ 1. For example, H1 / H2 is 0.2, 0.3, 0.4, 0.5, 0.6, 0.8, or 1. By controlling H1 / H2 within the above range, it is beneficial to form an isolation channel with good insulation isolation effect and improve the light utilization efficiency on the back side of the solar cell.

[0049] In some embodiments of the present application, reference is made to Figure 8 The sidewall 9 of the isolation trench 4 adjacent to the P-type doped region further comprises a reflective arm 16. The reflective arm is used to reflect the light emitted from the isolation trench back into the crystalline silicon substrate, thereby improving the light utilization rate of the solar cell.

[0050] In some embodiments of the present application, reference is made to Figure 8 The back side of the crystalline silicon substrate 1 is also provided with a first passivation layer 11 and a first anti-reflection layer 12 in sequence. The front side of the crystalline silicon substrate 1 has a second textured structure 23. The front side of the crystalline silicon substrate 1 is also provided with a second passivation layer 13 and a second anti-reflection layer 14 in sequence. In addition, electrode grid lines 15 are also provided in the P-type doped region and the N-type doped region, respectively.

[0051] In this application, the preparation process of the solar cell can be:

[0052] First coating treatment: Provide a polished crystalline silicon substrate, and use low-pressure chemical vapor deposition (LPCVD) to sequentially deposit a first tunneling oxide layer and a first intrinsic amorphous silicon layer on the back of the crystalline silicon substrate, wherein the thickness of the first tunneling oxide layer is 0.5nm~3nm, and the thickness of the first intrinsic amorphous silicon layer is 100nm~300nm; then dope the first intrinsic amorphous silicon layer by thermal diffusion, for example, using BCl3 as a doping source to obtain a P-type doping layer with a thickness of 200nm~400nm, and form a first mask oxide layer with a thickness of 20nm~60nm on the surface of the P-type doping layer. The semi-finished solar cell structure obtained after the first coating treatment is as follows: Figure 9 As shown, on the back side of the crystalline silicon substrate 1 are sequentially formed a first tunneling oxide layer 7, a P-type doped layer 2, and a first mask oxide layer 21. The CVD process of the present application includes but is not limited to low pressure chemical vapor deposition (LPCVP), plasma enhanced chemical vapor deposition (PECVD), and other processes.

[0053] First patterning treatment: Perform first patterning treatment on the semi-finished solar cell product after the first coating treatment to remove part of the first mask oxide layer 21; then perform alkaline liquid wet treatment on the semi-finished solar cell product using alkaline liquid to form Figure 10 The first patterned area 31 shown forms a reflective arm, which can be considered the portion of the P-type doped layer that has not been etched away by the alkaline solution. The first patterned area 31 is used to form an N-type doped region and an isolation trench in subsequent processes, and the areas on both sides of the first patterned area are used to form a P-type doped region in subsequent processes. The first patterning process can be performed using laser etching, dry etching, or wet etching using a mask template, and this application does not specifically limit the method. The alkaline solution can be a sodium hydroxide (NaOH) solution or a potassium hydroxide (KOH) solution, with a concentration of 8 wt% to 12 wt%, a process temperature of 80°C to 90°C, and a process time of 100s to 200s. The laser-related parameters of this application can be: based on the laser pulse width, it can be at least one of nanoseconds, picoseconds, and femtoseconds; based on the laser wavelength, the laser can be any of infrared, visible light, and ultraviolet light.

[0054] Second coating treatment: using CVD, the patterned area and non-patterned area on the back of the semi-finished solar cell after the first patterning treatment are sequentially deposited to form a second tunneling oxide layer and a second intrinsic amorphous silicon layer, wherein the thickness of the second tunneling oxide layer is 0.5nm~3nm, and the thickness of the second intrinsic amorphous silicon layer is 100nm~300nm; then the second intrinsic amorphous silicon layer is doped by thermal diffusion, for example, using PH3 as a doping source to obtain an N-type doping layer with a thickness of 200nm~400nm, and a second mask oxide layer with a thickness of 20nm~60nm is formed on the surface of the N-type doping layer. The structure of the semi-finished solar cell obtained after the second coating treatment is as follows: Figure 11 As shown, on the back side of the crystalline silicon substrate 1 are sequentially a second tunneling oxide layer 8 , an N-type doping layer 3 and a second mask oxide layer 22 .

[0055] Second patterning process: Perform second patterning process on the semi-finished solar cell product to remove part of the second mask oxide layer 22 to form Figure 12 The second graphical area 32 is shown.

[0056] The second patterning process can be performed by laser etching, or by dry etching or wet etching under the action of a mask template, and is not particularly limited in this application. The laser-related parameters of this application can be: based on the pulse width of the laser, it can be at least one of nanoseconds, picoseconds, and femtoseconds; based on the wavelength emitted by the laser, the laser can be any one of infrared, visible light, and ultraviolet light.

[0057] Texturing: Acid polishing is performed on the front of the semi-finished solar cell product after the second patterning process to remove the coating, and then the front of the semi-finished solar cell product is texturing treated. At the same time, the N-type doped layer 3, the second tunnel oxide layer 8 and the crystalline silicon substrate of the second patterning area 32 on the back are etched with a texturing solution. The process temperature is 65°C~80°C and the process time is 400s~700s. Since after the first patterning process, a first patterning area 31 with an inverted trapezoidal cross section is formed when viewed along the y direction, and after the second patterning process, a second patterning area 32 is formed, the texturing solution is affected by the above-mentioned patterning areas and the cross section of the first patterning area 31 is formed along the y direction. Figure 13The backside of the semi-finished solar cell is etched in the direction indicated by the arrows, forming an etching blind area 312 within the first patterned region 31. Simultaneously, the second mask oxide layer 22 within the first patterned region 31 protects the second tunneling oxide layer 8 and N-type doped layer 3 beneath it, allowing the texturing solution to flow from the second patterned region 32 into the crystalline silicon substrate for etching. When the etching depth ratio is too low (e.g., below 0.5), the first patterning process may be incomplete, forming recombination centers. Furthermore, it may lead to over-etching of the P-type and N-type doped regions during the texturing process, reducing the thickness of the cell in the isolation channel region, and thus affecting the overall performance of the device. When the etching depth ratio is too high (e.g., above 0.8), the wettability of the texturing solution in the etched region is insufficient, resulting in an excessively large area of ​​the first and second platform structures. These structures may even directly connect with the P-type doped region, forming a continuous leakage structure, significantly reducing the conversion efficiency of the solar cell. By controlling the etching depth ratio to be 0.5~0.8, the first boss structure and the second boss structure of the present application are formed, wherein the first boss structure is formed after etching the crystalline silicon substrate, and the second boss structure is formed after etching the N-type doped layer.

[0058] In this application, the etching depth ratio is expressed as: H3 / H4. Figure 7 , H3 is the height difference between the highest point of the P-type doping region and the highest point of the N-type doping region; H4 is the height difference between the highest point of the N-type doping region and the lowest point of the isolation channel region.

[0059] The texturing solution of the present application includes alkali, lignin, defoaming agent and wetting agent, wherein the content of alkali in the texturing solution is 0.8wt%~2wt%, the content of lignin in the texturing solution is 0.001wt%~0.03wt%, the content of defoaming agent in the texturing solution is 0.001wt%~0.03wt%, and the content of wetting agent in the texturing solution is 0.001wt%~0.03wt%. The alkali includes at least one of NaOH and KOH. By controlling the content of the wetting agent within the above range, the surface tension between the texturing solution and the crystalline silicon substrate can be reduced, and the surface contact effect of the texturing solution on the narrow space formed by the isolation trench 4 can be promoted, especially the narrow space formed below the reflective support arm 16 and the positive projection of the reflective support arm 16, which is not conducive to the exchange of macromolecular substances in the solution, which is conducive to the formation of the first boss structure and the second boss structure of the present application. The wetting agent includes but is not limited to a nonionic wetting agent, an anionic wetting agent or a cationic wetting agent, for example, at least one of polyoxyethylene, polyoxypropylene, sodium sulfate, sodium phosphate, dodecyltrimethylammonium chloride and sodium dodecylsulfonate.

[0060] After velveting, refer to Figure 14On the back side of the semi-finished solar cell, a first boss structure 5 and a second boss structure 6 are formed on the surface of the side wall 9 adjacent to the isolation trench 4 and the P-type doped region, and a first velvet structure 10 is formed on the surface of the crystalline silicon substrate in the isolation trench 4; on the front side of the semi-finished solar cell, a second velvet structure is formed on the surface of the crystalline silicon substrate.

[0061] Preparation of functional layer and electrode grid line: Using CVD method, aluminum oxide layer is deposited on the front and back of the semi-finished solar cell after texturing as passivation layer, and then silicon nitride layer and / or silicon oxynitride layer and / or silicon oxide layer are deposited on the surface of the passivation layer on the front and back as anti-reflection layer. Figure 8 The thickness of the first passivation layer 11 is 3 nm to 8 nm, and the thickness of the first anti-reflection layer 12 is 60 nm to 90 nm; the thickness of the second passivation layer 13 is 3 nm to 8 nm, and the thickness of the second anti-reflection layer 14 is 80 nm to 110 nm;

[0062] On the back of the semi-finished solar cell with functional layer, the electrode paste is coated on the anti-reflection layer by screen printing, and then sintered. Figure 8 , forming electrode grid lines 15.

[0063] This application does not specifically limit the method for controlling the dimensions of the first and second boss structures, so long as the objectives of this application are achieved. For example, during the texturing process, the dimensions (e.g., length and / or width) of the first and second boss structures can be controlled by controlling the etching depth ratio and / or the content of the wetting agent in the texturing solution.

[0064] The present application provides a photovoltaic module, which includes the solar cell described in any of the above embodiments.

[0065] The present application also provides a photovoltaic module for converting received light energy into electrical energy and transmitting it to an external load. The photovoltaic module comprises: at least one cell string, the cell string being formed by connecting a plurality of the aforementioned solar cells; an encapsulating film for covering the surface of the cell string; and a cover plate for covering the surface of the encapsulating film facing away from the cell string.

[0066] The photovoltaic module of the present application has a lower risk of electric leakage in the solar cells, so the risk of hot spots in the photovoltaic module is reduced.

[0067] Example

[0068] The solar cells and photovoltaic modules of the present application will be further described below with reference to more specific embodiments.

[0069] Example 1

[0070] <First Coating Process>

[0071] A polished crystalline silicon substrate (120 μm thick) is provided. A first tunneling oxide layer and a first intrinsic amorphous silicon layer are sequentially deposited on the back of the crystalline silicon substrate using LPCVD. The first intrinsic amorphous silicon layer is then doped with BCl3 as a doping source by thermal diffusion to obtain a P-type doped layer. A first mask oxide layer is formed on the surface of the P-type doped layer. The main component of the first mask oxide layer is silicon oxide. The semi-finished solar cell structure obtained after the first coating process is as follows: Figure 9 shown.

[0072] <First Graphics Processing>

[0073] The first patterning treatment is performed on the semi-finished solar cell product after the first coating treatment by laser etching to remove part of the first mask oxide layer; then the semi-finished solar cell product is subjected to alkaline liquid wet treatment. The structure of the semi-finished solar cell product obtained after the first patterning treatment is as follows Figure 10 shown.

[0074] <Second Coating Treatment>

[0075] Using CVD, the patterned area and the non-patterned area on the back of the semi-finished solar cell after the first patterning process are sequentially deposited to form a second tunneling oxide layer and a second intrinsic amorphous silicon layer. Then, the second intrinsic amorphous silicon layer is doped with PH3 as a doping source by thermal diffusion to obtain an N-type doped layer, and a second mask oxide layer is formed on the surface of the N-type doped layer. The main component of the second mask oxide layer is silicon oxide. The structure of the semi-finished solar cell obtained after the second coating process is as follows: Figure 11 shown.

[0076] <Second Graphics Processing>

[0077] The solar cell semi-finished product is subjected to a second patterning process to remove part of the second mask oxide layer to form a second patterned area. The structure of the solar cell semi-finished product obtained after the second patterning process is as follows: Figure 12 shown.

[0078] <Velveting>

[0079] The front of the solar cell semi-finished product after the second patterning treatment is subjected to acid polishing to remove the coating, and then the front of the solar cell semi-finished product is subjected to texturing treatment, and at the same time, the N-type doped layer, the second tunneling oxide layer and the crystalline silicon substrate in the second patterning area on the back are etched using a texturing solution, and the etching depth ratio is controlled to be 0.75, thereby forming a first boss structure 5 and a second boss structure 6, as well as a reflective support arm 16 on the back of the solar cell semi-finished product, on the side wall surface adjacent to the isolation channel and the P-type doped area, and forming a first velvet structure on the surface of the crystalline silicon substrate in the isolation channel 4; and forming a second velvet structure on the surface of the crystalline silicon substrate on the front of the solar cell semi-finished product. The structure of the solar cell semi-finished product obtained after texturing is as follows: Figure 14 In the texturing solution, the content of NaOH is 0.9wt%, the content of lignin is 0.005wt%, the content of defoaming agent is 0.003wt%, the content of wetting agent is 0.003wt%, and the wetting agent is sodium dodecyl sulfate.

[0080] <Preparation of functional layers and electrode lines>

[0081] Using ALD, aluminum oxide layers are deposited on the front and back of the semi-finished solar cell after texturing as passivation layers, and then silicon nitride layers are deposited on the surface of the passivation layers on the front and back as anti-reflection layers; on the back of the semi-finished solar cell with functional layers, electrode paste is applied to the P-type doping area and the N-type doping area by screen printing, and then sintered to form electrode grid lines to obtain a solar cell. The structure of a solar cell is as follows: Figure 8 shown.

[0082] The above is a detailed introduction to a solar cell and photovoltaic module disclosed in the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core inventions of the present application. At the same time, for those skilled in the art, according to the ideas of the present application, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present application.

Claims

1. A solar cell, characterized in that: include: A crystalline silicon substrate, wherein the back surface of the crystalline silicon substrate includes alternating P-type doped regions and N-type doped regions, the P-type doped regions correspond to the P-type doped layer, the N-type doped regions correspond to the N-type doped layer, and an isolation trench is provided between adjacent P-type doped regions and N-type doped regions; in: The sidewall of the isolation trench adjacent to the P-type doped region has a first boss structure. The first boss structure is provided with at least one second boss structure on a side facing away from the sidewall. The doping conductivity type of the second boss structure is N-type.

2. The solar cell according to claim 1, characterized in that A plurality of the second protrusion structures are distributed along the extending direction of the isolation trench.

3. The solar cell according to claim 1, wherein There is at least one first boss structure, and within a target length L3 along the extension direction of the isolation trench, there are N second boss structures, the sum of the lengths of the N second boss structures is L2, 0.01≤L2 / L3≤0.8, and N≥1.

4. The solar cell according to claim 1, wherein Along the extending direction of the sidewall, the width of the first boss structure is W1, the width of the second boss structure is W2, and 1.05≤W1 / W2≤2.

5. The solar cell according to claim 1, wherein The widest width of the second boss structure is Wmax, and 0.5 μm≤Wmax≤5 μm.

6. The solar cell according to claim 1, wherein The surface of the isolation trench has a first velvet structure, a height difference between the second boss structure and the P-type doping layer is H1, a height difference between the second boss structure and the first velvet structure is H2, 0.3μm≤H1≤3μm, and / or, 2μm≤H2≤8μm.

7. The solar cell according to claim 6, characterized in that 0.2≤H1 / H2≤1.

8. The solar cell according to claim 1, wherein The sidewall of the isolation channel adjacent to the P-type doping region further has a reflective arm.

9. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell according to any one of claims 1 to 8.

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