Passivation contact structure, preparation method thereof and solar cell

Abstract

The invention provides a passivation contact structure and a preparation method thereof, and a solar cell, the passivation contact structure comprises a silicon substrate, a buffer layer, a passivation dielectric layer and a covering layer are sequentially arranged on one surface of the silicon substrate in a direction far away from the silicon substrate, the buffer layer is made of one or more of silicon oxide, aluminum oxide and doped aluminum oxide, and the passivation dielectric layer is made of one or more of silicon oxide, aluminum oxide and doped aluminum oxide. The passivation dielectric layer is made of one or more of zinc oxide and doped zinc oxide, and the covering layer is made of titanium oxide. According to the passivation contact structure, the thickness of a film layer is reduced, the process time and the material cost are reduced, and parasitic absorption is also reduced.

Description

Technical Field

[0001] The present invention mainly relates to the field of solar energy technology, and particularly relates to a passivation contact structure, a preparation method thereof, and a solar cell. Background Art

[0002] A solar cell (or photovoltaic cell) is a component that converts solar energy into electrical energy. When sunlight shines on the semiconductor material on the surface of the photovoltaic cell, the semiconductor material absorbs the energy of photons, causing electrons in the semiconductor atoms to obtain sufficient energy to be excited from the covalent bond and form free electrons. These free electrons are separated under the action of the PN junction electric field to form a current, which can then drive the load to work.

[0003] As the efficiency of crystalline silicon solar cells is getting closer and closer to the theoretical limit, how to further reduce costs and improve efficiency has become an important issue in this field. Since the main light-receiving surface of crystalline silicon is the front surface, it is particularly important to reduce the optical loss of the front surface and improve the passivation contact quality of the front surface. However, currently, mainstream passivation contact structures, such as amorphous silicon and polycrystalline silicon, have strong parasitic absorption, and polycrystalline silicon is difficult to be compatible with low-temperature processes, which will cause large optical losses when applied to the front surface. In addition, the insulating passivation dielectric film is difficult to transport carriers. If the metal electrode penetrates the insulating dielectric film and contacts the crystalline silicon, additional defects and recombination centers will be introduced. Therefore, a transparent conductive passivation dielectric film with both lateral conductivity and passivation characteristics has become a current research hotspot. The new type of transparent conductive passivation dielectric film includes zinc oxide, whose process temperature is about 200°C, and a relatively thick (about 50 nm) aluminum oxide barrier layer needs to be covered and annealed at a high temperature above 400°C to activate the passivation performance. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to provide a passivation contact structure, a preparation method thereof, and a solar cell, which reduce the film thickness, reduce the process time and material cost, and reduce the parasitic absorption.

[0005] To solve the above technical problem, in a first aspect, the present invention provides a passivation contact structure, including: a silicon substrate, which successively has a buffer layer, a passivation dielectric layer, and a covering layer in a direction away from the silicon substrate on one surface of the silicon substrate, wherein the material of the buffer layer is one or more of silicon oxide, aluminum oxide, and doped aluminum oxide, the material of the passivation dielectric layer is one or more of zinc oxide and doped zinc oxide, and the material of the covering layer is titanium oxide.

[0006] Optionally, the doped aluminum oxide is titanium-doped aluminum oxide, and the atomic number ratio of titanium to aluminum in the titanium-doped aluminum oxide is 1:1 to 1:3.

[0007] Optionally, the doped zinc oxide is aluminum-doped zinc oxide, boron-doped zinc oxide, and / or gallium-doped zinc oxide.

[0008] Optionally, the thickness of the buffer layer is 0.5 nm to 2 nm, and / or the thickness of the passivation dielectric layer is 0.5 nm to 2 nm, and / or the thickness of the capping layer is 1 nm to 6 nm.

[0009] In a second aspect, the present invention provides a method for preparing a passivated contact structure, comprising: providing a silicon substrate; sequentially depositing a buffer layer, a passivation dielectric layer, and a capping layer on one surface of the silicon substrate, wherein the buffer layer is made of one or more of silicon oxide, aluminum oxide, and doped aluminum oxide, the passivation dielectric layer is made of one or more of zinc oxide and doped zinc oxide, and the capping layer is made of titanium oxide.

[0010] Optionally, the doped aluminum oxide is titanium-doped aluminum oxide; the process of depositing the buffer layer includes: introducing trimethylaluminum and water as precursors of aluminum oxide, and introducing titanium tetrachloride for titanium doping.

[0011] Optionally, the atomic layer deposition cycle ratio of titanium tetrachloride to trimethylaluminum is 1:1 - 1:3, and the deposition temperature is 50°C - 150°C.

[0012] Optionally, the doped zinc oxide is aluminum-doped zinc oxide; the process of depositing the passivation dielectric layer includes: introducing diethylzinc and water as precursors of zinc oxide, and introducing trimethylaluminum for aluminum doping.

[0013] Optionally, the atomic layer deposition cycle ratio of trimethylaluminum to diethylzinc is 1:6 - 1:30, and the deposition temperature is 50°C - 150°C.

[0014] Optionally, the process of depositing the capping layer includes: introducing titanium tetrachloride and water as precursors of titanium oxide, and the deposition temperature is 50°C - 150°C.

[0015] In a third aspect, the present invention provides a solar cell, comprising: a silicon substrate having opposite first and second surfaces; on the first surface of the silicon substrate, there are sequentially a diffusion layer, a passivation layer, and a first gate line along the direction away from the silicon substrate, wherein the first gate line passes through the passivation layer and is connected to the diffusion layer; on the second surface of the silicon substrate, there are sequentially a buffer layer, a passivation dielectric layer, and a capping layer along the direction away from the silicon substrate, wherein the silicon substrate and the buffer layer, the passivation dielectric layer, and the capping layer form a passivated contact structure as described in the first aspect; a first transparent electrode layer is provided on the surface of the capping layer away from the silicon substrate; and a second gate line is further included, and the second gate line is connected to the first transparent electrode layer.

[0016] Fourth aspect, the present invention provides a solar cell, comprising: a silicon substrate having opposite first and second surfaces; on the first surface of the silicon substrate, there are successively a tunneling layer, a doped silicon layer, and a second transparent electrode layer along the direction away from the silicon substrate; further comprising a third grid line connected to the second transparent electrode layer; on the second surface of the silicon substrate, there are successively a buffer layer, a passivation dielectric layer, and a cover layer along the direction away from the silicon substrate, wherein the silicon substrate and the buffer layer, the passivation dielectric layer, and the cover layer form a passivation contact structure as described in the first aspect; on the surface of the cover layer away from the silicon substrate, there is a third transparent electrode layer; further comprising a fourth grid line connected to the third transparent electrode layer.

[0017] Compared with the prior art, the present invention has the following advantages: The film layers of the improved passivation contact structure are thinner, which can significantly reduce the process time and material cost and reduce the parasitic absorption. In particular, using titanium oxide as the cover layer also has an additional chlorine passivation effect, which can effectively passivate the dangling bonds on the surface of crystalline silicon. And this passivation contact structure can be prepared at a lower process temperature without an annealing post-treatment process, significantly reducing the energy consumption and process cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are provided to further understand the present application. They are incorporated and constitute a part of the present application. The drawings illustrate embodiments of the present application and, together with this specification, serve to explain the principles of the present application. In the drawings:

[0019] Figure 1 is a schematic diagram of a passivation contact structure according to an embodiment of the present invention;

[0020] Figure 2 is a schematic flow chart of a preparation method of a passivation contact structure according to an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of the structure of a solar cell according to an embodiment of the present invention;

[0022] Figure 4 is a schematic diagram of the structure of a solar cell according to another embodiment of the present invention.

[0023] In the figures:

[0024] 101 - silicon substrate, 102 - buffer layer, 103 - passivation dielectric layer, 104 - cover layer;

[0025] 201 - diffusion layer, 202 - passivation layer, 203 - first grid line, 204 - first transparent electrode layer, 205 - second grid line;

[0026] 301 - Tunneling layer, 302 - Doped silicon layer, 303 - Second transparent electrode layer, 304 - Third gate line, 305 - Third transparent electrode layer, 306 - Fourth gate line. Detailed implementation manners

[0027] To more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some examples or embodiments of the present application. For those of ordinary skill in the art, without creative efforts, the present application can also be applied to other similar scenarios based on these drawings. Unless obvious from the language context or otherwise stated, the same reference numerals in the drawings represent the same structure or operation.

[0028] As shown in the present application and the claims, unless the context clearly indicates an exceptional situation, words such as "a", "an", "one", and / or "the" are not specifically singular and may also include plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of the clearly identified steps and elements, and these steps and elements do not constitute an exclusive list. The method or device may also include other steps or elements.

[0029] In addition, it should be noted that the use of words such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Without otherwise stating, the above words have no special meaning, so it cannot be understood as a limitation on the protection scope of the present application. In addition, although the terms used in the present application are selected from well-known and commonly used terms, some of the terms mentioned in the specification of the present application may be selected by the applicant according to his or her judgment, and their detailed meanings are described in the relevant parts of this description. In addition, it is required to understand the present application not only through the actual terms used, but also through the meaning implied by each term.

[0030] Reference Figure 1 As shown, the passivation contact structure provided in this embodiment solves the problems of the existing passivation contact structure having a relatively thick film layer and requiring a relatively high temperature for preparation. It mainly includes a silicon substrate 101, and sequentially has a buffer layer 102, a passivation dielectric layer 103, and a covering layer 104 on one surface of the silicon substrate 101 away from the silicon substrate 101. Among them, the material of the buffer layer 102 is one or more of silicon oxide, aluminum oxide, and doped aluminum oxide, the material of the passivation dielectric layer 103 is one or more of zinc oxide and doped zinc oxide, and the material of the covering layer 104 is titanium oxide.

[0031] In this embodiment, the silicon substrate 101 can be an n-type silicon substrate, and its resistivity can be 1 Ω·cm - 20 Ω·cm.

[0032] In this embodiment, the function of the buffer layer 102 is to optimize the energy band structure and the interface structure, and reduce the interface defects and lattice mismatch. In one implementation, the doped alumina is titanium-doped alumina, and the atomic number ratio of titanium to aluminum in the titanium-doped alumina is 1:1 to 1:3. Alumina doping can increase the conductivity. The titanium-doped alumina can be prepared by atomic layer deposition, and the process temperature is 50°C - 150°C; the thickness of the buffer layer 102 is 0.5nm - 2nm.

[0033] In this embodiment, the passivation dielectric layer 103 can be a transparent conductive film, which is used to provide field effect passivation and H passivation, and provide a channel for electron selective transport. It can be prepared by atomic layer deposition, and the preferred process temperature is 50°C - 150°C. In one implementation, the doped zinc oxide is aluminum-doped zinc oxide, boron-doped zinc oxide, and / or gallium-doped zinc oxide. The thickness of the passivation dielectric layer 103 is 0.5nm - 2nm.

[0034] When zinc oxide is used to passivate monocrystalline silicon, due to the work function mismatch, charge transfer will occur, which will cause the energy band of the silicon at the contact interface to bend and form an inversion, that is, the majority carrier concentration on one side of the silicon substrate 101 decreases and the minority carriers are enriched, resulting in a decrease in the field effect passivation performance. In this embodiment, a buffer layer 102 is provided between the silicon substrate 101 and the zinc oxide. In addition to providing additional chemical passivation, it can also adjust the energy band bending at the interface and prevent the recombination caused by the enrichment of minority carriers on the silicon surface.

[0035] In this embodiment, the precursors of the capping layer 104 are preferably titanium tetrachloride and water, which provide field effect passivation and chlorine passivation. The thickness of the capping layer 104 is 1nm - 6nm. Since the overall thickness of the passivated contact structure is relatively thin, the chlorine in the capping layer 104 can diffuse to the silicon interface during the preparation process to passivate the dangling bonds on the surface. Therefore, no post-annealing treatment process is required. The capping layer 104 can be prepared by atomic layer deposition.

[0036] In this embodiment, the passivated contact structure, where the buffer layer 102, the passivation dielectric layer 103, and the capping layer 104 are thinner, can significantly reduce the process time and material cost, and reduce the parasitic absorption. Especially when using titanium oxide as the capping layer 104, it also has an additional chlorine passivation effect, which can effectively passivate the dangling bonds on the silicon surface.

[0037] Another embodiment of the present invention provides a method for preparing a passivated contact structure, as shown in Figure 2 mainly including: S210, providing a silicon substrate; S220, sequentially depositing a buffer layer, a passivation dielectric layer, and a capping layer on one surface of the silicon substrate, where the material of the buffer layer is one or more of silicon oxide, alumina, and doped alumina, the material of the passivation dielectric layer is one or more of zinc oxide and doped zinc oxide, and the material of the capping layer is titanium oxide.

[0038] In one example, the doped alumina is titanium-doped alumina. The process of depositing the buffer layer includes introducing trimethylaluminum and water as the precursors of alumina, and introducing titanium tetrachloride for titanium doping. More preferably, the atomic layer deposition cycle ratio of titanium tetrachloride to trimethylaluminum is 1:1 - 1:3, and the deposition temperature is 50°C - 150°C.

[0039] In one example, the doped zinc oxide is aluminum-doped zinc oxide. The process of depositing the passivation dielectric layer includes introducing diethylzinc and water as the precursors of zinc oxide, and introducing trimethylaluminum for aluminum doping. More preferably, the atomic layer deposition cycle ratio of trimethylaluminum to the diethylzinc is 1:6 - 1:30, and the deposition temperature is 50°C - 150°C.

[0040] In one example, the process of depositing the capping layer includes introducing titanium tetrachloride and water as the precursors of titanium oxide, and the deposition temperature is 50°C - 150°C.

[0041] Exemplarily, taking the preparation of a passivated contact structure with an n-type monocrystalline silicon substrate as an example, the following preparation process is included: 1. Provide an n-type monocrystalline silicon substrate. After cleaning by the RCA standard cleaning method, use ALD (Atomic Layer Deposition) to sequentially deposit titanium-doped alumina as the buffer layer on the front and back surfaces of the silicon substrate. Introduce trimethylaluminum and water as the precursors of alumina, and introduce titanium tetrachloride for titanium doping. The atomic layer deposition cycle ratio of titanium tetrachloride to trimethylaluminum is 1:1 - 1:3, the deposition temperature is 50°C - 150°C, and the deposition film thickness is 0.5 nm - 2 nm to form semi-finished product one; 2. On the basis of semi-finished product one, use ALD to sequentially deposit aluminum-doped zinc oxide as the passivation dielectric layer on the front and back surfaces. Introduce diethylzinc and water as the precursors of zinc oxide, and introduce trimethylaluminum for aluminum doping. The atomic layer deposition cycle ratio of trimethylaluminum to diethylzinc is 1:6 - 1:30, the deposition temperature is 50°C - 150°C, and the deposition film thickness is 0.5 nm - 2 nm to form semi-finished product two; 3. On the basis of semi-finished product two, use ALD to sequentially deposit titanium oxide as the capping layer on the front and back surfaces. Introduce titanium tetrachloride and water as the precursors of titanium oxide, the deposition temperature is 50°C - 150°C, and the deposition film thickness is 1 nm - 6 nm, thereby forming a passivated contact structure.

[0042] The preparation method of the passivated contact structure in this embodiment can be prepared at a lower process temperature, without an annealing post-treatment process, significantly reducing energy consumption and process costs.

[0043] Another embodiment of the present invention provides a solar cell, refer to Figure 3As shown, it mainly includes a silicon substrate 101, which has opposite first surface (the upper surface shown in the figure) and second surface (the lower surface shown in the figure). On the first surface of the silicon substrate 101, there are successively a diffusion layer 201, a passivation layer 202, and a first gate line 203 along the direction away from the silicon substrate 101, wherein the first gate line 203 passes through the passivation layer 202 and is connected to the diffusion layer 201. On the second surface of the silicon substrate 101, there are successively a buffer layer 102, a passivation dielectric layer 103, and a cover layer 104 along the direction away from the silicon substrate 101, wherein the silicon substrate 101 and the buffer layer 102, the passivation dielectric layer 103, and the cover layer 104 form a passivated contact structure as shown in the foregoing embodiment. On the surface of the cover layer 104 away from the silicon substrate 101, there is a first transparent electrode layer 204, and it also includes a second gate line 205, and the second gate line 205 is connected to the first transparent electrode layer 204.

[0044] In this embodiment, the first gate line 203 can use silver metal as the gate line and penetrate the passivation layer 202 to contact the diffusion layer 201 by sintering. Similarly, the second gate line 205 can also be prepared by sintering.

[0045] In an example, the material of the passivation layer 202 can be one or a combination of alumina, silicon oxide, silicon oxynitride, and silicon nitride, and the preferred thickness of the passivation layer 202 is 50 nm to 200 nm.

[0046] In an example, the doping element of the diffusion layer 201 can be boron and / or gallium, the doping concentration of the diffusion layer 201 is 1E18 - 1E19 cm -3 , and the doping depth is 0.5 μm - 2 μm.

[0047] In this embodiment, the material of the first transparent electrode layer 204 can be indium tin oxide, and the thickness is 50 nm to 150 nm.

[0048] For other details of the passivated contact structure in this embodiment, reference can be made to the foregoing embodiment, and details will not be elaborated here.

[0049] The back surface of the solar cell in this embodiment adopts the passivated contact structure as described above, and the buffer layer, the passivation dielectric layer, and the cover layer are thinner, which can significantly reduce the process time and material cost and reduce the parasitic absorption. Especially when titanium oxide is used as the cover layer, it also has an additional chlorine passivation effect, which can effectively passivate the dangling bonds on the surface of crystalline silicon.

[0050] Another embodiment of the present invention provides a solar cell, refer to Figure 4As shown in the figure, it mainly includes: a silicon substrate 101, and the silicon substrate 101 has opposite first surface (the upper surface shown in the figure) and second surface (the lower surface shown in the figure). On the first surface of the silicon substrate 101, there are successively a tunneling layer 301, a doped silicon layer 302, and a second transparent electrode layer 303 along the direction away from the silicon substrate 101. It also includes a third gate line 304, and the third gate line 304 is connected to the second transparent electrode layer 303. On the second surface of the silicon substrate 101, there are successively a buffer layer 102, a passivation dielectric layer 103, and a cover layer 104 along the direction away from the silicon substrate 101, wherein the silicon substrate 101 and the buffer layer 102, the passivation dielectric layer 103, and the cover layer 104 form a passivation contact structure as shown in the foregoing embodiments. On the surface of the cover layer 104 away from the silicon substrate 101, there is a third transparent electrode layer 305. It also includes a fourth gate line 306, and the fourth gate line 306 is connected to the third transparent electrode layer 305.

[0051] In one example, the materials of the second transparent electrode layer 303 and the third transparent electrode layer 305 can be indium tin oxide, and their thickness is 50 nm to 150 nm.

[0052] In one example, the silicon substrate 101 can be an n-type silicon substrate, the tunneling layer 301 is a silicon dioxide tunneling layer, and its thickness is 0.5 nm - 1.5 nm. The doped silicon layer 302 is a p-type doped silicon layer, and it can adopt one or more combinations of polysilicon, amorphous silicon, and microcrystalline silicon. The doping concentration of the p-type doped silicon layer is 1E18 - 1E19 cm -3 . The thickness of the doped silicon layer 302 is 10 nm - 30 nm.

[0053] For other details about the passivation contact structure in this embodiment, reference can be made to the foregoing embodiments, and details will not be elaborated here.

[0054] The back surface of the solar cell in this embodiment adopts the passivation contact structure as described above. The buffer layer, the passivation dielectric layer, and the cover layer are thinner, which can significantly reduce the process time and material cost and reduce the parasitic absorption. Especially when titanium oxide is used as the cover layer, it also has an additional chlorine passivation effect, which can effectively passivate the dangling bonds on the surface of the crystalline silicon.

[0055] The basic concepts have been described above. Obviously, for those skilled in the art, the above invention disclosure is only an example and does not constitute a limitation to this application. Although not explicitly stated here, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are proposed in this application, so such modifications, improvements, and corrections still belong to the spirit and scope of the exemplary embodiments of this application.

[0056] Similarly, it should be noted that, in order to simplify the description disclosed in the present application and thus help the understanding of one or more embodiments of the invention, in the foregoing description of the embodiments of the present application, multiple features are sometimes grouped into one embodiment, drawing, or description thereof. However, this disclosure method does not mean that the features required by the subject matter of the present application are more than those mentioned in the claims. In fact, the features of the embodiments are fewer than all the features of the single embodiments disclosed above.

[0057] In some embodiments, numbers are used to describe components and the quantity of attributes. It should be understood that such numbers used for the description of embodiments are modified by the modifiers "about", "approximate" or "substantially" in some examples. Unless otherwise stated, "about", "approximate" or "substantially" indicate that the said numbers allow a variation of ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, and such approximate values may change according to the characteristics required by individual embodiments. In some embodiments, the numerical parameters should consider the specified significant digits and adopt the method of retaining the general number of digits. Although the numerical ranges and parameters used in some embodiments of the present application to confirm the breadth of their scope are approximate values, in specific embodiments, such numerical settings are as precise as possible within the feasible range.

[0058] Although the present application has been described with reference to the current specific embodiments, those of ordinary skill in the art in this technical field should recognize that the above embodiments are only used to illustrate the present application, and various equivalent changes or substitutions can be made without departing from the spirit of the present application. Therefore, as long as the changes and variations of the above embodiments are within the scope of the spirit of the present application, they will fall within the scope of the claims of the present application.

Claims

1. A passivation contact structure, characterized in that: include: A silicon substrate, wherein a buffer layer, a passivation dielectric layer and a covering layer are sequentially provided on a surface of the silicon substrate away from the silicon substrate, wherein the material of the buffer layer is one or more of silicon oxide, aluminum oxide and doped aluminum oxide, the material of the passivation dielectric layer is one or more of zinc oxide and doped zinc oxide, and the material of the covering layer is titanium oxide.

2. The passivation contact structure according to claim 1, characterized in that: The doped aluminum oxide is titanium-doped aluminum oxide, and the atomic ratio of titanium to aluminum in the titanium-doped aluminum oxide is 1:1 to 1:

3.

3. The passivation contact structure according to claim 1, characterized in that: The doped zinc oxide is aluminum-doped zinc oxide, boron-doped zinc oxide and / or gallium-doped zinc oxide.

4. The passivation contact structure according to claim 1, characterized in that: The thickness of the buffer layer is 0.5 nm to 2 nm, and / or the thickness of the passivation dielectric layer is 0.5 nm to 2 nm, and / or the thickness of the cover layer is 1 nm to 6 nm.

5. A method for preparing a passivation contact structure, characterized in that: include: Providing a silicon substrate; A buffer layer, a passivation dielectric layer and a covering layer are sequentially deposited on a surface of the silicon substrate, wherein the material of the buffer layer is one or more of silicon oxide, aluminum oxide and doped aluminum oxide, the material of the passivation dielectric layer is one or more of zinc oxide and doped zinc oxide, and the material of the covering layer is titanium oxide.

6. The method for preparing a passivation contact structure according to claim 5, characterized in that: The doped aluminum oxide is titanium-doped aluminum oxide; The process of depositing the buffer layer includes: introducing trimethylaluminum and water as precursors of aluminum oxide, and introducing titanium tetrachloride for titanium doping.

7. The method for preparing a passivation contact structure according to claim 6, characterized in that: The atomic layer deposition cycle ratio of the titanium tetrachloride and the trimethylaluminum is 1:1-1:3, and the deposition temperature is 50°C-150°C.

8. The method for preparing a passivation contact structure according to claim 5, characterized in that: The doped zinc oxide is aluminum-doped zinc oxide; The process of depositing the passivation dielectric layer includes: introducing diethyl zinc and water as precursors of zinc oxide, and introducing trimethyl aluminum for aluminum doping.

9. The method for preparing a passivation contact structure according to claim 8, characterized in that: The atomic layer deposition cycle ratio of the trimethylaluminum and the diethylzinc is 1:6-1:30, and the deposition temperature is 50°C-150°C.

10. The method for preparing a passivation contact structure according to claim 5, characterized in that: The process of depositing the covering layer includes: introducing titanium tetrachloride and water as precursors of titanium oxide, and the deposition temperature is 50°C-150°C.

11. A solar cell, characterized in that: include: A silicon substrate having a first surface and a second surface opposite to each other; On the first surface of the silicon substrate, there are a diffusion layer, a passivation layer and a first gate line in sequence along a direction away from the silicon substrate, wherein the first gate line passes through the passivation layer and is connected to the diffusion layer; On the second surface of the silicon substrate, there is a buffer layer, a passivation dielectric layer and a capping layer in sequence in a direction away from the silicon substrate, wherein the silicon substrate, the buffer layer, the passivation dielectric layer and the capping layer form a passivation contact structure as claimed in any one of claims 1 to 4; The cover layer has a first transparent electrode layer on a surface away from the silicon substrate; and further comprises a second gate line connected to the first transparent electrode layer.

12. A solar cell, characterized in that: include: A silicon substrate having a first surface and a second surface opposite to each other; A tunneling layer, a doped silicon layer, and a second transparent electrode layer are sequentially provided on the first surface of the silicon substrate in a direction away from the silicon substrate; and a third gate line is further provided, wherein the third gate line is connected to the second transparent electrode layer; On the second surface of the silicon substrate, there is a buffer layer, a passivation dielectric layer and a capping layer in sequence in a direction away from the silicon substrate, wherein the silicon substrate, the buffer layer, the passivation dielectric layer and the capping layer form a passivation contact structure as claimed in any one of claims 1 to 4; The cover layer has a third transparent electrode layer on a surface away from the silicon substrate; and further comprises a fourth gate line connected to the third transparent electrode layer.

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