Dynamic Fusion Accelerator

Abstract

The present invention provides a dynamic fusion accelerator, which belongs to the field of accelerator technology. The dynamic fusion accelerator is applied to a near-memory computing system based on the RISC-V instruction set architecture, and is configured to perform arithmetic and logical operations using a hardware reuse strategy. The dynamic fusion accelerator includes a mode switching mechanism module, an array clock, and at least one group of dynamic fusion processing units. The dynamic fusion accelerator is also configured to use the mode switching mechanism to enable the calculation path of at least one group of dynamic fusion processing units to be replaced, and to synchronize the clock signal using the array clock; the mode switching mechanism module is configured to adaptively configure the mode switching mechanism; and the output of the dynamic fusion accelerator is transmitted to other units via a shared bus. The dynamic fusion accelerator provided in an embodiment of the present invention adopts a hierarchical dynamic switching mechanism to realize hardware component reuse, and the switching mechanism of the dynamic fusion processing unit provides an alternative calculation path for the neural sublayer.

Description

Technical Field

[0001] The present invention relates to the technical field of accelerators, and in particular to a dynamic fusion accelerator. Background Art

[0002] The rise of big data has driven a shift in computing toward data-driven workloads, such as artificial intelligence (AI) and machine learning (ML). AI / ML applications have led to a surge in computing demand, enabling advanced capabilities in modern fields. This demand, coupled with the increasing complexity of neural network models, has accelerated the growth of memory and computing resources. In this computing paradigm driven by big data and AI / ML, accelerators (such as GPUs, TPUs, FPGAs, and ASICs) have become a core technology to meet this surge in computing demand. Accelerators significantly improve computing efficiency through specialized hardware and hardware-software co-design.

[0003] In related technologies, static accelerator architectures have limitations. Most application-specific integrated circuits (ASICs), such as TPUs, are optimized for fixed computing modes and are difficult to adapt to emerging algorithms. Summary of the Invention

[0004] An object of an embodiment of the present invention is to provide a dynamic fusion accelerator that can address the limitations of the static architecture of the accelerator.

[0005] To achieve the above objectives, an embodiment of the present invention provides a dynamic fusion accelerator, which is applied to a near-memory computing system based on the RISC-V instruction set architecture. The dynamic fusion accelerator is configured to perform arithmetic and logical operations using a hardware reuse strategy. The dynamic fusion accelerator includes a mode switching mechanism module, an array clock, and at least one group of dynamic fusion processing units. The dynamic fusion accelerator is further configured to utilize the mode switching mechanism of the mode switching mechanism module to enable the computational path of the at least one group of dynamic fusion processing units to be replaced, and utilize the array clock to synchronize the clock signal. The mode switching mechanism module is configured to adaptively configure the mode switching mechanism. The output of the dynamic fusion accelerator is transmitted to other units via a shared bus.

[0006] Optionally, the dynamic fusion accelerator is further configured to perform parameter transformation based on the PyTorch deep learning framework, and the parameter transformation includes reciprocal generation and symbol mapping. During the parameter transformation process, N decimal places are retained to ensure calculation accuracy.

[0007] Optionally, the mode switching mechanism is a dual-mode switching mechanism, and the mode switching mechanism module is further configured to utilize the dual-mode switching mechanism to reconfigure the computing path, thereby supporting multiple computing paradigms across neural layers. For the first mode switching mechanism, a first conditional signal is used at runtime to switch between basic multiplication and other arithmetic operations. The arithmetic operation receives two operands with a bit width of BW and generates a result with a bit width of 2*BW or BW+1. For the second mode switching mechanism, it is controlled by a second conditional signal to perform subtraction and division operations by reusing existing addition and multiplication units, thereby achieving reuse of hardware components.

[0008] Optionally, the dynamic fusion accelerator is configured to perform arithmetic logic operations using a hardware reuse strategy, including: during the initialization of the register array, storing parameter transformations from the PyTorch deep learning framework to achieve dynamic reconfiguration of the computing path; when the first conditional signal is high, the at least one group of dynamic fusion processing units performs a multiplication operation; when the first conditional signal is low, the at least one group of dynamic fusion processing units enters a hardware component reuse mode, and the hardware component reuse mode dynamically activates dual computing paths and adaptively maps them to the computing paths in neural network inference.

[0009] Optionally, the dynamic fusion accelerator is configured to perform arithmetic logic operations using a hardware multiplexing strategy, and further includes: when the second condition signal is at a high level, causing the first calculation path to perform multiplication and addition operations; when the second condition signal is at a low level, causing the second calculation path to use multiplication and addition for calculation, and perform subtraction and division operations; the temporary results generated by the first calculation path and the second calculation path are stored in a partition buffer.

[0010] Optionally, the array clock is also configured to generate a clock gating signal for activating or deactivating the at least one group of dynamic fusion processing units. When the clock gating signal is at a low level, the computing operation is paused, thereby eliminating static power consumption. The at least one group of dynamic fusion processing units partitions the clock gating signal, the first condition signal, and the second condition signal to each dynamic fusion processing unit, so that independent access can be achieved within one cycle.

[0011] Optionally, the two operands with a bit width of BW, the first condition signal, and the second condition signal are used to control each dynamic fusion processing unit and manage a hierarchical dynamic switching mechanism.

[0012] Optionally, in the loading stage, according to the neural sublayer loop, the array consisting of the first conditional signal and the second conditional signal is obtained, and the array consisting of the two operands with a bit width of BW is loaded according to the number of the at least one group of dynamic fusion processing units.

[0013] Optionally, a near memory computing system based on the RISC-V instruction set architecture includes a near memory architecture instruction set module based on software and hardware collaboration, an instruction set model module, an energy-efficient instruction path module, and a storage-computing integration module. The near memory architecture instruction set module is configured to integrate opcode configuration and operation mechanism in each instruction of the RISC-V instruction set so that the dedicated instruction set can implement corresponding execution control. The instruction set model module is configured to adopt an instruction arrangement method of neural network layer structure mapping, and minimize the number of instructions through loop instructions to support the iterative process. The energy-efficient instruction path module is configured as the instruction path that the dedicated instruction set follows to execute each stage of the sequence. The storage-computing integration module includes a storage component and the dynamic fusion accelerator. The storage-computing integration module is configured to dynamically switch the computing path according to instruction requirements by fusing storage and computing.

[0014] Optionally, the instruction set model module includes an instruction set model based on a neural network layer, and expands and arranges dynamic fusion processing units based on the neural network convolution kernel size of the instruction set model.

[0015] Through the above technical solution, an embodiment of the present invention provides a dynamic fusion accelerator, which is applied to a near-memory computing system based on the RISC-V instruction set architecture. The dynamic fusion accelerator is configured to perform arithmetic and logical operations using a hardware reuse strategy. The dynamic fusion accelerator includes a mode switching mechanism module, an array clock, and at least one group of dynamic fusion processing units. The dynamic fusion accelerator is also configured to use the mode switching mechanism to enable the calculation path of at least one group of dynamic fusion processing units to be replaced, and to synchronize the clock signal using the array clock; the mode switching mechanism module is configured to adaptively configure the mode switching mechanism; and the output of the dynamic fusion accelerator is transmitted to other units via a shared bus. The dynamic fusion accelerator provided by an embodiment of the present invention adopts a hierarchical dynamic switching mechanism to achieve hardware component reuse, and the switching mechanism of the dynamic fusion processing unit provides an alternative calculation path for the neural sublayer.

[0016] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the embodiments of the present invention, but do not constitute a limitation of the embodiments of the present invention. In the accompanying drawings:

[0018] Figure 1 is a schematic structural diagram of a dynamic fusion accelerator provided by an embodiment of the present invention;

[0019] Figure 2 is a schematic diagram of the structure of an example dynamic fusion accelerator;

[0020] Figure 3 This is a diagram of a custom RISC-V instruction set framework based on a near-memory architecture.

[0021] Figure 4 is a configuration diagram of an example dynamic fusion accelerator;

[0022] Figure 5 is a schematic diagram of an example scalable dynamic fusion processing unit.

[0023] Reference numerals

[0024] 10-mode switching mechanism module; 20-array clock; 30-dynamic fusion processing unit. DETAILED DESCRIPTION

[0025] The following describes the specific implementation of the embodiment of the present invention in detail with reference to the accompanying drawings. It should be understood that the specific implementation described herein is only used to illustrate and explain the embodiment of the present invention and is not used to limit the embodiment of the present invention.

[0026] As mentioned above, the static architecture of accelerators has limitations. To address this, embodiments of the present invention provide a dynamic fusion accelerator that can be applied to near-memory computing (NMC) systems based on the RISC-V instruction set architecture. This NMC system can use SOT-MRAM as a storage component and a dynamic fusion accelerator as a computing component, effectively reusing hardware components during inference.

[0027] Figure 1 This is a schematic diagram of the structure of the dynamic fusion accelerator provided by the embodiment of the present invention. Please refer to Figure 1 The dynamic fusion accelerator is configured to execute arithmetic and logical operations using a hardware multiplexing strategy. The dynamic fusion accelerator may include a mode switching mechanism module 10, an array clock 20, and at least one group of dynamic fusion processing units 30. In an embodiment of the present invention, the dynamic fusion accelerator is further configured to utilize the mode switching mechanism of the mode switching mechanism module 10 to enable substitution of computational paths of the at least one group of dynamic fusion processing units 30, and to utilize the array clock 20 to synchronize clock signals. The mode switching mechanism module 10 is configured to adaptively configure the mode switching mechanism. The output of the dynamic fusion accelerator is transmitted to other units via a shared bus.

[0028] Each dynamic fusion processing unit 30 may include a group of computing units.

[0029] In a preferred embodiment of the present invention, a near memory computing system based on the RISC-V instruction set architecture may include a near memory architecture instruction set module based on software and hardware collaboration, an instruction set model module, an energy-efficient instruction path module, and a storage-computing integration module. The near memory architecture instruction set module may be configured to integrate opcode configuration and operation mechanism in each instruction of the RISC-V instruction set so that the dedicated instruction set implements corresponding execution control; the instruction set model module is configured to adopt an instruction arrangement method of neural network layer structure mapping, and minimize the number of instructions through loop instructions to support the iterative process; the energy-efficient instruction path module is configured so that the dedicated instruction set follows the instruction path of each stage of sequential execution; the storage-computing integration module includes a storage component and the dynamic fusion accelerator, and the storage-computing integration module is configured to dynamically switch the computing path according to instruction requirements by fusing storage and computing.

[0030] Please combine Figure 2 as well as Figure 3 , an NMC system based on a customized RISC-V ISA can be used to improve the energy efficiency of the neural inference process. By extending the RISC-V instruction set framework (e.g., RV32 ISA) with a dedicated instruction set, additional functionality is added, including: 1) configurable accelerators for inference operations; 2) processing unit microarchitecture control; and 3) execution specifications across computing paradigms. For example, the near memory architecture instruction set module 10 is configured to achieve precise execution control by integrating opcode configuration and operation mechanisms in each instruction, such as Figure 3 (a) shows the instruction set model module. The instruction set model module is configured as a combination of a variety of specialized instruction sets based on the neural network layer instruction set model, which conforms to the computational structure of the neural layer. This model minimizes the number of instructions by looping instructions, thereby supporting iterative processes such as loading, computing, and transferring, as shown in Figure 2. Figure 3 (b) As shown. The energy-efficient instruction path module can be configured as a three-stage instruction path that follows a sequential execution of a dedicated instruction set, which can include the fetch-decode (FecDec), execute, and write-back stages. The FecDec stage can determine the decoding path, while the execute and write-back stages can be responsible for accelerator configuration and logical operations to ensure efficient processing. The decoded instructions can send control signals to the NMC system's storage and computing integration module 40 (memory and computing unit) through the storage interface, as shown in Figure 4. Figure 3As shown in (c). For the computing component of the NMC system, an embodiment of the present invention may be a dynamic fusion accelerator, which may utilize a hardware multiplexing strategy to perform arithmetic and logical operations. The NMC system may use SOT-MRAM as a storage component and a dynamic fusion accelerator as a computing component to effectively reuse hardware components during the inference process. The dynamic fusion accelerator utilizes a hardware multiplexing strategy to perform arithmetic and logical operations. Among them, the mode switching mechanism of the dynamic fusion processing unit (which may be referred to as a DF-PE unit or a DF-PE column) 30 enables the calculation path to be replaced. The synchronization of the clock signal of the DF-PE column and the adaptive configuration of the mode switching mechanism ensure the optimal utilization of hardware resources. Furthermore, the output of the dynamic fusion accelerator is transmitted to other units via a shared bus to form a data flow similar to a systolic array, such as Figure 2 As shown in Figure 3(d), the custom RISC-V instruction set architecture provided by the embodiment of the present invention provides support for energy-efficient neural reasoning by interconnecting dedicated instruction sets in the neural layer-based ISA mode and combining a three-stage instruction path to achieve dynamic fusion acceleration.

[0031] In a preferred embodiment of the present invention, the dynamic fusion accelerator can also be configured to perform parameter transformation based on the PyTorch deep learning framework, and the parameter transformation includes inverse generation and symbol mapping; during the parameter transformation process, N decimal places are retained to ensure calculation accuracy.

[0032] Please refer to Figure 4 For example, the parameter transformation based on PyTorch includes, for example, reciprocal generation (which may include moving variance, local scale, etc.) and symbol mapping (which may include moving average, local exponent, etc.). During the entire parameter transformation process, four decimal places, for example, may be retained to ensure calculation accuracy.

[0033] In a preferred embodiment of the present invention, the mode switching mechanism is a dual-mode switching mechanism, and the mode switching mechanism module 10 can also be configured to utilize the dual-mode switching mechanism to reconfigure the computational path, thereby supporting multiple computational paradigms across neural layers. Preferably, for the first mode switching mechanism, a runtime first conditional signal is used to switch between basic multiplication and other arithmetic operations, where the arithmetic operation receives two operands with a bit width of BW and generates a result with a bit width of 2*BW or BW+1; for the second mode switching mechanism, the second conditional signal is controlled to perform subtraction and division operations by reusing existing addition and multiplication units, thereby achieving reuse of hardware components.

[0034] Please refer to Figure 4, continuing with the above example, the DF-PE unit can implement a dual-mode switching mechanism to reconfigure the computation path to support multiple computational paradigms across neural layers. Computational operations such as convolution and normalization rely on basic arithmetic logic operations, which can include multiplication (MUL), subtraction (SUB), and addition (ADD). For the first mode switching mechanism, the runtime first condition signal (S1) can be used to switch between basic multiplication and other arithmetic operations, and the switching strategy can depend on the control flow. The arithmetic operation receives two operands (Op 1,2 ), and generates a result with a bit width of 2*BW (for multiplication) or BW+1 (for addition). The second mode switching mechanism, controlled by a second conditional signal (S2), allows hardware components to be reused by reusing existing addition and multiplication units to perform subtraction and division operations. This selection strategy can be determined by an array of runtime conditions (S1 and S2), optimizing hardware resource utilization.

[0035] In a preferred embodiment of the present invention, the dynamic fusion accelerator is configured to perform arithmetic and logical operations using a hardware reuse strategy, which may include: storing parameter transformations from the PyTorch deep learning framework during register array initialization to achieve dynamic reconfiguration of the computation path; when the first condition signal is high, the at least one group of dynamic fusion processing units performs a multiplication operation; when the first condition signal is low, the at least one group of dynamic fusion processing units enters a hardware component reuse mode. The hardware component reuse mode dynamically activates dual computation paths and adaptively maps them to the computation paths in neural network inference.

[0036] Please refer to Figure 4 Continuing with the previous example, the register arrays (Reg1, Reg2) store parameter transformations from PyTorch during initialization, enabling dynamic reconfiguration of the computation path. For example, when S1 is high, the DF-PE unit performs multiplication operations; when S1 is low, the DF-PE unit enters hardware component reuse mode. This mode dynamically activates dual computation paths, adaptively mapping them to latency-sensitive computation paths in neural network inference.

[0037] In a preferred embodiment of the present invention, the dynamic fusion accelerator is configured to perform arithmetic and logic operations using a hardware reuse strategy, and further includes: when the second condition signal is high, causing the first calculation path to perform multiplication and addition operations; and when the second condition signal is low, causing the second calculation path to use multiplication and addition for calculations and perform subtraction and division operations. Temporary results generated by the first calculation path and the second calculation path are stored in a partition buffer.

[0038] Please refer to Figure 4, continuing the above example, the first calculation path (also called calculation path 1) uses multiplication and addition components to obtain Reg1 <1> and Reg2 <0> When S2 is high, this path performs a multiplication and addition operation. <0> and Reg2 <1> Store the negative and inverse of the normalized moving average and moving variance respectively. When S2 is low, the first calculation path (also called calculation path 2) uses multiplication and addition to calculate Reg1 <1> and Reg2 <0> , performing subtraction and division operations. The temporary results generated by the above independent calculation paths are stored in the partition buffer, enabling efficient and seamless transmission to the DF-PE column.

[0039] In a preferred embodiment of the present invention, the instruction set model module includes an instruction set model based on a neural network layer, and the dynamic fusion processing unit is expanded and arranged based on the size of the neural network convolution kernel of the instruction set model.

[0040] Figure 5 For an example of an expandable DF-PE column, refer to Figure 5 , for example, it is organized based on the size of the neural network convolution kernel (K) to arrange columns (Cloumn) of size (size) K×K DF-PE units (Units). In a preferred embodiment of the present invention, the DF-PE column receives the operand Op 1,2 Arrays, intermediate result arrays, and condition arrays (S1 and S2). The condition arrays implement an efficient calculation control mechanism.

[0041] In a preferred embodiment of the present invention, the array clock is further configured to generate a clock gating signal for activating or deactivating the at least one group of dynamic fusion processing units. Preferably, when the clock gating signal is at a low level, computing operations are suspended, thereby eliminating static power consumption. The at least one group of dynamic fusion processing units partitions the clock gating signal, the first condition signal, and the second condition signal to each dynamic fusion processing unit, enabling independent access within a cycle.

[0042] Please refer to Figure 5 Continuing with the previous example, the DF-PE column also features a clock gating signal (PEcol_clock) that activates or deactivates the DF-PE column. For example, when PEcol_clock is low, computation is suspended, eliminating static power consumption. The DF-PE column can fully partition PEcol_clock, S1, and S2 to each DF-PE unit, enabling independent access within a single cycle.

[0043] In a preferred embodiment of the present invention, the two operands with a bit width of BW, the first condition signal, and the second condition signal are used to control each dynamic fusion processing unit and manage a hierarchical dynamic switching mechanism.

[0044] Please refer to Figure 5 , continuing the above example, the operand Op 1,2 , S1 and S2 arrays control each DF-PE column and manage the dynamic switching mechanism of the hierarchy.

[0045] In a preferred embodiment of the present invention, during the loading stage, according to the neural sublayer loop, an array consisting of the first conditional signal and the second conditional signal is obtained, and according to the number of the at least one group of dynamic fusion processing units, an array consisting of the two operands with a bit width of BW is loaded.

[0046] Please refer to Figure 5 , continuing the above example, in the loading phase, the S1 and S2 arrays are obtained according to the neural sublayer loop, and the operand Op 1,2 The array can be loaded according to the number of DF-PE columns. The intermediate buffer of each DF-PE column can be designed to be K×K in size, with a bandwidth of 2*BW, for example, which is the number of operations Op 1,2 The embodiment of the present invention realizes the centralized accumulation of calculation results, which facilitates subsequent summation operations.

[0047] Accordingly, the dynamic fusion accelerator provided by an embodiment of the present invention is applied to a near-memory computing system based on the RISC-V instruction set architecture. The dynamic fusion accelerator is configured to perform arithmetic and logical operations using a hardware reuse strategy. The dynamic fusion accelerator includes a mode switching mechanism module 10, an array clock 20, and at least one group of dynamic fusion processing units 30. The dynamic fusion accelerator is also configured to use the mode switching mechanism to enable the computational path of at least one group of dynamic fusion processing units 30 to be replaced, and to synchronize the clock signal using the array clock 20; the mode switching mechanism module 10 is configured to adaptively configure the mode switching mechanism; and the output of the dynamic fusion accelerator is transmitted to other units via a shared bus. The dynamic fusion accelerator provided by an embodiment of the present invention adopts a hierarchical dynamic switching mechanism to achieve hardware component reuse. The switching mechanism of the dynamic fusion processing unit 30 provides an alternative computational path for the neural sublayer. Furthermore, the clock enable signal and the runtime condition array control each DF-PE column to ensure reliable data management.

[0048] Furthermore, embodiments of the present invention also include a near-memory computing system based on the RISC-V instruction set architecture, comprising a near-memory architecture instruction set module, an instruction set model module, an energy-efficient instruction path module, and a storage-computation integration module, all based on software and hardware collaboration. The near-memory architecture instruction set module is configured to integrate opcode configurations and operating mechanisms into each instruction in the RISC-V instruction set, enabling the dedicated instruction set to implement corresponding execution control. The instruction set model module is configured to employ an instruction orchestration method that maps neural network layer structures, minimizing the number of instructions through loop instructions to support iteration. The energy-efficient instruction path module is configured to ensure that the dedicated instruction set follows the instruction path for sequential execution of each stage. The storage-computation integration module is configured to dynamically switch the computation path based on instruction requirements by integrating storage and computation. Embodiments of the present invention provide a customized RISC-V ISA for NMC systems to achieve energy-efficient neural network inference. The dedicated near-memory architecture instruction set provided by embodiments of the present invention is a dedicated instruction set based on opcode configurations and operating mechanisms. Furthermore, the opcode configuration assigns RISC-V-compatible opcodes and defines the configuration of accelerators, processing units, and arithmetic and logic instructions. Using this opcode configuration, three working mechanisms suitable for multiple precision neural network inference instructions were quickly defined and optimized. The embodiment of the present invention is based on the instruction set model of the neural network layer and utilizes the unique characteristics inherent in the neural network model. The neural hierarchical ISA model consists of three modules: layer feature extraction, instruction synthesis, and dynamic instruction coordination. These modules adjust instruction parameters according to the inherent characteristics of the neural layer at runtime. For energy-efficient instruction paths, the embodiment of the present invention constructs a three-stage sequential execution pipeline to manage the instruction flow. The instruction fetch-decode stage determines the decoding path of the instruction. In addition, the loop instruction stores the predefined decoded instructions to optimize subsequent processing. Then, the execution and write-back stages efficiently execute instructions and support efficient arithmetic and logical operations.

[0049] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0050] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0051] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0052] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0053] In a typical configuration, a computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0054] The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0055] Computer-readable media includes both permanent and non-permanent, removable and non-removable media that can be implemented using any method or technology to store information. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change RAM (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media such as modulated data signals and carrier waves.

[0056] It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements but also other elements not explicitly listed, or includes elements inherent to such process, method, commodity, or apparatus. In the absence of further limitations, an element defined by the phrase "comprises a ..." does not exclude the presence of other identical elements in the process, method, commodity, or apparatus that includes the element.

[0057] The above are merely embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application should all be included within the scope of the claims of the present application.

Claims

1. A dynamic fusion accelerator, characterized in that: The dynamic fusion accelerator is applied to a near-memory computing system based on the RISC-V instruction set architecture. The dynamic fusion accelerator is configured to perform arithmetic and logical operations using a hardware multiplexing strategy. The dynamic fusion accelerator includes a mode switching mechanism module, an array clock, and at least one group of dynamic fusion processing units. The dynamic fusion accelerator is further configured to utilize the mode switching mechanism of the mode switching mechanism module to enable the computation path of the at least one group of dynamic fusion processing units to be replaced, and utilize the array clock to synchronize the clock signal. The mode switching mechanism module is configured to adaptively configure the mode switching mechanism, The output of the dynamic fusion accelerator is transmitted to other units via a shared bus. The mode switching mechanism is a dual-mode switching mechanism, and the mode switching mechanism module is further configured to utilize the dual-mode switching mechanism to reconfigure the computational path, thereby supporting multiple computational paradigms across neural layers. For the first mode switching mechanism, a runtime first condition signal is used to switch between basic multiplication and other arithmetic operations. The arithmetic operation receives two operands with a bit width of BW and generates a result with a bit width of 2*BW or BW+1. The second mode switching mechanism is controlled by the second condition signal and performs subtraction and division operations by reusing existing addition and multiplication units, thereby achieving reuse of hardware components.

2. The dynamic fusion accelerator according to claim 1, characterized in that: The dynamic fusion accelerator is further configured to perform parameter transformation based on the PyTorch deep learning framework, wherein the parameter transformation includes reciprocal generation and symbol mapping. During the parameter transformation process, retain N decimal places to ensure calculation accuracy.

3. The dynamic fusion accelerator according to claim 1, characterized in that: The dynamic fusion accelerator is configured to perform arithmetic logic operations using a hardware multiplexing strategy, including: During the initialization of the register array, parameter transformations from the PyTorch deep learning framework are stored to enable dynamic reconfiguration of the computation path. When the first condition signal is at a high level, the at least one group of dynamic fusion processing units performs a multiplication operation, When the first condition signal is at a low level, the at least one group of dynamic fusion processing units enters a hardware component reuse mode. The hardware component reuse pattern dynamically activates dual computation paths and adaptively maps to computation paths in neural network inference.

4. The dynamic fusion accelerator according to claim 3, characterized in that: The dynamic fusion accelerator is configured to perform arithmetic and logical operations using a hardware multiplexing strategy and further includes: When the second condition signal is at a high level, the first calculation path is enabled to perform multiplication and addition operations. When the second condition signal is at a low level, the second calculation path is enabled to use multiplication and addition to calculate, and to perform subtraction and division operations, Temporary results generated by the first calculation path and the second calculation path are stored in a partition buffer.

5. The dynamic fusion accelerator according to claim 1, characterized in that: The array clock is further configured to generate a clock gating signal for activating or deactivating the at least one group of dynamic fusion processing units. When the clock gating signal is at a low level, the computing operation is suspended, thereby eliminating static power consumption. The at least one group of dynamic fusion processing units partitions the clock gating signal, the first condition signal, and the second condition signal to each dynamic fusion processing unit, so that independent access is achieved within one cycle.

6. The dynamic fusion accelerator according to claim 1, characterized in that: The two operands with a bit width of BW, the first condition signal, and the second condition signal are used to control each dynamic fusion processing unit and manage a hierarchical dynamic switching mechanism.

7. The dynamic fusion accelerator according to claim 6, characterized in that: In the loading stage, according to the neural sublayer loop, the array composed of the first conditional signal and the second conditional signal is obtained, and the array composed of the two operands with a bit width of BW is loaded according to the number of the at least one group of dynamic fusion processing units.

8. The dynamic fusion accelerator according to claim 1, characterized in that: The near-memory computing system based on the RISC-V instruction set architecture includes a near-memory architecture instruction set module based on software and hardware collaboration, an instruction set model module, an energy-efficient instruction path module, and a storage and computing integration module. The near memory architecture instruction set module is configured to integrate opcode configuration and operation mechanism into each instruction of the RISC-V instruction set so that the dedicated instruction set can realize corresponding execution control. The instruction set model module is configured to adopt an instruction arrangement method of neural network layer structure mapping, and minimize the number of instructions through loop instructions to support the iterative process. The energy-efficient instruction path module is configured as a dedicated instruction set that follows an instruction path for sequentially executing each stage. The storage and computing integration module includes a storage component and the dynamic fusion accelerator. The storage and computing integration module is configured to dynamically switch the computing path according to instruction requirements by fusing storage and computing.

9. The dynamic fusion accelerator according to claim 8, characterized in that: The instruction set model module includes an instruction set model based on a neural network layer, and expands and arranges dynamic fusion processing units based on the size of the neural network convolution kernel of the instruction set model.

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