Repackaging Method and Repackaging Structure of Encapsulated Chips

Abstract

The present invention discloses a re-packaging method and a re-packaging structure for a packaged chip. The re-packaging method includes: providing a packaged chip, where the packaged chip includes a target chip located within a package body and having test PADs, and at least a first region corresponding to the test PADs of the target chip is provided on the surface of the package body; etching the package body located in the first region until the test PADs of the target chip are exposed; corroding the package body located in the first region until the test PADs of the target chip are exposed; disposing test patches on a second region on the surface of the package body, where the second region is different from the first region; forming bonding wires between the test PADs of the target chip and the test patches; and filling a packaging material within the first region. The re-packaging method and the re-packaging structure for the packaged chip of the present invention can greatly improve the test efficiency and success rate of the packaged chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of chip packaging, and in particular relates to a repackaging method and a repackaging structure of a packaged chip. Background Art

[0002] With the development of integrated circuits, packaging forms are also changing with each passing day, extending from single die (chip / die) packaging to multi-die packaging, but with it comes the problem of multi-die compatibility. In the multi-die packaging process, from the engineering batch stage to the mass production stage and then to the later use stage, compatibility issues always exist.

[0003] In the existing multi-die packaging structure, the test PADs of some dies are not wired after packaging. After a problem occurs in the packaging structure, it is impossible to directly perform functional testing, and the only way is to remove the die and repackage it for functional testing. However, removing the die is a destructive experiment, which may cause irreversible damage to the die during the operation, thereby causing the abnormal phenomenon to disappear or change.

[0004] The information disclosed in this background technology section is only intended to enhance the understanding of the overall background of the invention and should not be regarded as an acknowledgment or any form of suggestion that the information constitutes the prior art already known to a person skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a repackaging method and a repackaging structure for a packaged chip, which can greatly improve the testing efficiency and success rate of the packaged chip.

[0006] In order to achieve the above object, a technical solution provided by a specific embodiment of the present invention is as follows:

[0007] A repackaging method for a packaged chip, suitable for functional testing, the repackaging method comprising:

[0008] Providing a packaged chip, the packaged chip comprising a target chip located in a package body and having a test PAD, wherein a surface of the package body has at least a first area corresponding to the test PAD of the target chip;

[0009] Etching the package body located in the first area until a test PAD of the target chip is displayed;

[0010] Corroding the package located in the first area until the test PAD of the target chip is exposed;

[0011] Disposing the test patch in a second area on the surface of the package body, the second area being different from the first area;

[0012] forming a bonding wire between the test PAD of the target chip and the test patch;

[0013] Fill the encapsulation material in the first region and cure it.

[0014] In one or more embodiments of the present invention, etching the encapsulation body located in the first region to expose the test PAD of the target chip includes:

[0015] Adopt a laser etching process to perform partial etching on the encapsulation body located in the first region in the thickness direction until the test PAD of the target chip located below can be observed by the naked eye, and the encapsulation body above the test PAD of the target chip is not etched through during the etching process.

[0016] In one or more embodiments of the present invention, the laser power in the laser etching process is 4W - 6W.

[0017] In one or more embodiments of the present invention, etching the encapsulation body located in the first region to expose the test PAD of the target chip includes:

[0018] Use a de-encapsulation solvent to etch the remaining encapsulation body above the test PAD of the target chip corresponding to the first region until the encapsulation body above the test PAD of the target chip is completely etched away, exposing the test PAD of the target chip.

[0019] In one or more embodiments of the present invention, use a dropper to suck the de-encapsulation solvent and drop it onto the encapsulation body above the test PAD of the target chip corresponding to the first region.

[0020] In one or more embodiments of the present invention, setting the test patch on the second region of the surface of the encapsulation body includes:

[0021] Use an insulating adhesive to paste the test patch on the second region of the surface of the encapsulation body;

[0022] Cure the insulating adhesive to fix the test patch.

[0023] In one or more embodiments of the present invention, the curing temperature is 140°C - 150°C, and the curing time is 20min - 30min.

[0024] In one or more embodiments of the present invention, keep the temperature of the encapsulated chip at 120°C - 180°C during the etching process; and / or,

[0025] The distance between the second region and the first region is 1mm - 2mm.

[0026] In one or more embodiments of the present invention, during the process of forming a bonding wire between the test PAD of the target chip and the test patch, the bonding wire diameter is controlled to be 0.6 mil - 0.8 mil, the bonding ultrasonic current is 120 mAmps - 130 mAmps, and the arc height is 7 mil - 8 mil.

[0027] In one or more embodiments of the present invention, after the step of forming a bonding wire between the test PAD of the target chip and the test patch, it further includes:

[0028] The step of using an optical microscope to observe and confirm that the bonding wire is successfully bonded to both the test PAD of the target chip and the test patch and the sample is intact.

[0029] In one or more embodiments of the present invention, filling the encapsulation material in the first region includes:

[0030] Dropping the encapsulation material into the first region by means of dispensing or filling;

[0031] The encapsulation material covers the bonding wire; and / or, the encapsulation material is 0.5 mm - 2 mm higher than the highest point of the bonding wire;

[0032] Curing the encapsulation material.

[0033] In one or more embodiments of the present invention, the curing time is 25 min - 30 min.

[0034] A repackaging structure of an encapsulated chip, which is encapsulated by the above-mentioned repackaging method of an encapsulated chip.

[0035] Compared with the prior art, the repackaging method of the encapsulated chip of the present invention repackages the encapsulated chip by opening a part of the region of the encapsulated chip to expose the test PAD of the target chip and wire-bonding it to the test patch arranged on the surface of the encapsulated chip, so that the repackaged encapsulated chip is suitable for functional testing, with safe, efficient testing and cost savings, and can greatly improve the testing efficiency and success rate.

[0036] The repackaging method of the encapsulated chip of the present invention leads out the test PAD of the target chip by wire-bonding for functional testing. First, the test PAD of the target chip is exposed by means of laser etching and chemical reagent corrosion; then, the test patch is fixed on the surface of the encapsulated chip; then, wire-bonding is carried out between the test PAD and the test patch; finally, the exposed area is backfilled to repackage the encapsulated chip. The repackaging structure can be used for subsequent testing.

[0037] The repackaging method of the packaged chip of the present invention has a wide range of applications and can be applied to all packaged chips in the form of stacked dies or single dies. Moreover, the steps are simple, easy to operate, have a high success rate, and low cost. Description of the Drawings

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments recorded in the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0039] Figure 1 It is a process flow chart of the repackaging method of the packaged chip in an embodiment of the present invention. Detailed Embodiments

[0040] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present invention.

[0041] As Figure 1 shown, the repackaging method of the packaged chip in an embodiment of the present invention includes the following steps:

[0042] S1. Provide a packaged chip, where the packaged chip includes a target chip located in the package body and having test PADs, and at least a first area corresponding to the test PADs of the target chip is on the surface of the package body.

[0043] S2. Etch the package body located in the first area until the test PADs of the target chip are shown.

[0044] S3. Corrode the package body located in the first area until the test PADs of the target chip are exposed.

[0045] S4. Set the test patch on the second area on the surface of the package body, and the second area is different from the first area.

[0046] S5. Form bonding wires between the test PADs of the target chip and the test patch.

[0047] S6. Fill the package material in the first area and cure it.

[0048] It can be understood that if the packaged chip is a stacked die (chip / die) packaging structure, the target chip with test PADs is usually located at the top layer of multiple stacked chips. If the packaged chip is a single die packaging structure, the chip inside it is the target chip with test PADs.

[0049] In step S1, the position of the test PADs of the target chip inside the packaged chip can be located by X-ray, and the first area corresponding to the test PADs of the target chip on the surface of the package body located above the test PADs of the target chip can be defined according to the located position. The device for positioning the position can include an X-ray non-destructive testing device.

[0050] It can be understood that X-Ray Positioning refers to the technology of using the penetrability and imaging characteristics of X-rays to accurately determine the position of internal targets of objects or the human body. Currently, it is widely used in fields such as medical treatment, industrial inspection, and security inspection. The core of X-ray positioning is to achieve accurate mapping of spatial coordinates through imaging and geometric calculations, and its accuracy depends on the device (such as CT vs. ordinary X-ray machines) and algorithm support. X-ray positioning is already a mature technology, and this application does not elaborate on it in detail.

[0051] In step S1, the range of the first area should be smaller than the range of the surface of the packaged chip to which it belongs, and there should be a spacing of 4 mm - 5 mm between the edge of the first area and any edge of the surface of the packaged chip to which it belongs, facilitating subsequent setting of test patches on the surface of the packaged chip. In the thickness direction of the packaged chip, the range where the first area is located covers the test PADs of the target chip.

[0052] In step S2, a laser etching process can be used to partially etch the package body in the thickness direction located in the first area. The laser etching process does not need to etch through the package body located above the test PADs of the target chip, and the initial etching is until the test PADs of the target chip located below can be observed by the naked eye. That is, after the laser etching is completed, a thin layer of the package body still remains above the test PADs of the target chip. This design can protect the test PADs of the target chip and prevent the laser from damaging the test PADs of the target chip during the laser etching process. Preferably, the laser power in the laser etching process is 20% - 30% of the maximum power of the laser device; for example, if the maximum power of the laser device is about 20 W, then the laser power in the laser etching process is 4 W - 6 W.

[0053] The package body on the packaged chip can be epoxy resin, silica gel, etc.

[0054] In step S3, a dropper is used to suck the de-encapsulation solvent and drop it onto the encapsulation body that has been laser-etched above the test PAD of the target chip corresponding to the first region, to corrode the remaining encapsulation body above the test PAD of the target chip corresponding to the first region until the encapsulation body above the test PAD of the target chip is completely corroded away, exposing the test PAD of the target chip. During the corrosion process, by heating, the temperature of the encapsulated chip is always maintained at 120°C - 180°C. For example, it can be 120°C, 130°C, 140°C, 150°C, 160°C, 170°C or 180°C, etc., and preferably 150°C.

[0055] It can be understood that the de-encapsulation solvent is a chemical reagent used to dissolve or soften the encapsulation body of electronic components (such as epoxy resin, silica gel, etc.) in order to expose the internal structure of the encapsulated chip. If the material of the encapsulation body is epoxy resin, typical de-encapsulation solvents include: fuming nitric acid (HNO3) and concentrated sulfuric acid (H2SO4). Fuming nitric acid will rapidly corrode epoxy resin at high temperature (~180°C). Concentrated sulfuric acid can corrode epoxy resin above 200°C. If the material of the encapsulation body is silica gel or soft encapsulation glue, typical de-encapsulation solvents include: dimethyl sulfoxide (DMSO) and N-methylpyrrolidone (NMP). Dimethyl sulfoxide (DMSO) can gently dissolve silica gel under heating (~150°C) conditions. N-methylpyrrolidone (NMP) has selective solubility for epoxy resin.

[0056] The de-encapsulation solvent in this embodiment is a reagent formulated according to the material of the bonding wire. This de-encapsulation solvent has no corrosive effect on the target chip, the test PAD thereon, and the bonding wire, and will not cause damage to the target chip, the test PAD thereon, and the bonding wire.

[0057] In step S4, an insulating adhesive can be used to paste the test patch on the second region on the surface of the encapsulation body. The second region should be different from the first region, and preferably, the distance between the edge of the second region and the edge of the first region is 1 mm - 2 mm. After pasting, the insulating adhesive is heated and cured by a heating table to fix the test patch. Among them, the heating temperature is 140°C - 150°C. For example, it can be 140°C, 142°C, 144°C, 145°C, 147°C or 150°C, etc. The heating time is 20 min - 30 min. For example, it can be 20 min, 22 min, 24 min, 25 min, 27 min or 30 min, etc.

[0058] The test patch is preferably a conductive metal sheet, such as copper foil, aluminum foil, gold foil, silver foil, nickel foil or stainless steel foil, etc., and gold foil is preferred. The test patch is used to electrically lead out the test PAD of the target chip, so as to facilitate the testing of the functions of the target chip on the tester for the re-packaging structure. That is, the part of the test patch wire-bonded to the test PAD of the target chip will be re-packaged into the re-packaging structure in subsequent steps, while the rest of the test patch will be exposed outside the re-packaging structure. When the re-packaging structure is placed on the tester for testing the functions of the packaged chip, only the probing needle needs to contact the exposed test patch or wire-bond the exposed test patch to the test PCB board of the tester, and the function test of the target chip can be completed on the tester.

[0059] The insulating glue in this embodiment is a colloid that needs to be thermally cured. In other embodiments, the insulating glue can also be a colloid that does not require thermal curing.

[0060] It can be understood that in other embodiments, the test patch can also be arranged in the second area on the surface of the package body in other ways. For example, it can be welded, or fixed with an insulating curing glue, or directly placed on the surface of the package body and later fixed by partial covering with a plastic encapsulation material, etc. Among them, the present invention does not have special limitations on the type and specific composition of the insulating curing glue, and any curing glue well-known to those skilled in the art that can be used to fix the test patch and has insulating properties can be adopted. The components of the insulating curing glue can include a base material, a filler, a curing agent and an auxiliary agent. The present invention does not have special limitations on the base material, filler, curing agent and auxiliary agent in the insulating curing glue, and any base material, filler, curing agent and auxiliary agent well-known to those skilled in the art that can be used in the insulating curing glue can be adopted.

[0061] In step S5, the bond wire diameter is set to be 0.6 mil - 0.8 mil, the bond ultrasonic current is 120 mAmps - 130 mAmps, and the arc height is 7 mil - 8 mil, and wire bonding is carried out between the test PAD of the target chip and the test patch. It can be understood that the parameters required in the bonding process and the specific wire bonding method can be adjusted according to actual needs. After the bonding is completed, it is also necessary to observe with an optical microscope whether there is any cracking or poor soldering around the test PAD to confirm that the bond wire is successfully bonded to both the test PAD of the target chip and the test patch and the sample is intact.

[0062] In step S6, the encapsulated chip after wire bonding is placed on a heating stage, and the heating temperature is set to 100°C - 150°C. For example, it can be 100°C, 110°C, 120°C, 130°C, 140°C, 150°C, etc. Preferably, it is 125°C, and the heating time is 1 min - 2 min. For example, it can be 1 min, 1.2 min, 1.4 min, 1.5 min, 1.7 min, 2 min, etc. Then, encapsulating material is dropped into the opened first area by means of dispensing or filling, etc., and the encapsulating material is cured to complete the re - encapsulation of the encapsulated chip. Among them, the encapsulating material can be epoxy resin, silicone (silica gel), polyurethane (PU), acrylic resin, etc. The curing time is 25 min - 30 min. For example, it can be 25 min, 26 min, 27 min, 28 min, 29 min, 30 min, etc. The encapsulating material should cover the bonding wires, and / or, the encapsulating material is 0.5 mm - 2 mm higher than the highest point of the bonding wires.

[0063] An embodiment of the present invention also provides a re - encapsulated structure encapsulated by the above - mentioned re - encapsulation method of the encapsulated chip.

[0064] The following further describes the present invention with specific embodiments.

[0065] Embodiment 1:

[0066] 1. Open the lid of the encapsulation part of the encapsulated chip.

[0067] Take the encapsulated chip that needs to have its lid opened and place it on a laser machine. Laser - etch the encapsulation body through the test PAD position of the target chip inside the encapsulated chip located by X - ray until the test PAD of the target chip is seen. Among them, the laser power is 20% - 30% of the laser machine.

[0068] Drop the prepared de - encapsulation solvent (reagent proportioned according to the material of the bonding wires) onto the laser - opened position with a dropper and heat the encapsulated chip to 150°C, and continue to corrode the remaining encapsulation body inside the laser - opened position until the test PAD of the target chip is completely exposed, ensuring that the surface of the target chip is clean and undamaged.

[0069] 2. Curing.

[0070] Paste a metal sheet on the encapsulation body with insulating glue. The bonding position of the metal sheet is about 1 mm - 2 mm away from the laser - opened position. Place the whole on a heating stage, set the heating temperature to about 140°C - 150°C, and heat for 20 min - 30 min to cure the insulating glue and fix the metal sheet.

[0071] 3. Wire bonding.

[0072] Place the encapsulated chip with a metal sheet on the encapsulation machine table, and set the parameters of the encapsulation machine table. Bonding wire diameter: 0.6 mil - 0.8 mil; Bonding ultrasonic current (USG Current): 120 mAmps - 130 mAmps; Loop height: 7 mil - 8 mil. After setting the parameters, wire bond according to requirements.

[0073] 4. Observe.

[0074] Use an optical microscope to observe whether the wire bonding of the sample after wire bonding is intact, and test whether there is cracking or poor soldering around the PAD. After observing that the sample is intact, proceed to the next step of dispensing.

[0075] 5. Dispense and cure.

[0076] Place the sample on the heating machine table, set the heating temperature to 125 °C, wait for 1 min - 2 min, then drop the encapsulation material into the laser opening position until the encapsulation material covers the wire bonding position and is about 1 mm higher. Finally, place it on the heating table for 25 min - 30 min for curing to complete the re-encapsulation of the encapsulated chip.

[0077] Compared with the prior art, the method for re-encapsulating an encapsulated chip of the present invention re-encapsulates the encapsulated chip by opening a partial area of the encapsulated chip to expose the test PAD of the target chip and wire bonding it to the test patch provided on the surface of the encapsulated chip, so that the re-encapsulated encapsulated chip is suitable for functional testing, with safe, efficient testing and cost savings, and can greatly improve the testing efficiency and success rate.

[0078] The method for re-encapsulating an encapsulated chip of the present invention leads out the test PAD of the target chip by wire bonding for functional testing. First, the test PAD of the target chip is exposed by means of laser etching and chemical reagent corrosion; then, the test patch is fixed on the surface of the encapsulated chip; then, wire bonding is carried out between the test PAD and the test patch; finally, the exposed area is backfilled to re-encapsulate the encapsulated chip. The re-encapsulation structure can be used for subsequent testing.

[0079] The method for re-encapsulating an encapsulated chip of the present invention has a wide range of applications, can be applied to all encapsulated chips in the form of stacked die or single die encapsulation, and has simple steps, is easy to operate, has a high success rate, and low cost.

[0080] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

[0081] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A re-packaging method for packaged chips, applicable to functional testing, characterized in that, The re - encapsulation method includes: Providing a packaged chip, where the packaged chip includes a target chip located within a package body and having test PADs, and at least a first region corresponding to the test PADs of the target chip is on the surface of the package body; Etching the package body in the first region until the test PADs of the target chip are shown; Corroding the package body in the first region until the test PADs of the target chip are exposed; Setting a test patch on a second region on the surface of the package body, where the second region is different from the first region; Forming bonding wires between the test PADs of the target chip and the test patch; Filling and curing a packaging material within the first region.

2. The repackaging method of the packaged chip according to claim 1, wherein Etching the package body in the first region until the test PADs of the target chip are shown, including: Using a laser etching process to perform partial etching in the thickness direction on the package body in the first region until the test PADs of the target chip below can be observed by the naked eye, and the package body above the test PADs of the target chip is not etched through during the etching process.

3. The repackaging method of the packaged chip according to claim 2, wherein The laser power in the laser etching process is 4W - 6W.

4. The repackaging method of the encapsulated chip according to claim 1, wherein Corroding the package body in the first region until the test PADs of the target chip are exposed, including: Using a de - encapsulation solvent to corrode the remaining package body above the test PADs of the target chip corresponding to the first region until the package body above the test PADs of the target chip is completely corroded and the test PADs of the target chip are exposed.

5. The repackaging method of the encapsulated chip according to claim 4, wherein Using a dropper to suck the de - encapsulation solvent and drop it onto the package body above the test PADs of the target chip corresponding to the first region.

6. The repackaging method of the packaged chip according to claim 1, wherein Setting the test patch on the second region on the surface of the package body, including: Using an insulating adhesive to paste the test patch on the second region on the surface of the package body; Curing the insulating adhesive to fix the test patch.

7. The repackaging method of the packaged chip according to claim 6, wherein The curing temperature is 140℃ - 150℃, and the curing time is 20min - 30min.

8. The repackaging method of the packaged chip according to claim 1, characterized in that, During the corrosion process, the temperature of the packaged chip is maintained at 120℃ - 180℃; and / or, The distance between the second region and the first region is 1mm - 2mm.

9. The repackaging method of the packaged chip according to claim 1, wherein During the process of forming bonding wires between the test PADs of the target chip and the test patch, control the bonding wire diameter to be 0.6mil - 0.8mil, the bonding ultrasonic current to be 120mAmps - 130mAmps, and the arc height to be 7mil - 8mil.

10. The method for repackaging a packaged chip according to claim 1, characterized in that, After the step of forming bonding wires between the test PADs of the target chip and the test patch, it further includes: The step of observing with an optical microscope to confirm that the bonding wires are successfully bonded to both the test PADs of the target chip and the test patch and the sample is intact.

11. The repackaging method of the packaged chip according to claim 1, characterized in that, Filling the packaging material within the first region, including: Dropping the packaging material into the first region by means of dispensing or filling; The packaging material covers the bonding wires, and / or, the packaging material is 0.5mm - 2mm higher than the highest point of the bonding wires; Curing the packaging material.

12. A repackaging structure for encapsulating a chip, characterized in that, It is encapsulated by using the re - encapsulation method of the packaged chip as described in any one of claims 1 - 11.

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