Power supply topology circuit for high-conversion-ratio direct-current level converter and control method

Abstract

The invention discloses a power supply topology circuit for a high-conversion-ratio DC level converter and a control method. The circuit comprises a conversion ratio increasing structure, a voltage stress halving structure, a power inductor and an output capacitor. The method comprises the steps of obtaining a control signal and an input voltage signal; on the basis of a control signal, boosting processing is carried out on an input voltage signal, inductance magnetizing processing is carried out on a power inductor, and an output capacitor supplies power to an output load end; and based on the control signal, inductance demagnetization processing is performed on the power inductor, and power is supplied to the output load end through the inductive current. According to the embodiment of the invention, a higher voltage conversion ratio and higher conversion efficiency can be realized under a lower duty ratio. The method can be widely applied to the technical field of integrated circuit design.

Description

Technical Field

[0001] This application relates to the technical field of integrated circuit design, and particularly to a power supply topology circuit and a control method for a high conversion ratio DC level converter. Background Art

[0002] In the design of a boost DC level converter, a high voltage conversion ratio (CR, the ratio of the output voltage to the input voltage) will bring many difficulties to the design, including higher voltage and current stress, higher requirements for passive devices, etc., thus limiting the conversion efficiency of the level converter.

[0003] In summary, the technical problems existing in the related art need to be improved. Summary of the Invention

[0004] The main purpose of the embodiments of this application is to propose a power supply topology circuit and a control method for a high conversion ratio DC level converter, which can achieve a higher voltage conversion ratio and a higher conversion efficiency at a lower duty cycle.

[0005] To achieve the above object, on the one hand, an embodiment of this application proposes a power supply topology circuit for a high conversion ratio DC level converter. The circuit includes a conversion ratio boosting structure, a voltage stress halving structure, a power inductor, and an output capacitor. The output end of the conversion ratio boosting structure is connected to the input end of the power inductor, the output end of the power inductor is connected to the input end of the voltage stress halving structure, and the output end of the voltage stress halving structure is connected to the input end of the output capacitor, where:

[0006] The conversion ratio boosting structure is used to perform voltage conversion ratio boosting processing on the input voltage signal to obtain a boosted voltage signal;

[0007] The voltage stress halving structure is used to reduce the voltage stress on the power switch tube;

[0008] The power inductor is used to transmit the boosted voltage signal to the voltage stress halving structure;

[0009] The output capacitor is used to smoothly output the boosted voltage signal.

[0010] In some embodiments, the turns ratio boosting structure includes a first power switch, a second power switch, a third power switch, and a first flying capacitor. The first end of the first power switch is connected to the first end of the third power switch and connected to a high level. The second end of the first power switch, the first end of the first flying capacitor, the first end of the second power switch, and the voltage stress halving structure are connected to a first node. The second end of the third power switch, the second end of the first flying capacitor, and the power inductor are connected to a second node. The second end of the second power switch is grounded.

[0011] In some embodiments, the voltage stress halving structure includes a fourth power switch, a fifth power switch, a sixth power switch, a seventh power switch, a second flying capacitor, and a third flying capacitor. The first end of the second flying capacitor is connected to the turns ratio boosting structure. The second end of the second flying capacitor, the first end of the fourth power switch, and the first end of the sixth power switch are connected to a fourth node. The second end of the fourth power switch, the first end of the fifth power switch, the first end of the third flying capacitor, and the power inductor are connected to a third node. The second end of the third flying capacitor, the second end of the sixth power switch, and the first end of the seventh power switch are connected to a fifth node. The second end of the fifth power switch is grounded. The second end of the seventh power switch is connected to the output capacitor.

[0012] In some embodiments, the first end of the power inductor is connected to the turns ratio boosting structure, and the second end of the power inductor is connected to the voltage stress halving structure.

[0013] In some embodiments, the first end of the output capacitor is connected to the voltage stress halving structure, and the second end of the output capacitor is grounded.

[0014] To achieve the above object, on the other hand, an embodiment of the present application proposes a control method for a power supply topology circuit of a high turns ratio DC level converter. The method includes the following steps:

[0015] Obtain a control signal and an input voltage signal;

[0016] Based on the control signal, boost the input voltage signal and perform inductor magnetization on the power inductor, and the output capacitor supplies power to the output load terminal;

[0017] Based on the control signal, perform inductor demagnetization on the power inductor, and supply power to the output load terminal through the inductor current.

[0018] In some embodiments, during the stage of inductor magnetization processing, the first power switch, the fifth power switch, and the sixth power switch are all in the closed state, the second power switch, the third power switch, the fourth power switch, and the seventh power switch are all in the open state. The second end of the power inductor is grounded through the fifth power switch, the first node is connected to the input voltage signal through the first power switch, the terminal voltage of the first flying capacitor is set to the input voltage, and the terminal voltage of the second node is raised to twice the input voltage to magnetize the power inductor.

[0019] In some embodiments, during the stage of inductor magnetization processing, it further includes that the second flying capacitor and the third flying capacitor are connected in series through the first power switch, the fifth power switch, and the sixth power switch for charge redistribution, and the charge of the second flying capacitor flows to the third flying capacitor.

[0020] In some embodiments, during the stage of inductor demagnetization processing, the second power switch, the third power switch, the fourth power switch, and the seventh power switch are all in the closed state, the first power switch, the fifth power switch, and the sixth power switch are all in the open state. The first end of the power inductor is connected to the input voltage signal through the third power switch, and the first flying capacitor is connected to the input voltage signal through the second power switch and the third power switch.

[0021] In some embodiments, during the stage of inductor demagnetization processing, it further includes that the first flow direction of the inductor current charges the second flying capacitor through the second power switch and the fourth power switch, and the second flow direction of the inductor current supplies power to the output load terminal through the seventh power switch and the third flying capacitor.

[0022] The embodiments of the present application at least include the following beneficial effects: The present application provides a power supply topology circuit and a control method for a high conversion ratio DC level converter. This solution performs voltage conversion ratio boosting processing on the input voltage signal through a conversion ratio boosting structure, can achieve a higher voltage conversion ratio at a lower duty cycle, brings a smaller inductor current ripple, and allows a larger switching frequency. Furthermore, it reduces the voltage stress on the power switch through a voltage stress halving structure, which enables the voltage stress on the power switch to only bear half of the output voltage stress, so that a lower voltage switch can be used in this topology, effectively improving the conversion efficiency of the system. Finally, a power inductor and an output capacitor are introduced, adopting a hybrid structure of inductor and capacitor, making full use of the advantages brought by different structures, and being able to achieve a higher conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1It is a schematic structural diagram of a power topology circuit for a high-ratio DC level converter provided by an embodiment of the present application;

[0024] Figure 2 It is a schematic step flow diagram of a control method for a power topology circuit of a high-ratio DC level converter provided by an embodiment of the present application;

[0025] Figure 3 It is a schematic working process diagram of a power topology provided by an embodiment of the present application;

[0026] Figure 4 It is a schematic topology diagram of the magnetization stage provided by an embodiment of the present application;

[0027] Figure 5 It is a schematic topology diagram of the demagnetization stage provided by an embodiment of the present application;

[0028] Figure 6 It is a schematic structural diagram of a power stage circuit of a topology provided by an embodiment of the present application;

[0029] Figure 7 It is a schematic structural diagram of a controller and a driver provided by an embodiment of the present application. Detailed implementation manners

[0030] In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.

[0031] It can be understood that the terms "first", "second", etc. used in the present application can be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information can also be referred to as the second information, and similarly, the second information can also be referred to as the first information. Depending on the context, the words "if", "when" as used herein can be interpreted as "when...", "while...", or "in response to determining".

[0032] As used in this application, terms such as "at least one", "a plurality", "each", "any one", etc., "at least one" includes one, two or more, "a plurality" includes two or more, "each" refers to each one of the corresponding plurality, and "any one" refers to any one of the plurality.

[0033] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used herein are for the purpose of describing embodiments of this application only and are not intended to limit this application.

[0034] First of all, it should be noted that in order to improve the performance of the converter in high-voltage and large turns-ratio scenarios, the power topology of the hybrid architecture has many advantages. By combining the advantages of the switch capacitor converter and the inductive converter, and taking advantage of the higher design freedom of the hybrid architecture, the embodiments of the present invention propose a power topology of the hybrid architecture suitable for high-voltage and large turns-ratio application scenarios to achieve higher energy conversion efficiency.

[0035] In the related art, there are the following deficiencies:

[0036] 1) In high-voltage and large turns-ratio scenarios, the voltage stress on the switching devices is very high, and high-voltage devices with poor quality factor and high breakdown voltage have to be used, which increases the conduction loss and drive loss of the switching devices.

[0037] 2) According to the law of conservation of energy, V IN *I IN =V OUT *I OUT , so when the output is high voltage and the input is low voltage, there will be a large input current on the input side, which increases the overall heat dissipation on the path.

[0038] 3) Under pulse width modulation (PWM), the output voltage modulation of the converter depends on changing the duty cycle D, that is, D and CR are positively correlated. Therefore, in order to achieve a high conversion ratio, traditional converters have to use extreme duty cycles (D>0.9), and such a large duty cycle brings difficulties to the design of the controller and driver, makes it more difficult to control the dead time, and limits the further increase of the switching frequency.

[0039] Based on this, the embodiments of the present invention provide a power topology of the hybrid architecture suitable for high-voltage and large turns-ratio application scenarios to achieve higher energy conversion efficiency.

[0040] Referring to Figure 1 , Figure 1Schematic diagram of a power topology circuit for a high conversion ratio DC level converter provided by an embodiment of the present invention. Refer to Figure 1 , the circuit includes a conversion ratio boosting structure, a voltage stress halving structure, a power inductor and an output capacitor. The output end of the conversion ratio boosting structure is connected to the input end of the power inductor, the output end of the power inductor is connected to the input end of the voltage stress halving structure, and the output end of the voltage stress halving structure is connected to the input end of the output capacitor, where:

[0041] The conversion ratio boosting structure is used to perform voltage conversion ratio boosting processing on the input voltage signal to obtain a boosted voltage signal;

[0042] Specifically, the conversion ratio boosting structure includes a first power switch tube S 1 , a second power switch tube S 2 , a third power switch tube S 3 and a first flying capacitor C F1 . The first end of the first power switch tube is connected to the first end of the third power switch tube and connected to a high level. The second end of the first power switch tube, the first end of the first flying capacitor, and the first end of the second power switch tube are connected to the voltage stress halving structure at a first node V SW1 . The second end of the third power switch tube and the second end of the first flying capacitor are connected to the power inductor at a second node V SW2 , and the second end of the second power switch tube is grounded.

[0043] In this embodiment, on the input side, the first power switch tube S 1 , the second power switch tube S 2 , the third power switch tube S 3 and the first flying capacitor C F1 constitute a conversion ratio boosting structure, and its working mode is similar to that of a 1:2 charge pump. The input voltage is equivalently increased by using a switched capacitor, so that the entire power topology obtains a higher voltage conversion ratio (Conversion ratio, CR).

[0044] The voltage stress halving structure is used to reduce the voltage stress on the power switch tube;

[0045] Specifically, the voltage stress halving structure includes a fourth power switch tube S 4 , a fifth power switch tube S 5 , a sixth power switch tube S 6 , a seventh power switch tube S 7 , a second flying capacitor C F2 and a third flying capacitor C F3 . The first end of the second flying capacitor is connected to the conversion ratio boosting structure. The second end of the second flying capacitor, the first end of the fourth power switch tube, and the first end of the sixth power switch tube are connected at a fourth node V SW4, the second terminal of the fourth power switch, the first terminal of the fifth power switch, the first terminal of the third flying capacitor are connected to the power inductor and connected to the third node V SW3 , the second terminal of the third flying capacitor, the second terminal of the sixth power switch and the first terminal of the seventh power switch are connected to the fifth node V SW5 , the second terminal of the fifth power switch is grounded, and the second terminal of the seventh power switch is connected to the output capacitor.

[0046] In this embodiment, on the output side, the fourth power switch S 4 , the fifth power switch S 5 , the sixth power switch S 6 , the seventh power switch S 7 , the second flying capacitor C F2 and the third flying capacitor C F3 constitute a halved voltage stress structure (HVS), using the switched capacitor to bear a part of the output voltage, thereby reducing the stress on the switches and the inductor caused by the output voltage.

[0047] The power inductor is used to transmit the boosted voltage signal to the halved voltage stress structure;

[0048] Specifically, the first terminal of the power inductor is connected to the turns ratio boosting structure, and the second terminal of the power inductor is connected to the halved voltage stress structure.

[0049] The output capacitor C OUT is used to smooth the boosted output voltage signal.

[0050] Specifically, the first terminal of the output capacitor is connected to the halved voltage stress structure, and the second terminal of the output capacitor is grounded.

[0051] Please refer to Figure 2 , the embodiment of the present application also provides a control method for the power supply topology circuit of a high turns ratio DC level converter, which can implement the above-mentioned power supply topology circuit for a high turns ratio DC level converter. The method includes the following steps:

[0052] S100. Obtain a control signal and an input voltage signal;

[0053] In some specific embodiments, the power topology of the present invention is divided into two stages according to the different switch closing states and inductor states, namely the inductor magnetizing stage and the inductor demagnetizing stage. As Figure 3 shown, the control signal is a periodic signal, and the proposed power topology alternately operates in these two states according to the control signal.

[0054] S200. Based on the control signal, boost the input voltage signal and magnetize the power inductor, and the output capacitor supplies power to the output load terminal;

[0055] In some specific embodiments, during the stage of magnetizing the inductor, the first power switch, the fifth power switch, and the sixth power switch are all in the closed state, the second power switch, the third power switch, the fourth power switch, and the seventh power switch are all in the open state, the second end of the power inductor is grounded through the fifth power switch, the first node is connected to the input voltage signal through the first power switch, the terminal voltage of the first flying capacitor is set to the input voltage, the terminal voltage of the second node is boosted to twice the input voltage to magnetize the power inductor, and the second flying capacitor and the third flying capacitor are connected in series through the first power switch, the fifth power switch, and the sixth power switch for charge redistribution, and the charge of the second flying capacitor flows to the third flying capacitor.

[0056] In this embodiment, as Figure 4 shown, during this stage, the first power switch, the fifth power switch, and the sixth power switch are closed, the right side of the inductor is grounded through the fifth power switch, and the first node V SW1 is connected to the input voltage through the first power switch. Since the voltage across the first flying capacitor is set to V IN during the demagnetization stage, the voltage of the second node V SW2 is boosted to 2V IN to magnetize the inductor.

[0057] At the same time, on the output side, the second flying capacitor and the third flying capacitor are connected in series through the first power switch, the fifth power switch, and the sixth power switch. At this time, the two capacitors perform charge redistribution, and the charge is transferred from the second flying capacitor to the third flying capacitor to replenish the charge of the third flying capacitor.

[0058] During this stage, since the seventh power switch remains open, the output capacitor C OUT supplies power to the output load.

[0059] S300. Based on the control signal, perform inductor demagnetization on the power inductor, and supply power to the output load terminal through the inductor current;

[0060] In some specific embodiments, during the stage of inductor demagnetization processing, the second power switch, the third power switch, the fourth power switch, and the seventh power switch are all in the closed state, the first power switch, the fifth power switch, and the sixth power switch are all in the open state. The first end of the power inductor is connected to the input voltage signal through the third power switch, and the first flying capacitor is connected to the input voltage signal through the second power switch and the third power switch. The first flow direction of the inductor current charges the second flying capacitor through the second power switch and the fourth power switch, and the second flow direction of the inductor current supplies power to the output load terminal through the seventh power switch and the third flying capacitor.

[0061] In this embodiment, as Figure 5 shown, during this stage, the second power switch, the third power switch, the fourth power switch, and the seventh power switch are closed, and the remaining switches are open. The right side of the inductor is connected to the input voltage through the third power switch. At the same time, the first flying capacitor is connected to the input voltage through the second power switch and the third power switch. Therefore, the voltage across the first flying capacitor is set to V IN .

[0062] On the output side, there are two paths for the inductor current. The first path is to charge the second flying capacitor through the second power switch and the fourth power switch, and the second path is to supply power to the output through the seventh power switch and the third flying capacitor. Due to the existence of the third flying capacitor, a part of the high voltage on the C OUT capacitor on the output side is isolated. Therefore, the voltage stress on the fifth power switch and the sixth power switch is greatly reduced.

[0063] Finally, it should also be elaborated that, as Figure 6 shown, this is the implementation of the power stage circuit of the topology of the embodiment of the present invention. The power switch, the controller, and the driver are all integrated on a silicon wafer by integrated circuit technology. The topology structure of the power stage is the same as above, including the first power switch S 1 , the second power switch S 2 , the third power switch S 3 , the fourth power switch S 4 , the fifth power switch S 5 , the sixth power switch S 6 , the seventh power switch S 7 , the first flying capacitor C F1 , the second flying capacitor C F2 , the third flying capacitor C F3 , the output capacitor C OUT , and a power inductor, where the first power switch S 1 , the second power switch S 2 , the third power switch S 3 , the fourth power switch S4 5. The fifth power switch tube S 5 6. The sixth power switch tube S 6 and the seventh power switch tube S 7 are all implemented using MOS transistors, supplemented by corresponding drivers. The driver for each switch includes a bootstrap capacitor C BST and a buffer. Further, in addition to the power stage, as Figure 7 shown, in order to achieve the normal operation of the proposed power supply topology, a controller structure includes: a feedback network, a compensator, a comparator, a dead zone control logic, a level shifter, a drive circuit, etc.

[0064] In summary, the embodiments of the present invention have the following advantages compared with the prior art:

[0065] 1) The proposed topology structure adopts a hybrid structure of inductors and capacitors, making full use of the advantages brought by different structures, and can achieve higher conversion efficiency.

[0066] 2) Due to the application of the output-side switching capacitors C F2 and C F3 , part of the high output voltage on the output capacitor C OUT is borne by the switching capacitors C F2 and C F3 . This enables the voltage stress on the power switch to only withstand half of the output voltage stress. Thus, switches with a lower voltage can be used in this topology, which can effectively improve the conversion efficiency of the system.

[0067] 3) The conversion ratio (CR) of the proposed converter is (3 + D) / (1 - D), making it 3 to 4 times larger than that of traditional boost converters. This characteristic helps to achieve a higher V OUT / V IN at a lower duty cycle. For example, when CR = 10, D = 0.64, instead of D = 0.9 in traditional boost converters. This results in a smaller inductor current ripple (ΔI L ) and allows for a larger switching frequency (F SW ).

[0068] 4) The proposed power topology uses switching capacitors to redesign the magnetizing and demagnetizing voltages of the inductor, resulting in a shorter charging time and a longer discharging time, and more time to transfer the inductor current to the output terminal. This leads to a lower inductor current under the same load, thus significantly reducing the Joule heat dissipation on the path and improving the conversion efficiency. At the same conversion ratio, the inductor current can be reduced to half of the original.

[0069] It can be understood that the content in the above method embodiments is applicable to the system embodiments of the present application. The functions specifically implemented by the system embodiments of the present application are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those of the above method embodiments.

[0070] The preferred embodiments of the embodiments of the present application have been described above with reference to the accompanying drawings. However, this does not limit the scope of the rights of the embodiments of the present application. Any modifications, equivalent replacements, and improvements made by those skilled in the art without departing from the scope and essence of the embodiments of the present application shall fall within the scope of the rights of the embodiments of the present application.

Claims

1. A power topology circuit for a high-conversion ratio DC level converter, characterized in that: The circuit includes a conversion ratio improvement structure, a voltage stress halving structure, a power inductor and an output capacitor, wherein the output end of the conversion ratio improvement structure is connected to the input end of the power inductor, the output end of the power inductor is connected to the input end of the voltage stress halving structure, and the output end of the voltage stress halving structure is connected to the input end of the output capacitor, wherein: The conversion ratio boosting structure is used to perform voltage conversion ratio boosting processing on the input voltage signal to obtain a boosted voltage signal; The voltage stress halving structure is used to reduce the voltage stress on the power switch tube; The power inductor is used to transmit the boosted voltage signal to the voltage stress halving structure; The output capacitor is used to smoothly output the boosted voltage signal.

2. The circuit according to claim 1, characterized in that The conversion ratio improvement structure includes a first power switch tube, a second power switch tube, a third power switch tube and a first flying capacitor, the first end of the first power switch tube is connected to the first end of the third power switch tube and connected to a high level, the second end of the first power switch tube, the first end of the first flying capacitor, the first end of the second power switch tube and the voltage stress half reduction structure are connected to a first node, the second end of the third power switch tube, the second end of the first flying capacitor and the power inductor are connected to a second node, and the second end of the second power switch tube is grounded.

3. The circuit according to claim 1, characterized in that The voltage stress halving structure includes a fourth power switch tube, a fifth power switch tube, a sixth power switch tube, a seventh power switch tube, a second flying capacitor and a third flying capacitor, wherein a first end of the second flying capacitor is connected to the conversion ratio improvement structure, a second end of the second flying capacitor, a first end of the fourth power switch tube and a first end of the sixth power switch tube are connected to a fourth node, a second end of the fourth power switch tube, a first end of the fifth power switch tube and a first end of the third flying capacitor are connected to a third node with the power inductor, a second end of the third flying capacitor, a second end of the sixth power switch tube and a first end of the seventh power switch tube are connected to a fifth node, a second end of the fifth power switch tube is grounded, and a second end of the seventh power switch tube is connected to the output capacitor.

4. The circuit according to claim 1, characterized in that The first end of the power inductor is connected to the conversion ratio improvement structure, and the second end of the power inductor is connected to the voltage stress half reduction structure.

5. The circuit according to claim 1, characterized in that A first end of the output capacitor is connected to the voltage stress half reduction structure, and a second end of the output capacitor is grounded.

6. A control method for a power topology circuit of a high-conversion ratio DC level converter, characterized in that: The method comprises the following steps: Obtaining control signals and input voltage signals; Based on the control signal, the input voltage signal is boosted and the power inductor is magnetized, and the output capacitor supplies power to the output load end; Based on the control signal, the power inductor is subjected to inductor demagnetization processing, and the output load end is powered by the inductor current.

7. The method according to claim 6, characterized in that During the inductor magnetization process, the first power switch tube, the fifth power switch tube and the sixth power switch tube are all in a closed state, the second power switch tube, the third power switch tube, the fourth power switch tube and the seventh power switch tube are all in a disconnected state, the second end of the power inductor is grounded through the fifth power switch tube, the first node is connected to the input voltage signal through the first power switch tube, the terminal voltage of the first flying capacitor is set to the input voltage, and the terminal voltage of the second node is increased to twice the input voltage to magnetize the power inductor.

8. The method according to claim 7, characterized in that The inductor magnetization processing stage also includes: the second flying capacitor and the third flying capacitor are connected in series through the first power switch tube, the fifth power switch tube and the sixth power switch tube to redistribute the charge, and the charge of the second flying capacitor flows to the third flying capacitor.

9. The method according to claim 7, characterized in that: During the inductor demagnetization process, the second power switch tube, the third power switch tube, the fourth power switch tube and the seventh power switch tube are all in a closed state, the first power switch tube, the fifth power switch tube and the sixth power switch tube are all in a disconnected state, the first end of the power inductor is connected to the input voltage signal through the third power switch tube, and the first flying capacitor is connected to the input voltage signal through the second power switch tube and the third power switch tube.

10. The method according to claim 9, characterized in that The stage of the inductor demagnetization processing also includes: the first flow direction of the inductor current charges the second flying capacitor through the second power switch tube and the fourth power switch tube, and the second flow direction of the inductor current supplies power to the output load end through the seventh power switch tube and the third flying capacitor.

Images