Bootstrap circuit and integrated chip
By designing an integrated bootloader circuit within the integrated chip, using switch control units and energy storage components to achieve boost output of high-end control signals, the problem of complex and costly bootloader circuit design in the prior art is solved, and the integrated high-voltage driving output is realized.
Patent Information
- Application Number
- CN202411957088.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-29
- Publication Date
- 2025-06-03
AI Technical Summary
The existing bootloader circuit design is on the periphery of the integrated chip, which makes the peripheral circuit design complex and costly, making it difficult to realize integrated high-voltage drive output.
A bootstrap circuit integrated into an integrated chip is designed, including a switch control unit and an energy storage element. The switch control unit controls the charging and discharging of the energy storage element according to the driving signal, and realizes the boost output of the high-end control signal.
The integrated high-voltage drive output is realized, reducing the complexity and cost of peripheral circuits and ensuring the normal output of high-end control signals.
Smart Images
Figure CN120090611A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of integrated circuit technology, and particularly to a bootstrap circuit and an integrated chip. Background Art
[0002] With the development of industrial level and science and technology, the speed of replacement of power electronic products is getting faster and faster, and people's requirements for performance are also getting higher and higher. Among them, as an important part of today's monolithic integrated intelligent power drive chips, high-voltage drive signals often need to cooperate with a bootstrap circuit to boost and output. However, conventional bootstrap circuits are generally designed on the periphery of the integrated chip, resulting in complex design of the peripheral circuit and increased cost. Therefore, it is of great significance to design a bootstrap circuit applied to an integrated chip. Summary of the Invention
[0003] In view of the deficiencies of the above-mentioned prior art, the purpose of the present invention is to provide a bootstrap circuit and an integrated chip, which are mainly applied to the high-voltage drive output of the integrated chip, can achieve integration, and reduce costs.
[0004] To achieve the above purpose, the present invention adopts the following technical solutions:
[0005] A bootstrap circuit, the bootstrap circuit is powered by a bus voltage VB and a power supply voltage VCC, the bootstrap circuit is connected to a drive signal terminal HIN and a control signal terminal HO, the bootstrap circuit includes a switch control unit and an energy storage element, the drive signal terminal HIN is used to output a high-side drive signal, the control signal terminal HO is used to output a high-side control signal, the switch control unit receives the high-side drive signal and controls the charging and discharging of the energy storage element, the switch control unit is connected to the control signal terminal HO, and the energy storage element is used to boost the high-side control signal.
[0006] In the bootstrap circuit, the switch control unit includes a field effect transistor M1, a field effect transistor M2, a field effect transistor M3, a field effect transistor M4, and a resistor R1. The channel types of the field effect transistor M3 and the field effect transistor M4 are opposite. The drive signal terminal HIN is respectively connected to the gates of the field effect transistor M3 and the field effect transistor M4. The bus voltage VB is successively connected to the floating ground VS through the source and drain of the field effect transistor M3 and the source and drain of the field effect transistor M4. The bus voltage VB is connected to the gate of the field effect transistor M1 through the source and drain of the field effect transistor M3. The bus voltage VB is successively connected to the floating ground VS through the resistor R1 and the source and drain of the field effect transistor M1. The gate of the field effect transistor M2 is connected to the end of the resistor R1 far from the bus voltage VB. The bus voltage VB is connected to the control signal terminal HO through the source and drain of the field effect transistor M2. The sources and drains of the field effect transistor M1, the field effect transistor M2, the field effect transistor M3, and the field effect transistor M4 are all connected in the forward direction. The bus voltage VB is connected to the power supply voltage VCC, and the bus voltage VB is connected to the floating ground VS through an energy storage element.
[0007] In the bootstrap circuit, the channel types of the field effect transistor M3, the field effect transistor M1, and the field effect transistor M2 are the same.
[0008] In the bootstrap circuit, an inverting unit is further included. The inverting unit inverts the high-end drive signal output from the drive signal terminal HIN and outputs it to the switch control unit.
[0009] In the bootstrap circuit, the inverting unit includes an upper inverting unit and a lower inverting unit. Both the upper inverting unit and the lower inverting unit are provided with an input terminal, an output terminal, a power supply terminal, and a ground terminal. The input terminals of the upper inverting unit and the lower inverting unit are both connected to the drive signal terminal HIN. The output terminal of the upper inverting unit is connected to the gate of the field effect transistor M3. The output terminal of the lower inverting unit is connected to the gate of the field effect transistor M4. The power supply terminals of the upper inverting unit and the lower inverting unit are both connected to the bus voltage VB. The ground terminals of the upper inverting unit and the lower inverting unit are both connected to the floating ground VS.
[0010] In the bootstrap circuit, both the upper inverting unit and the lower inverting unit include at least one group of inverters. The number of inverters in the upper inverting unit and the lower inverting unit satisfies the same parity. The inverter is a CMOS inverter composed of an NMOS transistor and a PMOS transistor.
[0011] In the bootstrap circuit, both the upper inverting unit and the lower inverting unit include an even number of groups of inverters. The channel types of the field effect transistor M3, the field effect transistor M1, and the field effect transistor M2 are the same.
[0012] In the bootstrap circuit, the upper inverter unit and the lower inverter unit both include an odd number of inverter stages, and the field effect transistor M4 has the same channel type as the field effect transistors M1 and M2.
[0013] In the bootstrap circuit, the power supply voltage VCC is connected to the bus voltage VB through the diode D1. The positive electrode of the diode D1 is connected to the power supply voltage VCC, and its negative electrode is connected to the bus voltage VB.
[0014] In the bootstrap circuit, the energy storage element is set as a capacitor.
[0015] In the bootstrap circuit, the energy storage element is set as an inductor.
[0016] The bootstrap circuit further includes a field effect transistor M5. The gate of the field effect transistor M5 is connected to the control signal terminal HO, its drain is connected to the bus voltage VB, and its source is connected to the floating ground VS.
[0017] This application also provides an integrated chip, which includes the above-mentioned bootstrap circuit, high-side drive output circuit, low-side drive output circuit, input interface circuit, drive signal terminal HIN, drive signal terminal LIN, control signal terminal HO, and control signal terminal LO. The input interface circuit is used to filter the high-side drive signal input from the drive signal terminal HIN and the low-side drive signal input from the drive signal terminal LIN, and output the high-side drive signal to the high-side drive output circuit and the low-side drive signal to the low-side drive output circuit. The high-side drive output circuit outputs a high-side control signal to the control signal terminal HO through the bootstrap circuit, and the low-side drive output circuit outputs a low-side control signal to the control signal terminal LO. The bootstrap circuit is used to boost the high-side control signal.
[0018] In the integrated chip, a dead-time control circuit is further included. The input interface circuit is connected to the high-side drive output circuit and the low-side drive output circuit respectively through the dead-time control circuit.
[0019] In the integrated chip, a field effect transistor M6 is further included. The gate of the field effect transistor M6 is connected to the control signal terminal LO, its drain is connected to the floating ground VS, and its source is grounded.
[0020] Beneficial effects:
[0021] The present invention provides a bootstrap circuit and an integrated chip. The switch control unit can control the charging and discharging of the energy storage element according to the level change of the high-side driving signal output from the driving signal terminal HIN. When the high-side control signal needs to be output from the control signal terminal HO, the energy storage element discharges to boost the voltage of the high-side control signal, so as to enable the normal output of the high-side control signal, and the bootstrap circuit is used in the integrated chip. Description of the Drawings
[0022] Figure 1 It is the first embodiment of the bootstrap circuit provided by the present invention;
[0023] Figure 2 It is the second embodiment of the bootstrap circuit provided by the present invention;
[0024] Figure 3 It is the third embodiment of the bootstrap circuit provided by the present invention;
[0025] Figure 4 It is the fourth embodiment of the bootstrap circuit provided by the present invention;
[0026] Figure 5 It is the topological structure diagram of the integrated chip provided by the present invention.
[0027] Description of the main component symbols: 1 - bootstrap circuit, 11 - switch control unit, 12 - energy storage element, 13 - inverter unit, 131 - upper inverter unit, 132 - lower inverter unit, 133 - inverter, 2 - high-side drive output circuit, 3 - low-side drive output circuit, 4 - input interface circuit, 5 - dead-time control circuit. Detailed Embodiments
[0028] The present invention provides a bootstrap circuit and an integrated chip. To make the purpose, technical solution and effects of the present invention clearer and more definite, the following further describes the present invention in detail with reference to the accompanying drawings and by way of examples. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.
[0029] In the description of the present invention, it should be understood that the terms "first", "second", "third" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features.
[0030] Please refer to Figure 1, this application provides a bootstrap circuit. The bootstrap circuit 1 is powered by a bus voltage VB and a power supply voltage VCC. The bootstrap circuit 1 is connected to a drive signal terminal HIN and a control signal terminal HO. The bootstrap circuit 1 includes a switch control unit 11 and an energy storage element 12. The drive signal terminal HIN is used to output a high-side drive signal, and the control signal terminal HO is used to output a high-side control signal. The switch control unit 11 receives the high-side drive signal and controls the charge and discharge of the energy storage element 12. The switch control unit 11 is connected to the control signal terminal HO, and the energy storage element 12 is used to boost the high-side control signal.
[0031] It should be noted that the drive signal terminal HIN is the input terminal of the high-side drive signal of the integrated chip, the control signal terminal HO is the output terminal of the high-side control signal of the integrated chip, the bus voltage VB is the voltage of the high-voltage terminal in the integrated chip, and the power supply voltage VCC is the voltage provided by the external power supply of the integrated chip. Therefore, in the bootstrap circuit 1 provided by this application, the switch control unit 11 boosts the high-side control signal output from the control signal terminal HO of the integrated chip based on the level change of the high-side drive signal over time, that is, the timing change of the signal, and the state of the energy storage element 12 also switches between charging and discharging.
[0032] Please refer to Figure 1 , specifically, the switch control unit 11 includes a field effect transistor M1, a field effect transistor M2, a field effect transistor M3, a field effect transistor M4, and a resistor R1. The channel types of the field effect transistor M3 and the field effect transistor M4 are opposite. The drive signal terminal HIN is respectively connected to the gates of the field effect transistor M3 and the field effect transistor M4. The bus voltage VB is connected to the floating ground VS through the source and drain of the field effect transistor M3 and the source and drain of the field effect transistor M4 in sequence. The bus voltage VB is connected to the gate of the field effect transistor M1 through the source and drain of the field effect transistor M3. The bus voltage VB is connected to the floating ground VS through the resistor R1 and the source and drain of the field effect transistor M1 in sequence. The gate of the field effect transistor M2 is connected to the end of the resistor R1 far from the bus voltage VB. The bus voltage VB is connected to the control signal terminal HO through the source and drain of the field effect transistor M2. The sources and drains of the field effect transistor M1, the field effect transistor M2, the field effect transistor M3, and the field effect transistor M4 are all connected in the positive direction. The bus voltage VB is connected to the power supply voltage VCC. The bus voltage VB is connected to the floating ground VS through the energy storage element 12. It should be noted that the floating ground VS is a reference potential generated based on the integrated chip. Refer to Figure 3 、 Figure 4 It can be seen that the reference of the floating ground VS is based on the control signal terminal HO and the control signal terminal LO in the integrated chip.
[0033] Further, the channel types of the field effect transistor M3, the field effect transistor M1, and the field effect transistor M2 are the same.
[0034] Please refer to Figure 1 , and taking Embodiment 1 as an example, based on the design method of the above-mentioned switch control unit 11, if it is determined that the channel type of the field effect transistor M3 is a PMOS transistor, then the field effect transistor M4 is set as an NMOS transistor, and the field effect transistors M1 and M2 are both set as PMOS transistors. When a low level is input to the drive signal terminal HIN, the field effect transistor M3 is turned on, the field effect transistor M4 is turned off, the gate voltage of the field effect transistor M1 rises to the bus voltage VB, and the field effect transistor M1 is turned off. Similarly, the field effect transistor M2 is turned off, and the power supply voltage VCC charges the energy storage element 12, and the voltage difference is VCC. When a high level is input to the drive signal terminal HIN, the field effect transistor M3 is turned off, the field effect transistor M4 is turned on, the gate voltage of the field effect transistor M1 reaches the floating ground VS, the field effect transistor M1 is turned on, the field effect transistor M2 is turned on, and at the same time the energy storage element 12 discharges, raising the voltage of the control signal terminal HO. In an ideal state, the raised voltage is VB + VCC.
[0035] In addition, for those skilled in the art, based on the implementation manner of Embodiment 1, if it is determined that the channel type of the field effect transistor M3 is an NMOS transistor, then it can be confirmed that the field effect transistor M4 is set as a PMOS transistor, and the field effect transistors M1 and M2 are NMOS transistors. The level control principle is the same as above and will not be elaborated here.
[0036] Please refer to Figures 2 - 4 , the bootstrap circuit 1 further includes an inverting unit 13. The inverting unit 13 is added on the basis of the implementation manner of Embodiment 1. The inverting unit 13 performs inverting processing on the high-end drive signal output from the drive signal terminal HIN and outputs it to the switch control unit 11. Among them, the inverting unit 13 can amplify and filter the signal output from the drive signal terminal HIN, improving the reliability of this circuit.
[0037] Specifically, the inverting unit 13 includes an upper inverting unit 131 and a lower inverting unit 132. The upper inverting unit 131 and the lower inverting unit 132 are each provided with an input terminal, an output terminal, a power supply terminal, and a ground terminal. The input terminals of the upper inverting unit 131 and the lower inverting unit 132 are both connected to the drive signal terminal HIN. The output terminal of the upper inverting unit 131 is connected to the gate of the field effect transistor M3, and the output terminal of the lower inverting unit 132 is connected to the gate of the field effect transistor M4. The power supply terminals of the upper inverting unit 131 and the lower inverting unit 132 are both connected to the bus voltage VB, and the ground terminals of the upper inverting unit 131 and the lower inverting unit 132 are both connected to the floating ground VS. Based on the above circuit design, that is, the upper inverting unit 131 controls the switching of the field effect transistor M3, and the lower inverting unit 132 controls the switching of the field effect transistor M4, so as to realize the level control of the switching control unit 11.
[0038] Further, the upper inverting unit 131 and the lower inverting unit 132 each include at least one group of inverters 133. The number of inverters 133 in the upper inverting unit 131 and the lower inverting unit 132 satisfies the same parity, that is, the number of inverters 133 included in the upper inverting unit 131 and the number of inverters 133 included in the lower inverting unit 132 are both odd or both even. This setting can ensure that the levels of the signals processed by the upper inverting unit 131 and the lower inverting unit 132 after inverting are both high level or both low level. The inverter 133 is a CMOS inverter composed of an NMOS transistor and a PMOS transistor.
[0039] Please refer to Figure 2, in the second embodiment, preferably, the number of inverters 133 provided in the upper inverter unit 131 and the lower inverter unit 132 is the same, which is an even number, and both are set to two groups. The inverter 133 is a CMOS inverter composed of an NMOS transistor and a PMOS transistor. Specifically, the connection method of the two groups of inverters in the upper inverter unit 131 is as follows: the drive signal terminal HIN is respectively connected to the gates of the NMOS transistor and the PMOS transistor of the first group of inverters. The source of the NMOS transistor is connected to the bus voltage VB, and the source of the PMOS transistor is connected to the floating ground VS. The gates of the NMOS transistor and the PMOS transistor of the second group of inverters are connected together with the gates and drains of the NMOS transistor and the PMOS transistor of the first group of inverters. The source of the NMOS transistor of the second group of inverters is connected to the bus voltage VB, and the source of the PMOS transistor is connected to the floating ground VS. The gate of the field effect transistor M3 is respectively connected to the drains of the NMOS transistor and the PMOS transistor of the second group of inverters. Based on the above connection method, the signal passing through the upper inverter unit 131 undergoes two inversion processes, that is, when the input is a high level, the output is still a high level. Similarly, the connection method of the two groups of inverters in the lower inverter unit 132 is the same as that of the upper inverter unit 131. The two groups of inverters are also connected in series to control the field effect transistor M4.
[0040] Please refer to Figure 3 , in the third embodiment, the number of inverters 133 provided in the upper inverter unit 131 and the lower inverter unit 132 is the same, both are set to three groups, which is an odd number. When the level signal passes through the inverter unit 13, if the input is a high level, the output is a low level. Referring to the channel type setting method of the field effect transistors M1 - M4 in the reference switch control unit 11, those skilled in the art can change the channel types of the field effect transistors M1 - M4 in the implementation manner of the third embodiment to obtain Figure 4 the implementation manner of the fourth embodiment in
[0041] 1. When the upper inverter unit 131 and the lower inverter unit 132 are both provided with an even number of inverters 133, the channel types of the field effect transistor M3, the field effect transistor M1, and the field effect transistor M2 are the same.
[0042] 2. In the bootstrap circuit 1, when the upper inverter unit 131 and the lower inverter unit 132 are both provided with an odd number of inverters 133, the channel types of the field effect transistor M4, the field effect transistor M1, and the field effect transistor M2 are the same.
[0043] Based on the above embodiments 1 to 4, those skilled in the art can add several groups of inverters 133 to the implementation manner of the first embodiment and adjust the channel type settings of the field effect transistors M1 - M4, and the obtained implementation manners are all within the protection scope of this application.
[0044] Preferably, the power supply voltage VCC is connected to the bus voltage VB through a diode D1. The positive electrode of the diode D1 is connected to the power supply voltage VCC, and its negative electrode is connected to the bus voltage VB. The diode D1 plays a role of reverse cut-off to prevent the current generated when the energy storage element 12 discharges from flowing back to the power supply.
[0045] Preferably, the energy storage element 12 is set as a capacitor or an inductor. Considering that this circuit is integrated in a chip, the capacitor has a smaller volume and better energy storage effect compared to the inductor. Therefore, a capacitor is preferentially used as the energy storage element 12.
[0046] Preferably, in the bootstrap circuit 1, a field-effect transistor M5 is further included. The gate of the field-effect transistor M5 is connected to the control signal terminal HO, its drain is connected to the bus voltage VB, and its source is connected to the floating ground VS. The field-effect transistor M5 mainly plays an isolation role, reducing signal interference and improving the reliability of the chip.
[0047] Please refer to Figure 5 , this application also provides an integrated chip, including the bootstrap circuit 1, high-side drive output circuit 2, low-side drive output circuit 3, input interface circuit 4, drive signal terminal HIN, drive signal terminal LIN, control signal terminal HO, and control signal terminal LO as described above. The input interface circuit 4 is used to filter the high-side drive signal input from the drive signal terminal HIN and the low-side drive signal input from the drive signal terminal LIN, and output the high-side drive signal to the high-side drive output circuit 2 and the low-side drive signal to the low-side drive output circuit 3. The high-side drive output circuit 2 outputs a high-side control signal to the control signal terminal HO through the bootstrap circuit 1, the low-side drive output circuit 3 outputs a low-side control signal to the control signal terminal LO, and the bootstrap circuit 1 is used to boost the high-side control signal.
[0048] Furthermore, in the integrated chip, a dead-time control circuit 5 is further included. The input interface circuit 4 is respectively connected to the high-side drive output circuit 2 and the low-side drive output circuit 3 through the dead-time control circuit 5. When a signal enters the dead-time control circuit 5, a certain dead time will be generated between the high-side drive signal and the low-side drive signal to prevent the high-side and low-side related power devices driven in the chip from conducting simultaneously, resulting in a through short-circuit fault.
[0049] Preferably, please refer to Figure 3 , Figure 4, in the integrated chip, a field effect transistor M6 is further included. The gate of the field effect transistor M6 is connected to the control signal terminal LO, its drain is connected to the floating ground VS, and its source is grounded. It has the same function as the field effect transistor M5, also playing an isolation role, reducing signal interference, and improving the reliability of the chip.
[0050] It can be understood that for those of ordinary skill in the art, equivalent substitutions or changes can be made according to the technical solution of the present invention and its inventive concept, and all such changes or substitutions should fall within the protection scope of the claims appended to the present invention.
Claims
1. A bootstrap circuit, characterized in that: The bootstrap circuit is powered by a bus voltage VB and a power supply voltage VCC. The bootstrap circuit is connected to a drive signal terminal HIN and a control signal terminal HO. The bootstrap circuit includes a switch control unit and an energy storage element. The drive signal terminal HIN is used to output a high-end drive signal. The control signal terminal HO is used to output a high-end control signal. The switch control unit receives the high-end drive signal and controls the charging and discharging of the energy storage element. The switch control unit is connected to the control signal terminal HO. The energy storage element is used to boost the high-end control signal.
2. The bootstrap circuit according to claim 1, characterized in that The switch control unit includes a field effect tube M1, a field effect tube M2, a field effect tube M3, a field effect tube M4, and a resistor R1. The field effect tube M3 has a channel type opposite to that of the field effect tube M4. The drive signal terminal HIN is connected to the gate of the field effect tube M3 and the gate of the field effect tube M4 respectively. The bus voltage VB is connected to the floating ground VS successively through the source and drain of the field effect tube M3 and the source and drain of the field effect tube M4. The bus voltage VB is connected to the gate of the field effect tube M1 through the source and drain of the field effect tube M3. The bus voltage VB is connected to the floating ground VS through the resistor R1 and the source and drain of the field effect transistor M1 in sequence, the gate of the field effect transistor M2 is connected to the end of the resistor R1 away from the bus voltage VB, the bus voltage VB is connected to the control signal terminal HO through the source and drain of the field effect transistor M2, the source and drain of the field effect transistor M1, the field effect transistor M2, the field effect transistor M3, and the field effect transistor M4 are all positively connected, the bus voltage VB is connected to the power supply voltage VCC, and the bus voltage VB is connected to the floating ground VS through an energy storage element.
3. The bootstrap circuit according to claim 2, characterized in that: The channel type of the field effect transistor M3 is the same as that of the field effect transistor M1 and the field effect transistor M2.
4. The bootstrap circuit according to claim 2, characterized in that: It also includes an inverting unit, which inverts the high-end driving signal output by the driving signal terminal HIN and outputs the inverted signal to the switch control unit.
5. The bootstrap circuit according to claim 4, characterized in that: The inverting unit includes an upper inverting unit and a lower inverting unit. The upper inverting unit and the lower inverting unit are both provided with an input terminal, an output terminal, a power supply terminal, and a ground terminal. The input terminals of the upper inverting unit and the lower inverting unit are both connected to the driving signal terminal HIN, the output terminal of the upper inverting unit is connected to the gate of the field effect tube M3, the output terminal of the lower inverting unit is connected to the gate of the field effect tube M4, the power supply terminals of the upper inverting unit and the lower inverting unit are both connected to the bus voltage VB, and the ground terminals of the upper inverting unit and the lower inverting unit are both connected to the floating ground VS.
6. The bootstrap circuit according to claim 5, characterized in that: The upper inverting unit and the lower inverting unit each include at least one group of inverters. The numbers of inverters in the upper inverting unit and the lower inverting unit are the same odd and the same even. The inverters are CMOS inverters composed of NMOS tubes and PMOS tubes.
7. The bootstrap circuit according to claim 6, characterized in that: The upper inverting unit and the lower inverting unit both include an even number of inverters, and the field effect transistor M3 has the same channel type as the field effect transistor M1 and the field effect transistor M2.
8. The bootstrap circuit according to claim 6, characterized in that: The upper inverting unit and the lower inverting unit both include an odd-numbered array of inverters, and the field effect transistor M4 has the same channel type as the field effect transistor M1 and the field effect transistor M2.
9. The bootstrap circuit according to claim 2, characterized in that: The power supply voltage VCC is connected to the bus voltage VB through a diode D1 , wherein the anode of the diode D1 is connected to the power supply voltage VCC, and the cathode of the diode D1 is connected to the bus voltage VB.
10. The bootstrap circuit according to claim 1, characterized in that: The energy storage element is configured as a capacitor.
11. The bootstrap circuit according to claim 1, characterized in that: The energy storage element is configured as an inductor.
12. The bootstrap circuit according to claim 1, characterized in that: It also includes a field effect transistor M5, wherein the gate of the field effect transistor M5 is connected to the control signal terminal HO, the drain of the field effect transistor M5 is connected to the bus voltage VB, and the source of the field effect transistor M5 is connected to the floating ground VS.
13. An integrated chip, characterized in that: The invention comprises a bootstrap circuit as described in any one of claims 1 to 12, a high-side drive output circuit, a low-side drive output circuit, an input interface circuit, a drive signal terminal HIN, a drive signal terminal LIN, a control signal terminal HO, and a control signal terminal LO, wherein the input interface circuit is used to filter the high-end drive signal input from the drive signal terminal HIN and the low-end drive signal input from the drive signal terminal LIN, and output the high-end drive signal to the high-side drive output circuit and the low-end drive signal to the low-side drive output circuit, the high-side drive output circuit outputs a high-end control signal to the control signal terminal HO through the bootstrap circuit, and the low-side drive output circuit outputs a low-end control signal to the control signal terminal LO, and the bootstrap circuit is used to boost the high-end control signal.
14. The integrated chip according to claim 13, characterized in that: It also includes a dead zone control circuit, and the input interface circuit is connected to the high-side drive output circuit and the low-side drive output circuit respectively through the dead zone control circuit.
15. The integrated chip according to claim 14, characterized in that: It also includes a field effect transistor M6, wherein the gate of the field effect transistor M6 is connected to the control signal terminal LO, the drain of the field effect transistor M6 is connected to the floating ground VS, and the source of the field effect transistor M6 is grounded.