Low-noise readout circuit for medium-wave infrared detector and control method of low-noise readout circuit
By using a combination of cell-level circuit module, sampling and amplification circuit module and single-climbing column-level ADC module in the reading circuit of the mid-wave infrared detector, combined with relevant dual sampling technology and timing control, the problem of additional noise in the reading circuit is solved, and signal processing effect with lower noise and higher signal-to-noise ratio is achieved.
Patent Information
- Application Number
- CN202510161126.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-13
- Publication Date
- 2025-06-03
AI Technical Summary
There is a problem in the reading circuit of existing mid-wave infrared detectors that introduce additional noise in the circuit structure and timing design, which affects the signal-to-noise ratio and signal processing accuracy.
A low-noise reading circuit including a cell-level circuit module, a sampling and amplification circuit module and a single-climbing column-level ADC module is adopted. Fixed mode noise and low-frequency noise are effectively suppressed through related dual sampling technology and timing control.
The noise level of the entire readout circuit is reduced, the signal-to-noise ratio and signal processing accuracy is improved, and the noise introduced by the additional sampling capacitor is avoided.
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Abstract
Description
Technical Field
[0001] This application belongs to the field of readout circuits for infrared detectors, and particularly relates to a low-noise readout circuit for mid-wave infrared detectors and its control method. Background Art
[0002] Infrared detection technology can achieve all-weather detection during both day and night, has a wider spectral sensing range and stronger environmental adaptability, and can obtain richer background information and target information than visible light detectors. Therefore, it has been widely used in the aerospace and military fields. Its main applications include remote sensing reconnaissance, missile guidance, missile defense warning, individual soldier night vision systems, etc., to achieve combat goals such as rapid reconnaissance, missile warning, and real-time battlefield analysis. Infrared detectors have gone through three generations of development. Currently, the pixel scale of the third-generation high-performance cooled infrared focal plane detectors has reached the tens of millions level, and the output method is digital output. Therefore, based on the application requirements of all-weather detection of infrared detectors and the development of existing technologies, low background noise, digital output, and ultra-large area arrays have become the development directions of the readout circuits for the third-generation high-performance infrared detectors.
[0003] However, in the readout circuits of existing infrared detectors, the pixel-level circuit has a timing design that first outputs the pixel photoelectric signal and then outputs the pixel reset signal. Although the 1 / f noise of the pixel circuit can be eliminated through the correlated double sampling part, due to the non-correlation of the two sampling voltages, the sampling noise of the pixel circuit will double, which is not conducive to reducing the noise of the pixel circuit. In addition, in the readout circuit of mid-wave infrared detectors, after the PGA circuit is mostly used to achieve sampling and amplification, the two sampling voltage values are stored on two sampling capacitors, and quantization is completed through the ADC circuit in the next timing stage. Although the frame rate can be optimized, the sampling capacitors will introduce additional two sampling noises. Therefore, the existing readout circuits for mid-wave infrared detectors have problems of additional noise introduced by the circuit structure and timing design. Summary of the Invention
[0004] The purpose of the embodiments of this application is to provide a low-noise readout circuit for mid-wave infrared detectors and its control method, which solves the problem of additional noise introduced by the circuit structure and timing design in the readout circuit of mid-wave infrared detectors.
[0005] To achieve the above objective, this application adopts the following technical solutions: In a first aspect, a low-noise readout circuit for a mid-wave infrared detector includes a pixel-level circuit module, a sampling and amplification circuit module, and a single-slope column-level ADC module; The pixel-level circuit module is connected to an infrared detection device and is used for sampling the photoelectric signal generated by the infrared detection device; The sampling and amplifying circuit module is connected to the pixel-level circuit module, and is configured to sample and amplify the pixel reset signal and the optoelectronic signal output by the pixel-level circuit module; The single-slope column-level ADC module is connected to the sampling and amplifying circuit module, and is configured to quantify the analog voltage values output by the sampling and amplifying circuit module respectively during two sampling timing phases, and output the difference between the two quantified digital codes; Wherein, each infrared detection device in the full array corresponds to one of the pixel-level circuit modules, and each column of infrared detection devices in the full array corresponds to one of the sampling and amplifying circuit modules and one of the single-slope column-level ADC modules.
[0006] In a possible implementation manner, the pixel-level circuit module includes a first MOS transistor, a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a first capacitor, a second capacitor, and a first switch; The first MOS transistor and the first capacitor are serially coupled between the power supply terminal VDD and the ground terminal; The first MOS transistor and the first capacitor are connected to a first common node; The second MOS transistor and the second capacitor are serially coupled between the power supply terminal VDD and the ground terminal; The second MOS transistor and the second capacitor are connected to a second common node; The source terminal of the third MOS transistor is used to connect to an external infrared detection device, and the drain terminal of the third MOS transistor is connected to the first common node; Both ends of the first switch are respectively connected to the first common node and the second common node; The fourth MOS transistor, the fifth MOS transistor, and the sixth MOS transistor are serially coupled between the power supply terminal VDD and the ground terminal; The gate of the fourth MOS transistor is connected to the second common node, the source terminal of the fourth MOS transistor is connected to the drain terminal of the fifth MOS transistor, the source terminal of the fifth MOS transistor is connected to the drain terminal of the sixth MOS transistor, and the source terminal of the sixth MOS transistor is connected to the ground terminal; The source terminal of the fifth MOS transistor is connected to the input terminal of the sampling and amplifying circuit module.
[0007] In a possible implementation manner, the sampling and amplifying circuit module includes a single-stage amplifier, a third capacitor, a fourth capacitor, a second switch, a third switch, and a fourth switch; One end of the third capacitor is connected to the connection point of the fifth MOS transistor and the sixth MOS transistor, and the other end of the third capacitor is connected to the input end of the single-stage amplifier. The third capacitor and the single-stage amplifier are connected to a third common node; The output end of the single-stage amplifier is connected to the input end of the single-slope column-level ADC module. The output end of the single-stage amplifier and the input end of the single-slope column-level ADC module are connected to a fourth common node; One end of the second switch is connected to the third common node, and the other end is connected to the fourth common node; The third switch and the fourth switch are serially coupled between the fourth common node and the reference voltage Vref; One end of the fourth capacitor is connected to the third common node, and the other end is connected to the connection point of the third switch and the fourth switch.
[0008] In a possible implementation, the single-slope column-level ADC module includes a single-slope ADC and a fifth switch; One end of the fifth switch is connected to the fourth common node, and the other end is connected to the first input end of the single-slope ADC; The second input end of the single-slope ADC is connected to the ramp voltage ramp reference input signal Vramp, the third input end of the single-slope ADC is connected to the counter starting value Init, the fourth input end of the single-slope ADC is connected to the count control signal Sign, and the output end of the single-slope ADC is used to output a signal.
[0009] In a possible implementation, the first MOS transistor and the second MOS transistor both use NMOS transistors, and the first switch uses a complementary switch structure of an NMOS transistor and a PMOS transistor.
[0010] In a second aspect, a control method for a low-noise readout circuit for a mid-wave infrared detector includes the following steps: S1: The pixel-level circuit module resets the second capacitor through the second MOS transistor and outputs a pixel reset signal; S2: An optoelectronic signal is formed on the second capacitor through the first switch, and a pixel optoelectronic signal is output; S3: The sampling and amplifying circuit module samples and amplifies the pixel reset signal and the optoelectronic signal in sequence; S4: The single-slope column-level ADC module quantifies the analog voltage values output by the sampling and amplifying circuit module during two sampling timing stages respectively, and outputs the difference between the two quantized digital codes.
[0011] In a possible implementation, the specific steps include: At the first moment, the first MOS transistor is turned on, and after resetting the first capacitor, it is turned off; At the second moment, the third MOS transistor is turned on, and the optoelectronic signal is transferred and stored. The conduction duration of the third MOS transistor can be configured according to usage requirements. After completing the transfer and storage, the third MOS transistor is turned off; At the third moment, the fifth MOS transistor is turned on to select the pixel-level circuit module to be output; At the fourth moment, the second MOS transistor is turned on, and after resetting the second capacitor, it is turned off; At the fifth moment, the second switch, the fourth switch, and the fifth switch are turned on. After the output of the sampling and amplification circuit module is established, the second switch is turned off first, and then the fourth switch is turned off; At the sixth moment, after the third switch is turned on, the single-slope column-level ADC module inputs the ramp reference signal Vramp to perform analog-to-digital conversion on the reference voltage output by the first-stage sampling and amplification circuit module. After the conversion is completed, the fifth switch is turned off, and the input of the ramp reference signal Vramp returns to the starting voltage value; At the seventh moment, the first switch is turned on. After the optoelectronic signal is formed on the second capacitor, the first switch is turned off; At the eighth moment, the fifth switch is turned on again. The single-slope column-level ADC module inputs the ramp reference signal Vramp to perform analog-to-digital conversion on the voltage output by the second-stage sampling and amplification circuit module. After the conversion is completed, the fifth switch is turned off, and the input of the ramp reference signal Vramp returns to the starting voltage value; At the ninth moment, after the third switch is turned off, the fifth MOS transistor is turned off, completing the sampling, amplification, and analog-to-digital conversion processes of the selected pixel-level circuit module.
[0012] In a possible implementation manner, the capacitance values of the first capacitor and the second capacitor in the pixel-level circuit module are the same.
[0013] In a possible implementation manner, the single-stage amplifier in the sampling and amplification circuit module adopts a cascode single-stage amplifier structure.
[0014] In a possible implementation manner, the initial value Init of the counter in the single-slope column-level ADC module is the digital code corresponding to a negative value. The counting conditions of the counter in the two quantization processes are configured through the counting control signal Sign, so that the digital code output by the single-slope column-level ADC module is the difference between the digital codes output by the two quantizations.
[0015] Compared with the prior art, the present application has the following beneficial effects: A low-noise readout circuit for a mid-wave infrared detector provided by the present application. The pixel-level circuit module samples the optoelectronic signal generated by the infrared detection device to obtain a signal containing target information. The sampling and amplification circuit module samples and amplifies the pixel reset signal and the optoelectronic signal to enhance the signal strength for subsequent processing. The single-slope column-level ADC module quantifies the amplified analog voltage values in two sampling timing phases and outputs the difference, effectively suppressing the fixed pattern noise and low-frequency noise in the circuit through the correlated double sampling principle and reducing the noise level of the entire readout circuit.
[0016] In a possible implementation, the third capacitor is used to sample the signal output by the pixel-level circuit module, and the single-stage amplifier amplifies the sampled signal to increase the amplitude of the signal. The second switch plays a feedback role during the sampling process and can make the amplifier output quickly stable at a specific stage. The third switch and the fourth switch cooperate with the fourth capacitor to adjust the amplifier gain and introduce the reference voltage Vref by selecting different connection states, ensuring accurate sampling and amplification of the pixel reset signal and the optoelectronic signal in different working stages.
[0017] In a possible implementation, the fifth switch controls whether the analog voltage value output by the sampling and amplification circuit module is input to the single-slope ADC for quantization. The single-slope ADC quantifies the input analog voltage value according to the ramp reference input signal Vramp, the counter starting value Init, and the count control signal Sign. Through specific counting rules and starting value settings, the difference between the two quantization digital codes is output to achieve the conversion from analog signal to digital signal, and the common-mode noise and fixed bias in the circuit are further eliminated by using the difference output method.
[0018] In a possible implementation, the NMOS transistor has the advantages of fast switching speed and small on-resistance, and can efficiently complete the capacitor reset and signal transfer operations. The first switch adopts a complementary switch structure of NMOS and PMOS, combining the advantages of NMOS and PMOS transistors, reducing the on-resistance of the first switch, reducing the loss during signal transmission, and at the same time improving the anti-interference ability and reliability of the first switch, ensuring the stable operation of the pixel-level circuit module.
[0019] A control method for a low-noise readout circuit for a mid-wave infrared detector. First, the pixel-level circuit module outputs the pixel reset signal and the optoelectronic signal, then the sampling and amplification circuit module samples and amplifies these two signals, and finally the single-slope column-level ADC module performs quantization and outputs the difference. This orderly operation process realizes the complete processing of the infrared detection signal, effectively eliminates the pixel sampling noise through the correlated double sampling technology, and at the same time avoids the noise introduced by the additional sampling capacitor, improving the signal-to-noise ratio and signal processing accuracy of the readout circuit.
[0020] In a possible implementation, through precise timing control, the conduction and cutoff of each MOS transistor and switch are sequentially controlled at different times, realizing a series of operations such as the reset of the first capacitor and the second capacitor, the transfer and storage of the optoelectronic signal, the selection of the pixel-level circuit module, the sampling and amplification of the sampling and amplification circuit module, and the analog-to-digital conversion of the single-slope column-level ADC module. This timing control ensures that the entire readout circuit can accurately process the infrared detection signal according to the predetermined process, further optimizing the signal processing process, reducing the noise interference, and improving the performance and stability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 FIG. is a schematic diagram of the overall structure of a low-noise readout circuit for a mid-wave infrared detector provided by the present application; Figure 2 FIG. is a timing diagram of a control method for a low-noise readout circuit for a mid-wave infrared detector provided by the present application.
[0022] Reference numerals in the drawings: 101, pixel-level circuit module; 11, first MOS transistor; 12, second MOS transistor; 13, third MOS transistor; 14, first switch; 15, fifth MOS transistor; 16, fourth MOS transistor; 17, sixth MOS transistor; 18, first capacitor; 19, second capacitor; 102, sampling and amplification circuit module; 21, second switch; 22, third switch; 23, fourth switch; 24, third capacitor; 25, fourth capacitor; 26, single-stage amplifier; 103, single-slope column-level ADC module; 31, fifth switch; 32, single-slope ADC. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0023] The following further describes in detail the specific embodiments of the present application with reference to the accompanying drawings.
[0024] In a first aspect, as Figure 1 shown, a low-noise readout circuit for a mid-wave infrared detector according to the present application may include a pixel-level circuit module 101, a sampling and amplification circuit module 102, and a single-slope column-level ADC module 103.
[0025] The pixel-level circuit module 101 is connected to the infrared detection device and is used for sampling the optoelectronic signal generated by the infrared detection device. The pixel-level circuit module 101 adopts an integration-then-readout timing sequence.
[0026] The sampling and amplification circuit module 102 is connected to the pixel-level circuit module 101 and is used for sampling and amplifying the pixel reset signal and the optoelectronic signal output by the pixel-level circuit module 101.
[0027] The single-slope column-level ADC module 103 is connected to the sampling and amplification circuit module 102, and is used to quantize the analog voltage values output by the sampling and amplification circuit module 102 during two sampling timing phases, and output the difference between the two quantized digital codes.
[0028] Among them, each infrared detection device in the full array corresponds to a pixel-level circuit module 101, and each column of infrared detection devices in the full array corresponds to a sampling and amplification circuit module 102 and a single-slope column-level ADC module 103.
[0029] In the embodiment of the present application, the pixel-level circuit module 101 samples the optoelectronic signal generated by the infrared detection device to obtain a signal containing target information. The sampling and amplification circuit module 102 samples and amplifies the pixel reset signal and the optoelectronic signal to enhance the signal strength for subsequent processing. The single-slope column-level ADC module 103 quantizes the amplified analog voltage values during two sampling timing phases respectively, and outputs the difference, effectively suppressing the fixed pattern noise and low-frequency noise in the circuit through the correlated double sampling principle, and reducing the noise level of the entire readout circuit.
[0030] In a possible embodiment, the pixel-level circuit module 101 may include a first MOS transistor 11, a second MOS transistor 12, a third MOS transistor 13, a fourth MOS transistor 16, a fifth MOS transistor 15, a sixth MOS transistor 17, a first capacitor 18, a second capacitor 19, and a first switch 14.
[0031] The first MOS transistor 11 and the first capacitor 18 are serially coupled between the power supply terminal VDD and the ground terminal.
[0032] The first MOS transistor 11 and the first capacitor 18 are connected to a first common node.
[0033] Specifically, the first MOS transistor 11 is a reset control transistor.
[0034] The drain of the first MOS transistor 11 is connected to the power supply terminal VDD, and the source of the first MOS transistor 11 is connected to the upper plate of the first capacitor 18.
[0035] The lower plate of the first capacitor 18 is grounded, and the first capacitor 18 is a charge integration capacitor.
[0036] The second MOS transistor 12 and the second capacitor 19 are serially coupled between the power supply terminal VDD and the ground terminal.
[0037] The second MOS transistor 12 and the second capacitor 19 are connected to a second common node.
[0038] Specifically, the second MOS transistor is a reset control transistor, and the second capacitor 19 is a charge transfer capacitor.
[0039] The drain terminal of the second MOS transistor 12 is connected to the power supply terminal VDD, the source terminal of the second MOS transistor 12 is connected to the upper plate of the second capacitor 19, and the lower plate of the second capacitor 19 is connected to the ground terminal.
[0040] The source terminal of the third MOS transistor 13 is used to connect to an external infrared detection device, and the drain terminal of the third MOS transistor 13 is connected to the first common node.
[0041] The third MOS transistor 13 is an integration control transistor, and the optoelectronic signal generated by the external infrared detector is input to the source terminal of the third MOS transistor 13.
[0042] Both ends of the first switch 14 are respectively connected to the first common node and the second common node.
[0043] Specifically, the first switch 14 is a charge transfer control switch, and through the first switch 14, the conduction or disconnection of the first capacitor 18 and the second capacitor 19 can be controlled.
[0044] The fourth MOS transistor 16, the fifth MOS transistor 15, and the sixth MOS transistor 17 are serially coupled between the power supply terminal VDD and the ground terminal.
[0045] The drain of the fourth MOS transistor 16 is connected to the power supply terminal VDD, the gate of the fourth MOS transistor 16 is connected to the second common node, and the source of the fourth MOS transistor 16 is connected to the drain of the fifth MOS transistor 15.
[0046] The source of the fifth MOS transistor 15 is connected to the drain of the sixth MOS transistor 17, and the source of the sixth MOS transistor 17 is connected to the ground terminal.
[0047] The source of the fifth MOS transistor 15 is connected to the input terminal of the sampling and amplifying circuit module 102, and the fifth MOS transistor 15 outputs the output image position reset signal and optoelectronic signal to the sampling and amplifying circuit module 102.
[0048] Specifically, the fourth MOS transistor 16 is set as an NMOS transistor, the fifth MOS transistor 15 is a row selection control transistor, and the sixth MOS transistor 17 is an active load.
[0049] In an embodiment of the present application, the first MOS transistor 11 is used to reset the first capacitor 18 to prepare for storing the optoelectronic signal. When the third MOS transistor 13 is turned on, the optoelectronic signal generated by the external infrared detection device is transferred and stored on the first capacitor 18, and the second MOS transistor 12 resets the second capacitor 19. When the first switch 14 is turned on, the optoelectronic signal stored on the first capacitor 18 is transferred to the second capacitor 19. Through the source follower structure composed of the fourth MOS transistor 16, the fifth MOS transistor 15, and the sixth MOS transistor 17, the pixel reset signal and the optoelectronic signal on the second capacitor 19 are output in the form of a low output impedance, improving the signal driving ability and transmission stability, and at the same time realizing signal sampling and preprocessing at the pixel level.
[0050] In a possible embodiment, the sampling and amplifying circuit module 102 may include a single-stage amplifier 26, a third capacitor 24, a fourth capacitor 25, a second switch 21, a third switch 22, and a fourth switch 23.
[0051] One end of the third capacitor 24 is connected to the connection point of the fifth MOS transistor 15 and the sixth MOS transistor 17, and the other end of the third capacitor 24 is connected to the input end of the single-stage amplifier 26, and the third capacitor 24 and the single-stage amplifier 26 are connected at a third common node.
[0052] Optionally, the third capacitor 24 is a sampling capacitor, and the third capacitor 24 samples the pixel reset signal and the optoelectronic signal at the output end of the pixel-level circuit module 101.
[0053] The output end of the single-stage amplifier 26 is connected to the input end of the single-slope column-level ADC module 103, and the output end of the single-stage amplifier 26 and the input end of the single-slope column-level ADC module 103 are connected at a fourth common node.
[0054] Specifically, the single-stage amplifier 26 uses negative gain amplification.
[0055] One end of the second switch 21 is connected to the third common node, and the other end is connected to the fourth common node.
[0056] Optionally, the second switch 21 is a feedback switch, and the conduction or disconnection between the input end and the output end of the single-stage amplifier 26 can be controlled through the second switch 21.
[0057] The third switch 22 and the fourth switch 23 are serially coupled between the fourth common node and the reference voltage Vref.
[0058] One end of the third switch 22 is connected to the fourth common node, the other end is connected to the fourth switch 23, and the other end of the fourth switch 23 is connected to the reference voltage Vref.
[0059] One end of the fourth capacitor 25 is connected to the third common node, and the other end is connected to the connection between the third switch 22 and the fourth switch 23.
[0060] Optionally, the third switch 22 and the fourth switch 23 are gating switches, and the fourth capacitor 25 is an amplification capacitor. By configuring the capacitance ratio of the third capacitor 24 and the fourth capacitor 25, the amplification of the pixel output voltage response multiple can be achieved.
[0061] In the embodiment of the present application, the third capacitor 24 is used to sample the signal output by the pixel-level circuit module 101, and the single-stage amplifier 26 amplifies the sampled signal to increase the amplitude of the signal. The second switch 21 plays a feedback role during the sampling process and can make the amplifier output quickly stable at a specific stage. The third switch 22 and the fourth switch 23 cooperate with the fourth capacitor 25 to adjust the amplifier gain and introduce the reference voltage Vref by selecting different connection states, ensuring accurate sampling and amplification of the pixel reset signal and the optoelectronic signal at different working stages.
[0062] In a possible embodiment, the single-slope column-level ADC module 103 includes a single-slope ADC 32 and a fifth switch 31.
[0063] One end of the fifth switch 31 is connected to the fourth common node, and the other end is connected to the first input end of the single-slope ADC 32.
[0064] The second input end of the single-slope ADC 32 is connected to the ramp voltage ramp reference input signal Vramp, the third input end of the single-slope ADC 32 is connected to the counter initial value Init, the fourth input end of the single-slope ADC 32 is connected to the count control signal Sign, and the output end of the single-slope ADC 32 is used to output a signal.
[0065] The analog voltage value output by the sampling and amplification circuit module 102 is input to the first input end of the single-slope ADC 32 through the fifth switch 31, the ramp reference input signal Vramp, the counter initial value Init, and the count control signal Sign are respectively input to the corresponding input ends of the single-slope ADC 32, and finally, the difference between the two quantization digital codes is output from the output end of the single-slope ADC 32.
[0066] In the embodiment of the present application, the fifth switch 31 controls whether the analog voltage value output by the sampling and amplifying circuit module 102 is input to the single-slope ADC 32 for quantization. The single-slope ADC 32 quantizes the input analog voltage value according to the ramp reference input signal Vramp, the counter starting value Init, and the counting control signal Sign. By specific counting rules and starting value settings, the difference between the two quantization digital codes is output, realizing the conversion from analog signal to digital signal, and further eliminating the common-mode noise and fixed bias in the circuit by using the difference output method.
[0067] In a possible embodiment, the first MOS transistor 11 and the second MOS transistor 12 both adopt NMOS transistors, and the first switch 14 adopts a complementary switch structure of NMOS transistors and PMOS transistors.
[0068] In the embodiment of the present application, the NMOS transistor has the advantages of fast switching speed and small on-resistance, and can efficiently complete the reset of the capacitor and the transfer operation of the signal. The first switch 14 adopts a complementary switch structure of NMOS and PMOS, combining the advantages of NMOS and PMOS transistors, reducing the on-resistance of the first switch 14, reducing the loss in the signal transmission process, and at the same time improving the anti-interference ability and reliability of the first switch 14, ensuring the stable operation of the pixel-level circuit module 101.
[0069] Second aspect, as Figure 2 shown, a control method for a low-noise readout circuit for a mid-wave infrared detector includes the following steps: S1: The pixel-level circuit module 101 resets the second capacitor 19 through the second MOS transistor 12 and outputs a pixel reset signal.
[0070] S2: An optoelectronic signal is formed on the second capacitor 19 through the first switch 14, and a pixel optoelectronic signal is output.
[0071] S3: The sampling and amplifying circuit module 102 samples and amplifies the pixel reset signal and the optoelectronic signal in sequence.
[0072] S4: The single-slope column-level ADC module 103 quantizes the analog voltage value output by the sampling and amplifying circuit module 102 respectively during two sampling timing phases, and outputs the difference between the two quantization digital codes.
[0073] Specifically, the optoelectronic signal generated by the external infrared detection device is input to the pixel-level circuit module 101. First, the pixel-level circuit module 101 outputs a pixel reset signal and an optoelectronic signal, then the sampling and amplifying circuit module 102 samples and amplifies these two signals, and finally the single-slope column-level ADC module 103 performs quantization and outputs the difference.
[0074] In the embodiment of the present application, first, the pixel-level circuit module 101 outputs a pixel reset signal and a photoelectric signal. Then, the sampling and amplification circuit module 102 samples and amplifies these two signals. Finally, the single-slope column-level ADC module 103 quantifies and outputs the difference. This orderly operation process realizes the complete processing of the infrared detection signal, effectively eliminates the pixel sampling noise through the correlated double sampling technology, and at the same time avoids the noise introduced by the additional sampling capacitor, improving the signal-to-noise ratio and signal processing accuracy of the readout circuit.
[0075] In a possible embodiment, the specific steps include: At the first moment, in the full-frame pixel integration stage, the first MOS transistor 11 is turned on, and after resetting the first capacitor 18, it is turned off.
[0076] At the second moment, the third MOS transistor 13 is turned on to transfer and store the photoelectric signal. The conduction duration of the third MOS transistor 13 can be configured according to the usage requirements. After completing the transfer and storage, the third MOS transistor 13 is turned off, and the full-frame pixel integration stage is completed.
[0077] That is, in the pixel array row-by-row readout stage, at the third moment, the fifth MOS transistor 15 is turned on to select the pixel-level circuit module 101 that needs to be output.
[0078] At the fourth moment, the second MOS transistor 12 is turned on, and after resetting the second capacitor 19, it is turned off.
[0079] In the first sampling stage, at the fifth moment, the second switch 21, the fourth switch 23, and the fifth switch 31 are turned on. After the output establishment of the sampling and amplification circuit module 102 is completed, the second switch 21 is turned off first, and then the fourth switch 23 is turned off.
[0080] At the sixth moment, after the third switch 22 is turned on, the single-slope column-level ADC module 103 inputs the ramp reference signal Vramp to perform analog-to-digital conversion on the reference voltage output by the sampling and amplification circuit module 102 in the first stage. After the conversion is completed, the fifth switch 31 is turned off, and the input of the ramp reference signal Vramp returns to the starting voltage value.
[0081] In the second sampling stage, at the seventh moment, the first switch 14 is turned on. After the photoelectric signal is formed on the second capacitor 19, the first switch 14 is turned off.
[0082] In the second conversion stage, at the eighth moment, the fifth switch 31 is turned on again. The single-slope column-level ADC module 103 inputs the ramp reference signal Vramp to perform analog-to-digital conversion on the voltage output by the sampling and amplification circuit module 102 in the second stage. After the conversion is completed, the fifth switch 31 is turned off, and the input of the ramp reference signal Vramp returns to the starting voltage value.
[0083] After the two conversion stages are completed, at the ninth moment, after the third switch 22 is turned off, the fifth MOS transistor 15 is turned off, completing the sampling, amplification, and analog-to-digital conversion processes of the selected pixel-level circuit module 101.
[0084] In the embodiment of the present application, through precise timing control, the conduction and turning off of each MOS transistor and switch are sequentially controlled at different moments, realizing a series of operations such as the reset of the first capacitor 18 and the second capacitor 19, the transfer and storage of the optoelectronic signal, the selection of the pixel-level circuit module 101, the sampling and amplification of the sampling and amplification circuit module 102, and the analog-to-digital conversion of the single-slope column-level ADC module 103. This timing control ensures that the entire readout circuit can accurately process the infrared detection signal according to the predetermined process, further optimizing the signal processing process, reducing noise interference, and improving the performance and stability of the circuit.
[0085] In a possible embodiment, the capacitance values of the first capacitor 18 and the second capacitor 19 in the pixel-level circuit module 101 are the same.
[0086] In the embodiment of the present application, the capacitance values of the first capacitor 18 and the second capacitor 19 are the same. During the process of transferring the optoelectronic signal from the first capacitor 18 to the second capacitor 19, it can ensure the accurate transfer and proportional relationship of the signal, making the pixel reset signal and the optoelectronic signal of the two samplings have better correlation, thereby more effectively eliminating the pixel sampling noise through the correlated double sampling technique and improving the signal processing accuracy of the pixel-level circuit module 101.
[0087] In a possible embodiment, the single-stage amplifier 26 in the sampling and amplification circuit module 102 adopts a cascode single-stage amplifier 26 structure.
[0088] In the embodiment of the present application, the single-stage amplifier 26 adopts a cascode single-stage amplifier 26 structure, which has high gain, high output impedance, and good frequency response characteristics. It can efficiently amplify the pixel reset signal and the optoelectronic signal, while suppressing the noise and interference in the circuit, improving the amplification performance and signal quality of the sampling and amplification circuit module 102, and providing a more accurate analog signal for the subsequent analog-to-digital conversion.
[0089] In a possible embodiment, the initial value Init of the counter in the single-slope column-level ADC module 103 is the digital code corresponding to a negative value. The counting conditions of the counter during the two quantization processes are configured through the counting control signal Sign, so that the digital code output by the single-slope column-level ADC module 103 is the difference between the digital codes output by the two quantizations.
[0090] In the embodiment of the present application, the counter starting value Init is set to the digital code corresponding to a negative value, and the counting condition of the counter during the two quantization processes is configured through the counting control signal Sign, so that the single-slope column-level ADC module 103 can accurately output the difference between the two quantization digital codes. This setting method simplifies the subsequent signal processing process, directly obtains the difference information between the pixel reset signal and the optoelectronic signal, and further eliminates the fixed bias and common-mode noise in the circuit, improving the accuracy and reliability of the digital output.
[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: modifications to the technical solutions described in the foregoing embodiments, or equivalent replacements of some or all of the technical features therein, do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.
Claims
1. A low noise readout circuit for a medium wave infrared detector, characterized in that: It comprises a pixel-level circuit module (101), a sampling and amplification circuit module (102) and a single-slope column-level ADC module (103); The pixel-level circuit module (101) is connected to the infrared detection device and is used to sample the photoelectric signal generated by the infrared detection device; The sampling and amplifying circuit module (102) is connected to the pixel level circuit module (101) and is used to sample and amplify the pixel reset signal and the photoelectric signal output by the pixel level circuit module (101); The single-slope column-level ADC module (103) is connected to the sampling and amplifying circuit module (102) and is used to quantize the analog voltage value output by the sampling and amplifying circuit module (102) in two sampling timing stages, and output the difference between the two quantized digital codes; Each infrared detection device in the full array corresponds to one pixel-level circuit module (101), and each column of infrared detection devices in the full array corresponds to one sampling and amplifying circuit module (102) and one single-slope column-level ADC module (103).
2. The low noise readout circuit for medium wave infrared detector according to claim 1, characterized in that: The pixel-level circuit module (101) comprises a first MOS transistor (11), a second MOS transistor (12), a third MOS transistor (13), a fourth MOS transistor (16), a fifth MOS transistor (15), a sixth MOS transistor (17), a first capacitor (18), a second capacitor (19) and a first switch (14); The first MOS transistor (11) and the first capacitor (18) are coupled in series between a power supply terminal VDD and a ground terminal; The first MOS transistor (11) and the first capacitor (18) are connected to a first common node; The second MOS transistor (12) and the second capacitor (19) are coupled in series between a power supply terminal VDD and a ground terminal; The second MOS transistor (12) and the second capacitor (19) are connected to a second common node; The source end of the third MOS transistor (13) is used to be connected to an external infrared detection device, and the drain end of the third MOS transistor (13) is connected to the first common node; Two ends of the first switch (14) are respectively connected to a first common node and a second common node; The fourth MOS transistor (16), the fifth MOS transistor (15) and the sixth MOS transistor (17) are coupled in series between the power supply terminal VDD and the ground terminal; The gate of the fourth MOS transistor (16) is connected to the second common node, the source of the fourth MOS transistor (16) is connected to the drain of the fifth MOS transistor (15), the source of the fifth MOS transistor (15) is connected to the drain of the sixth MOS transistor (17), and the source of the sixth MOS transistor (17) is connected to the ground; The source end of the fifth MOS transistor (15) is connected to the input end of the sampling and amplifying circuit module (102).
3. The low noise readout circuit for medium wave infrared detector according to claim 2, characterized in that: The sampling and amplifying circuit module (102) comprises a single-stage amplifier (26), a third capacitor (24), a fourth capacitor (25), a second switch (21), a third switch (22) and a fourth switch (23); One end of the third capacitor (24) is connected to the connection point between the fifth MOS transistor (15) and the sixth MOS transistor (17), the other end of the third capacitor (24) is connected to the input end of the single-stage amplifier (26), and the third capacitor (24) and the single-stage amplifier (26) are connected to a third common node; The output end of the single-stage amplifier (26) is connected to the input end of the single-slope column-level ADC module (103), and the output end of the single-stage amplifier (26) and the input end of the single-slope column-level ADC module (103) are connected to a fourth common node; One end of the second switch (21) is connected to the third common node, and the other end is connected to the fourth common node; The third switch (22) and the fourth switch (23) are coupled in series between the fourth common node and a reference voltage Vref; One end of the fourth capacitor (25) is connected to the third common node, and the other end is connected to the connection point between the third switch (22) and the fourth switch (23).
4. The low noise readout circuit for a medium wave infrared detector according to claim 3, characterized in that: The single-slope column-level ADC module (103) comprises a single-slope ADC (32) and a fifth switch (31); One end of the fifth switch (31) is connected to the fourth common node, and the other end is connected to the first input end of the single slope ADC (32); The second input terminal of the single slope ADC (32) is connected to the slope voltage ramp reference input signal Vramp, the third input terminal of the single slope ADC (32) is connected to the counter start value Init, the fourth input terminal of the single slope ADC (32) is connected to the count control signal Sign, and the output terminal of the single slope ADC (32) is used to output a signal.
5. The low noise readout circuit for medium wave infrared detector according to claim 2, characterized in that: The first MOS transistor (11) and the second MOS transistor (12) are both NMOS transistors, and the first switch (14) is a complementary switch structure of an NMOS transistor and a PMOS transistor.
6. A control method for a low-noise readout circuit for a medium-wave infrared detector based on any one of claims 1 to 5, characterized in that: The following steps are involved: S1: The pixel-level circuit module (101) resets the second capacitor (19) through the second MOS transistor (12) and outputs a pixel reset signal; S2: forming a photoelectric signal on the second capacitor (19) through the first switch (14) and outputting a pixel photoelectric signal; S3: the sampling and amplification circuit module (102) samples and amplifies the pixel reset signal and the photoelectric signal in sequence; S4: The single-slope column-level ADC module (103) quantizes the analog voltage value output by the sampling and amplifying circuit module (102) in two sampling timing stages, and outputs the difference between the two quantized digital codes.
7. The control method for a low noise readout circuit for a medium wave infrared detector according to claim 5, characterized in that: The specific steps include: At a first moment, the first MOS transistor (11) is turned on, the first capacitor (18) is reset, and then turned off; At the second moment, the third MOS transistor (13) is turned on to transfer and store the photoelectric signal. The duration of the conduction of the third MOS transistor (13) can be configured according to usage requirements. After the transfer and storage are completed, the third MOS transistor (13) is turned off. At the third moment, the fifth MOS transistor (15) is turned on to select the pixel-level circuit module (101) that needs to output; At a fourth moment, the second MOS transistor (12) is turned on, the second capacitor (19) is reset, and then turned off; At the fifth moment, the second switch (21), the fourth switch (23) and the fifth switch (31) are turned on, and after the output of the sampling and amplifying circuit module (102) is established, the second switch (21) is turned off first, and then the fourth switch (23) is turned off; At the sixth moment, after the third switch (22) is turned on, the single slope column-level ADC module (103) inputs the ramp reference signal Vramp, performs analog-to-digital conversion on the reference voltage output by the first stage sampling and amplifying circuit module (102), and after the conversion is completed, the fifth switch (31) is turned off, and the ramp reference signal Vramp input returns to the starting voltage value; At the seventh moment, the first switch (14) is turned on, and after a photoelectric signal is formed on the second capacitor (19), the first switch (14) is turned off; At the eighth moment, the fifth switch (31) is turned on again, the single slope column-level ADC module (103) inputs the ramp reference signal Vramp, and performs analog-to-digital conversion on the output voltage of the second-stage sampling and amplifying circuit module (102). After the conversion is completed, the fifth switch (31) is turned off, and the ramp reference signal Vramp input returns to the starting voltage value; At the ninth moment, after the third switch (22) is turned off, the fifth MOS transistor (15) is turned off, completing the sampling, amplification and analog-to-digital conversion process of the selected pixel-level circuit module (101).
8. The control method for a low noise readout circuit for a medium wave infrared detector according to claim 5, characterized in that: The first capacitor (18) and the second capacitor (19) in the pixel-level circuit module (101) have the same capacitance.
9. The control method for a low noise readout circuit for a medium wave infrared detector according to claim 5, characterized in that: The single-stage amplifier (26) in the sampling and amplifying circuit module (102) adopts a common-source and common-gate single-stage amplifier structure.
10. The control method for a low noise readout circuit for a medium wave infrared detector according to claim 5, characterized in that: The counter start value Init in the single-slope column-level ADC module (103) is a digital code corresponding to a negative value, and the counting conditions of the counter in two quantization processes are configured by a counting control signal Sign, so that the single-slope column-level ADC module (103) outputs a digital code that is a difference between the two quantization output digital codes.