Digital front-end processing system suitable for ORAN beam forming

Abstract

The invention discloses a digital front-end processing system suitable for ORAN beam forming, which comprises an O-RU ORAN interface, a Timing Module, an uplink beam forming processing link and a downlink beam forming processing link, and is characterized in that the O-RU ORAN interface is responsible for analyzing C-Plane, U-Plane, S-Plane and M-Plane link plane data; the Timing module is responsible for synchronizing a signal at the time of 10ms and providing a time sequence control signal for all the modules; and the downlink beam forming processing link comprises a downlink IQ (In-phase Quadrature) data, a BeamID (Beam Identity), a Beamforming Weight data cache, a DL (Downlink) Scheduling, a DL Scheduling, a Downlink Beamforming System, an IFFT (Inverse Fast Fourier Transform) / FFT (Fast Fourier Transform) / PowerScaling module and a DL DFE (Downlink Downlink) Chainin module, and the downlink beam forming processing link comprises a downlink IQ (In-phase Quadrature) data cache, a BeamID (Beamforming Identity) and Beamforming Weight data cache, a DL Scheduling (Downlink). According to the system, a modular design framework is adopted, different hardware schemes are convenient to transplant, ORAN Split7.2 x Category B devices of different manufacturers are directly connected in a butt joint mode, an upgrading interface is reserved, ORAN WG4section extension types are supported to be added, MATLAB algorithm module analysis and verification are provided, and the module efficiency and stability are high.

Description

Technical Field

[0001] The present invention relates to the field of wireless communication technologies, and particularly to a digital front-end processing system applicable to ORAN beamforming. Background Art

[0002] Currently, traditional wireless communication devices mainly complete beamforming digital front-end processing in the following ways:

[0003] In a wireless communication device, data interaction of the entire system is completed through the eCPRI or CPRI interface protocol between the digital device and the radio frequency device.

[0004] Its disadvantages are as follows: The beamforming protocol definitions of different device manufacturers are different, resulting in non-dockable use of digital devices and radio frequency devices of different manufacturers. If new beamforming function definitions need to be supported, new logical interfaces need to be added, and system expansion is not convenient. Summary of the Invention

[0005] The purpose of the present invention is to provide a digital front-end processing system applicable to ORAN beamforming to solve the problems raised in the above background art.

[0006] To achieve the above purpose, the present invention provides the following technical solution: A digital front-end processing system applicable to ORAN beamforming includes an O-RU ORAN interface, a Timing Module, an uplink beamforming processing link, and a downlink beamforming processing link. The O-RU ORAN interface is responsible for parsing C-Plane, U-Plane, S-Plane, and M-Plane link plane data; the Timing module is responsible for the 10ms time synchronization signal and providing timing control signals to all modules; the downlink beamforming processing link includes a downlink IQ data and BeamID and Beamforming Weight data cache, DL ScheduleControl, DL Schedule Muxing, Downlink Beamforming System, IFFT / FFT / PowerScaling, and DL DFE Chain modules; the uplink beamforming processing link includes a cache for uplink IQ data and BeamID and BF Weight data, UL Schedule Control, UL Schedule Muxing, Uplink Beamforming System, IFFT / FFT / PowerScaling, and UL DFE Chain modules.

[0007] Preferably, the RU ORAN interface: implements the functions of parsing the O-RAN C plane, U plane, M plane, and S plane, and core supports four 25Gbps Ethernet ports, including C plane section extension 1 parsing, and provides Beam ID and Beam Weight interfaces.

[0008] Preferably, the Timing module: uses the timing system of the PTP 1588v2 protocol to achieve clock frequency and phase synchronization of the O-DU and O-RU devices, parses the network data stream sent by the O-DU device into S-Plane data, performs synchronization at the 10ns level through PCM4L, PTP4L, and the kernel driver and the underlying hardware timestamp system, and then distributes the synchronized time information to the uplink and downlink beamforming digital front-end systems for processing.

[0009] Preferably, the downlink beamforming processing link:

[0010] Caching of downlink IQ data, BeamID, and BF Weight data;

[0011] Downlink Schedule Control;

[0012] Downlink Schedule Muxing;

[0013] Downlink Beamforming System;

[0014] IFFT / FFT / PowerScaling;

[0015] Downlink DFE Chain.

[0016] Preferably, the uplink beamforming processing link:

[0017] Caching of uplink IQ data, BeamID, and BF Weight data;

[0018] Uplink Schedule Control;

[0019] Uplink Schedule Muxing;

[0020] Uplink Beamforming System;

[0021] IFFT / FFT / PowerScaling;

[0022] Uplink DFE Chain.

[0023] Preferably, the uplink beamforming processing link and the downlink beamforming processing link perform weight processing on all IQ data according to the time information given by the timing module.

[0024] Preferably, the C-plane section extension 1 is applicable to sending beamforming weights from the O-DU to the O-RU. When the section extension 1 appears in the section description, the O-RU shall associate the beamforming weight ID transmitted in the section extension 1 with the beamforming weight set transmitted in the section description. In subsequent C-Plane messages, the same beamId can be called without sending the beamforming weights again.

[0025] Preferably, the beamforming weights are transmitted on the interface through C-Plane messages.

[0026] Compared with the prior art, the beneficial effects of the present invention are:

[0027] The system modular design framework is convenient for transplanting different hardware solutions. The ORAN Split7.2x Category B devices of different manufacturers can be directly docked. An upgrade interface is reserved to support adding ORAN WG4 section extension types, providing MATLAB algorithm module analysis and verification, with high module efficiency and high stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is the system block diagram of the present invention;

[0029] Figure 2 It is the schematic diagram of the O-RU ORAN interface of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0031] Please refer to Figure 1-2, the present invention provides a technical solution: a digital front-end processing system applicable to ORAN beamforming, including an O-RU ORAN interface, a Timing Module, an uplink beamforming processing link, and a downlink beamforming processing link. The O-RU ORAN interface is responsible for parsing the C-Plane, U-Plane, S-Plane, and M-Plane link plane data; the Timing module is responsible for the 10ms time synchronization signal and providing timing control signals to all modules; the downlink beamforming processing link includes downlink IQ data, BeamID, and Beamforming Weight data caches, DL ScheduleControl, DL Schedule Muxing, Downlink Beamforming System, IFFT / FFT / PowerScaling, and DL DFE Chain modules; the uplink beamforming processing link includes uplink IQ data, BeamID, and BF Weight data caches, UL Schedule Control, UL Schedule Muxing, Uplink Beamforming System, IFFT / FFT / PowerScaling, and UL DFE Chain modules.

[0032] A digital front-end processing system applicable to ORAN beamforming mainly realizes the digital front-end processing of beamforming in ORAN devices, exchanges and transmits control plane messages between digital devices and radio frequency devices, and is used to process user data as well as scheduling and beamforming parameters. Among them, section extension 1 is mainly an extension type related to beamforming weight, which is applicable to sending Beam Weight from a digital device to a radio frequency device, and this Weight is sent together with the BeamID.

[0033] In the present invention, the RU ORAN interface: realizes the functions of parsing the O-RAN C plane, U plane, M plane, and S plane, and core supports four 25Gbps Ethernet ports, including the parsing of C plane section extension 1, and provides Beam ID and Beam Weight interfaces.

[0034] In the present invention, the Timing module: uses the time synchronization system of the PTP 1588v2 protocol to achieve clock frequency and phase synchronization of O-DU and O-RU devices, parses the network data stream sent by the O-DU device into S-Plane data, performs 10ns-level synchronization through PCM4L, PTP4L, and the kernel driver and the underlying hardware timestamp system, and then distributes the synchronized time information to the uplink and downlink beamforming digital front-end systems for processing.

[0035] In the present invention, the downlink beamforming processing link:

[0036] Caching of downlink IQ data, BeamID, and BF Weight data;

[0037] Downlink Schedule Control;

[0038] Downlink Schedule Muxing;

[0039] Downlink Beamforming System;

[0040] IFFT / FFT / PowerScaling;

[0041] Downlink DFE Chain.

[0042] In the present invention, the uplink beamforming processing link:

[0043] Caching of uplink IQ data, BeamID, and BF Weight data;

[0044] Uplink Schedule Control;

[0045] Uplink Schedule Muxing;

[0046] Uplink Beamforming System;

[0047] IFFT / FFT / PowerScaling;

[0048] Uplink DFE Chain.

[0049] In the present invention, the uplink beamforming processing link and the downlink beamforming processing link perform weight processing on all IQ data according to the time information given by the timing module.

[0050] In the present invention, the C-plane section extension 1 is applicable to transmitting beamforming weights from the O-DU to the O-RU. When section extension 1 appears in the section description, the O-RU shall associate the beamforming weight ID transmitted in section extension 1 with the beamforming weight set transmitted in the section description. In subsequent C-Plane messages, the same beamId can be called without transmitting the beamforming weights again.

[0051] In the present invention, the beamforming weights are transmitted on the interface through C-Plane messages.

[0052] This system uses the VHDL coding language and integrates the ORAN fronthaul interface interconnected between the O-DU and the O-RU. It includes: 10 / 25G line rate Fronthaul Interface; C-Plane, U-Plane, S-Plane, M-Plane link data processing; Beamforming Management; AXI-Lite configuration interface; Fronthaul Interface Package filter module processing; ORAN router module; support for the 1588v2 protocol; support for module simulation and system simulation.

[0053] ORAN C-Plane section extension 1 is applicable to sending beamforming weights from the O-DU to the O-RU. When section extension 1 appears in the section description, the O-RU shall associate the beamforming weight ID transmitted in section extension 1 with the beamforming weight set transmitted in the section description. In subsequent C-Plane messages, the same beamId can be called without sending the beamforming weights again. The meanings of each field are as follows:

[0054]

[0055] ORAN C-Plane section extension 2 is applicable to sending beamforming attributes from the ODU to the ORU;

[0056]

[0057] This system obtains beamforming-related information from the ORAN C-Plane section field and then sends it to the uplink beamforming processing link and the downlink beamforming processing link modules, and performs weight processing on all IQ data according to the time information given by the timing module.

[0058] In the present invention, the beamforming weights are transmitted on the interface through C-Plane messages.

[0059] For frequency-domain beamforming, the operations can be considered as follows:

[0060] X = [X0 X1…Xp-1] represents the frequency-domain IQ data of a data segment, where P is the number of REs in this data segment, Xi is an RE, X ∈ L*1, and L is the number of streams.

[0061] W = [W0 W1…Wp-1] represents the beamforming weights associated with the x-array, where Wi is the beamforming weight of RE Xi, wI ∈ K*L, and K is the number of array elements.

[0062] Note: The O-DU can send W for each PRB or PRB packet, and the O-RU can send W for each PRB or PRB packet.

[0063] The output Y = [Y0 Y1…Yp-1] after beamforming is expressed as: Yi = Wi * Xi

[0064] where Yi is the beamforming output of RE Xi, Yi ∈ K*1.

[0065] The above formula refers to DL beamforming, but the same principle also applies to UL.

[0066] The present invention: The downlink beamforming processing link includes the following modules:

[0067] Downlink BFM IO includes the following functions

[0068] 10ms synchronization symbol timing signal

[0069] U-Plane IQ data

[0070] C-Plane Beam ID Memory

[0071] C-Plane Beamforming Weight Memory

[0072] AXI control register interface

[0073] Downlink Schedule Control includes the following functions:

[0074] 10ms synchronization timing control signal;

[0075] Manage the carrier enable signal and related parameter settings;

[0076] Schedule beamforming memory processing one cycle before the U-Plane to align I / Q with the relevant weights;

[0077] Stagger the layer buffer processing cycle to avoid using pipeline processing in the subsequent module;

[0078] Generate the iFFT AXI stream control signal and insert the IFFT control packet at the beginning of each round;

[0079] Add a configurable delay to the iFFT AXI stream control signal to account for the processing delay through other modules before reaching the iFFT;

[0080] The Downlink Schedule BFM includes the following functions:

[0081] Beamforming data caching processing flow;

[0082] Initialize the BID cache when the round_start signal is detected by the Timing Controller;

[0083] Report the round_done signal to the Timing Controller;

[0084] After the IFFT is completed, reorder the PRBs for the U-Plane data;

[0085] Check if the current symbol number is within the start and last symbol ranges defined in the BID cache;

[0086] Read from the BFW cache by BeamID and integer;

[0087] Convert the 9b / 4b floating-point beamforming weight format to a 16b fixed-point value;

[0088] The Downlink Schedule uplane includes the following functions:

[0089] U-Plane data caching processing flow;

[0090] Start reading U-Plane data when the round_start signal is detected by the Timing Controller;

[0091] Report the round_done signal to the Timing Controller;

[0092] The IFFT reads and reorders the U-Plane data.

[0093] The Downlink Schedule uplane includes the following functions:

[0094] Downlink data multiplexing;

[0095] Manage the Beamforming weights for different spatial streams;

[0096] Downlink bypass;

[0097] Downlink Beamforming System:

[0098] Bypass function;

[0099] U-Plane, BID, BFW data cache;

[0100] Instantiate BID / BFW RAM;

[0101] BFW Mantissa Memory-Dual Page, Two DP RAM;

[0102] BFW Exponent Memory;

[0103] Downlink DFE Chain:

[0104] Phase compensation;

[0105] IFFT and Output Scaling;

[0106] URAM Reader from Timing Controller;

[0107] URAM Writer from Timing Controller;

[0108] The uplink beamforming processing link includes the following modules:

[0109] Uplink BFM IO includes the following functions:

[0110] 10ms synchronous symbol timing signal;

[0111] U-Plane IQ data;

[0112] C-Plane Beam ID Memory;

[0113] C-Plane Beamforming Weight Memory;

[0114] AXI control register interface.

[0115] Uplink Schedule Control includes the following functions:

[0116] 10ms synchronous timing control signal;

[0117] Manage carrier enable signal and related settings;

[0118] Schedule beamforming memory processing one cycle before the U-Plane to align I / Q with the relevant weights;

[0119] Stagger the layer cache processing cycles to avoid using pipeline options in the b_mf module;

[0120] Generate iFFT AXI stream control signals and insert ifft_ctrl packets at the start of each round;

[0121] Add a configurable delay to the iFFT AXI stream control signals to account for the processing delay through other modules before reaching the iFFT.

[0122] Uplink Schedule BFM includes the following functions:

[0123] Beamforming cache processing flow;

[0124] Initialize the BID cache when the round_start signal is detected from the Timing Controller;

[0125] Report the round_done signal to the Timing Controller;

[0126] After IFFT is completed, reorder the PRB for U-Plane data;

[0127] Check whether the current symbol number is within the start and last symbol ranges defined in the BID cache;

[0128] Generate iFFT AXI stream control signals by reading from the BFW cache according to BeamID and integer, and insert ifft_ctrl packets at the start of each round;

[0129] Convert the 9b / 4b floating-point beamforming weight format to 16b fixed-point values.

[0130] Uplink Schedule uplane includes the following functions:

[0131] U-Plane data cache processing flow;

[0132] Start reading U-Plane data when the round_start signal is detected from the Timing Controller;

[0133] Report the round_done signal to the Timing Controller;

[0134] Reorder the U-Plane data read by IFFT.

[0135] The uplink schedule uplane includes the following functions:

[0136] Uplink data multiplexing;

[0137] Manage beamforming weights for different spatial streams;

[0138] Downlink bypass.

[0139] Uplink Beamforming System:

[0140] Bypass function;

[0141] U-Plane, BID, BFW data caching;

[0142] Instantiate BID / BFW RAM;

[0143] BFW Mantissa Memory-Dual Page, Two DP RAM;

[0144] BFW Exponent Memory.

[0145] Uplink DFE Chain:

[0146] Phase compensation;

[0147] UL Timing Alignment Delay;

[0148] IFFT and Output Scaling;

[0149] URAM Reader from Timing Controller;

[0150] URAM Writer from Timing Controller.

[0151] The present invention is mainly applied to the beamforming implementation of ORAN radio frequency devices, mainly exchanging and transmitting control plane messages between digital devices and radio frequency devices, for processing user data as well as scheduling and beamforming parameters. When section extension 1 appears in the ORAN control plane section description, the O-RU associates the beamforming weight ID transmitted in section extension 1 with the beamforming weight set transmitted in the section description, and then combines the time synchronization information of the synchronization plane to perform corresponding processing on the IQ data. This processing module is implemented using FPGA logic and is divided into uplink and downlink beamforming processing links. Advantages: Following the ORAN WG4 protocol standard, ORAN Split7.2x Category B devices from different manufacturers can be directly docked. If new beamforming functions need to be supported, only new section extension processing logic needs to be added, and it has the ability of system expansion.

[0152] The content not described in detail in this specification belongs to the prior art well-known to those skilled in the art. Although the embodiments of the present invention have been shown and described, for those of ordinary skill in the art, it can be understood that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A digital front-end processing system suitable for ORAN beamforming, characterized in that: It includes O-RU ORAN interface, Timing Module, uplink beamforming processing link and downlink beamforming processing link. The O-RU ORAN interface is responsible for parsing C-Plane, U-Plane, S-Plane and M-Plane link plane data; the Timing module is responsible for 10ms time synchronization signal and provides timing control signal to all modules; the downlink beamforming processing link includes downlink IQ data and BeamID and Beamforming Weight data cache, DL Schedule Control, DL Schedule Muxing, Downlink Beamforming System, IFFT / FFT / PowerScaling, DL DFE Chain module; the uplink beamforming processing link includes uplink IQ data and BeamID and BF Weight data cache, UL Schedule Control, ULSchedule Muxing, Uplink Beamforming System, IFFT / FFT / PowerScaling, UL DFE Chain module.

2. A digital front-end processing system suitable for ORAN beamforming according to claim 1, characterized in that: The RU ORAN interface: implements the O-RAN C-plane, U-plane, M-plane and S-plane parsing functions, the core supports four 25Gbps Ethernet ports, including C-plane section extension 1 parsing, and provides Beam ID and Beam Weight interfaces.

3. The digital front-end processing system suitable for ORAN beamforming according to claim 1, characterized in that: The Timing module uses the PTP 1588v2 protocol timing system to achieve clock frequency and phase synchronization between O-DU and O-RU devices, parses the network data stream sent by the O-DU device into S-Plane data, performs 10ns-level synchronization through PCM4L and PTP4L as well as the kernel driver and the underlying hardware timestamp system, and then distributes the synchronized time information to the uplink and downlink beamforming digital front-end system for processing.

4. The digital front-end processing system suitable for ORAN beamforming according to claim 1, characterized in that: The downlink beamforming processing link: Cache of downlink IQ data, BeamID, and BF Weight data; Downlink Schedule Control; Downlink Schedule Muxing; Downlink Beamforming System; IFFT / FFT / PowerScaling; Downlink DFE Chain.

5. The digital front-end processing system suitable for ORAN beamforming according to claim 1, characterized in that: The uplink beamforming processing link: Cache for uplink IQ data, BeamID, and BF Weight data; Uplink Schedule Control; Uplink Schedule Muxing; Uplink Beamforming System; IFFT / FFT / PowerScaling; Uplink DFE Chain.

6. The digital front-end processing system suitable for ORAN beamforming according to claim 1, characterized in that: The uplink beamforming processing link and the downlink beamforming processing link perform weight processing on all IQ data according to the time information provided by the timing module.

7. The digital front-end processing system suitable for ORAN beamforming according to claim 2, characterized in that: The C-plane section extension 1 is applicable to sending beamforming weights from O-DU to O-RU. When section extension 1 appears in the section description, O-RU shall associate the beamforming weight ID passed in section extension 1 with the beamforming weight set passed in the section description. In subsequent C-Plane messages, the same beamId can be called without sending the beamforming weights again.

8. The digital front-end processing system suitable for ORAN beamforming according to claim 7, characterized in that: The beamforming weights are transmitted on the interface via a C-Plane message.

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