Efficient B time code decoding system and method based on multi-frequency clock configuration

Abstract

The present invention discloses an efficient decoding system and method for B time code based on multi-frequency clock configuration, which relates to the technical field of signal decoding and is used to solve the problems of the accuracy and stability of B time code decoding. The method identifies and adapts clock sources of different frequencies, and uses global clock resources to detect the rising edge and falling edge of the clock signal. By calculating the clock frequency, duty cycle, and clock error, the input clock frequency is dynamically adjusted to ensure the stability of the clock. The characteristic data of stable and unstable clocks are determined, and the PLL is further adjusted to adapt to clock input signals of different frequencies. The method also preprocesses the B time code signal and decodes the signal using a finite state machine. Finally, a timing circuit and a PPS jitter elimination circuit are combined to ensure the time synchronization and clock stability of the system. The present invention has the advantages of high precision and high stability and is applicable to systems that require high-precision clock synchronization.

Description

Technical Field

[0001] The present invention relates to the technical field of signal decoding, and more specifically, to an efficient B time code decoding system and method based on multi-frequency clock configuration. Background Art

[0002] In modern high-precision clock synchronization systems, B time code decoding is widely used in fields such as satellite navigation, communication, and precision measurement. With the continuous development of technology, the requirements for clock accuracy and stability are increasing day by day. Traditional clock decoding methods mainly target fixed-frequency clock signals, but with the change of the system operating frequency, the prior art fails to effectively handle the adaptation of multi-frequency clock sources and the dynamic adjustment of clock errors. These methods often cannot guarantee accurate decoding in high-frequency or unstable frequency environments, resulting in error accumulation or synchronization failure, affecting the reliability and accuracy of the system.

[0003] In the prior art, although there are some methods to detect the clock frequency, most methods cannot comprehensively consider the frequency fluctuation, duty cycle change of the clock, and the dynamic error adjustment of the system.

[0004] In view of the above problems, the present invention proposes a solution. Summary of the Invention

[0005] In order to overcome the above-mentioned defects of the prior art, embodiments of the present invention provide an efficient B time code decoding system and method based on multi-frequency clock configuration to solve the problems raised in the above background art.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] In a preferred embodiment, it includes:

[0008] Step 1: Identify and adapt clock sources with different frequencies, and classify them according to the clock frequency stability;

[0009] Step 2: Preprocess the B time code signal according to the priority level;

[0010] Step 3: Maintain time accuracy and correct errors based on the FPGA timekeeping circuit;

[0011] Step 4: Eliminate signal jitter based on the PPS de-jitter circuit of the FPGA.

[0012] In a preferred embodiment, in Step 1, receive the clock signal, generate a stable reference clock, and calculate the input clock frequency.

[0013] In a preferred embodiment, in step 1, the rising edge time, falling edge time, and duty cycle deviation of the clock signal are detected; the rising and falling edge times and duty cycle deviation of the current clock frequency are weighted and summed to determine the clock error S of the current clock frequency. An error threshold Ys is set. If the clock error S of the current clock frequency is greater than or equal to the error threshold Ys, it indicates that the clock frequency belongs to an unstable clock frequency; if the clock error S of the current clock frequency is less than the error threshold Ys, it indicates that the clock frequency belongs to a stable clock frequency.

[0014] In a preferred embodiment, in step 1, the maximum allowable deviation threshold Eb between the clock frequency and the reference clock is defined; the time window width T1, that is, the stable time range required for B time code decoding, is defined, and a time error Es is set: the fluctuation amplitude Δf of the clock frequency and the standard deviation σ of the clock frequency are calculated; the clock frequency influence coefficient Ki is determined, and an influence threshold Yk is set. If the influence coefficient Ki is greater than or equal to the influence threshold Yk, the PLL enlarges the clock frequency adjustment amplitude; if the influence coefficient Ki is less than the influence threshold Yk, the PLL reduces the clock frequency adjustment amplitude.

[0015] In a preferred embodiment, in step 2, the matching degree between the B time code signal and the clock frequency and the envelope stability data are obtained. The matching degree between the B time code signal and the clock frequency and the envelope stability data are weighted and summed to determine the priority P of the B time code signal. The B time code signals are processed from high to low according to the priority P of the B time code signal.

[0016] In a preferred embodiment, in step 2, the high-frequency noise of the B time code signal is removed; the key time information of the B time code signal is extracted; based on the threshold determination logic implemented by FPGA, combined with the high-level duration and signal period obtained in step 1, a pulse high-level duration determination threshold is set; the B time code signal is decoded.

[0017] In a preferred embodiment, in step 3, the deviation between the decoded time and the clock is calculated. When the external time source is lost based on FPGA, it automatically switches to the FPGA timekeeping circuit and maintains time synchronization; after the clock signal is restored, the decoded time is re-compared and the error is corrected.

[0018] In a preferred embodiment, in step 4, the PPS signal is obtained; the time deviation ΔTpps of consecutive multiple PPS pulses is calculated, and a jitter deviation threshold Tp is set. When the time deviation ΔTpps is greater than or equal to the jitter deviation threshold Tp, stable time output is required.

[0019] In a preferred embodiment, it includes: a clock identification and adaptation module, a clock error calculation and adjustment module, a B time code signal preprocessing module, and a B time code decoding and correction module, with signal connections between the modules;

[0020] The clock recognition and adaptation module is mainly used to recognize and adapt clock signals of different frequencies, generate a stable reference clock through the PLL inside the FPGA, and calculate the input clock frequency;

[0021] The clock error calculation and adjustment module calculates the clock error and optimizes the clock frequency by dynamically adjusting the PLL configuration to ensure that the clock stability meets the decoding accuracy requirements;

[0022] The B time code signal preprocessing module judges the matching degree of the received B time code signal, analyzes the envelope stability, and extracts key information through filtering and zero-crossing detection;

[0023] The B time code decoding and correction module decodes the B time code using a finite state machine and corrects the decoding error through a timing circuit to ensure the time synchronization accuracy.

[0024] The present invention discloses an efficient B time code decoding system and method based on multi-frequency clock configuration, which relates to the technical field of signal decoding and is used to solve the problems of the accuracy and stability of B time code decoding; the method recognizes and adapts clock sources of different frequencies and uses global clock resources to detect the rising and falling edges of the clock signal. By calculating the clock frequency, duty cycle, and clock error, the input clock frequency is dynamically adjusted to ensure the clock stability. The characteristic data of stable and unstable clocks are determined, and the PLL is further adjusted to adapt to clock input signals of different frequencies. The method also preprocesses the B time code signal and decodes the signal using a finite state machine. Finally, combined with a timing circuit and a PPS jitter elimination circuit, the time synchronization and clock stability of the system are ensured. The present invention has the advantages of high precision and high stability and is applicable to systems that require high-precision clock synchronization. Description of the Drawings

[0025] Figure 1 It is a schematic structural diagram of the efficient B time code decoding system based on multi-frequency clock configuration of the present invention.

[0026] Figure 2 It is an operation flow chart of the efficient B time code decoding method based on multi-frequency clock configuration of the present invention. Detailed Embodiments

[0027] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention. Embodiment

[0028] The present invention discloses an efficient decoding method for B time code based on multi-frequency clock configuration, as Figure 2 shown, including:

[0029] Step 1: Identify and adapt clock sources of different frequencies;

[0030] Use the global clock pin GCLK as the external clock input port. If the clock signal is a single-ended signal LVCMOS, directly connect it to the GCLK pin; if the clock signal is a differential signal LVDS, use an IBUFDS differential input buffer to convert the differential signal into a single-ended signal and then connect it to the GCLK pin;

[0031] After that, use the time window method to count the input clock cycles. The specific process is as follows:

[0032] Generate a stable reference clock inside the FPGA through the internal PLL / MMCM of the FPGA. At the same time, create a counter inside the FPGA, count from 0 to 100000, and set a fixed time window T, which is determined by the 100MHz reference clock count: T = 100000 clock cycles;

[0033] Use a rising edge detection module. Within the time window T, when each rising edge of the input clock occurs, input the clock into the counter, detect the number of rising edges of the input clock signal, and count the number of input clock pulses N; then, within the measured period T, calculate the input clock frequency fin according to the number of input clock pulses N. The specific formula is: fin = N / T.

[0034] Store the identified clock frequency into the internal register of the FPGA.

[0035] After that, use a high-precision global clock counter based on the global clock resources of the FPGA to sample the input clock signal, use the double-edge trigger method to detect the rising edge time Trise and falling edge time Tfall of the clock signal respectively, and store the current count value as a timestamp;

[0036] Calculate the period Tclk of the input clock signal:

[0037] Tclk = Trise(i + 1) - Trise(i);

[0038] Calculate the high-level time Thigh and low-level time Tlow:

[0039] Thigh = Tfall(i) - Trise(i);

[0040] Tlow = Trise(i + 1) - Tfall(i);

[0041] Calculate the duty cycle D:

[0042] D = (Thigh / Tclk) × 100%;

[0043] Analyze the mean and standard deviation of historical duty cycle data using K - means clustering to determine the ideal duty cycle D1, and calculate the duty cycle deviation ΔD based on the ideal duty cycle and the current duty cycle:

[0044] ΔD = |D - D1|;

[0045] Weighted sum the rising and falling edge times of the current clock frequency and the duty cycle deviation to determine the clock error S of the current clock frequency, specifically according to the formula:

[0046]

[0047] Among them, Qy represents the weight of the rising and falling edge times of the current clock frequency, Qz represents the weight of the current duty cycle deviation, Treise(i) represents the actual rising edge time of the input clock signal detected at the i - th sampling point, and Tideal - rise(i) represents the ideal rising edge time at the i - th sampling point;

[0048] Set the error threshold Ys, and compare the clock error S of the current clock frequency with the stability score threshold Ys. If the clock error S of the current clock frequency is greater than or equal to the error threshold Ys, it indicates that the stability of this clock frequency is weak and it belongs to an unstable clock frequency; if the clock error S of the current clock frequency is less than the error threshold Ys, it indicates that the stability of this clock frequency is strong and it belongs to a stable clock frequency;

[0049] Furthermore, clarify and quantify the accuracy requirements for B - time - code decoding:

[0050] Step S1: Define the maximum allowable deviation threshold Eb between the input clock frequency and the reference clock frequency, and compare it with the maximum allowable deviation between the input clock frequency and the reference clock frequency during the decoding process:

[0051] Eb = |fin - fre| ≤ Δfmax;

[0052] Among them, fin represents the input clock frequency, fre represents the reference clock frequency, and Δfmax represents the maximum allowable deviation between the clock frequency and the reference clock;

[0053] Step S2: Define the time - window width T1, which is the stable time range required for B - time - code decoding, and set the time error Es:

[0054] Es = |Tw - Ts|;

[0055] Among them, Tw represents the actual time window, and Ts represents the time synchronization accuracy required for B - time - code decoding.

[0056] Obtain the characteristic data of the stable clock frequency and the unstable clock frequency:

[0057] Step S3: Calculate the fluctuation amplitude Δf of the clock frequency:

[0058] Δf = max(fin) - min(fin);

[0059] Step S4: Calculate the standard deviation σ of the clock frequency:

[0060]

[0061] where fi represents the clock frequency at each time point, μ represents the mean value of the clock frequency, and N represents the number of sampling points;

[0062] Combine the accuracy requirement of B time code decoding with the characteristic data of stable and unstable clock frequencies to determine the influence coefficient: Ki = f(Eb, Es, S, Δf, σ), where f represents a comprehensive function;

[0063] After that, use the influence coefficient Ki to adjust the configuration of the FPGA phase-locked loop (PLL) to dynamically adjust the input clock frequency. The specific steps are as follows:

[0064] Step S5: Input the influence coefficient Ki into the PLL control module, and set the influence threshold Yk. If the influence coefficient Ki is greater than or equal to the influence threshold Yk, the PLL will increase the clock frequency adjustment amplitude; if the influence coefficient Ki is less than the influence threshold Yk, the PLL will decrease the clock frequency adjustment amplitude;

[0065] Finally, send a clock frequency adjustment completion signal to notify the B time code decoding module to use the new clock frequency parameters to adapt to the B time code signal input with different clock frequencies.

[0066] Step 2: Preprocess the B time code signal;

[0067] After receiving the B time code signal, determine the priority of the B time code signal according to the matching degree between the B time code and the clock frequency and the envelope stability of the B time code signal in Step 1. The specific process is as follows:

[0068] Step B1: Obtain the matching degree data between the B time code and the clock frequency;

[0069] Specifically, after receiving the B time code signal, according to the maximum allowable deviation threshold Eb between the clock frequency and the reference clock in Step 1, when the error threshold Eb is less than or equal to the maximum allowable deviation Δfmax, it indicates that the matching degree between the B time code and the clock frequency is high at this time; when the maximum allowable deviation threshold Eb between the clock frequency and the reference clock is greater than the maximum allowable deviation Δfmax, it indicates that the matching degree between the B time code and the clock frequency is low at this time;

[0070] Step B2: Obtain the envelope stability data of the B time code signal;

[0071] Specifically, perform Hilbert transform on the received B time code signal to obtain the analytical form of the B time code signal, and then calculate the envelope of the B time code signal; calculate the standard deviation Bb of the envelope of the B time code signal, which is denoted as the envelope stability data of the B time code signal;

[0072] Step B3: Determine the priority P of the B time code signal by weighted summation of the matching degree between the B time code and the clock frequency and the envelope stability data of the B time code signal. Specifically, according to the formula:

[0073]

[0074] where, w1 represents the weight of the matching degree between the B time code and the clock frequency, w2 represents the weight of the envelope stability of the B time code signal, and Bb(max) represents the maximum standard deviation of the envelope signal, which is used to normalize the envelope stability;

[0075] Furthermore, process the B time code signals in descending order according to the priority P of the B time code signals;

[0076] The specific processing process of the B time code signal is as follows:

[0077] Use a second-order IIR filter to perform low-pass filtering on the B time code signal to remove high-frequency noise. The cut-off frequency is set to fc = 1.2×fbaseband, where the baseband frequency is usually 1 kHz. Specifically, according to the formula:

[0078]

[0079] Use the zero-crossing detection circuit built in the FPGA, set the zero-point threshold. When the B time code signal is added or subtracted with the threshold and the result changes from negative to positive (or from positive to negative), record the time stamp and extract the key time information of the B time code signal;

[0080] Then, perform normalization processing on the B time code signal to ensure that the signal amplitude range is fixed, which is convenient for FPGA processing;

[0081] Since the code element information of the B time code is distinguished by the high-level time, according to the threshold judgment logic, combined with the high-level duration and the signal period obtained in step 1, set the pulse high-level duration judgment threshold:

[0082] Set the high-level time threshold range for the code element "1": T1,min ≤ Thigh ≤ T1,max;

[0083] Set the high-level time threshold range for the code element "0": T0,min ≤ Thigh ≤ T0,max;

[0084] Set the time threshold for the start code: Tstart,min ≤ Thigh ≤ Tstart,max;

[0085] It should be noted that the threshold determination logic implemented based on FPGA is as follows:

[0086] After each measurement of Thigh, compare its value:

[0087] If Thigh is within the range of symbol "1", store "1";

[0088] If Thigh falls within the range of symbol "0", store "0";

[0089] If Thigh falls within the range of the start code, store "start code";

[0090] If it exceeds all ranges, discard the data and trigger the error handling mechanism;

[0091] After that, use a finite state machine (FSM) to decode the B time code signal, and the processing flow is as follows:

[0092] IDLE state: Wait for the signal to enter the valid area;

[0093] SYNC state: Detect the synchronization frame header;

[0094] DECODE state: Parse 60-bit data and identify "0" / "1" according to the pulse width;

[0095] CHECKSUM state: Calculate the CRC checksum, verify the data correctness, and if it passes, store it in the FPGA time register, otherwise discard it;

[0096] Step 3: Maintain the time accuracy and correct the error based on the FPGA timing circuit;

[0097] Calculate the deviation between the decoded time and the clock, specifically according to the formula: ΔT = Tdecoded - Tsystem; where, Tdecoded represents the system time obtained after decoding the B time code, and Tsystem represents the current FPGA internal system time.

[0098] Based on the FPGA, perform stability judgment on the external time source and trigger the timing switching logic. When the external time source is lost, automatically switch to the FPGA timing circuit, and use a temperature-compensated crystal oscillator (TCXO) to maintain short-term time accuracy, provide a stable clock, and maintain time synchronization;

[0099] After the GPS or OCXO clock signal is restored, re-compare the decoded time and correct the error;

[0100] After that, the Exponential Moving Average (EMA) algorithm is adopted to smoothly adjust the decoding time, specifically according to the formula: Tadj = α × Tnew + (1 - α)Told, where α represents the smoothing factor, Tnew represents the time value measured in the latest measurement, and Told represents the time value saved in the previous time.

[0101] Step 4: Eliminate signal jitter through the PPS debounce circuit based on FPGA;

[0102] Obtain the PPS signal through the dedicated PPS input port of the FPGA;

[0103] Calculate the time deviation ΔTpps of consecutive multiple PPS pulses, and determine whether there is a jitter phenomenon. Specifically, according to the formula: ΔTpps = Tpps(i) - Tpps(i - 1), set the jitter deviation threshold Tp, and compare the time deviation ΔTpps with the jitter deviation threshold Tp. When the time deviation ΔTpps is greater than or equal to the jitter deviation threshold Tp, it indicates that there is a severe jitter phenomenon. At this time, after the input PPS signal is shaped by the buffer, the phase of the PPS signal is tracked by the Phase-Locked Loop (PLL) to stabilize the time output; and through time window filtering, eliminate the sudden deviation; when the time deviation ΔTpps is less than the jitter deviation threshold Tp, it indicates that there is no severe jitter phenomenon.

[0104] The present invention also proposes an efficient decoding system for B time code based on multi-frequency clock configuration, as Figure 1 shown, including: a clock identification and adaptation module, a clock error calculation and adjustment module, a B time code signal preprocessing module, and a B time code decoding and correction module, with signal connections between the modules;

[0105] The clock identification and adaptation module is mainly used to identify and adapt clock signals of different frequencies, generate a stable reference clock through the internal PLL of the FPGA, and calculate the input clock frequency;

[0106] The clock error calculation and adjustment module calculates the clock error and optimizes the clock frequency by dynamically adjusting the PLL configuration to ensure that the clock stability meets the decoding accuracy requirements;

[0107] The B time code signal preprocessing module performs matching degree judgment and envelope stability analysis on the received B time code signal, and extracts key information through filtering and zero-crossing detection;

[0108] The B time code decoding and correction module decodes the B time code using a finite state machine and corrects the decoding error through a timing circuit to ensure the time synchronization accuracy;

[0109] The above formulas are all dimensionless and take their numerical values for calculation. The formulas are obtained by collecting a large amount of data for software simulation to get a formula closest to the actual situation. The preset parameters in the formulas are set by those skilled in the art according to the actual situation.

[0110] The above embodiments can be implemented in whole or in part by software, hardware, firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product.

[0111] Those of ordinary skill in the art can realize that the modules and algorithm steps of each example described in combination with the embodiments disclosed in this article can be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and the inventive constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this application.

[0112] In addition, in each embodiment of this application, the functional modules can be integrated into one processing module, or each module can exist physically alone, or two or more modules can be integrated into one module.

[0113] As described above, the above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art within the technical scope disclosed in this application can easily think of changes or substitutions, which should all be covered within the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0114] Finally: The above is only the preferred embodiment of the present invention and is not used to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. An efficient decoding method for B time code based on multi-frequency clock configuration It is characterized in that it includes: Step 1: Identify clock sources adapted to different frequencies and classify them according to clock frequency stability; Step 2: Preprocess the B time code signal according to the priority; Step 3: Maintain time accuracy and correct errors based on the FPGA timekeeping circuit; Step 4: Eliminate signal jitter based on the FPGA PPS jitter elimination circuit; In Step 1, receive the clock signal, generate a stable reference clock, and calculate the input clock frequency; In Step 1, detect the rising edge time, falling edge time, and duty cycle deviation of the clock signal; weighted sum the rising and falling edge times and duty cycle deviation of the current clock frequency to determine the clock error S of the current clock frequency, set the error threshold Ys. If the clock error S of the current clock frequency is greater than or equal to the error threshold Ys, it indicates that the clock frequency belongs to an unstable clock frequency; if the clock error S of the current clock frequency is less than the error threshold Ys, it indicates that the clock frequency belongs to a stable clock frequency; In Step 1, define the maximum allowable deviation threshold Eb between the clock frequency and the reference clock; define the time window width T1, which is the stable time range required for B time code decoding, and set the time error Es: calculate the fluctuation amplitude Δf of the clock frequency and the standard deviation σ of the clock frequency; determine the clock frequency influence coefficient Ki, set the influence threshold Yk. If the influence coefficient Ki is greater than or equal to the influence threshold Yk, the PLL expands the clock frequency adjustment amplitude; if the influence coefficient Ki is less than the influence threshold Yk, the PLL reduces the clock frequency adjustment amplitude; Finally, send a clock frequency adjustment completion signal to notify the B time code decoding module to use the new clock frequency parameters to adapt to the B time code signal input with different clock frequencies.

2. The high-efficiency B time code decoding method based on multi-frequency clock configuration according to claim 1, characterized in that: In Step 2, obtain the matching degree between the B time code signal and the clock frequency and the envelope stability data, weighted sum the matching degree between the B time code signal and the clock frequency and the envelope stability data to determine the priority P of the B time code signal, and process the B time code signal from high to low according to the priority P of the B time code signal.

3. The high-efficiency B time code decoding method based on multi-frequency clock configuration according to claim 2, wherein: In Step 2, remove the high-frequency noise of the B time code signal; extract the key time information of the B time code signal; based on the threshold determination logic implemented by the FPGA, combine the high-level duration and signal period obtained in Step 1 to set the pulse high-level duration determination threshold; decode the B time code signal.

4. The high-efficiency B time code decoding method based on multi-frequency clock configuration according to claim 3, characterized in that: In Step 3, calculate the deviation between the decoded time and the clock. When the external time source is lost based on the FPGA, automatically switch to the FPGA timekeeping circuit and maintain time synchronization; after the clock signal is restored, re-compare the decoded time and correct the error.

5. The efficient B time code decoding method based on multi-frequency clock configuration according to claim 4, characterized in that; In Step 4, obtain the PPS signal; calculate the time deviation ΔTpps of consecutive multiple PPS pulses, set the jitter deviation threshold Tp. When the time deviation ΔTpps is greater than or equal to the jitter deviation threshold Tp, stable time output is required.

6. An efficient B time code decoding system based on multi-frequency clock configuration for implementing any one of the efficient B time code decoding methods based on multi-frequency clock configuration described in the above claims 1-5, characterized in that: It includes: A clock identification and adaptation module, a clock error calculation and adjustment module, a B time code signal preprocessing module, a B time code decoding and correction module, and the signals between the modules are connected; The clock recognition and adaptation module is mainly used to recognize and adapt clock signals of different frequencies, generate a stable reference clock through the PLL inside the FPGA, and calculate the input clock frequency; The clock error calculation and adjustment module calculates the clock error and optimizes the clock frequency by dynamically adjusting the PLL configuration to ensure that the clock stability meets the decoding accuracy requirements; The B time code signal preprocessing module judges the matching degree of the received B time code signal, analyzes the envelope stability, and extracts key information through filtering and zero-crossing detection; The B time code decoding and correction module decodes the B time code using a finite state machine and corrects the decoding error through a timing circuit to ensure the time synchronization accuracy.

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