Image compression and decompression method, system and equipment based on FPGA (Field Programmable Gate Array) and medium

Abstract

The invention discloses an image compression and decompression method, system and equipment based on an FPGA (Field Programmable Gate Array) and a medium, belongs to the technical field of digital image processing, and aims to solve the technical problems of low compression ratio, large image quality loss, low hardware implementation resource utilization rate, high power consumption and high cost in the existing image compression technology. According to the technical scheme, the method comprises the steps of image preprocessing, wherein a color image is converted into a grayscale image or an RGB color space is converted into a YCbCr color space, and a preprocessed image is obtained; haar wavelet transformation: performing Haar wavelet transformation on the preprocessed image, and extracting a low-frequency component and a high-frequency component of the image; convolution auto-encoder compression: inputting the image after Haar wavelet transform into a convolution auto-encoder for further compression, and obtaining a compressed image; and image decompression: decompressing the compressed image data to obtain a restored original image.

Description

Technical Field

[0001] The present invention relates to the technical field of digital image processing, and specifically to an image compression and decompression method, system, device and medium based on FPGA. Background Art

[0002] With the rapid development of digital technology, the proportion of images in the Internet and storage devices is increasing day by day. Whether it is daily photos, videos, or image data in professional fields such as medical images and satellite images, their quantity and scale are constantly expanding. However, a large amount of image data brings challenges in storage and transmission. Uncompressed image data occupies a large amount of storage space, increasing storage costs; during transmission, it also occupies a large amount of bandwidth, resulting in low transmission efficiency. Especially in the case of limited network bandwidth, the latency and jitter problems of image transmission seriously affect the user experience.

[0003] Traditional image compression methods such as JPEG can reduce the amount of image data to a certain extent, but there are certain limitations between the compression ratio and image quality. JPEG uses discrete cosine transform to process images, and some high-frequency information will be discarded during the quantization process, which may lead to obvious distortion of images at high compression ratios, such as block effect, detail loss and other problems. Although JPEG2000 has certain improvements in image quality and compression ratio, and uses technologies such as wavelet transform, it still cannot fully meet some application scenarios with strict requirements for image quality and compression efficiency.

[0004] In addition, there are also some deficiencies in the hardware implementation of existing image compression methods. Some software-based compression algorithms are highly flexible, but have high computational complexity and slow processing speed, and cannot meet the requirements of applications with high real-time requirements, such as real-time video monitoring, high-definition video transmission, etc. In terms of hardware implementation, some traditional hardware architectures have low resource utilization and high power consumption when processing image compression, and it is difficult to be applied in resource-constrained devices. Summary of the Invention

[0005] The technical task of the present invention is to provide an image compression and decompression method, system, device and medium based on FPGA to solve the problems of low compression ratio, large loss of image quality, low resource utilization and high power consumption in existing image compression technologies.

[0006] The technical task of the present invention is achieved in the following way. An image compression and decompression method based on FPGA is as follows:

[0007] Image preprocessing: Convert the color image into a grayscale image or convert the RGB color space into the YCbCr color space to obtain the preprocessed image;

[0008] Haar wavelet transform: Perform Haar wavelet transform on the preprocessed image to extract the low-frequency and high-frequency components of the image. Among them, the Haar wavelet transform realizes image downsampling and feature extraction by calculating the average value and difference of adjacent pixels, and obtains the image after Haar wavelet transform.

[0009] Convolutional autoencoder compression: Input the image after Haar wavelet transform into the convolutional autoencoder for further compression to obtain the compressed image.

[0010] Image decompression: Decompress the compressed image data to obtain the restored original image. Preferably, when converting a color image to a grayscale image, the grayscale formula is as follows:

[0011] Gray = 0.299×R + 0.587×G + 0.114×B;

[0012] Among them, R, G, and B respectively represent the pixel values of the red, green, and blue components;

[0013] When converting the RGB color space to the YCbCr color space, the YCbCr color space divides the image into a luminance component and a chrominance component, and the conversion formula is as follows:

[0014] Y = 0.299×R + 0.587×G + 0.114×B;

[0015] Cb = -0.1687×R - 0.3313×G + 0.5×B + 128;

[0016] Cr = 0.5×R - 0.4187×G - 0.0813×B + 128;

[0017] Among them, Y represents the luminance component; Cb and Cr represent the chrominance components.

[0018] Preferably, the Haar wavelet transform is as follows:

[0019] Horizontal direction transformation: For each row of pixels, calculate the average value and difference of adjacent pixels. Among them, the average value represents the low-frequency component of the image; the difference represents the high-frequency component of the image. Among them, the low-frequency component L of the image = 1 / 2(x 2i + x 2i+1 ); the high-frequency component H of the image = 1 / 2(x 2i - x 2i+1 ); x 2i and x 2i+1 are the values of adjacent pixels;

[0020] Vertical direction transformation: For each column of pixels, the average value and difference of adjacent pixels are also calculated, and finally four sub-bands are obtained, namely LL (low frequency - low frequency), LH (low frequency - high frequency), HL (high frequency - low frequency), and HH (high frequency - high frequency);

[0021] Threshold processing: To further reduce the data volume, threshold processing can be performed on the high-frequency components. Specifically, the high-frequency components less than the threshold are set to zero, thereby realizing data sparsification.

[0022] Preferably, the convolutional autoencoder includes an encoder and a decoder. The encoder compresses the image features through convolutional layers and pooling layers, and the decoder reconstructs the compressed features into an image through upsampling and convolutional layers;

[0023] Among them, the encoder includes an input layer, an encoding convolutional layer, an encoding activation layer, and a pooling layer; the input layer is used to receive the preprocessed image data; the encoding convolutional layer is used to perform a convolution operation on the preprocessed image input using a convolution kernel to extract the features of the image; the encoding activation layer is used to use the ReLU activation function to set negative values to zero and enhance the non-linear representation of the features; the pooling layer is used to reduce the size of the feature map through max pooling or average pooling to reduce the computational complexity;

[0024] The decoder includes an upsampling layer, a decoding convolutional layer, a decoding activation layer, and an output layer; the upsampling layer is used to restore the size of the feature map through an upsampling operation; the decoding convolutional layer is used to perform a convolution operation on the feature map using a convolution kernel to reconstruct the image features; the decoding activation layer is used to use the ReLU activation function to enhance the non-linear representation of the features; the output layer is used to output the reconstructed image data.

[0025] More preferably, the image decompression is specifically as follows:

[0026] Convolutional autoencoder decoding: Input the compressed image data into the decoder of the convolutional autoencoder, and reconstruct the image features through upsampling and convolution operations;

[0027] Inverse Haar wavelet transform: Perform an inverse Haar wavelet transform on the reconstructed image features to restore the pixel values of the original image;

[0028] Image post-processing: Convert the restored image data into the original format. Specifically, convert the grayscale image back to a color image or convert the YCbCr color space back to the RGB color space.

[0029] An FPGA-based image compression and decompression system, which includes:

[0030] A storage module for storing the input image data and the processed intermediate results;

[0031] Wavelet transform module, used to extract the low-frequency component and high-frequency component of an image through wavelet transform;

[0032] Convolutional autoencoder module, used to input the image after Haar wavelet transform into a convolutional autoencoder for further compression, obtain the compressed image, and then decompress the compressed image data to obtain the restored original image;

[0033] Data transmission module, used to transmit the processed image data to an external storage or display device.

[0034] Preferably, the storage module stores the input image data and the processed intermediate results through the Block RAM of the FPGA, converts the input image data into a one-dimensional array, and writes it into the Block RAM row by row;

[0035] The hardware logic for the wavelet transform module to implement Haar wavelet transform includes horizontal and vertical transforms; and uses the adder and shift operations of the FPGA to calculate the average value and difference value, thereby obtaining the low-frequency component and high-frequency component, and performing threshold processing on the high-frequency component to reduce the data volume.

[0036] More preferably, the convolutional autoencoder module uses the programmable logic of the FPGA to implement the encoding and decoding processes of the convolutional autoencoder; among them, the convolutional operations in the encoding and decoding processes are implemented through the multipliers and adders of the FPGA; the activation function (ReLU) in the encoding and decoding processes is implemented through the comparators of the FPGA; the upsampling operations in the encoding and decoding processes are implemented through the interpolation logic of the FPGA;

[0037] The data transmission module realizes the reading and writing of data, transmits the processed image data to an external storage or display device, and uses the transmission and reception model of the FPGA to realize the synchronous transmission of data.

[0038] An electronic device, comprising: a memory and at least one processor;

[0039] Wherein, a computer program is stored on the memory;

[0040] The at least one processor executes the computer program stored in the memory, so that the at least one processor executes the FPGA-based image compression and decompression method as described above.

[0041] A computer-readable storage medium, in which a computer program is stored, and the computer program can be executed by a processor to implement the FPGA-based image compression and decompression method as described above.

[0042] The image compression and decompression method, system, device, and medium based on FPGA of the present invention have the following advantages:

[0043] (1) By combining the advantages of Haar transform and autoencoder, the present invention designs a dynamic threshold compression mechanism, adaptively adjusts the quantization strategy according to the image content, and realizes efficient image compression and decompression on the FPGA platform. It solves the problems existing in the existing image compression technologies, such as low compression ratio, large loss of image quality, low utilization rate of hardware implementation resources, and high power consumption. It improves the image storage and transmission efficiency, while ensuring the image quality and reducing the hardware resource consumption and power consumption.

[0044] (2) The present invention combines hardware acceleration and deep learning. By implementing Haar wavelet transform and convolutional autoencoder on the FPGA, it makes full use of the hardware resources, improves the processing speed and energy efficiency; combines the advantages of Haar wavelet transform and convolutional autoencoder to achieve efficient image compression and decompression while maintaining high image quality; at the same time, it can be flexibly configured according to different application scenarios and requirements, and is applicable to a variety of image processing tasks.

[0045] (3) High-quality and high-efficiency compression: By combining Haar wavelet transform and convolutional autoencoder, the present invention realizes efficient image compression and decompression while maintaining high image quality, significantly reducing the image storage space and transmission bandwidth.

[0046] (4) Low power consumption and low resource occupancy: The present invention makes full use of the parallel processing ability and hardware resources of the FPGA, and the power consumption of the entire system is significantly reduced, which is suitable for embedded systems.

[0047] (5) Strong adaptability: The present invention has a configurable architecture, can adjust parameters according to different application requirements, so as to adapt to the image compression requirements in various application scenarios; the dynamic threshold mechanism can optimize the compression effect for different image contents, and can be applicable to different fields such as static images, video compression, image enhancement, image denoising, and image super-resolution.

[0048] (6) End-to-end low latency: The present invention adopts FPGA hardware acceleration, with faster processing speed, which can significantly reduce the processing latency of image compression and decompression and ensure real-time requirements.

[0049] (7) Aiming at the problems existing in the current image compression and decompression, such as low compression ratio, large loss of image quality, low utilization rate of hardware implementation resources, and high power consumption, the present invention designs a dynamic threshold compression mechanism by combining the advantages of Haar transform and autoencoder, adaptively adjusts the quantization strategy according to the image content, and realizes efficient image compression and decompression on the FPGA platform, improves the image storage and transmission efficiency, while ensuring the image quality and reducing the hardware resource consumption and power consumption.

[0050] (8) The present invention has the characteristics of high efficiency, excellent quality, low power consumption, less resource occupation, strong self - adaptability, low latency, and easy implementation. It can be applied in a wide range of fields and has high practicality and promotion value. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The present invention will be further described below in conjunction with the drawings.

[0052] FIG Figure 1 is a flowchart of the image compression and decompression method based on FPGA;

[0053] FIG Figure 2 is a flowchart of the implementation of the wavelet transform module;

[0054] FIG Figure 3 is a block diagram of the implementation of Haar low - pass and high - pass filters;

[0055] FIG Figure 4 is a block diagram of the implementation of threshold compression;

[0056] FIG Figure 5 is a block diagram of the implementation of sending and receiving;

[0057] FIG Figure 6 is a flowchart of the implementation of auto - encoding compression. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0058] The method, system, device, and medium for image compression and decompression based on FPGA of the present invention will be described in detail below with reference to the accompanying drawings of the specification and specific embodiments.

[0059] Embodiment 1:

[0060] As shown in FIG Figure 1 This embodiment provides a method for image compression and decompression based on FPGA, and the method is as follows:

[0061] S1. Image pre - processing: Convert the color image into a grayscale image or convert the RGB color space into the YCbCr color space to obtain the pre - processed image;

[0062] S2. Haar wavelet transform: Perform Haar wavelet transform on the pre - processed image to extract the low - frequency component and high - frequency component of the image; among them, the Haar wavelet transform realizes the down - sampling and feature extraction of the image by calculating the average value and difference of adjacent pixels, and obtains the image after Haar wavelet transform;

[0063] S3. Convolutional auto - encoder compression: Input the image after Haar wavelet transform into the convolutional auto - encoder for further compression to obtain the compressed image;

[0064] S4. Image decompression: Decompress the compressed image data to obtain the restored original image.

[0065] When converting the color image in step S1 of this embodiment into a grayscale image, the grayscale formula is specifically as follows:

[0066] Gray = 0.299×R + 0.587×G + 0.114×B;

[0067] Among them, R, G, and B respectively represent the pixel values of the red, green, and blue components;

[0068] When converting the RGB color space into the YCbCr color space, the YCbCr color space divides the image into a luminance component and a chrominance component, and the conversion formula is specifically as follows:

[0069] Y = 0.299×R + 0.587×G + 0.114×B;

[0070] Cb = -0.1687×R - 0.3313×G + 0.5×B + 128;

[0071] Cr = 0.5×R - 0.4187×G - 0.0813×B + 128;

[0072] Among them, Y represents the luminance component; Cb and Cr represent the chrominance components.

[0073] The Haar wavelet transform in step S2 of this embodiment is specifically as follows:

[0074] S201. Horizontal direction transformation: For each row of pixels, calculate the average value and difference of adjacent pixels; among them, the average value represents the low-frequency component of the image; the difference represents the high-frequency component of the image; among them, the low-frequency component L of the image = 1 / 2(x 2i + x 2i+1 ); the high-frequency component H of the image = 1 / 2(x 2i - x 2i+1 ); x 2i and x 2i+1 are the values of adjacent pixels;

[0075] S202. Vertical direction transformation: For each column of pixels, also calculate the average value and difference of adjacent pixels, and finally obtain four sub-bands, namely LL (low frequency - low frequency), LH (low frequency - high frequency), HL (high frequency - low frequency), and HH (high frequency - high frequency);

[0076] S203. Threshold processing: In order to further reduce the data volume, threshold processing can be performed on the high-frequency components, specifically: the high-frequency components less than the threshold are set to zero, so as to achieve data sparsification.

[0077] As attachedFigure 2 As shown, the wavelet compression component performs Haar transform and threshold compression on the pixel values stored in the read-only memory component, and writes the values into the random access memory component. The image passes through the Haar filter, and the obtained values are threshold compressed to obtain sub-bands. As attached Figure 3 As shown, in the Haar filter, for the low-pass filter, half of the average of consecutive input samples is calculated, the previous value is added to the current value, and then downsampling by a factor of 2 is achieved through a right shift operation. For the high-pass filter, half of the difference between the current value and the previous value is calculated, and signed subtraction of the current value and the previous value is performed through a right shift operation, and downsampling by a factor of 2 is achieved.

[0078] As attached Figure 4 As shown, during threshold compression, by checking the most significant bit (MSB) to determine whether the pixel value is negative. If the MSB is 1, the pixel value is negative, otherwise the pixel value is positive. Then the pixel value is compared with the threshold through a comparator. In the FPGA, values less than the threshold are reduced to zero, while values greater than the threshold are used as the output of wavelet compression. The comparator used here is an 8-bit unsigned absolute value comparator, which is composed of a carry-serial adder and a binary complement.

[0079] As attached Figure 5 As shown, in the case of sending and receiving, when a new data byte is requested from the memory, the request_new_data signal is set high. The transmitter sets the current address on the address bus and indicates that the data is ready by setting the out_data_ready signal high. The receiver should set the request_new_data signal low, process the data, and then set it high again. The current address is implemented by a counter, and the counter is incremented by 1 each time a data byte is sent. Once all the content in the memory has been sent, the transmitter sets the finished_transmitting signal high to inform the receiver that there is no more data to receive.

[0080] The convolutional autoencoder in step S3 of this embodiment includes an encoder and a decoder. The encoder compresses the image features through convolutional layers and pooling layers, and the decoder reconstructs the compressed features into an image through upsampling and convolutional layers;

[0081] Among them, the encoder includes an input layer, an encoding convolutional layer, an encoding activation layer, and a pooling layer; the input layer is used to receive the preprocessed image data; the encoding convolutional layer is used to perform a convolution operation on the input preprocessed image using a convolution kernel to extract the features of the image; the encoding activation layer is used to use the ReLU activation function to set negative values to zero and enhance the non-linear representation of the features; the pooling layer is used to reduce the size of the feature map through max pooling or average pooling and reduce the computational complexity;

[0082] The decoder includes an upsampling layer, a decoding convolutional layer, a decoding activation layer, and an output layer; the upsampling layer is used to restore the size of the feature map through upsampling operations; the decoding convolutional layer is used to perform convolutional operations on the feature map using convolutional kernels to reconstruct image features; the decoding activation layer is used to use the ReLU activation function to enhance the non-linear representation of features; the output layer is used to output the reconstructed image data.

[0083] As shown in the Figure 6 appendix, during the auto-encoding compression process, a two-dimensional convolutional layer generates a convolutional kernel, which is combined with the input to generate an output tensor. If the "use bias" option is set to True, a bias vector will be generated and connected to the output. If the activation parameter is set to a value other than None, the output will also be affected. Max pooling is used to reduce the number of features in the output feature map of the convolutional layer, and reducing the number of features can reduce the training computation. Upsampling is because real-world datasets may be severely imbalanced, which can affect the effectiveness of statistical methods and machine learning models. Therefore, upsampling means adding data samples to the minority class to generate a more balanced dataset. The Adam algorithm is used to optimize the model, which is a stochastic gradient descent method based on adaptive estimation of first and second moments. Model fitting means training the model for a fixed number of epochs. An epoch represents the number of times a machine learning algorithm runs on the complete training dataset, and the cutoff value is set to 2000. The final prediction output is in Keras, and various calculations are executed in batches to help us predict the results.

[0084] The image decompression in step S4 of this embodiment is specifically as follows:

[0085] S401. Decoding by the convolutional auto-encoder: Input the compressed image data into the decoder of the convolutional auto-encoder, and reconstruct the image features through upsampling and convolutional operations;

[0086] S402. Inverse Haar wavelet transform: Perform an inverse Haar wavelet transform on the reconstructed image features to restore the pixel values of the original image;

[0087] S403. Image post-processing: Convert the restored image data into the original format, specifically: restore the grayscale image to a color image or convert the YCbCr color space back to the RGB color space.

[0088] To verify the effectiveness of this embodiment, a system test was conducted in this embodiment, and the peak signal-to-noise ratio and mean squared error were used to evaluate the images. The results show that these two values measured in this embodiment achieved better results for most images, and had obvious advantages in terms of compression ratio. And the hardware acceleration implemented by FPGA significantly improved the processing speed. Therefore, this embodiment is superior to traditional image compression methods in terms of image quality, compression ratio, and processing speed.

[0089] Therefore, by combining the advantages of Haar transform and autoencoder, efficient image compression and decompression are realized on the FPGA platform, improving image storage and transmission efficiency, while ensuring image quality, reducing hardware resource consumption and power consumption. It has a configurable architecture and a dynamic threshold mechanism, which can adapt to different application requirements and scenarios, and has high practicality and promotion value.

[0090] Example 2:

[0091] This embodiment provides an FPGA-based image compression and decompression system, which includes:

[0092] A storage module for storing input image data and processed intermediate results;

[0093] A wavelet transform module for extracting the low-frequency and high-frequency components of an image through wavelet transform;

[0094] A convolutional autoencoder module for inputting the image after Haar wavelet transform into the convolutional autoencoder for further compression to obtain the compressed image, and then decompressing the compressed image data to obtain the restored original image;

[0095] A data transmission module for transmitting the processed image data to an external storage or display device.

[0096] In this embodiment, the storage module stores the input image data and processed intermediate results through the Block RAM of the FPGA, and converts the input image data into a one-dimensional array and writes it into the Block RAM row by row.

[0097] The hardware logic for implementing Haar wavelet transform in this embodiment's wavelet transform module includes horizontal and vertical transforms; and uses the adder and shift operations of the FPGA to calculate the average value and difference, thereby obtaining the low-frequency and high-frequency components, and performing threshold processing on the high-frequency components to reduce the data volume.

[0098] The convolutional autoencoder module in this embodiment uses the programmable logic of the FPGA to implement the encoding and decoding processes of the convolutional autoencoder; among them, the convolutional operations in the encoding and decoding processes are implemented through the multiplier and adder of the FPGA; the activation function (ReLU) in the encoding and decoding processes is implemented through the comparator of the FPGA; the upsampling operation in the encoding and decoding processes is implemented through the interpolation logic of the FPGA.

[0099] The data transmission module in this embodiment realizes data reading and writing, transmits the processed image data to an external storage or display device, and uses the transmission and reception model of the FPGA to realize synchronous data transmission.

[0100] Example 3:

[0101] This embodiment also provides an electronic device, including: a memory and a processor;

[0102] Wherein, the memory stores computer-executable instructions;

[0103] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the FPGA-based image compression and decompression method in any embodiment of the present invention.

[0104] The processor may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor may be a microprocessor or the processor may also be any conventional processor, etc.

[0105] The memory can be used to store computer programs and / or modules. The processor realizes various functions of the electronic device by running or executing the computer programs and / or modules stored in the memory, and by calling the data stored in the memory. The memory mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system, application programs required for at least one function, etc.; the data storage area can store data created according to the use of the terminal, etc. In addition, the memory may further include a high-speed random access memory, and may also include a non-volatile memory, such as a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash memory card, at least one magnetic disk storage period, a flash memory device, or other volatile solid-state storage devices.

[0106] Embodiment 4:

[0107] This embodiment also provides a computer-readable storage medium, in which multiple instructions are stored. The instructions are loaded by the processor, so that the processor executes the FPGA-based image compression and decompression method in any embodiment of the present invention. Specifically, a system or device equipped with a storage medium may be provided. Software program codes for implementing the functions in any one of the above embodiments are stored on the storage medium, and the computer (or CPU or MPU) of the system or device reads and executes the program codes stored in the storage medium.

[0108] In this case, the program code read from the storage medium itself can implement the functions of any one of the above embodiments. Therefore, the program code and the storage medium storing the program code constitute a part of the present invention.

[0109] Examples of storage media for providing program code include floppy disks, hard disks, magneto-optical disks, optical disks (such as CD-ROM, CD-R, CD-RW, DVD-ROM, DVD-RYM, DVD-RW, DVD+RW), magnetic tapes, non-volatile memory cards, and ROM. Optionally, the program code can be downloaded from a server computer via a communication network.

[0110] In addition, it should be clear that not only can the functions of any one of the above embodiments be realized by executing the program code read by the computer, but also by causing the operating system or the like operating on the computer based on the instructions of the program code to complete part or all of the actual operations.

[0111] Furthermore, it can be understood that the program code read from the storage medium is written into the memory provided in the expansion board inserted into the computer or into the memory provided in the expansion unit connected to the computer, and then based on the instructions of the program code, the CPU or the like installed on the expansion board or the expansion unit is caused to execute part and all of the actual operations, thereby realizing the functions of any one of the above embodiments.

[0112] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An image compression and decompression method based on FPGA, characterized in that: The method is as follows: Image preprocessing: converting a color image into a grayscale image or converting an RGB color space into a YCbCr color space to obtain a preprocessed image; Haar wavelet transform: Perform Haar wavelet transform on the preprocessed image to extract the low-frequency and high-frequency components of the image. The Haar wavelet transform calculates the average and difference of adjacent pixels to achieve image downsampling and feature extraction, and obtains the image after Haar wavelet transform. Convolutional autoencoder compression: The image after Haar wavelet transform is input into the convolutional autoencoder for further compression to obtain the compressed image; Image decompression: Decompress the compressed image data to obtain the restored original image.

2. The FPGA-based image compression and decompression method according to claim 1, characterized in that: When a color image is converted to a grayscale image, the grayscale formula is as follows: Gray=0.299×R+0.587×G+0.114×B; Among them, R, G, and B represent the pixel values ​​of red, green, and blue components respectively; When the RGB color space is converted to the YCbCr color space, the YCbCr color space divides the image into brightness components and chrominance components. The conversion formula is as follows: Y=0.299×R+0.587×G+0.114×B; Cb=-0.1687×R-0.3313×G+0.5×B+128; Cr=0.5×R-0.4187×G-0.0813×B+128; Among them, Y represents the brightness component; Cb and Cr represent the chrominance components.

3. The FPGA-based image compression and decompression method according to claim 1, characterized in that: The Haar wavelet transform is as follows: Horizontal transformation: For each row of pixels, calculate the average and difference of adjacent pixels; the average represents the low-frequency component of the image; the difference represents the high-frequency component of the image; the low-frequency component of the image L = 1 / 2 (x 2i +x 2i+1 ); the high frequency component of the image H = 1 / 2 (x 2i -x 2i+1 ); x 2i and x 2i+1 is the value of the neighboring pixel; Vertical transformation: For each column of pixels, the average and difference of adjacent pixels are calculated, and finally four sub-bands are obtained, namely LL, LH, HL and HH; Threshold processing: Threshold processing is performed on high-frequency components. Specifically, high-frequency components less than the threshold are set to zero, thereby achieving data sparseness.

4. The FPGA-based image compression and decompression method according to claim 1, characterized in that: The convolutional autoencoder consists of an encoder and a decoder. The encoder compresses image features through convolutional layers and pooling layers, and the decoder reconstructs the compressed features into an image through upsampling and convolutional layers. The encoder includes an input layer, an encoding convolution layer, an encoding activation layer and a pooling layer; the input layer is used to receive preprocessed image data; the encoding convolution layer is used to use a convolution kernel to perform a convolution operation on the input preprocessed image to extract image features; the encoding activation layer is used to use a ReLU activation function to set negative values ​​to zero and enhance the nonlinear representation of features; the pooling layer is used to reduce the size of the feature map through maximum pooling or average pooling to reduce computational complexity; The decoder includes an upsampling layer, a decoding convolution layer, a decoding activation layer and an output layer; the upsampling layer is used to restore the size of the feature map through upsampling operations; the decoding convolution layer is used to perform convolution operations on the feature map using convolution kernels to reconstruct image features; the decoding activation layer is used to use the ReLU activation function to enhance the nonlinear representation of features; the output layer is used to output the reconstructed image data.

5. The FPGA-based image compression and decompression method according to any one of claims 1 to 4, characterized in that: Image decompression is as follows: Convolutional autoencoder decoding: The compressed image data is input into the decoder of the convolutional autoencoder, and the image features are reconstructed through upsampling and convolution operations; Inverse Haar wavelet transform: Perform inverse Haar wavelet transform on the reconstructed image features to restore the pixel values ​​of the original image; Image post-processing: converting the restored image data to the original format, specifically: restoring the grayscale image to a color image or converting the YCbCr color space back to the RGB color space.

6. An image compression and decompression system based on FPGA, characterized in that: The system includes: A storage module, used for storing input image data and processed intermediate results; A wavelet transform module, used for extracting low-frequency components and high-frequency components of an image through wavelet transform; The convolutional autoencoder module is used to input the image after Haar wavelet transformation into the convolutional autoencoder for further compression to obtain the compressed image, and then decompress the compressed image data to obtain the restored original image; The data transmission module is used to transmit the processed image data to an external storage or display device.

7. The FPGA-based image compression and decompression system according to claim 6, characterized in that: The storage module stores the input image data and the processed intermediate results through the Block RAM of the FPGA, converts the input image data into a one-dimensional array, and writes it into the Block RAM line by line; The wavelet transform module implements the hardware logic of Haar wavelet transform including horizontal and vertical transformations; and uses the adder and shift operation of FPGA to calculate the average value and the difference, thereby obtaining the low-frequency component and the high-frequency component, performing threshold processing on the high-frequency component, and reducing the amount of data.

8. The FPGA-based image compression and decompression system according to claim 6 or 7, characterized in that: The convolutional autoencoder module uses the programmable logic of the FPGA to implement the encoding and decoding process of the convolutional autoencoder; wherein the convolution operation in the encoding and decoding process is implemented by the multiplier and adder of the FPGA; the activation function in the encoding and decoding process is implemented by the comparator of the FPGA; the upsampling operation in the encoding and decoding process is implemented by the interpolation logic of the FPGA; The data transmission module realizes the reading and writing of data, transmits the processed image data to an external storage or display device, and uses the transmission and reception model of the FPGA to realize the synchronous transmission of data.

9. An electronic device, characterized in that: include: memory and at least one processor; Wherein, the memory stores a computer program; The at least one processor executes the computer program stored in the memory, so that the at least one processor performs the FPGA-based image compression and decompression method according to any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which can be executed by a processor to implement the FPGA-based image compression and decompression method according to any one of claims 1 to 5.

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