Layout patterns for static random access memory
By designing diffusion regions with opposite electrical properties and step gate structures in SRAM, the problem of charge accumulation affecting transistor electrical properties is solved, and the yield of the product and the yield of the production process is improved.
Patent Information
- Application Number
- CN202311732883.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-11-29
- Filing Date
- 2023-12-15
- Publication Date
- 2025-06-03
AI Technical Summary
In static random access memory (SRAM), charge accumulated under the gate structure affects the electrical properties of the transistor, resulting in a decrease in product yield.
An improved SRAM layout pattern is designed with electrically opposite diffusion regions located below the gate of the transistor and releasing charge through the contact structure. At the same time, the gate structure is designed in a stepped shape to avoid the distance between adjacent gates too close, staggering word lines contact and diffusion regions, and reducing rounding of the pattern.
Through the design of the diffusion zone, the impact of charge accumulation on the electrical properties of the transistor is avoided and the product yield is improved. The step-shaped gate structure further improves the yield of the manufacturing process.
Smart Images
Figure CN120091556A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a static random access memory (SRAM), and more particularly to a layout pattern of a static random access memory (SRAM) having an L-shaped gate structure and body contact. Background Art
[0002] In an embedded static random access memory (embedded SRAM), it includes a logic circuit and a static random access memory connected to the logic circuit. The static random access memory itself is a type of volatile memory cell, that is, when the power supplied to the static random access memory disappears, the stored data will be erased simultaneously. The static random access memory stores data by using the conductive state of transistors in the memory cell. The design of the static random access memory is based on mutually coupled transistors, without the problem of capacitor discharge, and does not require continuous charging to maintain data non-loss, that is, no memory update operation is required. This is different from the way of storing data by using the charged state of capacitors in the dynamic random access memory (DRAM), which is also a volatile memory. The access speed of the static random access memory is quite fast, so it has applications such as being used as a cache memory in a computer system. Summary of the Invention
[0003] The present invention provides a layout pattern of a static random-access memory (SRAM), including a substrate, a plurality of diffusion regions located on the substrate, each diffusion region at least including a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region, a plurality of gate structures located on the substrate, each gate structure extending along a first direction (X direction) and spanning a plurality of diffusion regions to form a plurality of transistors, wherein the plurality of transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1), and a second access transistor (PG2). Among them, a first gate structure is included in the plurality of gate structures. From a top view, the first gate structure has a stepped shape, and the first gate structure spans the first diffusion region and the second diffusion region and forms the first access transistor (PG1), wherein the first diffusion region and the second diffusion region are adjacent and in direct contact.
[0004] The present invention is characterized in that an improved layout pattern of a static random access memory is proposed, which includes some diffusion regions with opposite electrical properties, beside the diffusion regions under the gates of each transistor. In this way, the charges accumulated under the gate structure can flow out through the diffusion regions, and then the charges are released through the contact structure, avoiding affecting the electrical properties of the transistors and improving the product yield. In addition, the gate structure is designed to be stepped (viewed from the top view), which has improvements such as avoiding the adjacent gates being too close, staggering the word line contact from the diffusion region, and reducing the rounding of the pattern. Therefore, the manufacturing process yield can be improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0005] Figure 1 is a circuit diagram of an SRAM cell;
[0006] Figure 2 is a schematic cross-sectional structure diagram of a transistor;
[0007] Figure 3 is a layout diagram of a static random access memory (SRAM) cell according to a first preferred embodiment of the present invention;
[0008] Figure 4A is Figure 3 an enlarged schematic diagram of the first gate structure G1 and the nearby region in
[0009] Figure 4B is an enlarged schematic diagram of the first gate structure G1 and the nearby region in another embodiment;
[0010] Figures 5 to 7 is a layout diagram of a static random access memory (SRAM) cell according to a first preferred embodiment of the present invention.
[0011] SYMBOL DESCRIPTION
[0012] 10: Static random access memory (SRAM) cell
[0013] 12: Substrate
[0014] 12A: Silicon layer
[0015] 12B: Insulating layer
[0016] 12C: Silicon layer
[0017] 14: Gate dielectric layer
[0018] 16: Depletion region
[0019] 18: Region
[0020] BCT1: First body contact
[0021] BCT2: Second Substrate Contact
[0022] BLCT: Bit Line Contact
[0023] BL1: Bit Line
[0024] BL2: Bit Line
[0025] C: Corner Portion
[0026] CONT: Contact Structure
[0027] N + -DIFF: N-Type Diffusion Region
[0028] N-well: N-Type Well
[0029] P + -DIFF: P-Type Diffusion Region
[0030] P-well: P-Type Well
[0031] D1: First Diffusion Region
[0032] D2: Second Diffusion Region
[0033] D3: Third Diffusion Region
[0034] D4: Fourth Diffusion Region
[0035] D5: Fifth Diffusion Region
[0036] D6: Sixth Diffusion Region
[0037] D7: Seventh Diffusion Region
[0038] D8: Eighth Diffusion Region
[0039] Dr: Drain
[0040] E1: First Side
[0041] E2: Second Side
[0042] E3: Third Side
[0043] E4: Fourth Side
[0044] E5: Fifth Side
[0045] POLY: Gate Structure
[0046] G1: First Gate Structure
[0047] G2: Second Gate Structure
[0048] G3: Third Gate Structure
[0049] G4: Fourth Gate Structure
[0050] L1: Length
[0051] L2: Length
[0052] M1: First Metal Layer
[0053] M2: Second Metal Layer
[0054] M3: Third Metal Layer
[0055] NCT: Node Contact
[0056] N1: Storage Node
[0057] N2: Storage Node
[0058] O: Center Point
[0059] P1: First Part
[0060] P2: Second Part
[0061] PU1: First Pull - up Transistor
[0062] PU2: Second Pull - up Transistor
[0063] PD1: First Pull - down Transistor
[0064] PD2: Second Pull - down Transistor
[0065] PG1: First Access Transistor
[0066] PG2: Second Access Transistor
[0067] R: Region
[0068] Sr: Source
[0069] STI: Shallow Trench Isolation
[0070] V1: First Vertical Contact
[0071] V2: Second Vertical Contact
[0072] Vcc: Voltage Source
[0073] Vss: Voltage Source
[0074] VssCT: Vss Voltage Source Contact
[0075] WL: Word Line
[0076] WLCT: Word Line Contact Detailed Implementation Manner
[0077] To enable those of ordinary skill in the art to which the present invention pertains to further understand the present invention, the preferred embodiments of the present invention are specifically enumerated below, and in conjunction with the accompanying drawings, the composition and the intended effects of the present invention are described in detail.
[0078] For convenience of description, the accompanying drawings of the present invention are only schematic for easier understanding of the present invention, and their detailed proportions can be adjusted according to the design requirements. Regarding the up and down relationships of the relative components in the figures described in the text, those skilled in the art should understand that it refers to the relative positions of the objects, so they can all be flipped to present the same components, and this should all fall within the scope disclosed in this specification. This is hereby stated first.
[0079] Please refer to Figure 1 , Figure 1 , which shows the circuit diagram of a static random access memory (SRAM) cell of the present invention. In this embodiment, an SRAM cell 10 preferably consists of a first pull-up transistor (Pull-Up device) PU1, a second pull-up transistor PU2, a first pull-down transistor (Pull-Down device) PD1, a second pull-down transistor PD2, a first access transistor (pass gate device) PG1, and a second access transistor PG2 to form a flip-flop. Among them, the first pull-up transistor PU1 and the second pull-up transistor PU2, and the first pull-down transistor PD1 and the second pull-down transistor PD2 form a latch circuit (latch), enabling data to be latched at the storage nodes (Storage Node) N1 or N2. In addition, the first pull-up transistor PU1 and the second pull-up transistor PU2 are used as active loads, and they can also be replaced by ordinary resistors as pull-up transistors. In this case, it is a four-transistor static random access memory (four-device SRAM, 4T-SRAM). In addition, in this embodiment, a source region of each of the first pull-up transistor PU1 and the second pull-up transistor PU2 is electrically connected to a voltage source Vcc, and a source region of each of the first pull-down transistor PD1 and the second pull-down transistor PD2 is electrically connected to a voltage source Vss.
[0080] In one embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 of the SRAM cell 10 are composed of P-type metal oxide semiconductor (PMOS) transistors, while the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, and the second access transistor PG2 are composed of N-type metal oxide semiconductor (NMOS) transistors. However, the present invention is not limited thereto. Among them, the first pull-up transistor PU1 and the first pull-down transistor PD1 together form an inverter, and the two ends of the series circuit formed by the two are respectively coupled to a voltage source Vcc and a voltage source Vss. Similarly, the second pull-up transistor PU2 and the second pull-down transistor PD2 form another inverter, and the two ends of the series circuit formed by the two are also respectively coupled to the voltage source Vcc and the voltage source Vss. The above two inverters are coupled to each other to store data.
[0081] In addition, at the storage node N1, the gates of the second pull-down transistor PD2 and the second pull-up transistor PU2, and the drains of the first pull-down transistor PD1, the first pull-up transistor PU1, and the first access transistor PG1 are electrically connected respectively; similarly, at the storage node N2, the gates of the first pull-down transistor PD1 and the first pull-up transistor PU1, and the drains of the second pull-down transistor PD2, the second pull-up transistor PU2, and the second access transistor PG2 are electrically connected respectively. As for the gates of the first access transistor PG1 and the second access transistor PG2, they are respectively coupled to the word line WL, and the sources of the first access transistor PG1 and the second access transistor PG2 are respectively coupled to the corresponding bit lines BL1 and BL2.
[0082] In this embodiment, as Figure 1 shown, the substrate of the first pull-down transistor PD1 is connected to the substrate of the first access transistor PG1 and is commonly connected to the voltage source Vss. Similarly, the substrate of the second pull-down transistor PD2 is connected to the substrate of the second access transistor PG2 and is commonly connected to the voltage source Vss. In this way, it can be avoided that the charges stored in the substrate of the pull-down transistors PD1, PD2 and the access transistors PG1, PG2 affect the electrical properties of the transistors, which will be described in detail in the following paragraphs.
[0083] The SRAM cell 10 includes six transistors, and thus can be referred to as a six-transistor static random access memory (6T-SRAM). However, the SRAM cell of the present invention is not limited to using 6T-SRAM, and other SRAM patterns with more transistors, such as 8T-SRAM and 10T-SRAM, can also be used as the SRAM cell of the present invention.
[0084] When a transistor is formed on a silicon-on-insulator (SOI) substrate, some charges may accumulate under the gate structure and be trapped, and the accumulated charges may cause electrical instability in the transistor. Figure 2 A schematic diagram of a cross-sectional structure of a transistor is shown. Figure 2 As shown, the substrate 12 is a SOI substrate, which includes a silicon layer 12A, an insulating layer 12B and a silicon layer 12C stacked from bottom to top, a gate structure POLY is located on the substrate 12, a gate dielectric layer 14 is included between the gate structure POLY and the substrate 12, the substrate on both sides of the gate structure includes a source Sr and a drain Dr respectively, and a shallow trench isolation (STI) is located outside the source Sr and the drain Dr. A depletion region 16 is included below the gate structure POLY and between the source Sr and the drain Dr. However, there is a region 18 below the depletion region 16, located between the depletion region 16 and the insulating layer 12B, and some charges may be accumulated in the region 18, but these charges cannot be discharged from the region 18, and the charges accumulated in the region 18 may affect the electrical properties of the transistor.
[0085] To solve the above problems, in some embodiments, the diffusion regions under the pull-down transistors PD1 and PD2 and the access transistors PG1 and PG2 are extended so that the charges under the gate can be led out and released through the diffusion regions. Details will be described in the following paragraphs.
[0086] Figure 3 FIG. 1 is a layout diagram of a static random access memory (SRAM) cell according to a first preferred embodiment of the present invention. In this embodiment, the static random access memory cell 10 is located in a region R and is disposed on a substrate 12, such as a silicon-on-insulator (SOI) substrate, and a plurality of N-type diffusion regions N are disposed on the substrate 12. + -DIFF and P-type diffusion area P + -DIFF, hereinafter collectively referred to as diffusion region DIFF, and shallow trench isolation STI is provided around each diffusion region DIFF.
[0087] In addition, a plurality of gate structures POLY are included on the substrate 12. Each of the above transistors (including the first pull-up transistor PU1, the second pull-up transistor PU2, the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, and the second access transistor PG2) includes a gate structure G spanning over at least one diffusion region DIFF to form each transistor.
[0088] As Figure 3 shown, in order to clearly define the positions of the gate structures POLY and the diffusion regions DIFF, the gate structure POLY is divided into a first gate structure G1, a second gate structure G2, a third gate structure G3, and a fourth gate structure G4, and the diffusion region D is also divided into a first diffusion region D1, a second diffusion region D2, a third diffusion region D3, a fourth diffusion region D4, a fifth diffusion region D5, a sixth diffusion region D6, a seventh diffusion region D7, and an eighth diffusion region D8. Among them, the first gate structure G1 spans over the first diffusion region D1 to form the first access transistor PG1; the second gate structure G2 spans over the first diffusion region D1 to form the first pull-down transistor PD1; the second gate structure G2 spans over the fourth diffusion region D4 to form the first pull-up transistor PU1; the third gate structure G3 spans over the fifth diffusion region D5 to form the second access transistor PG2; the fourth gate structure G4 spans over the fifth diffusion region D5 to form the second pull-down transistor PD2; the fourth gate structure G4 spans over the eighth diffusion region D8 to form the second pull-up transistor PU2. It can be understood that the first gate structure G1, the second gate structure G2, the third gate structure G3, and the fourth gate structure G4 all belong to the gate structure G, and the first diffusion region D1, the second diffusion region D2, the third diffusion region D3, the fourth diffusion region D4, the fifth diffusion region D5, the sixth diffusion region D6, the seventh diffusion region D7, and the eighth diffusion region D8 all belong to the diffusion region DIFF. In the present invention, the first gate structure G1, the second gate structure G2, the third gate structure G3, and the fourth gate structure G4 are preferably arranged along a first direction (for example, the X-axis direction).
[0089] In addition, in this embodiment, the end (the end close to the first pull-down transistor PD1) of the second gate structure G2 is designed in an L shape, that is, the end of the second gate structure G2 has a protruding portion. Similarly, the end (the end close to the second pull-down transistor PD2) of the fourth gate structure G4 is also designed in an L shape, that is, the end of the fourth gate structure G4 has a protruding portion. However, the present invention is not limited thereto. In other embodiments of the present invention, the second gate structure G2 and the fourth gate structure G4 can also be designed in different shapes according to requirements, such as a straight bar shape, etc., which all fall within the scope of the present invention.
[0090] Within region R, there are also multiple metal layers (not shown in the figure) and contact structure CONT. The metal layers and contact structure V are mainly used to electrically connect each transistor to other components, such as word lines, bit lines, voltage sources, or to connect storage nodes as the interconnection structure of the transistors. The materials of the metal layers and contact posts CT are, for example, metals, and the two may have the same material. For the sake of simplicity of the drawings, Figure 3 the positions of some metal layers are not shown in the figure. However, for a clearer illustration, in Figure 3 the transistors, word lines, bit lines, voltage sources, etc. connected to each component are marked beside the respective components in the figure to clearly show the connection relationships of the components.
[0091] In addition, in Figure 3 the embodiment, since the first pull-down transistor PD1, the second pull-down transistor PD2, the first access transistor PG1, and the second access transistor PG2 are composed of N-type metal oxide semiconductor transistors, the diffusion regions DIFF spanned by them are also N-type doped diffusion regions and are located on the P-type well (P-well) of the substrate 12. Conversely, since the first pull-up transistor PU1 and the second pull-up transistor PU2 are composed of P-type metal oxide semiconductor transistors, the diffusion regions DIFF spanned by them are also P-type doped diffusion regions and are located on the N-type well (N-well) of the substrate 12. That is to say, as Figure 2 shown, the first diffusion region D1 and the fifth diffusion region D5 are N-type diffusion regions, while the second diffusion region D2, the third diffusion region D3, the fourth diffusion region D4, the sixth diffusion region D6, the seventh diffusion region D7, and the eighth diffusion region D8 are P-type diffusion regions, and the substrate 12 directly under each gate structure G1-G4 is a P-type well (P-well) or an N-type well (N-well). In Figure 3 , the diffusion regions within the dotted line range N + are N-type diffusion regions, and the diffusion regions within the dotted line range P + are P-type diffusion regions. That is to say, Figure 3 in + “N + -DIFF” represents an N-type diffusion region, “P Figure 3 -DIFF” represents a P-type diffusion region, and the N-type diffusion regions and P-type diffusion regions are represented by different mesh bottoms. Additionally, in
[0092] Because Figure 3In the layout pattern shown, the pattern in the left half (including the first pull-up transistor PU1, the first pull-down transistor PD1, and the first access transistor PG1) and the pattern in the right half (including the second pull-up transistor PU2, the second pull-down transistor PD2, and the second access transistor PG2) are symmetrically distributed along the center point O. Therefore, in the following paragraph descriptions, the pattern features of the left half will be emphasized, and the patterns in the right half have the same features and will not be repeated.
[0093] In addition, from Figure 3 it can be seen that the contact structure CONT further includes a first substrate contact BCT1 located on the second diffusion region D2 (at the position framed by the dashed line), a second substrate contact BCT2 located on the third diffusion region D3, a word line contact WLCT located on the first gate structure G1 and electrically connected to the word line WL, a bit line contact BLCT located on the first diffusion region D1 and electrically connected to the bit line BL1, a Vss voltage source contact VssCT located on the first diffusion region D1 and electrically connected to the voltage source Vss, and a node contact NCT located on the first diffusion region D1 and between the first gate structure G1 and the second gate structure G2. It can be understood that the above-mentioned first substrate contact BCT1, second substrate contact BCT2, word line contact WLCT, bit line contact BLCT, Vss voltage source contact VssCT, and node contact NCT all belong to the contact structure CONT. In addition, the above-mentioned contact patterns are all located in the left half of the pattern. However, due to the symmetry of the layout pattern of this embodiment, the right half also has the same contact structure, but these contact structures are omitted and not described.
[0094] In this embodiment, both the second diffusion region D2 and the third diffusion region D3 are connected to the first diffusion region D1, and the second diffusion region D2 has a conductive type complementary to that of the first diffusion region D1 (for example, the second diffusion region D2 is P-type and the first diffusion region D1 is N-type). Similarly, the third diffusion region D3 has a conductive type complementary to that of the first diffusion region D1 (for example, the third diffusion region D3 is P-type and the first diffusion region D1 is N-type). Through this configuration, the charges accumulated under the gate of the transistor can be released through adjacent and electrically complementary diffusion regions.
[0095] Taking the first access transistor PG1 as an example, since the gate structure of the first access transistor PG1 straddles the first diffusion region D1 which is N-type, for the first access transistor PG1, its source Sr and drain Dr are N-type. Relatively, P-type charges will accumulate in the region directly below the gate and be restricted by the N-type source Sr and drain Dr. These charges, if Figure 2 in the embodiment shown, will be restricted directly below the gate structure and cannot be discharged. However, through the improved design of the present invention, as Figure 3As shown, the P-type charge directly under the gate structure of the first access transistor PG1 can flow out through the second diffusion region D2, which is also P-type, and will subsequently be connected to the first substrate contact BCT1 via a metal silicide layer (not shown in the figure) formed on the surfaces of the diffusion regions D1 - D8, enabling the release of the charge. Similarly, the charge (P-type charge) accumulated directly under the gate structure of the first pull-down transistor PD1 will also flow out through the P-type third diffusion region D3 and will subsequently be connected to the second substrate contact BCT2 via a metal silicide layer (not shown in the figure), enabling the release of the charge. As for the second pull-down transistor PD2 and the second access transistor PG2, they are also in the same manner, and the accumulated charges can flow out through the seventh diffusion region D7 and the sixth diffusion region D6 respectively. Since the second pull-down transistor PD2 and the second access transistor PG2 are symmetric patterns of the first pull-down transistor PD1 and the first access transistor PG1 along the center point O, they will not be repeated here.
[0096] Another feature of this embodiment is that the shape of the first gate structure G1 (and the symmetric third gate structure G3) is a special stepped shape. As Figure 3 shown by the dashed box around the first gate structure G1 in Figure 4A , Figure 4A illustrated Figure 3 in the enlarged schematic diagram of the first gate structure G1 and the nearby area in Figure 4A . Note that for the simplicity of the drawings, Figure 4A only the first gate structure G1, the first diffusion region D1, the second diffusion region D2, and the word line contact WLCT are emphasized and drawn, and the rest of the components are omitted. As Figure 4A shown, the first gate structure G1 has a stepped shape. More specifically, the first gate structure G1 includes an L-shaped first part P1 and a strip-shaped second part P2. The first part includes a first side E1, a second side E2, and a third side E3, all arranged along the first direction (e.g., the X direction). The second part P2 includes a fourth side E4 and a fifth side E5, both arranged along the first direction (the X direction). Among them, the first side E1 is aligned with the fourth side E4, but the second side E2, the third side E3, and the fourth side E4 are not aligned with each other.
[0097] In this embodiment, the first gate structure G1 is designed to be stepped, which has some advantages compared to gate structures of other shapes. For example, please refer to Figure 4B , Figure 4B which shows an enlarged schematic diagram of the first gate structure G1 and the nearby area in another embodiment. In Figure 4B the shown embodiment, the first gate structure G1 is designed to be cross-shaped. And Figure 4A the stepped first gate structure G1 shown in Figure 4BThe cross-shaped first gate structure G1 pattern shown contains fewer right-angled parts, so the probability of rounding can be reduced when forming the pattern, avoiding changes in the gate length or gate width of each transistor due to rounding. In addition, Figure 4A The first gate structure G1 shown is flat and does not protrude from the boundary of the region R (i.e., the upper boundary). Therefore, when multiple SRAM cells are arranged, the first gate structure G1 can maintain a greater distance from other adjacent gate structures, reducing the probability of short circuits due to contact between the gate structures.
[0098] In addition, as Figure 4A The first gate structure G1 shown includes a second part P2 extending downward (-Y direction), where the word line contact WLCT is located on the second part P2 but does not overlap with the second diffusion region D2. This can avoid the problem of short circuits caused by the word line contact WLCT contacting the second diffusion region D2 when the word line contact WLCT is offset. In contrast, as Figure 4B In the pattern shown, the word line contact WLCT overlaps with the second diffusion region D2 (with the first gate structure G1 in between). However, if the positions of the second diffusion region D2 or the word line contact WLCT are offset due to alignment problems during the manufacturing process, the second diffusion region D2 and the word line contact WLCT may contact each other outside the first gate structure G1, causing a short circuit. Therefore, as Figure 4A In the designed pattern, the word line contact WLCT is designed to be located on the second part P2 but not to overlap with the second diffusion region D2, which can more effectively avoid the above alignment problems.
[0099] In addition, according to Figure 3 and Figure 4A 's structure, the present invention also has several features. First, the diffusion region (such as the first diffusion region D1) of this case has a corner part C, and the corner part C is covered by the first gate structure G1, that is, the corner part C of the first diffusion region D1 overlaps with the first gate structure G1. Due to the pattern symmetry, the fifth diffusion region D5 will also have a corner part overlapping with the third gate structure G3. In this way, the corner part of the diffusion region is covered by the gate structure, reducing the risk of leakage current.
[0100] In addition, please refer to Figure 3 and Figure 4A, in the pattern of the present invention, the length of the junction boundary between the first diffusion region D1 and the second diffusion region D2 is defined as L1, and the length of the portion of the stepped first gate structure G1 covering the above-mentioned junction boundary is defined as L2, where L2 is greater than L1. That is to say, from a top view, the stepped first gate structure G1 completely covers the junction boundary between the first diffusion region D1 and the second diffusion region D2. Since leakage current is more likely to occur at the junction of diffusion regions with different conductivity types, in this embodiment, the gate structure completely covers the junction of diffusion regions with different conductivity types, which can reduce the probability of leakage current generated at the junction of the diffusion regions through silicide.
[0101] In addition, in order to improve the uniformity of the overall pattern, as Figure 3 shown, preferably, in this embodiment, the distance from the upper edge of the word line contact WLCT to the first substrate contact BCT1 in the second direction (Y direction) is equal to the distance from the lower edge of the word line contact WLCT to the second substrate contact BCT2 in the second direction (Y direction). In addition, the distance from the first substrate contact BCT1 to the bit line contact BLCT in the first direction (X direction) is equal to the distance from the second substrate contact BCT2 to the Vss voltage source contact in the first direction (X direction), and is also equal to the distance from the word line contact WLCT to the node contact NCT1 in the first direction (X direction).
[0102] Subsequently, as Figure 5 , Figure 6 and Figure 7 shown, a first metal layer M1, a first via V1, a second metal layer M2, a second via V2, and a third metal layer M3 are sequentially formed on the Figure 3 SRAM cell layout diagram shown. The functions of the above-mentioned metal layers and vias are to connect each transistor or node to other voltage sources or components, or to connect different ends of each transistor to each other, etc. The materials of the metal layers and vias are, for example, metals with good conductivity, such as copper, tungsten, etc., but are not limited thereto. It should be noted that the first substrate contact BCT1, the second substrate contact BCT2, and the voltage source Vss will be connected through the above-mentioned metal layers and vias, thereby achieving the effect of discharging charges. More specifically, in this embodiment, since the first pull-down transistor PD1 and the first access transistor PG1 each include a substrate contact, and the second pull-down transistor PD2 and the second access transistor PG2 also each include a substrate contact, these four substrate contacts will be connected to the voltage source Vss through the third metal layer M3. Other features regarding the metal layers and vias belong to the known technologies in the art and will not be elaborated here.
[0103] In summary of the above specification and drawings, the present invention provides a layout pattern of a static random-access memory (SRAM) cell 10, which includes a substrate 12, and a plurality of diffusion regions (N + -DIFF or P + -DIFF) are located on the substrate 12. Each diffusion region DIFF includes at least a first diffusion region D1, a second diffusion region D2, a third diffusion region D3, and a fourth diffusion region D4. A plurality of gate structures POLY are located on the substrate. Each gate structure POLY extends along a first direction (X direction) and straddles the plurality of diffusion regions DIFF to form a plurality of transistors. Among them, the plurality of transistors include a first pull-up transistor (PU1), a first pull-down transistor (PD1), a second pull-up transistor (PU2), a second pull-down transistor (PD2), a first access transistor (PG1), and a second access transistor (PG2). Among them, a first gate structure G1 is included in the plurality of gate structures POLY. From a top view, the first gate structure G1 has a stepped shape, and the first gate structure G1 straddles the first diffusion region D1 and the second diffusion region D2 and forms the first access transistor (PG1), where the first diffusion region D1 and the second diffusion region D2 are adjacent and in direct contact.
[0104] In some embodiments of the present invention, the first gate structure G1 further includes a first part P1 and a second part P2. From a top view, the first part P1 has an L shape, and the second part P2 has a long strip shape.
[0105] In some embodiments of the present invention, the first part P1 has a first side E1, a second side E2, and a third side E3 extending along the first direction (X direction), and the second part P2 has a fourth side E4 and a fifth side E5 extending along the first direction (X direction).
[0106] In some embodiments of the present invention, the first side E1 and the fourth side E4 are in contact with each other and aligned in the first direction.
[0107] In some embodiments of the present invention, the sum of the lengths of the first side E1 and the fourth side E4 is equal to the sum of the lengths of the second side E2, the third side E3, and the fifth side E5.
[0108] In some embodiments of the present invention, the width of the second diffusion region D2 in a second direction (Y direction) is smaller than the width of the first side E1 to the third side E3 in the second direction (Y direction), where the second direction is perpendicular to the first direction (please refer to Figure 4A ).
[0109] In some embodiments of the present invention, a first part P1 overlaps with a first diffusion region D1 and a second diffusion region D2, and a second part P2 overlaps with the second diffusion region D2.
[0110] In some embodiments of the present invention, there is also a second gate structure G2 spanning across the first diffusion region D1 and a third diffusion region D3 to form a first pull-down transistor (PD1), wherein the first diffusion region D1 is adjacent to and in direct contact with the third diffusion region D3.
[0111] In some embodiments of the present invention, the second diffusion region D2 is not in direct contact with the third diffusion region D3.
[0112] In some embodiments of the present invention, the second gate structure G2 spans across a fourth diffusion region D4 to form a first pull-up transistor (PU1).
[0113] In some embodiments of the present invention, the first diffusion region D1 has a first conductivity type (e.g., N-type), while the second diffusion region D2, the third diffusion region D3, and the fourth diffusion region D4 have a second conductivity type (e.g., P-type).
[0114] In some embodiments of the present invention, there is also a word line contact WLCT electrically connected to the first gate structure G1, and from a top view, the word line contact WLCT does not overlap with the second diffusion region D2.
[0115] In some embodiments of the present invention, there is also a first substrate contact BCT1 located on the second diffusion region D2 and electrically connected to the second diffusion region D2.
[0116] In some embodiments of the present invention, there is also a second substrate contact BCT2 located on the third diffusion region D3 and electrically connected to the third diffusion region D3.
[0117] In some embodiments of the present invention, the pitch between the word line contact WLCT and the first substrate contact BCT1 in a second direction (Y direction) is equal to the pitch between the word line contact WLCT and the second substrate contact BCT2 in the second direction, where the second direction is perpendicular to the first direction.
[0118] In some embodiments of the present invention, the first substrate contact BCT1, the second substrate contact BCT2, and the word line contact WLCT are aligned with each other in the second direction.
[0119] In some embodiments of the present invention, the word line contact WLCT is not aligned with the first part P1 in a first direction (for Figure 3 example, the word line contact WLCT is located at the lower left of the first part P1 and is not aligned horizontally).
[0120] In some embodiments of the present invention, a bit line contact BLCT is further included, electrically connecting the first diffusion region D1 and a source electrode of the first access transistor (PG1), and a Vss voltage source contact VssCT is further included, electrically connected to the first diffusion region D1 and a source electrode of the first pull-down transistor (PD1) (please refer to Figure 1 and Figure 3 ).
[0121] In some embodiments of the present invention, a node contact NCT is further included, electrically connected to the first diffusion region D1 and located between the first gate structure G1 and the second gate structure G2.
[0122] In some embodiments of the present invention, the bit line contact BLCT, the Vss voltage source contact VssCT and the node contact NCT are aligned with each other in a second direction (Y direction).
[0123] The present invention is characterized in that an improved static random access memory layout pattern is proposed, which includes some diffusion regions with opposite electrical properties beside the diffusion regions under the gates of each transistor. In this way, the charge accumulated under the gate structure can flow out through the diffusion region, and then the charge is released through the contact structure, avoiding affecting the electrical properties of the transistor and improving the product yield. In addition, the gate structure is designed to be stepped (viewed from the top view), which has improvements such as avoiding the adjacent gates being too close, staggering the word line contact and the diffusion region, and reducing the rounding of the pattern. Therefore, the manufacturing process yield can be improved.
[0124] The above are only the preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope covered by the present invention.
Claims
1. A layout pattern of a static random - access memory (SRAM), comprising: A substrate; A plurality of diffusion regions located on the substrate, each diffusion region at least comprising a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; A plurality of gate structures located on the substrate, each gate structure extending along a first direction (X - direction) and spanning across the plurality of diffusion regions to form a plurality of transistors, wherein the plurality of transistors includes a first pull - up transistor (PU1), a first pull - down transistor (PD1), a second pull - up transistor (PU2), a second pull - down transistor (PD2), a first access transistor (PG1), and a second access transistor (PG2); Wherein, Among the plurality of gate structures, there is a first gate structure which, when viewed from a top view, has a stepped shape, and the first gate structure spans across the first diffusion region and the second diffusion region and forms the first access transistor (PG1), wherein the first diffusion region and the second diffusion region are adjacent and in direct contact.
2. The layout pattern of the static random - access memory according to claim 1, wherein the first gate structure further comprises a first part and a second part. When viewed from the top view, the first part has an L - shape, and the second part has a long - strip shape.
3. The layout pattern of the static random - access memory according to claim 2, wherein the first part has a first side, a second side, and a third side extending along the first direction, and the second part has a fourth side and a fifth side extending along the first direction.
4. The layout pattern of the static random - access memory according to claim 3, wherein the first side and the fourth side are in contact with each other and are aligned in the first direction.
5. The layout pattern of the static random - access memory according to claim 3, wherein the sum of the lengths of the first side and the fourth side is equal to the sum of the lengths of the second side, the third side, and the fifth side.
6. The layout pattern of the static random - access memory according to claim 3, wherein the width of the second diffusion region in a second direction (Y - direction) is less than the width of the region from the first side to the third side in the second direction, wherein the second direction is perpendicular to the first direction.
7. The layout pattern of the static random - access memory according to claim 2, wherein the first part overlaps with the first diffusion region and the second diffusion region, the second part overlaps with the second diffusion region, and the first diffusion region has a corner part which overlaps with the first part.
8. The layout pattern of the static random - access memory according to claim 1, further comprising a second gate structure spanning across the first diffusion region and the third diffusion region and forming the first pull - down transistor (PD1), wherein the first diffusion region and the third diffusion region are adjacent and in direct contact.
9. The layout pattern of the static random - access memory according to claim 8, wherein the second diffusion region and the third diffusion region are not in direct contact.
10. The layout pattern of the static random access memory as claimed in claim 8, wherein the second gate structure straddles the fourth diffusion region and forms the first pull-up transistor (PU1).
11. The layout pattern of the static random access memory as claimed in claim 1, wherein the first diffusion region has a first conductivity type, and the second diffusion region, the third diffusion region and the fourth diffusion region have a second conductivity type.
12. The layout pattern of the static random access memory as claimed in claim 2, further comprising a word line contact electrically connected to the first gate structure, wherein, when viewed from the top view, the word line contact does not overlap with the second diffusion region.
13. The layout pattern of the static random access memory as claimed in claim 12, further comprising a first substrate contact located on the second diffusion region and electrically connected to the second diffusion region.
14. The layout pattern of the static random access memory as claimed in claim 13, further comprising a second substrate contact located on the third diffusion region and electrically connected to the third diffusion region.
15. The layout pattern of the static random access memory as claimed in claim 14, wherein the pitch between the word line contact and the first substrate contact in a second direction (Y direction) is equal to the pitch between the word line contact and the second substrate contact in the second direction, wherein the second direction is perpendicular to the first direction.
16. The layout pattern of the static random access memory as claimed in claim 15, wherein the first substrate contact, the second substrate contact and the word line contact are aligned with each other in the second direction.
17. The layout pattern of the static random access memory as claimed in claim 12, wherein the word line contact and the first portion are not aligned with each other in the first direction.
18. The layout pattern of the static random access memory as claimed in claim 1, further comprising a bit line contact electrically connected to the first diffusion region and the source of the first access transistor (PG1), and further comprising a Vss voltage source contact electrically connected to the first diffusion region and the source of the first pull-down transistor (PD1).
19. The layout pattern of the static random access memory as claimed in claim 18, further comprising a node contact electrically connected to the first diffusion region and located between the first gate structure and the second gate structure.
20. The layout pattern of the static random access memory as claimed in claim 19, wherein the bit line contact, the Vss voltage source contact and the node contact are aligned with each other in a second direction (Y direction).