Strain super junction insulated gate bipolar transistor and preparation method thereof

Abstract

The invention discloses a strained super-junction insulated gate bipolar transistor, which comprises a substrate made of a semiconductor material, a buffer layer and a base region are formed on the surface of the substrate; an emitter contact region is formed on the surface of the base region; a base region contact region is formed on the outer side of the base region emitter region; a stop layer is formed on the surface of the buffer layer; collector contact regions are arranged on the surfaces of the stop layers; an N-type doped column and a P-type doped column are arranged on the surface of the buffer layer; a gate dielectric layer is also arranged above the base region; a gate electrode is arranged above the gate dielectric layer; emitting electrodes are arranged on the surfaces of the emitting electrode contact region and the base region contact region; the surface of the collector contact region is provided with a collector. The invention also discloses a preparation method of the strain super junction insulated gate bipolar transistor. The problems that in the prior art, the ionization impurity scattering effect is remarkable, the carrier mobility of a drift region is severely declined, and a device is difficult to optimize by increasing the super junction concentration in the past are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a strained superjunction insulated gate bipolar transistor. The present invention also relates to a method for manufacturing a strained superjunction insulated gate bipolar transistor. Background Art

[0002] On the premise of meeting specific breakdown voltage requirements, pursuing lower on-state voltage drop and shorter turn-off time are hot research issues and key technical indicators for IGBTs. However, the bipolar conduction operating mode of IGBTs increases the turn-off time while reducing the on-state voltage drop, and the on-state voltage drop and turn-off time form a contradictory relationship. The drift region of high-voltage IGBT devices occupies most of the area and contributes most of the on-resistance value of the IGBT device. Optimizing it can significantly reduce the on-state voltage drop of the IGBT device. Introducing a superjunction structure into IGBT devices has been proven to improve device performance. Superjunction IGBT (SJ-IGBT) devices have two operating modes: unipolar and bipolar. Correspondingly, there are two optimization spaces with high and low concentrations, both of which show better performance than conventional field-stop IGBT (FS-IGBT). In the unipolar mode, the SJ-IGBT does not have the non-equilibrium carrier recombination process, achieving fast turn-off, and reducing the on-state voltage drop by increasing the doping concentration of N and P columns. In the bipolar mode, the SJ-IGBT accelerates the carrier extraction speed in the drift region by virtue of the P-type column, improving the turn-off speed, and mainly achieving a low on-state voltage drop by increasing the non-equilibrium carrier concentration. Since the unipolar SJ-IGBT is not restricted by the non-equilibrium carrier recombination effect, when the superjunction doping concentration increases to a certain extent, the performance of the unipolar mode is better than that of the bipolar mode and has more potential. On the other hand, with the progress of the process node, the column pitch of the superjunction structure develops towards a narrower direction to achieve a stronger inter-column charge compensation effect and a higher doping concentration. However, when the superjunction column pitch enters the sub-micron size, the ionized impurity scattering effect becomes more significant, severely deteriorating the carrier mobility in the drift region, making it difficult to continue to optimize the device by increasing the superjunction concentration in the past, which poses a challenge to the continuous optimization of the on-state voltage drop of unipolar superjunction IGBT devices. Summary of the Invention

[0003] The purpose of the present invention is to provide a strained superjunction insulated gate bipolar transistor, which solves the problem in the prior art that the ionized impurity scattering effect is significant, severely deteriorating the carrier mobility in the drift region, and it is difficult to continue to optimize the device by increasing the superjunction concentration in the past.

[0004] Another purpose of the present invention is to provide a method for manufacturing a strained superjunction insulated gate bipolar transistor.

[0005] The first technical solution adopted by the present invention is a strained superjunction insulated gate bipolar transistor, which includes a substrate of semiconductor material; a buffer layer and a base region are formed on the surface of the substrate; an emitter contact region is formed on the surface of the base region; a base contact region is formed outside the base emitter region; a stop layer is formed on the surface of the buffer layer; a collector contact region is provided on the surface of the stop layer; an N-type doped column and a P-type doped column are provided on the surface of the buffer layer; a gate dielectric layer is further provided above the base region; a gate electrode is provided above the gate dielectric layer; an emitter is provided on the surfaces of the emitter contact region and the base contact region; a collector is provided on the surface of the collector contact region.

[0006] The characteristics of the first technical solution of the present invention further lie in that The buffer layer, the stop layer, the collector contact region, the base region, the emitter contact region, the base contact region, and the N-type doped column belong to the same type of semiconductor material, the P-type doped column belongs to a heterogeneous semiconductor material, and the lattice constant of the P-type doped column is greater than that of the substrate; the P-type doped column is embedded in the surface of the semiconductor material substrate, and the contact surface between the P-type doped column and the substrate belongs to a heterogeneous interface, with lattice mismatch strain; the semiconductor materials of the N-type columns and the heterogeneous semiconductor materials of the P-type columns are alternately arranged on the surface of the substrate.

[0007] The stop layer is disposed between the collector contact region and the buffer layer, and a base region exists between the emitter contact region and the buffer layer, the N-type doped column, and the P-type doped column.

[0008] The doping types of the substrate, the base region, the base contact region, and the collector contact region belong to the same type of doping, and the doping types of the buffer layer, the emitter contact region, and the stop layer are the same and belong to another type of doping.

[0009] The doping types of the P-type doped column and the N-type doped column are opposite, the P-type doped column and the N-type doped column and the buffer layer are heterogeneous materials, the lattice constant of the P-type doped column is greater than the lattice constants of the N-type doped column and the buffer layer, the P-type doped column is a germanium-silicon alloy, and the N-type doped column and the buffer layer are silicon.

[0010] The right boundary of the superjunction structure is in contact with the stop layer, and the left side of the superjunction structure is in contact with the base region; the longitudinal thickness of the stop layer is greater than the thicknesses of the N-type doped column and the P-type doped column.

[0011] The depth of the emitter contact region is less than the depth of the base region, and the depth of the collector contact region is less than the depth of the buffer layer; the longitudinal thickness of the strained superjunction is less than the thickness of the buffer layer.

[0012] The materials of the emitter and the collector are copper metal; The material of the gate electrode is polysilicon, and the thickness is 1 - 2 μm; The material of the gate dielectric layer is silicon dioxide, and the thickness is 0.2 - 0.8 μm; The gate electrode and the gate dielectric layer are located above the device channel region. The left boundary of the gate electrode and the gate dielectric layer covers the emitter contact region, and the right boundary of the gate electrode and the gate dielectric layer partially covers the N-type doped columns and P-type doped columns of the superjunction; P-type single crystal silicon is used as the substrate material, and the substrate concentration is 10 14 ~10 15 cm -3 .

[0013] The buffer layer is N-type doped, the buffer layer thickness is 2 - 4 μm, and the buffer layer concentration is 10 14 ~10 15 cm -3 , and the buffer layer length is 30 - 60 μm; The base region is P-type doped, the base region thickness is 1 - 2 μm, and the concentration is 10 16 ~10 17 cm -3 , and the length is 2 - 5 μm; The emitter contact region is N-type heavily doped, the depth is 0.2 - 0.5 μm, and the concentration is 10 18 ~10 20 cm -3 , and the length is 0.5 - 1 μm; The collector contact region is P-type heavily doped, the depth is 0.2 - 0.5 μm, and the concentration is 10 18 ~10 20 cm-3, and the length is 0.5 - 1 μm; The base contact region is P-type heavily doped, the depth is 0.2 - 0.5 μm, and the concentration is 10 18 ~10 20 cm -3 , and the length is 0.5 - 1 μm; The widths and concentrations of the P-type doped columns and N-type doped columns that make up the strained superjunction are the same, and the concentration is 10 16 ~10 17 cm -3 , the lengths are all 30 - 60 μm, the widths are all 0.2 - 1 μm, and the depths are all 1 - 2 μm; The hetero-semiconductor material of the P-type doped column is germanium-silicon alloy (Si0.7Ge0.3), and the semiconductor material of the N-type doped column is single crystal silicon; The stop layer is N-type doped, and the concentration is 10 14 cm -3 ~10 16 cm -3 , the depth is 1 - 2 μm, and the length is 2 - 4 μm.

[0014] The second technical solution adopted by the present invention is a preparation method of a strain superjunction insulated gate bipolar transistor, which is specifically implemented according to the following steps: Step 1: Use an element-doped semiconductor material as the substrate; Step 2: Sequentially form a buffer layer, a base region, and a stop layer on the substrate through ion implantation or thermal diffusion processes; Step 3: Respectively form a collector contact region and a base contact region in the stop layer and the base region through ion implantation processes; Step 4: Form an emitter contact region in the base region through an ion implantation process; Step 5: Form a high-concentration N-type doped region on the surface of the buffer layer through ion implantation or thermal diffusion processes; Step 6: Etch the high-concentration N-type doped region to form N-type doped columns arranged in an interleaved manner; Step 7: Form P-type doped columns in the trenches by using selective epitaxial growth or physical / chemical vapor deposition methods, and incorporate appropriate impurities during the process to adjust the lattice constant and electrical characteristics of the material; Step 8: Perform chemical mechanical planarization on the surface of the device to achieve fine surface planarization by combining chemical etching and mechanical polishing; Step 9: Sequentially grow or deposit a dielectric layer and deposit an electrode material on the surface of the device to form a dielectric layer and an electrode material with excellent conductivity, so as to improve the electric field control ability and reduce leakage current; Step 10: Pattern the dielectric layer and the electrode material through photolithography and etching processes, and only retain the material of the base region to form a gate dielectric layer and a gate electrode; Step 11: Before depositing the metal layer, first deposit a pre-metal dielectric on the surface of the device to play a role in insulation protection or interface optimization; Step 12: Etch the pre-metal dielectric layer to form emitter electrode vias and collector electrode vias, and deposit a conductive material as a plug in the vias to achieve electrical connection between the emitter contact region, the base contact region, and the collector contact region inside the device and the surface electrodes of the device; Step 13: Complete the subsequent electrode preparation according to the conventional device surface electrode preparation process.

[0015] The beneficial effects of the present invention are as follows: 1. In conventional superjunction devices, there is no strain-induced carrier mobility enhancement effect. The carrier mobility in the superjunction region decreases as the superjunction pillar width decreases and the doping concentration increases, which limits the continuous optimization of the on-state voltage drop of superjunction devices. The present invention can achieve a strain-induced carrier mobility enhancement effect in superjunction devices. There is a lattice mismatch between the P-type pillars and the N-type pillars. The P-type pillars with a larger lattice constant introduce a tensile stress parallel to the heterojunction plane into the N-type pillars, and the N-type pillars with a smaller lattice constant introduce a compressive stress parallel to the heterojunction plane into the P-type pillars. The tensile stress parallel to the carrier transport direction increases the electron mobility of the N-type pillars; on the contrary, the compressive stress parallel to the carrier transport direction increases the hole mobility of the P-type pillars. The electron and hole mobilities in the drift region of the superjunction device are increased simultaneously, effectively alleviating the carrier mobility degradation problem faced by narrow-width and high-concentration superjunction structures, and reducing the on-resistance of the superjunction device. 2. Conventional strain devices can only optimize the mobility of a single carrier (electrons or holes). The lateral strain superjunction insulated gate bipolar transistor of the present invention can optimize the electron and hole mobilities in the drift region simultaneously, achieving the simultaneous enhancement of the mobilities of both carriers, and significantly reducing the on-resistance of power devices. 3. Compared with conventional strain technologies, the strain superjunction technology can introduce a considerable strain effect in a large-size drift region, solving the strain relaxation problem faced by traditional stress sources when applied to large-size devices. 4. The alternately arranged heterosemiconductor material pillars can apply stress to each other. The P-type pillars on both sides of the N-type pillar introduce stress into the N-type pillar, and the stresses from the two heterointerfaces on both sides are superimposed on each other within the N-type pillar, enhancing the strain effect. Similarly, the N-type pillars on both sides of the P-type pillar introduce stress into the P-type pillar, and the strain effect is also enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 FIG. is a three-dimensional schematic diagram of the strain superjunction insulated gate bipolar transistor of the present invention.

[0017] In the figure, 1. Substrate; 2. Buffer layer; 3. Stop layer; 4. Collector contact region; 5. Base region; 6. Emitter contact region; 7. Base contact region; 8. N-type doped pillar; 9. P-type doped pillar; 10. Gate electrode; 11. Emitter; 12. Gate dielectric layer; 13. Collector. DETAILED DESCRIPTION OF THE INVENTION

[0018] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0019] The strain superjunction insulated gate bipolar transistor of the present invention has a structure as Figure 1, including a substrate 1 made of semiconductor material; a buffer layer 2 and a base region 5 are formed on the surface of the substrate 1; an emitter contact region 6 is formed on the surface of the base region 5; a base contact region 7 is formed outside the emitter region of the base region 5; a stop layer 3 is formed on the surface of the buffer layer 2; a collector contact region 4 is on the surface of the stop layer 3; an N-type doped column 8 and a P-type doped column 9 are on the surface of the buffer layer 2; a gate dielectric layer 12 is also provided above the base region 5; a gate electrode 10 is provided above the gate dielectric layer 12; an emitter 11 is provided on the surfaces of the emitter contact region 6 and the base contact region 7; a collector 13 is provided on the surface of the collector contact region 4.

[0020] The buffer layer 2, the stop layer 3, the collector contact region 4, the base region 5, the emitter contact region 6, the base contact region 7, and the N-type doped column 8 are made of the same type of semiconductor material, and the P-type doped column 9 is made of a heterogeneous semiconductor material. The lattice constant of the P-type doped column 9 is greater than that of the substrate 1. The P-type doped column 9 is embedded in the surface of the semiconductor material substrate 1, and the contact surface between the P-type doped column 9 and the substrate 1 is a heterogeneous interface with lattice mismatch strain. The semiconductor materials of the N-type columns and the heterogeneous semiconductor materials of the P-type columns are arranged alternately on the substrate surface.

[0021] The stop layer 3 is provided between the collector contact region 4 and the buffer layer 2, and the base region 5 exists between the emitter contact region 6 and the buffer layer 2, the N-type doped column 8, and the P-type doped column 9.

[0022] The doping types of the substrate 1, the base region 5, the base contact region 7, and the collector contact region 4 belong to the same type of doping (N or P-type doping), and the doping types of the buffer layer 2, the emitter contact region 6, and the stop layer 3 are the same and belong to another type of doping (P or N-type doping). That is, the doping types of these regions of the buffer layer 2, the emitter contact region 6, and the stop layer 3 are the same. However, whether it is an NMOS or a PMOS, the doping types of these regions are always opposite to those of the substrate 1, the base region 5, the base contact region 7, and the collector contact region 4.

[0023] The doping type of the P-type doped column 9 is opposite to that of the N-type doped column 8. The P-type doped column 9 and the N-type doped column 8 are made of heterogeneous materials with the buffer layer 2. The lattice constant of the P-type doped column 9 is greater than that of the N-type doped column 8 and the buffer layer 2. The P-type doped column 9 is a germanium-silicon alloy, and the N-type doped column 8 and the buffer layer 2 are made of silicon.

[0024] The N-type doped column 8 is subjected to a tensile stress parallel to the carrier transport direction, and the P-type doped column 9 is subjected to a compressive stress parallel to the carrier transport direction. The P-type doped column 9 transports holes, and the N-type doped column 8 transports electrons. Both electrons and holes participate in current transport. The tensile stress parallel to the carrier transport direction increases the electron mobility; on the contrary, the compressive stress parallel to the carrier transport direction increases the hole mobility.

[0025] The strain superjunction structure is applicable to both N-type and P-type IGBT devices. The P-type IGBT device has the same structure as the N-type device, but with the opposite doping type. The ratio of the width of the N-type doping column 8 to the width of the P-type doping column 9 is adjusted according to the charge balance, and the value is equal to or close to 1. The depth of the P-type doping column 9 is equal to the depth of the N-type doping column 8, and the length of the P-type doping column 9 in the x direction is equal to the length of the N-type doping column 8 in the x direction. The lengths of the N-type doping column 8 and the P-type doping column 9 are adjusted according to the breakdown voltage requirement of the device, and the value is > 20 μm. The doping concentrations of the lateral strain superjunction N-type doping column 8 and P-type doping column 9 are adjusted according to the width of the column, and the value is on the order of 1016 cm-3 to 1017 cm-3. The right boundary of the superjunction structure is in contact with the stop layer 3, and the left side of the superjunction structure is in contact with the base region 5. The longitudinal thickness of the stop layer 3 is greater than the thicknesses of the N-type doping column 8 and the P-type doping column 9. The depth of the emitter contact region 6 is less than the depth of the base region 5, and the depth of the collector contact region 4 is less than the depth of the buffer layer 2. The longitudinal thickness of the strain superjunction is less than the thickness of the buffer layer 2. The buffer layer 2 can be selected to include various doping methods such as uniform doping, zoned doping, and linear doping. The preparation method of the strain superjunction insulated gate bipolar transistor of the present invention is specifically implemented according to the following steps: Step 1: Use an element-doped semiconductor material as the substrate 1. Step 2: Sequentially form the buffer layer 2, the base region 5, and the stop layer 3 on the substrate 1 by ion implantation or thermal diffusion processes. Step 3: Form the collector contact region 4 and the base contact region 7 in the stop layer 3 and the base region 5 respectively by ion implantation processes. Step 4: Form the emitter contact region 6 in the base region 5 by ion implantation process. Step 5: Form a high-concentration N-type doping region on the surface of the buffer layer 2 by ion implantation or thermal diffusion process. Step 6: Etch the high-concentration N-type doping region to form staggered N-type doping columns 8. Step 7: Form the P-type doping column 9 in the trench by selective epitaxial growth or physical / chemical vapor deposition method, and incorporate an appropriate amount of impurities during the process to adjust the lattice constant and electrical properties of the material. Step 8: Perform chemical mechanical polishing (CMP) treatment on the device surface to achieve fine surface planarization by combining chemical etching and mechanical grinding. Step 9: Sequentially grow (by oxidation or other suitable processes) or deposit (by chemical vapor deposition, physical vapor deposition, or other suitable processes) a dielectric layer 12 (an insulating material such as silicon oxide, silicon nitride, or hafnium oxide) and an electrode material 10 (such as polysilicon, metal, or metal alloy) on the device surface to form a high-quality dielectric layer 12 and an electrode material 10 with excellent conductivity, so as to improve the electric field control ability and reduce leakage current; Step 10: Pattern the dielectric layer 12 and the electrode material 10 through photolithography and etching processes (such as plasma etching, wet etching), and only retain the material of the base region 5 to form a gate dielectric layer 12 and a gate electrode 10; Step 11: Before depositing the metal layer, first deposit a pre-metal dielectric (such as silicon dioxide or TEOS, etc.) on the device surface to play a role in insulation protection or interface optimization; Step 12: Etch the pre-metal dielectric layer to form an emitter electrode via 11 and a collector electrode via 13, and deposit a conductive material (such as aluminum, copper, tungsten, or other metal / metal alloy) into the vias as plugs to achieve electrical connection between the emitter contact region 6, the base contact region 7, and the collector contact region 4 inside the device and the electrodes on the device surface; Step 13: Complete the subsequent electrode preparation according to the conventional device surface electrode preparation process.

[0026] Example 1 The strain superjunction insulated gate bipolar transistor of the present invention has a structure as Figure 1 , and includes a substrate 1 of semiconductor material; a buffer layer 2 and a base region 5 are formed on the surface of the substrate 1; an emitter contact region 6 is formed on the surface of the base region 5; a base contact region 7 is formed outside the emitter region of the base region 5; a stop layer 3 is formed on the surface of the buffer layer 2; a collector contact region 4 is on the surface of the stop layer 3; N-type doped columns 8 and P-type doped columns 9 are on the surface of the buffer layer 2; a gate dielectric layer 12 is further provided above the base region 5; a gate electrode 10 is provided above the gate dielectric layer 12; an emitter 11 is provided on the surfaces of the emitter contact region 6 and the base contact region 7; a collector 13 is provided on the surface of the collector contact region 4.

[0027] The buffer layer 2, the stop layer 3, the collector contact region 4, the base region 5, the emitter contact region 6, the base contact region 7, and the N-type doped columns 8 belong to the same type of semiconductor material, the P-type doped column 9 belongs to a hetero-semiconductor material, and the lattice constant of the P-type doped column 9 is greater than that of the substrate 1; the P-type doped column 9 is embedded in the surface of the semiconductor material substrate 1, and the contact surface between the P-type doped column 9 and the substrate 1 is a hetero-interface with lattice mismatch strain; the semiconductor materials of the N-type columns and the hetero-semiconductor materials of the P-type columns are alternately arranged on the substrate surface.

[0028] Example 2 The strain superjunction insulated gate bipolar transistor of the present invention has a structure asFigure 1 , including a substrate 1 made of semiconductor material; a buffer layer 2 and a base region 5 are formed on the surface of the substrate 1; an emitter contact region 6 is formed on the surface of the base region 5; a base contact region 7 is formed outside the emitter region of the base region 5; a stop layer 3 is formed on the surface of the buffer layer 2; a collector contact region 4 is on the surface of the stop layer 3; an N-type doped column 8 and a P-type doped column 9 are on the surface of the buffer layer 2; a gate dielectric layer 12 is also provided above the base region 5; a gate electrode 10 is provided above the gate dielectric layer 12; an emitter 11 is provided on the surfaces of the emitter contact region 6 and the base contact region 7; a collector 13 is provided on the surface of the collector contact region 4.

[0029] The buffer layer 2, the stop layer 3, the collector contact region 4, the base region 5, the emitter contact region 6, the base contact region 7, and the N-type doped column 8 are made of the same type of semiconductor material, the P-type doped column 9 is made of a hetero-semiconductor material, and the lattice constant of the P-type doped column 9 is greater than that of the substrate 1; the P-type doped column 9 is embedded in the surface of the semiconductor material substrate 1, and the contact surface between the P-type doped column 9 and the substrate 1 is a hetero-interface with lattice mismatch strain; the semiconductor material of the N-type column and the hetero-semiconductor material of the P-type column are alternately arranged on the substrate surface.

[0030] The stop layer 3 is disposed between the collector contact region 4 and the buffer layer 2, and the base region 5 exists between the emitter contact region 6 and the buffer layer 2, the N-type doped column 8, and the P-type doped column 9.

[0031] The doping types of the substrate 1, the base region 5, the base contact region 7, and the collector contact region 4 belong to the same type of doping (N or P-type doping), and the doping types of the buffer layer 2, the emitter contact region 6, and the stop layer 3 are the same and belong to another type of doping (P or N-type doping). That is, the doping types of these regions of the buffer layer 2, the emitter contact region 6, and the stop layer 3 are the same. However, whether it is NMOS or PMOS, the doping types of these regions are always opposite to those of the substrate 1, the base region 5, the base contact region 7, and the collector contact region 4.

[0032] The doping type of the P-type doped column 9 is opposite to that of the N-type doped column 8. The P-type doped column 9 and the N-type doped column 8 and the buffer layer 2 are made of hetero-materials. The lattice constant of the P-type doped column 9 is greater than that of the N-type doped column 8 and the buffer layer 2. The P-type doped column 9 is a germanium-silicon alloy, and the N-type doped column 8 and the buffer layer 2 are made of silicon.

[0033] The N-type doped column 8 is subjected to a tensile stress parallel to the carrier transport direction, and the P-type doped column 9 is subjected to a compressive stress parallel to the carrier transport direction. The P-type doped column 9 transports holes, and the N-type doped column 8 transports electrons. Both electrons and holes participate in current transport. The tensile stress parallel to the carrier transport direction increases the electron mobility; on the contrary, the compressive stress parallel to the carrier transport direction increases the hole mobility.

[0034] The strain superjunction structure is applicable to both N-type and P-type IGBT devices. The P-type IGBT device has the same structure as the N-type device, but the doping types are opposite. The ratio of the width of the N-type doping column 8 to the width of the P-type doping column 9 is adjusted according to the charge balance condition, and the value is equal to or close to 1. The depth of the P-type doping column 9 is equal to the depth of the N-type doping column 8. The length of the P-type doping column 9 in the x direction is equal to the length of the N-type doping column 8 in the x direction. The lengths of the N-type doping column 8 and the P-type doping column 9 are adjusted according to the breakdown voltage requirement of the device, and the value > 20 μm. The doping concentrations of the laterally-strained superjunction N-type doping column 8 and P-type doping column 9 are adjusted according to the width of the column, and the value is of the order of 1016 cm-3 to 1017 cm-3. Example 3 The material of the substrate is an elemental semiconductor material. On this basis, the drift region of the LSSJ-IGBT device is designed as alternately arranged high-concentration N-type and P-type regions, which are closely adjacent in the lateral direction and are respectively called P-columns and N-columns. The P-type column is a hetero-semiconductor material with a lattice constant larger than that of the substrate material. The contact surface between the P-type column and the N-type column is a hetero-interface with lattice mismatch. The P-type column with a larger lattice constant introduces a tensile stress parallel to the hetero-junction plane to the N-type column, and the N-column with a smaller lattice constant introduces a compressive stress parallel to the hetero-junction plane to the P-type column. The tensile stress parallel to the carrier transport direction increases the electron mobility of the N-type column, and the compressive stress parallel to the carrier transport direction increases the hole mobility of the P-type column. The above alternately arranged hetero N-type and P-type columns are called the strain superjunction structure. The drift region of the laterally-strained superjunction insulated gate bipolar transistor of the present invention transports both electrons and holes simultaneously. The strain superjunction structure used in the drift region of the IGBT device can increase the mobilities of both carriers simultaneously and reduce the on-state voltage drop of the device. The buffer layer located below the superjunction region of the IGBT device can not only eliminate the substrate-assisted depletion effect but also serve as an electron transport channel to further reduce the on-state voltage drop of the IGBT.

[0035] Laterally Strained Superjunction Insulated Gate Bipolar Transistor (LSSJ-IGBT). There are two operating modes for superjunction IGBTs, namely the unipolar mode and the bipolar mode. In the unipolar mode, there is no non-equilibrium carrier recombination process in the superjunction IGBT, enabling fast turn-off. The on-state voltage drop is mainly reduced by increasing the doping concentrations of the superjunction N and P columns. In the present invention, a laterally strained superjunction structure is designed in the drift region of a lateral IGBT (LIGBT). This structure consists of alternately arranged N-type columns and P-type columns. The N-type columns and P-type columns are made of heterogeneous semiconductor materials and have similar doping concentrations to achieve charge balance. There is a lattice mismatch between the P-type columns and the N-type columns. The P-type columns with a larger lattice constant introduce a tensile stress parallel to the heterointerface to the N-type columns, and the N columns with a smaller lattice constant introduce a compressive stress parallel to the heterointerface to the P-type columns. The tensile stress parallel to the carrier transport direction increases the electron mobility of the N-type columns; conversely, the compressive stress parallel to the carrier transport direction increases the hole mobility of the P-type columns. The carrier mobilities of both types in the drift region of the new LSSJ-IGBT device are increased simultaneously. A buffer layer is introduced below the laterally strained superjunction region to counteract the auxiliary depletion effect from the substrate. In the off state, the P-type and N-type regions of the laterally strained superjunction form an electric field shielding effect, generating an almost uniform electric field distribution and increasing the breakdown voltage value of the device; in the on state, the high-concentration superjunction columns increase the flux of electrons and holes, and the strain effect simultaneously increases the mobilities of electrons and holes, both of which jointly reduce the on-state voltage drop value of the device. The strained superjunction technology proposed in this invention patent can significantly reduce the on-state voltage drop of LSSJ-IGBT devices while achieving a high breakdown voltage.

[0036] Example 4 The specific structure of the laterally strained superjunction insulated gate bipolar transistor is as Figure 1 shown.

[0037] The materials of the emitter 11 and the collector 13 are copper metal; The material of the gate electrode 10 is polysilicon, and its thickness is 1 - 2 μm; The material of the gate dielectric layer 12 is silicon dioxide, and its thickness is 0.2 - 0.8 μm; The gate electrode 10 and the gate dielectric layer 12 are located above the device channel region. The left boundary of the gate electrode 10 and the gate dielectric layer 12 covers the emitter contact region, and the right boundary of the gate electrode 10 and the gate dielectric layer 12 partially covers the N-type doped columns 8 and P-type doped columns 9 of the superjunction; P-type single-crystalline silicon is used as the material of the substrate 1, which is adjusted according to the breakdown voltage requirement. For devices with a breakdown voltage > 1000V, the thickness is greater than 60 μm, and the concentration of the substrate 1 is 10 14 ~10 15 cm-3 ; The buffer layer 2 is N-type doped, the thickness of the buffer layer 2 is 2-4 μm, and the concentration of the buffer layer 2 is 10 14 ~10 15 cm-3, and the length of the buffer layer 2 is 30-60 μm; The base region 5 is P-type doped, the thickness of the base region 5 is 1-2 μm, and the concentration is 10 16 ~10 17 cm-3, and the length is 2-5 μm; The emitter contact region 6 is heavily N-type doped, the depth is 0.2-0.5 μm, and the concentration is 10 18 ~10 20 cm -3 , and the length is 0.5-1 μm; The collector contact region 4 is heavily P-type doped, the depth is 0.2-0.5 μm, and the concentration is 10 18 ~10 20 cm -3 , and the length is 0.5-1 μm; The base contact region 7 is heavily P-type doped, the depth is 0.2-0.5 μm, and the concentration is 10 18 ~10 20 cm -3 , and the length is 0.5-1 μm; The widths and concentrations of the P-type doped columns 9 and N-type doped columns 8 that form the strained superjunction are the same, and the concentration is 10 16 ~10 17 cm -3 , the lengths are both 30-60 μm, the widths are both 0.2-1 μm, and the depths are both 1-2 μm; The hetero-semiconductor material of the P-type doped column 9 is a germanium-silicon alloy (Si0.7Ge0.3), and the semiconductor material of the N-type doped column 8 is single-crystalline silicon; The stop layer 3 is N-type doped, and the concentration is 10 14 cm -3 ~10 16 cm -3 , the depth is 1-2 μm, and the length is 2-4 μm.

[0038] Example 5 Step 1: Use a single-crystalline silicon material doped with P-type elements as the substrate; Step 2: Sequentially form an N-type buffer layer and a P-type base region on the substrate through an ion implantation process; Step 2: Form an N-type stop layer on the N-type buffer layer through an ion implantation process; Step 5: Introduce a high-concentration N-type doped region on the surface of the buffer layer through an ion implantation process, and use it as the superjunction N-type column in the future; Step 3: Form the base contact and the emitter region in the P-type base region through ion implantation process. Step 3: Form the collector contact in the N-type stop layer through ion implantation process. Step 6: In the superjunction N-type region, form a staggered shallow trench structure through etching process, and the etching depth is not less than the depth of the N-type superjunction region. Step 7: In the trench, form a P-type germanium-silicon alloy layer by using the method of low-temperature selective epitaxial growth. During the epitaxial growth process, an appropriate amount of germanium (Ge) and boron (Boron) are doped as doping elements to adjust the lattice constant and electrical properties of the material.

[0039] Step 8: Perform chemical mechanical polishing (CMP) treatment on the device surface, and achieve fine surface flatness by combining chemical etching and mechanical grinding to further reduce the surface roughness. Step 9: Form a high-quality silicon dioxide dielectric layer through deposition process to provide excellent electrical insulation performance and interface stability. Subsequently, deposit polysilicon electrode material on the dielectric layer to ensure that the electrode has good conductivity and adhesion. Step 10: Pattern the dielectric layer and the electrode material through photolithography process to form a silicon dioxide gate dielectric and a polysilicon gate electrode structure.

[0040] Step 11: Before depositing the metal layer, first deposit a layer of silicon dioxide dielectric material on the device surface as a pre-metal dielectric to play a role in insulation protection or interface optimization.

[0041] Step 12: Form vias in the pre-metal dielectric layer through dry etching (such as reactive ion etching) process, and fill tungsten metal in the vias as plugs to achieve electrical connection between different layers inside the device.

[0042] Step 13: Uniformly deposit conductive metal copper on the surface of the pre-metal dielectric layer through physical vapor deposition (PVD) process, use photolithography technology to define the pattern of the electrode and perform patterning through dry etching process to form gate, emitter and collector electrodes.

[0043] Example 6 Operating mode of the lateral-strain superjunction IGBT (taking the N-type IGBT as an example): Turn-on conduction process: The collector is connected to a high level and the emitter is connected to a low level. When the gate voltage (VGE) is higher than the threshold voltage (Vth), an electron-conducting channel is formed on the surface of the P-type base region. Electrons are injected from the N+ emitter into the channel region and then enter the N-type stop layer through the superjunction N-type column region and the N-type buffer layer. The PN junction formed by the P+ collector contact region / N-type stop layer is forward-biased, and the electrons reaching the N-type stop layer flow out through the anode electrode via the PN junction; the P-type column region / N-type stop layer / P+ anode form a PNP triode, holes are injected from the P+ anode, enter the superjunction P-type column region through the PNP triode, and the holes in the P-type column region flow out from the cathode electrode through the P-type base region. At this time, the device is turned on and enters the conducting state, and both electrons and holes participate in the current transport simultaneously.

[0044] Turn-off and cut-off process: When the gate voltage (VGE) is lower than the threshold voltage (Vth), the channel is disconnected, and electrons from the emitter cannot flow into the N-type column region and the N-type buffer layer, and the electron transport path is truncated. At the same time, no electrons flow into the N-type stop layer, and the PNP triode formed by the P-type column region / N-type stop layer / P+ collector has no base current, and the triode enters the off state. The holes in the collector cannot enter the P-type column region, and the hole transport path is also truncated. At this time, the device is turned off and enters the cut-off state, and the collector voltage of the device is borne by the superjunction region.

[0045] In the present invention, the lengths of the strained superjunction N and P-type columns can be adjusted according to the breakdown voltage requirements of the device. The larger the length, the larger the breakdown voltage, and the more prominent the advantages of the strained superjunction, with a value of ≥30 μm; The widths of the strained superjunction N and P-type columns can be further optimized according to the actual process conditions. The column width decreases as the process line width decreases, with a value of ≤1 μm; The doping concentrations of the strained superjunction N and P-type columns are adjusted according to the column width. The smaller the column width, the larger the doping concentration, with a value in the order of 1016~1017 cm-3; The depth of the strained superjunction can also be adjusted according to the actual process conditions. The larger the superjunction depth, the smaller the on-state voltage drop, with a value of ≥1 μm; The material types of the strained superjunction N and P-type columns are selected according to the quality of the heterointerface. The hetero materials include, but are not limited to, Si as the N-type column / Si1-xGex alloy as the N-type column and Si1-xCx alloy as the N-type column / Si as the N-type column. The thickness of the buffer layer is adjusted accordingly according to the longitudinal breakdown voltage requirements. The larger the thickness, the larger the longitudinal breakdown voltage of the device, with a value ≥1 μm; The doping concentration of the buffer layer is adjusted according to the doping concentration of the substrate, and should offset the influence of the substrate on the charge balance of the superjunction, with a value of 10 14 ~10 15 cm-3; The doping method of the buffer layer can be selected according to the breakdown voltage requirement, including uniform doping, zoned doping, linear doping, etc. The linear doping has good effect but high cost.

Claims

1. A strained superjunction insulated gate bipolar transistor, characterized in that: The invention comprises a substrate (1) of semiconductor material; a buffer layer (2) and a base region (5) are formed on the surface of the substrate (1); an emitter contact region (6) is formed on the surface of the base region (5); a base contact region (7) is formed outside the emitter region of the base region (5); a stop layer (3) is formed on the surface of the buffer layer (2); a collector contact region (4) is formed on the surface of the stop layer (3); an N-type doped column (8) and a P-type doped column (9) are formed on the surface of the buffer layer (2); the combination of the N-type doped column (8) and the P-type doped column (9) is called a strained super junction; a gate dielectric layer (12) is also provided above the base region (5); a gate electrode (10) is provided above the gate dielectric layer (12); an emitter (11) is provided on the surfaces of the emitter contact region (6) and the base contact region (7); and a collector (13) is provided on the surface of the collector contact region (4).

2. The strained superjunction insulated gate bipolar transistor according to claim 1, characterized in that: The buffer layer (2), stop layer (3), collector contact region (4), base region (5), emitter contact region (6), base region contact region (7), and N-type doped columns (8) belong to the same type of semiconductor material; the P-type doped columns (9) belong to a heterogeneous semiconductor material; the lattice constant of the P-type doped columns (9) is greater than the lattice constant of the substrate (1); the P-type doped columns (9) are embedded in the surface of the semiconductor material substrate (1); the contact surface between the P-type doped columns (9) and the substrate (1) is a heterogeneous interface, and lattice mismatch strain exists; the semiconductor material of the N-type columns and the heterogeneous semiconductor material of the P-type columns are alternately arranged on the surface of the substrate.

3. The strained superjunction insulated gate bipolar transistor according to claim 2, characterized in that: The stop layer (3) is arranged between the collector contact region (4) and the buffer layer (2), and a base region (5) is present between the emitter contact region (6) and the buffer layer (2), the N-type doped column (8) and the P-type doped column (9).

4. The strained superjunction insulated gate bipolar transistor according to claim 3, characterized in that: The doping types of the substrate (1), base region (5), base region contact region (7), and collector contact region (4) are of the same type of doping, and the doping types of the buffer layer (2), emitter contact region (6), and stop layer (3) are the same and belong to another type of doping.

5. The strained superjunction insulated gate bipolar transistor according to claim 4, characterized in that: The doping types of the P-type doped column (9) and the N-type doped column (8) are opposite; the P-type doped column (9), the N-type doped column (8) and the buffer layer (2) are heterogeneous materials; the lattice constant of the P-type doped column (9) is greater than the lattice constant of the N-type doped column (8) and the buffer layer (2); the P-type doped column (9) is a germanium-silicon alloy, and the N-type doped column (8) and the buffer layer (2) are silicon.

6. The strained superjunction insulated gate bipolar transistor according to claim 5, characterized in that: The right boundary of the super junction structure is in contact with the stop layer (3), and the left boundary of the super junction structure is in contact with the base region (5); the longitudinal thickness of the stop layer (3) is greater than the thickness of the N-type doped column (8) and the P-type doped column (9).

7. The strained superjunction insulated gate bipolar transistor according to claim 6, characterized in that: The depth of the emitter contact region (6) is less than the depth of the base region (5), the depth of the collector contact region (4) is less than the depth of the buffer layer (2); and the longitudinal thickness of the strain super junction is less than the thickness of the buffer layer (2).

8. The strained superjunction insulated gate bipolar transistor according to claim 7, characterized in that: The emitter (11) and collector (13) are made of copper metal; The gate electrode (10) is made of polysilicon and has a thickness of 1 to 2 μm; The gate dielectric layer (12) is made of silicon dioxide and has a thickness of 0.2 to 0.8 μm; The gate electrode (10) and the gate dielectric layer (12) are located above the device channel region, the left edges of the gate electrode (10) and the gate dielectric layer (12) cover the emitter contact region, and the right edges of the gate electrode (10) and the gate dielectric layer (12) partially cover the N-type doped column (8) and the P-type doped column (9) of the super junction; The material of the substrate (1) is P-type single crystal silicon, and the concentration of the substrate (1) is 10 14 ~10 15 cm -3 .

9. The strained superjunction insulated gate bipolar transistor according to claim 7, characterized in that: The buffer layer (2) is N-type doped, the thickness of the buffer layer (2) is 2 to 4 μm, and the concentration of the buffer layer (2) is 1014 to 1015 cm -3 , the buffer layer (2) has a length of 30 to 60 μm; The base region (5) is P-type doped, the thickness of the base region (5) is 1 to 2 μm, and the concentration is 10 16 ~10 17 cm -3 , length is 2 to 5 μm; The emitter contact region (6) is heavily N-type doped, with a depth of 0.2 to 0.5 μm and a concentration of 10 18 ~10 20 cm -3 , length is 0.5~1μm; The collector contact region (4) is heavily doped with P-type, with a depth of 0.2 to 0.5 μm and a concentration of 10 18 ~10 20 cm -3 , length is 0.5~1μm; The base contact region (7) is heavily doped with P-type, with a depth of 0.2 to 0.5 μm and a concentration of 10 18 ~10 20 cm -3 , length is 0.5~1μm; The width and concentration of the P-type doped column (9) and the N-type doped column (8) constituting the strained superjunction are consistent, and the concentration is 10 16 ~10 17 cm -3 , the length is 30-60 μm, the width is 0.2-1 μm, and the depth is 1-2 μm; The heterogeneous semiconductor material of the P-type doped column (9) is a germanium-silicon alloy, and the semiconductor material of the N-type doped column (8) is single crystal silicon; The stop layer (3) is N-type doped with a concentration of 10 14 cm -3 ~10 16 cm -3 , the depth is 1 to 2 μm and the length is 2 to 4 μm.

10. A method for preparing a strained superjunction insulated gate bipolar transistor, characterized in that: Follow the steps below to implement it: Step 1: using an element-doped semiconductor material as a substrate (1); Step 2: forming a buffer layer (2), a base region (5) and a stop layer (3) in sequence on the substrate (1) by ion implantation or thermal diffusion process; Step 3, forming a collector contact region (4) and a base contact region (7) in the stop layer (3) and the base region (5) respectively by an ion implantation process; Step 4: forming an emitter contact region (6) in the base region (5) by an ion implantation process; Step 5: forming a high-concentration N-type doping region on the surface of the buffer layer (2) by ion implantation or thermal diffusion process; Step 6, etching the high-concentration N-type doping region to form staggered N-type doping columns (8); Step 7: forming a P-type doped column (9) in the trench by selective epitaxial growth or physical / chemical vapor deposition, and doping an appropriate amount of impurities in the process to adjust the lattice constant and electrical properties of the material; Step 8: Perform chemical mechanical planarization on the device surface to achieve fine surface flatness by combining chemical etching and mechanical grinding; Step 9: sequentially growing or depositing a dielectric layer (12) and depositing an electrode material (10) on the surface of the device to form a dielectric layer (12) and an electrode material (10) with good conductivity, so as to improve the electric field control capability and reduce leakage current; Step 10: patterning the dielectric layer (12) and the electrode material (10) by photolithography and etching processes, retaining only the material of the base region (5), so as to form a gate dielectric layer (12) and a gate electrode (10); Step 11: Before depositing the metal layer, a pre-metal dielectric is deposited on the device surface to provide insulation protection or interface optimization. Step 12, etching the pre-metal dielectric layer to form an emitter electrode through hole (11) and a collector electrode through hole (13), and depositing a conductive material into the through holes as plugs to achieve electrical connection between the emitter contact region (6), the base contact region (7) and the collector contact region (4) inside the device and the surface electrodes of the device; Step 13: Complete subsequent electrode preparation according to conventional device surface electrode preparation process.

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