Transverse strain super-junction metal oxide semiconductor field effect transistor and preparation method thereof

Abstract

The invention discloses a lateral strain super junction metal oxide semiconductor field effect transistor, which comprises a substrate made of a semiconductor material, a buffer region and a base region are formed on the surface of the substrate, a heavily doped source electrode contact region is formed on the surface of the base region, and a base region contact region is formed on the outer side of the source electrode contact region in the base region; a heavily doped drain contact region is formed on the surface of the buffer region; the N-type doped column and the P-type doped column are located on the surface of the buffer area, lattice mismatch and strain exist between the N-type doped column and the P-type doped column, and the combination is called a strain super junction; the gate dielectric layer is located on the surface of the base region; the gate electrode is located on the surface of the gate dielectric layer; the source electrode is positioned on the surfaces of the source electrode contact region and the base region contact region; the drain electrode is located on the surface of the drain contact region. According to the invention, the problems of super junction carrier mobility degradation and limited super junction on-resistance optimization caused by too high super junction doping concentration in the prior art are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and particularly relates to a lateral-strained superjunction metal-oxide-semiconductor field-effect transistor. The present invention also relates to a method for manufacturing a lateral-strained superjunction metal-oxide-semiconductor field-effect transistor. Background Art

[0002] On the premise of meeting specific breakdown voltage requirements, pursuing lower on-resistance and shorter turn-off time are hot research issues and key technical indicators of LDMOS. It has been proven that introducing a superjunction structure into a lateral double-diffused MOSFET (LDMOS for short) can improve device performance. Due to the charge balance mechanism, the superjunction structure has a high doping concentration. With the progress of the process node, the column pitch of the superjunction structure develops towards a narrower direction to achieve a stronger inter-column charge compensation effect and a higher doping concentration. However, when the superjunction column pitch enters the sub-micron size, the corresponding doping concentration reaches 10 16 cm-3 or even approaches the order of 10 17 cm-3, and the ionized impurity scattering effect becomes more significant, seriously deteriorating the carrier mobility in the drift region. It is difficult to continue to optimize the device by increasing the superjunction concentration as before, which poses a challenge to the continuous optimization of the on-resistance of the superjunction MOS device. The superjunction region of a high-voltage LDMOS device occupies most of the area and contributes most of the on-resistance value of the LDMOS device. Optimizing it can significantly reduce the on-resistance of the LDMOS device. Strain technology has been proven to be a means to improve carrier mobility by modulating the energy band structure of semiconductor materials to change the distribution of carriers among valleys and the effective mass of carriers. The purpose of this patent is to optimize the carrier mobility in the drift region of a superjunction LDMOS device based on strained silicon technology. Summary of the Invention

[0003] The purpose of the present invention is to provide a lateral-strained superjunction metal-oxide-semiconductor field-effect transistor, which solves the problems of superjunction carrier mobility degradation and limited optimization of superjunction on-resistance caused by too high superjunction doping concentration in the prior art.

[0004] Another purpose of the present invention is to provide a method for manufacturing a lateral-strained superjunction metal-oxide-semiconductor field-effect transistor.

[0005] The first technical solution adopted by the present invention is a lateral-strain superjunction metal-oxide-semiconductor field-effect transistor, which includes a substrate made of semiconductor material. A buffer region and a base region are formed on the surface of the substrate. A heavily doped source electrode contact region is formed on the surface of the base region, and a base region contact region is formed outside the source electrode contact region in the base region; a heavily doped drain electrode contact region is formed on the surface of the buffer region; N-type doped columns and P-type doped columns are located on the surface of the buffer region. There is lattice mismatch and strain between the N-type doped columns and the P-type doped columns, and the combination is called a strain superjunction; a gate dielectric layer is located on the surface of the base region; a gate electrode is located on the surface of the gate dielectric layer; a source electrode is located on the surfaces of the source electrode contact region and the base region contact region; a drain electrode is located on the surface of the drain electrode contact region.

[0006] The characteristics of the first technical solution of the present invention also lie in that

[0007] The buffer region, the base region, the drain electrode contact region, the source electrode contact region, the base region contact region, and the N-type doped columns are included in the substrate and belong to the same type of semiconductor material. The P-type doped columns belong to heterogeneous semiconductor materials, and the lattice constant of the P-type doped columns is greater than the lattice constant of the substrate; the P-type doped columns are embedded in the surface of the semiconductor material substrate, and the contact surface between the P-type doped columns and the substrate belongs to a heterogeneous interface, with lattice mismatch strain; the semiconductor materials of the N-type doped columns and the heterogeneous semiconductor materials of the P-type doped columns are arranged alternately on the surface of the substrate.

[0008] There is a base region between the source electrode contact region and the buffer region, and between the N-type doped columns and the P-type doped columns. The doping types of the substrate, the base region, the base region contact region, and the drain electrode contact region belong to the same type of doping (N or P-type doping). The doping types of the buffer region and the source electrode contact region are the same and belong to another type of doping (P or N-type doping). The doping types of the P-type doped columns and the N-type doped columns are opposite. The right side of the superjunction structure is in contact with the drain electrode contact region, and the left side boundary of the superjunction structure is in contact with the base region. The longitudinal thickness of the lateral-strain superjunction is less than the thickness of the buffer layer.

[0009] The P-type doped columns, the N-type doped columns, and the buffer layer are heterogeneous materials. The lattice constant of the P-type doped columns is greater than the lattice constants of the N-type doped columns and the buffer layer. The material of the P-type doped columns is germanium-silicon alloy, and the materials of the N-type doped columns and the buffer layer are silicon.

[0010] The N-type doped columns are subjected to tensile stress parallel to the carrier transport direction, and the P-type doped columns are subjected to compressive stress parallel to the carrier transport direction.

[0011] For the P-type LDMOS device, holes are transmitted through the P-type doped columns to achieve current transmission. At this time, the electrons in the N-type doped columns do not participate in current transmission, which can improve the hole mobility of the P-type columns in the P-type LDMOS device. For the N-type LDMOS device, electrons are transmitted through the N-type doped columns to achieve current transmission. At this time, the holes in the P-type doped columns do not participate in current transmission, which can improve the electron mobility of the N-type columns in the N-type LDMOS device.

[0012] The ratio of the width of the N-type doped column to the width of the P-type doped column is equal to or close to 1; the depth of the P-type doped column is equal to the depth of the N-type doped column, and the length of the P-type doped column in the x direction is equal to the length of the N-type doped column in the x direction; the depth of the source electrode contact region is less than the depth of the base region, and the depth of the drain electrode contact region is less than the depth of the buffer layer.

[0013] The second technical solution adopted in the present invention is a method for manufacturing a lateral-strain superjunction metal-oxide elemental semiconductor field-effect transistor, comprising the following steps:

[0014] Step 1: Use an element-doped semiconductor material as a substrate;

[0015] Step 2: Sequentially form an N-type buffer layer and a P-type base region on the substrate by ion implantation or thermal diffusion processes;

[0016] Step 3: Respectively form a drain electrode contact region and a base region contact region in the P-type base region by ion implantation process;

[0017] Step 4: Form a source electrode contact region in the P-type base region by ion implantation process;

[0018] Step 5: Form a high-concentration N-type doped region on the surface of the buffer layer by ion implantation or thermal diffusion process as the subsequent strained superjunction N-type column region;

[0019] Step 6: In the superjunction N-type region, form an interleaved shallow trench structure by etching process;

[0020] Step 7: In the trenches, form a P-type heterolayer by selective epitaxial growth or physical / chemical vapor deposition method, and incorporate an appropriate amount of impurities as doping elements to adjust the lattice constant and electrical properties of the material;

[0021] Step 8: Perform chemical mechanical planarization (CMP) treatment on the device surface to achieve fine surface planarization by combining chemical etching and mechanical polishing;

[0022] Step 9: Sequentially grow (by oxidation or other suitable processes) or deposit (by chemical vapor deposition, physical vapor deposition or other suitable processes) a dielectric layer (such as insulating materials like silicon oxide, silicon nitride or hafnium oxide) and deposit an electrode material (such as polysilicon, metal or metal alloy, etc.) on the device surface to form a high-quality dielectric layer and an electrode material with excellent conductivity, so as to improve the electric field control ability and reduce leakage current;

[0023] Step 10: Pattern the dielectric layer and the electrode material by photolithography and etching processes (such as plasma etching, wet etching) to form a gate dielectric layer and a gate electrode structure;

[0024] Step 11: Before depositing the metal layer, deposit a pre-metal dielectric material on the device surface first to play a role in insulation protection or interface optimization;

[0025] Step 12: Form vias in the dielectric layer through an etching process, and deposit a conductive material (such as aluminum, copper, tungsten, or other metal / metal alloy) into the vias as plugs to achieve electrical connection between different layers inside the device;

[0026] Step 13: Uniformly deposit a conductive material (such as aluminum, copper, tungsten, or other metal / metal alloy) on the surface of the pre-metal dielectric, and perform patterning through photolithography and etching processes. Based on the conventional semiconductor device fabrication process, deposit and pattern the device surface to form source and drain electrodes.

[0027] The characteristics of the second technical solution of the present invention also lie in that

[0028] The impurity doped in Step 7 is one of germanium or boron.

[0029] The beneficial effects of the present invention are as follows: In conventional superjunction devices, there is no strain-induced carrier mobility enhancement effect. The carrier mobility in the superjunction region decreases as the superjunction pillar width decreases and the doping concentration increases, which limits the continuous optimization of the on-resistance of superjunction devices. 1. The present invention can achieve a strain-induced electron mobility enhancement effect in superjunction devices. Lattice mismatch occurs between P-type pillars and N-type pillars. The P-type pillar with a larger lattice constant introduces a tensile stress parallel to the heterointerface plane to the N-type pillar, and the N-type pillar with a smaller lattice constant introduces a compressive stress parallel to the heterointerface plane to the P-type pillar. The tensile stress parallel to the carrier transport direction increases the electron mobility of the N-type pillar; the electron mobility in the drift region of the superjunction device increases, effectively alleviating the carrier mobility degradation problem faced by narrow-width, high-concentration superjunction structures, and reducing the on-resistance of superjunction devices. 2. In the prior art, the stress applied in the x direction undergoes stress relaxation as the device size increases. The present invention eliminates the stress relaxation in the x direction of the device by applying stress in the Z direction; 3. Compared with conventional strain technologies, the strained superjunction technology can introduce a considerable strain effect in a large-size drift region, solving the strain relaxation problem faced by traditional stress sources when applied to large-size devices. 4. The alternately arranged hetero-semiconductor material pillars can apply stress to each other. The P-type pillars on both sides of the N-type pillar introduce stress to the N-type pillar, and the stresses from the hetero-interfaces on both sides are superimposed on each other inside the N-type pillar, enhancing the strain effect. Similarly, the N-type pillars on both sides of the P-type pillar introduce stress to the P-type pillar, and the strain effect is also enhanced. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a three-dimensional schematic diagram of the lateral strained superjunction metal-oxide elemental semiconductor field-effect transistor of the present invention;

[0031] Figure 2is a cross-sectional view of the device of the present invention along the xoy direction;

[0032] Figure 3 is a cross-sectional view of the device of the present invention along the xoz direction;

[0033] Figure 4 is a cross-sectional view of the device of the present invention along the yoz direction.

[0034] In the figure, 1. Substrate; 2. Buffer layer; 3. Drain; 4. Drain contact region; 5. Base region; 6. Source electrode contact region; 7. Base region contact region; 8. N-type doped column; 9. P-type doped column; 10. Gate electrode; 11. Source electrode; 12. Gate dielectric layer. Detailed implementation manners

[0035] The present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0036] In the present invention, a lateral strain superjunction structure is designed in the drift region of a lateral MOS (LDMOS). This structure is composed of alternately arranged N-type columns and P-type columns. The N-type columns and P-type columns are hetero-semiconductor materials with similar doping concentrations to achieve charge balance. There is a lattice mismatch between the P-type columns and the N-type columns. The P-type columns with a larger lattice constant introduce a tensile stress parallel to the hetero-junction plane to the N-type columns, and the N-type columns with a smaller lattice constant introduce a compressive stress parallel to the hetero-junction plane to the P-type columns. The tensile stress parallel to the carrier transport direction improves the electron mobility of the N-type columns. The stresses caused by the hetero-semiconductor layers on both sides of the silicon columns are superimposed within the silicon columns, further enhancing the strain effect and carrier mobility in the silicon column region. A buffer layer is introduced below the lateral strain superjunction region to offset the auxiliary depletion effect from the substrate. In the off state, the P-type and N-type regions of the lateral strain superjunction form an electric field shielding effect to produce an almost uniform electric field distribution, improving the breakdown voltage value of the device; in the on state, the high-concentration superjunction columns increase the electron flux, and the strain effect improves the electron mobility, reducing the on-resistance value of the device. The strain superjunction technology proposed in this invention patent can significantly reduce the on-resistance of SJ-LDMOS devices while achieving a high breakdown voltage.

[0037] The lateral strain superjunction metal oxide semiconductor field effect transistor of the present invention has a structure as Figures 1 to 4As shown, there is a substrate 1 including a semiconductor material. A buffer region 2 and a base region 5 are formed on the surface of the substrate. A heavily doped source electrode contact region 6 is formed on the surface of the base region 5. A base region contact region 7 is formed outside the source electrode contact region 6 in the base region 5; a heavily doped drain electrode contact region 4 is formed on the surface of the buffer region 2; an N-type doped column 8 and a P-type doped column 9 are located on the surface of the buffer region 2. There is a lattice mismatch and strain between the N-type doped column 8 and the P-type doped column 9, and the combination is called a strained superjunction; a gate dielectric layer 12 is located on the surface of the base region 5; a gate electrode 10 is located on the surface of the gate dielectric layer 12; a source electrode 11 is located on the surfaces of the source electrode contact region 6 and the base region contact region 7; a drain electrode 3 is located on the surface of the drain electrode contact region 4.

[0038] The buffer region 2, the base region 5, the drain electrode contact region 4, the source electrode contact region 6, the base region contact region 7, and the N-type doped column 8 are included in the substrate 1 and belong to the same type of semiconductor material. The P-type doped column 9 belongs to a heterogeneous semiconductor material, and the lattice constant of the P-type doped column 9 is greater than the lattice constant of the substrate 1; the P-type doped column 9 is embedded in the surface of the semiconductor material substrate 1, and the contact surface between the P-type doped column 9 and the substrate 1 is a heterogeneous interface with lattice mismatch strain; the semiconductor materials of the N-type doped column 8 and the heterogeneous semiconductor material of the P-type doped column 9 are alternately arranged on the substrate surface.

[0039] There is a base region 5 between the source electrode contact region 6 and the buffer region 2, and between the N-type doped column 8 and the P-type doped column 9. The doping types of the substrate 1, the base region 5, the base region contact region 7, and the drain electrode contact region 4 belong to the same type of doping (N or P-type doping). The doping types of the buffer region 2 and the source electrode contact region 6 are the same and belong to another type of doping (P or N-type doping). The doping types of the P-type doped column 9 and the N-type doped column 8 are opposite. The right side of the superjunction structure is in contact with the drain electrode contact region 4, and the left side boundary of the superjunction structure is in contact with the base region 5. The longitudinal thickness of the lateral strained superjunction is less than the thickness of the buffer layer 2.

[0040] The P-type doped column 9, the N-type doped column 8, and the buffer layer 2 are heterogeneous materials. The lattice constant of the P-type doped column 9 is greater than the lattice constants of the N-type doped column 8 and the buffer layer 2. The material of the P-type doped column 9 is a germanium-silicon alloy, and the materials of the N-type doped column 8 and the buffer layer 2 are silicon.

[0041] The N-type doped column 8 is subjected to a tensile stress parallel to the carrier transport direction, and the P-type doped column 9 is subjected to a compressive stress parallel to the carrier transport direction. The tensile stress parallel to the carrier transport direction improves the electron mobility.

[0042] The P-type LDMOS device relies on the P-type doped column 9 to transmit holes for current transmission. At this time, the electrons in the N-type doped column do not participate in current transmission, which can improve the hole mobility of the P-type column in the P-type LDMOS device. For the N-type LDMOS device, it relies on the N-type doped column 8 to transmit electrons to achieve current transmission. At this time, the holes in the P-type doped column do not participate in current transmission, which can improve the electron mobility of the N-type column in the N-type LDMOS device.

[0043] The strained superjunction structure is applicable to both N-type and P-type LDMOS devices. The P-type LDMOS device has the same device structure as that Figure 1 shown in the present invention, and the doping type is opposite to that Figure 1 described in the present invention.

[0044] The ratio of the width of the N-type doped column 8 to the width of the P-type doped column 9 is adjusted according to the charge balance situation, and the typical value is equal to or close to 1; the depth of the P-type doped column 9 is equal to the depth of the N-type doped column 8, and the length of the P-type doped column 9 in the x direction is equal to the length of the N-type doped column 8 in the x direction; the depth of the source electrode contact region 6 is less than the depth of the base region 5, and the depth of the drain electrode contact region 4 is less than the depth of the buffer layer 2.

[0045] The N-type buffer layer can be selected to include various doping methods such as uniform doping, zoned doping, and linear doping.

[0046] The length of the strained superjunction region composed of the width of the N-type doped column 8 and the P-type doped column 9 is adjusted according to the breakdown voltage requirement of the device, and the typical value > 20 μm;

[0047] The doping concentrations of the N-type doped column 8 and the P-type doped column 9 in the lateral strained superjunction are adjusted according to the width of the column, and the typical value is 10 16 cm -3 ~10 17 cm -3 order of magnitude.

[0048] The manufacturing method of the lateral strained superjunction metal-oxide-semiconductor field-effect transistor of the present invention is characterized by including the following steps:

[0049] Step 1: Use a semiconductor material doped with elements as the substrate 1;

[0050] Step 2: Sequentially form an N-type buffer layer 2 and a P-type base region 5 on the substrate 1 through an ion implantation or thermal diffusion process (including steps such as lithography, implantation, and annealing);

[0051] Step 3: The P-type base region 5 respectively forms a drain electrode contact region 4 and a base region contact region 7 through an ion implantation process;

[0052] Step 4: Form a source electrode contact region 6 in the P-type base region through an ion implantation process;

[0053] Step 5: A high-concentration N-type doped region is formed on the surface of the buffer layer through ion implantation or thermal diffusion process, serving as the subsequent strained superjunction N-type column region;

[0054] Step 6: In the superjunction N-type region, an interleaved shallow trench structure is formed through etching process;

[0055] Step 7: A P-type heterolayer is formed in the trench by selective epitaxial growth or physical / chemical vapor deposition method, and an appropriate amount of impurities are doped as doping elements to adjust the lattice constant and electrical properties of the material;

[0056] Step 8: The surface of the device is subjected to chemical mechanical polishing (CMP) treatment to achieve fine surface planarization by combining chemical etching and mechanical grinding;

[0057] Step 9: A dielectric layer (insulating materials such as silicon oxide, silicon nitride or hafnium oxide, etc.) is grown (oxidation or other suitable processes) or deposited (chemical vapor deposition, physical vapor deposition or other suitable processes) on the surface of the device in sequence, and an electrode material (such as polysilicon, metal or metal alloy, etc.) is deposited to form a high-quality dielectric layer and an electrode material with excellent conductivity, so as to improve the electric field control ability and reduce leakage current;

[0058] Step 10: The dielectric layer and the electrode material are patterned through photolithography and etching processes (such as plasma etching, wet etching) to form the gate dielectric layer 12 and the gate electrode 10 structure;

[0059] Step 11: Before depositing the metal layer, a metal pre-dielectric material is deposited on the surface of the device first to play a role of insulation protection or interface optimization;

[0060] Step 12: A through hole is formed in the dielectric layer through etching process, and a conductive material (such as aluminum, copper, tungsten or other metal / metal alloy) is deposited into the through hole as a plug to realize the electrical connection between different layers inside the device;

[0061] Step 13: A conductive material (such as aluminum, copper, tungsten or other metal / metal alloy) is uniformly deposited on the surface of the metal pre-dielectric, and is patterned through photolithography and etching processes. Based on the conventional semiconductor device preparation process, the surface of the device is deposited and patterned to form the source electrode 11 and the drain electrode 3.

[0062] The impurity doped in Step 7 is one of germanium or boron.

[0063] Embodiment 1

[0064] The lateral strained superjunction metal oxide semiconductor field effect transistor of the present invention has a structure as shown in Figures 1 to 4As shown, it includes a substrate 1 made of semiconductor material. A buffer region 2 and a base region 5 are formed on the surface of the substrate. A heavily doped source electrode contact region 6 is formed on the surface of the base region 5. A base contact region 7 is formed outside the source electrode contact region 6 in the base region 5. A heavily doped drain electrode contact region 4 is formed on the surface of the buffer region 2. An N-type doped column 8 and a P-type doped column 9 are located on the surface of the buffer region 2. There is a lattice mismatch and strain between the N-type doped column 8 and the P-type doped column 9, and the combination is called a strained superjunction. A gate dielectric layer 12 is located on the surface of the base region 5. A gate electrode 10 is located on the surface of the gate dielectric layer 12. A source electrode 11 is located on the surfaces of the source electrode contact region 6 and the base contact region 7. A drain electrode 3 is located on the surface of the drain electrode contact region 4.

[0065] Example 2

[0066] The lateral strained superjunction metal oxide semiconductor field effect transistor of the present invention has a structure as Figures 1 to 4 As shown, it includes a substrate 1 made of semiconductor material. A buffer region 2 and a base region 5 are formed on the surface of the substrate. A heavily doped source electrode contact region 6 is formed on the surface of the base region 5. A base contact region 7 is formed outside the source electrode contact region 6 in the base region 5. A heavily doped drain electrode contact region 4 is formed on the surface of the buffer region 2. An N-type doped column 8 and a P-type doped column 9 are located on the surface of the buffer region 2. There is a lattice mismatch and strain between the N-type doped column 8 and the P-type doped column 9, and the combination is called a strained superjunction. A gate dielectric layer 12 is located on the surface of the base region 5. A gate electrode 10 is located on the surface of the gate dielectric layer 12. A source electrode 11 is located on the surfaces of the source electrode contact region 6 and the base contact region 7. A drain electrode 3 is located on the surface of the drain electrode contact region 4.

[0067] The buffer region 2, the base region 5, the drain electrode contact region 4, the source electrode contact region 6, the base contact region 7, and the N-type doped column 8 are included in the substrate 1 and belong to the same type of semiconductor material. The P-type doped column 9 belongs to a heterogeneous semiconductor material, and the lattice constant of the P-type doped column 9 is greater than that of the substrate 1. The P-type doped column 9 is embedded in the surface of the semiconductor material substrate 1, and the contact surface between the P-type doped column 9 and the substrate 1 is a heterogeneous interface with lattice mismatch strain. The semiconductor material of the N-type doped column 8 and the heterogeneous semiconductor material of the P-type doped column 9 are alternately arranged on the substrate surface.

[0068] Example 3

[0069] The lateral strained superjunction metal oxide semiconductor field effect transistor of the present invention has a structure as Figures 1 to 4As shown, a substrate 1 including a semiconductor material has a buffer layer 2 and a base region 5 formed on its surface. A heavily doped source electrode contact region 6 is formed on the surface of the base region 5, and a base region contact region 7 is formed outside the source electrode contact region 6 in the base region 5; a heavily doped drain contact region 4 is formed on the surface of the buffer layer 2; N-type doped columns 8 and P-type doped columns 9 are located on the surface of the buffer layer 2. There is a lattice mismatch and strain between the N-type doped columns 8 and the P-type doped columns 9, and the combination is called a strained superjunction; a gate dielectric layer 12 is located on the surface of the base region 5; a gate electrode 10 is located on the surface of the gate dielectric layer 12; a source electrode 11 is located on the surfaces of the source electrode contact region 6 and the base region contact region 7; a drain electrode 3 is located on the surface of the drain contact region 4.

[0070] The buffer layer 2, the base region 5, the drain contact region 4, the source electrode contact region 6, the base region contact region 7, and the N-type doped columns 8 are included in the substrate 1 and belong to the same type of semiconductor material. The P-type doped columns 9 belong to a heterogeneous semiconductor material, and the lattice constant of the P-type doped columns 9 is greater than that of the substrate 1; the P-type doped columns 9 are embedded in the surface of the semiconductor material substrate 1, and the contact surface between the P-type doped columns 9 and the substrate 1 is a heterogeneous interface with lattice mismatch strain; the semiconductor materials of the N-type doped columns 8 and the heterogeneous semiconductor materials of the P-type doped columns 9 are alternately arranged on the substrate surface.

[0071] There is a base region 5 between the source electrode contact region 6 and the buffer layer 2, and between the N-type doped columns 8 and the P-type doped columns 9. The doping types of the substrate 1, the base region 5, the base region contact region 7, and the drain contact region 4 belong to the same type of doping (N or P-type doping). The doping types of the buffer layer 2 and the source electrode contact region 6 are the same and belong to another type of doping (P or N-type doping). The doping types of the P-type doped columns 9 and the N-type doped columns 8 are opposite. The right side of the superjunction structure is in contact with the drain contact region 4, and the left side boundary of the superjunction structure is in contact with the base region 5. The longitudinal thickness of the lateral strained superjunction is less than the thickness of the buffer layer 2.

[0072] The P-type doped columns 9, the N-type doped columns 8, and the buffer layer 2 are heterogeneous materials. The lattice constant of the P-type doped columns 9 is greater than that of the N-type doped columns 8 and the buffer layer 2. The material of the P-type doped columns 9 is a germanium-silicon alloy, and the materials of the N-type doped columns 8 and the buffer layer 2 are silicon.

[0073] The N-type doped columns 8 are subjected to a tensile stress parallel to the carrier transport direction, and the P-type doped columns 9 are subjected to a compressive stress parallel to the carrier transport direction. The tensile stress parallel to the carrier transport direction improves the electron mobility.

[0074] Example 4

[0075] The preparation method of the lateral strained superjunction metal oxide elemental semiconductor field effect transistor of the present invention includes the following steps:

[0076] Step 1: Use an element-doped semiconductor material as the substrate 1;

[0077] Step 2: An N-type buffer layer 2 and a P-type base region 5 are sequentially formed on the substrate 1 by ion implantation or thermal diffusion processes (including steps such as photolithography, implantation, and annealing).

[0078] Step 3: Drain contact regions 4 and base contact regions 7 are respectively formed in the P-type base region 5 by ion implantation process.

[0079] Step 4: Source electrode contact regions 6 are formed in the P-type base region by ion implantation process.

[0080] Step 5: A highly doped N-type region is formed on the surface of the buffer layer by ion implantation or thermal diffusion process, serving as the subsequent strained superjunction N-type column region.

[0081] Step 6: In the superjunction N-type region, an interleaved shallow trench structure is formed by etching process.

[0082] Step 7: A P-type heterolayer is formed in the trench by selective epitaxial growth or physical / chemical vapor deposition method, and an appropriate amount of impurity is doped as a doping element to adjust the lattice constant and electrical properties of the material; the impurity doped in Step 7 is one of germanium or boron.

[0083] Step 8: The surface of the device is subjected to chemical mechanical polishing (CMP) treatment to achieve fine surface planarization by combining chemical etching and mechanical grinding.

[0084] Step 9: A dielectric layer (insulating materials such as silicon oxide, silicon nitride, or hafnium oxide) is grown (by oxidation or other suitable processes) or deposited (by chemical vapor deposition, physical vapor deposition, or other suitable processes) on the surface of the device in sequence, and an electrode material (such as polysilicon, metal, or metal alloy, etc.) is deposited to form a high-quality dielectric layer and an electrode material with excellent conductivity, so as to improve the electric field control ability and reduce leakage current.

[0085] Step 10: The dielectric layer and the electrode material are patterned by photolithography and etching processes (such as plasma etching, wet etching) to form a gate dielectric layer 12 and a gate electrode 10 structure.

[0086] Step 11: Before depositing the metal layer, a metal pre-dielectric material is first deposited on the surface of the device to play a role in insulation protection or interface optimization.

[0087] Step 12: Through etching process, vias are formed in the dielectric layer, and a conductive material (such as aluminum, copper, tungsten, or other metal / metal alloy) is deposited into the vias as plugs to achieve electrical connection between different layers inside the device.

[0088] Step 13: Uniformly deposit a conductive material (such as aluminum, copper, tungsten, or other metals / metal alloys) on the surface of the pre-metal dielectric, and perform patterning through photolithography and etching processes. Based on the conventional semiconductor device fabrication process, deposit and pattern the device surface to form the source electrode 11 and the drain electrode 3.

[0089] Example 5

[0090] The laterally-strained superjunction metal-oxide elemental semiconductor field-effect transistor designed by the present invention achieves a lower on-resistance while achieving a high breakdown voltage compared to the conventional superjunction LDMOS device.

[0091] Operating mode of the laterally-strained superjunction LDMOS (taking the N-type MOS as an example):

[0092] Turn-on conduction process:

[0093] The drain is connected to a high level, and the source electrode is connected to a low level. When the gate voltage (VGS) is higher than the threshold voltage (Vth), an electron-conducting channel is formed on the surface of the P-type base region. Electrons are injected from the N+ source electrode into the channel region, then pass through the superjunction N-type column region and the N-type buffer layer, and flow out through the drain region by the drain electrode. At this time, the device is turned on and enters the conduction state, and the current transport is mainly participated by electrons.

[0094] Example 6

[0095] The laterally-strained superjunction metal-oxide elemental semiconductor field-effect transistor designed by the present invention achieves a lower on-resistance while achieving a high breakdown voltage compared to the conventional superjunction LDMOS device.

[0096] Operating mode of the laterally-strained superjunction LDMOS (taking the N-type MOS as an example):

[0097] Turn-off cut-off process:

[0098] When the gate voltage (VGS) is lower than the threshold voltage (Vth), the channel is disconnected, electrons from the source electrode cannot flow into the N-type column region and the N-type buffer layer, the electron transport path is truncated, holes in the drain cannot enter the P-type column region, and the hole transport path is also truncated. At this time, the device is turned off and enters the cut-off state, and the drain voltage of the device is borne by the superjunction region.

[0099] The material of the substrate is elemental semiconductor material. On this basis, the drift region of the SJ-LDMOS device is designed as a high-concentration N-type and P-type region with an alternating arrangement structure. These regions are closely adjacent to each other in the transverse direction and are respectively called P-columns and N-columns. The P-type column is a hetero-semiconductor material, and its lattice constant is greater than that of the substrate material. The contact surface between the P-type column and the N-type column is a hetero-interface and there is a lattice mismatch. The P-type column with a larger lattice constant introduces a tensile stress parallel to the hetero-junction plane to the N-type column, and the N-column with a smaller lattice constant introduces a compressive stress parallel to the hetero-junction plane to the P-column. The tensile stress parallel to the carrier transport direction improves the electron mobility of the N-type column. The above-mentioned alternately arranged hetero N-type and P-type columns are called a strained super-junction structure. The strained super-junction structure used in the drift region of the LDMOS device can improve the electron mobility and reduce the on-resistance of the device. Introducing a buffer layer under the super-junction region of the LDMOS device can not only eliminate the substrate-assisted depletion effect but also serve as an electron transport channel to further reduce the LDMOS on-resistance.

[0100] The present invention further makes the following optimizations:

[0101] The lengths of the strained super-junction N-type and P-type columns can be adjusted according to the breakdown voltage requirements of the device. The larger the length, the larger the breakdown voltage, and the more prominent the advantages of the strained super-junction. The typical value is ≥30 μm;

[0102] The widths of the strained super-junction N-type and P-type columns can be further optimized according to the actual process conditions. The column width decreases as the process line width decreases. The typical value is ≤1 μm;

[0103] The doping concentrations of the strained super-junction N-type and P-type columns are adjusted according to the column width. The smaller the column width, the larger the doping concentration. The typical value is 10 16 ~10 17 cm -3 order of magnitude;

[0104] The depth of the strained super-junction can also be adjusted according to the actual process conditions. The larger the super-junction depth, the smaller the on-resistance. The typical value is ≥1 μm;

[0105] The material types of the strained super-junction N-type and P-type columns are selected according to the quality of the hetero-interface. Typical hetero-materials include but are not limited to Si as the N-type column / Si1-xGex alloy as the P-type column and Si1-xCx alloy as the P-type column / Si as the N-type column.

[0106] The thickness of the buffer layer is adjusted accordingly according to the longitudinal breakdown voltage requirements. The larger the thickness, the larger the longitudinal breakdown voltage of the device. The typical value is ≥1 μm;

[0107] The doping concentration of the buffer layer is adjusted according to the substrate doping concentration, and the influence of the substrate on the charge balance of the super-junction should be offset. The typical value is 10 14 ~10 15 cm-3 ;

[0108] The doping method of the buffer layer can be selected according to the breakdown voltage requirement, including uniform doping, zoned doping, linear doping, etc. The linear doping has good effect but high cost.

[0109] The prior art proposes to optimize the on-resistance of LDMOS devices with a lateral superjunction structure. The superjunction structure reduces the on-resistance of the device by increasing the doping concentration in the drift region of the LDMOS device. However, when the doping concentration is increased to a certain extent, a significant carrier mobility degradation problem is caused. On the basis of retaining the high-concentration characteristics of the superjunction structure, the present invention introduces a strain mechanism into the lateral superjunction structure and uses the strain-induced carrier mobility enhancement technology to improve the carrier mobility degradation problem. The present invention can further reduce the on-resistance of the device.

Claims

1. A lateral strained superjunction metal oxide semiconductor field effect transistor, characterized in that: A substrate (1) comprising semiconductor materials is provided, a buffer region (2) and a base region (5) are formed on the surface of the substrate, a heavily doped source electrode contact region (6) is formed on the surface of the base region (5), and a base region contact region (7) is formed outside the source electrode contact region (6) in the base region (5); a heavily doped drain contact region (4) is formed on the surface of the buffer region (2); an N-type doped column (8) and a P-type doped column (9) are located on the surface of the buffer region (2), lattice mismatch and strain exist between the N-type doped column (8) and the P-type doped column (9), and the combination is called a strain super junction; The gate dielectric layer (12) is located on the surface of the base region (5); the gate electrode (10) is located on the surface of the gate dielectric layer (12); the source electrode (11) is located on the surfaces of the source electrode contact region (6) and the base region contact region (7); and the drain electrode (3) is located on the surface of the drain contact region (4).

2. The lateral strained superjunction metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The buffer zone (2), the base zone (5), the drain contact zone (4), the source electrode contact zone (6), the base zone contact zone (7), and the N-type doped column (8) are contained in the substrate (1) and belong to the same type of semiconductor material; the P-type doped column (9) belongs to a heterogeneous semiconductor material; the lattice constant of the P-type doped column (9) is greater than the lattice constant of the substrate (1); the P-type doped column (9) is embedded in the surface of the semiconductor material substrate (1); the contact surface between the P-type doped column (9) and the substrate (1) is a heterogeneous interface, and there is lattice mismatch strain; the semiconductor material of the N-type doped column (8) and the heterogeneous semiconductor material of the P-type doped column (9) are alternately arranged on the substrate surface.

3. The lateral strained superjunction metal oxide semiconductor field effect transistor according to claim 1, characterized in that: A base region (5) exists between the source electrode contact region (6) and the buffer region (2), and between the N-type doping column (8) and the P-type doping column (9); the substrate (1), the base region (5), the base region contact region (7), and the drain contact region (4) have the same doping type; the buffer region (2) and the source electrode contact region (6) have the same doping type and belong to another doping type; the P-type doping column (9) and the N-type doping column (8) have opposite doping types; the right side of the super junction structure contacts the drain contact region (4); the left side boundary of the super junction structure contacts the base region (5); and the longitudinal thickness of the transverse strain super junction is less than the thickness of the buffer layer (2).

4. The lateral strained superjunction metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The P-type doped column (9), the N-type doped column (8) and the buffer layer (2) are heterogeneous materials; the lattice constant of the P-type doped column (9) is greater than the lattice constant of the N-type doped column (8) and the buffer layer (2); the material of the P-type doped column (9) is a germanium-silicon alloy, and the material of the N-type doped column (8) and the buffer layer (2) is silicon.

5. The lateral strained superjunction metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The N-type doped column (8) is subjected to a tensile stress parallel to the carrier transmission direction, and the P-type doped column (9) is subjected to a compressive stress parallel to the carrier transmission direction.

6. The lateral strained superjunction metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The P-type LDMOS device relies on the P-type doped column (9) to transmit holes to achieve current transmission. At this time, the electrons of the N-type doped column do not participate in the current transmission, which can improve the hole mobility of the P-type column of the P-type LDMOS device. For the N-type LDMOS device, the electrons rely on the N-type doped column (8) to transmit electrons to achieve current transmission. At this time, the holes of the P-type doped column do not participate in the current transmission, which can improve the electron mobility of the N-type column of the N-type LDMOS device.

7. The lateral strained superjunction metal oxide semiconductor field effect transistor according to claim 1, characterized in that: The ratio of the width of the N-type doped column (8) to the width of the P-type doped column (9) is equal to or close to 1; the depth of the P-type doped column (9) is equal to the depth of the N-type doped column (8); the length of the P-type doped column (9) along the x direction is equal to the length of the N-type doped column (8) along the x direction; the depth of the source electrode contact region (6) is less than the depth of the base region (5); and the depth of the drain contact region (4) is less than the depth of the buffer layer (2).

8. A method for preparing a lateral strain superjunction metal oxide semiconductor field effect transistor, characterized in that: The following steps are involved: Step 1: using an element-doped semiconductor material as a substrate (1); Step 2: forming an N-type buffer layer (2) and a P-type base region (5) on the substrate (1) in sequence by ion implantation or thermal diffusion; Step 3, forming a drain contact region (4) and a base contact region (7) in the P-type base region (5) by an ion implantation process; Step 4, forming a source electrode contact region (6) in the P-type base region by an ion implantation process; Step 5: forming a high-concentration N-type doping region on the surface of the buffer layer by ion implantation or thermal diffusion process, which serves as a subsequent strained super junction N-type column region; Step 6: In the super junction N-type region, a staggered shallow trench structure is formed by etching process; Step 7: forming a P-type heterogeneous layer in the trench by selective epitaxial growth or physical / chemical vapor deposition, and doping an appropriate amount of impurities as doping elements to adjust the lattice constant and electrical properties of the material; Step 8: Perform chemical mechanical planarization (CMP) on the device surface to achieve fine surface flatness by combining chemical etching and mechanical grinding; Step 9: sequentially growing or depositing a dielectric layer and depositing an electrode material on the surface of the device to form a dielectric layer and an electrode material with excellent conductivity; Step 10: patterning the dielectric layer and the electrode material by photolithography and etching processes to form a gate dielectric layer (12) and a gate electrode (10) structure; Step 11: Before depositing the metal layer, a layer of pre-metal dielectric material is deposited on the device surface to play a role in insulation protection or interface optimization; Step 12: forming a through hole in the dielectric layer by an etching process, and depositing a conductive material into the through hole as a plug to achieve electrical connection between different layers inside the device; Step 13: uniformly deposit a conductive material on the surface of the metal front dielectric and perform patterning through photolithography and etching processes. Based on conventional semiconductor device manufacturing processes, the device surface is deposited and patterned to form a source electrode (11) and a drain electrode (3).

9. The method for preparing a lateral strained superjunction metal oxide semiconductor field effect transistor according to claim 8, characterized in that: The impurity doped in step 7 is one of germanium or boron.

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