Solar cell, manufacturing method thereof and photovoltaic module

Abstract

The invention discloses a solar cell, a manufacturing method thereof and a photovoltaic module, relates to the technical field of photovoltaic, and is used for optimizing the cell efficiency of the solar cell with an amorphous silicon film layer. The solar cell comprises a semiconductor substrate having a first surface and a second surface opposite to each other; the first semiconductor layer is arranged on the first face, the first semiconductor layer is provided with a first part located in the middle area of the first face and a second part located in the edge area of the first face, and the crystallization rate of the first part is larger than that of the second part; wherein the edge region surrounds the middle region, the edge region is adjacent to the edge of the first surface, and the first semiconductor layer comprises at least one of amorphous silicon and nanocrystalline silicon.

Description

[0001] This application claims the priority of a Chinese patent with an application number of 202411017051.5 and an application title of "A Solar Cell, Its Manufacturing Method, and a Photovoltaic Module" submitted to the Chinese Patent Office on July 26, 2024. The entire content thereof is incorporated herein by reference. Technical Field

[0002] The present invention relates to the field of photovoltaic technology, and particularly to a solar cell, its manufacturing method, and a photovoltaic module. Background Art

[0003] In the structure of a solar cell, a non - crystalline silicon layer on a textured surface is treated with a laser. After the non - crystalline silicon layer absorbs light, its temperature rises, H in the non - crystalline silicon layer escapes, the effective doping increases, and the contact resistance of the solar cell can be reduced after the laser treatment, thereby reducing the energy loss during the current collection process and improving the cell efficiency. However, if the area of the laser treatment is unreasonable, it will cause an increase in recombination in some areas of the solar cell, affecting the cell efficiency. Summary of the Invention

[0004] The purpose of the present invention is to provide a solar cell, its manufacturing method, and a photovoltaic module to reduce the contact resistance while reducing recombination and improving the cell efficiency.

[0005] In a first aspect, the present invention provides a solar cell, comprising:

[0006] A semiconductor substrate having opposite first and second surfaces;

[0007] A first semiconductor layer disposed on the first surface, the first semiconductor layer having a first portion in the middle region of the first surface and a second portion in the edge region of the first surface, the crystallization rate of the first portion being greater than that of the second portion; wherein the edge region surrounds the middle region and is adjacent to the edge of the first surface, and the first semiconductor layer comprises at least one of amorphous silicon and nanocrystalline silicon.

[0008] In the case of adopting the above technical solution, only the first part of the first semiconductor layer located in the middle region of the semiconductor substrate forms a crystallization structure, so that there are both a crystallized part and another non-crystallized part in the first part, while the second part of the first semiconductor layer located in the edge region of the semiconductor substrate is not crystallized and retains the original amorphous structure, making the overall crystallization rate of the first part of the first semiconductor layer greater than that of the second part. The crystallization structure in the first part is formed by laser irradiation. Due to the non-uniformity of the entire laser beam and the non-uniform thickness of the first semiconductor layer, when the laser acts on the edge of the semiconductor substrate, the laser will damage the passivation of the first semiconductor layer at the edge position, thereby increasing the recombination at the edge position. Therefore, in this application, the crystallization structure is not formed by laser at the edge, and the amorphous structure at the edge of the first semiconductor layer is retained, leaving the second part at the edge, thereby ensuring the passivation effect of the second part located at the edge, reducing the recombination at the edge, and having a first part with a relatively large crystallization rate in the middle region of the first semiconductor layer, reducing the contact resistance. Therefore, by reasonably setting the region with a crystallization structure on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized, and the cell efficiency is improved.

[0009] In some possible implementation manners, the first semiconductor layer entirely covers the first surface, the first part is rectangular in shape, and the second part is annular in shape. With such a setting, the entire first surface of the solar cell is covered with the first semiconductor layer, which can form one side of a double-sided solar cell and can be used as a P region or an N region, and a heterojunction structure can be formed on the first semiconductor layer on this surface. As long as the first semiconductor layer in this application is used, the double-sided solar cell can also be applicable to the cell structure in this application where the edge is an amorphous structure and the middle region has a crystallization structure to improve the cell efficiency.

[0010] In some possible implementation manners, the solar cell further includes a third amorphous semiconductor layer disposed on the second surface. The third semiconductor layer includes a polysilicon layer or an amorphous silicon layer, and the conductivity types of the first semiconductor layer and the third amorphous semiconductor layer are different. With such a setting, when the third semiconductor layer includes an amorphous silicon layer, the entire surface of both sides of the semiconductor substrate is provided with an amorphous silicon layer, and heterojunction structures can be formed on the amorphous silicon layers on both sides, thereby forming a double-sided heterojunction cell. When the third semiconductor layer includes polysilicon, a polysilicon layer passivation structure can be formed on the second surface, and a passivation structure of an amorphous silicon layer or a nanocrystalline silicon layer can be formed on the first surface, thereby forming a double-sided hybrid cell. As long as there is an amorphous silicon layer and / or a nanocrystalline silicon layer, the double-sided heterojunction cell and the double-sided hybrid cell can also be applicable to the cell structure in this application where the edge is an amorphous structure and the middle region has a crystallization structure to improve the cell efficiency.

[0011] In some possible implementations, the third semiconductor layer is a polysilicon layer, the semiconductor layer is arranged in strips on the second surface, or the third semiconductor layer is entirely arranged on the second surface, and the third semiconductor layer includes a thicker portion arranged in strips and a thinner portion other than the thicker portion.

[0012] In some possible implementations, the solar cell further includes a second semiconductor layer disposed on the first surface, the first semiconductor layer includes a plurality of first strip portions extending along the first direction, the second semiconductor layer includes a plurality of second strip portions extending along the first direction, the first strip portions and the second strip portions are alternately arranged along the second direction, the first semiconductor layer and the second semiconductor layer have different conductivity types, and the first direction and the second direction intersect. In order to realize the arrangement of the P region and the N region on the first surface, the first semiconductor layer is one of the P region and the N region, and the second semiconductor layer is the other of the P region and the N region. For the strip-shaped first strip portion, the first portion is located in the middle region of the extension direction of the first strip portion, and the second portion is located in the edge regions at both ends of the extension direction. The arrangement of the edge amorphous structure of the first semiconductor layer is realized.

[0013] In some possible implementations, within the first strip portion, the first portion includes a strip-shaped middle portion extending along the first direction and strip-shaped edge portions arranged on both sides of the middle portion along the second direction, and the crystallization rate of the middle portion is greater than the crystallization rate of the edge portions. That is, in the second direction, the first portion does not all have the same crystallization rate, but the crystallization rate of the middle portion is greater than the crystallization rate of the edge portions on both sides, and the amorphous structure is reserved on both sides of the first portion in the second direction, and the crystallization rate can be the same as that of the second portion, so that the middle portion with a relatively high crystallization rate does not include the overlapping portion of the first strip portion overlapping the second strip portion, so that the first strip portion and the second strip portion of different conductivity types have better insulation in the overlapping portion, reducing leakage.

[0014] In some possible implementations, in the first strip portion, the width of the edge portion on one side of the middle portion along the second direction is less than or equal to 100 μm. In this way, the width of the edge portion is reduced as much as possible to increase the area of ​​the middle portion, reduce contact resistance, and improve current collection capability.

[0015] In some possible implementations, the second semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer. In this way, by selecting different materials for the second semiconductor layer, a back contact battery with different structures in the P region and the N region can be formed. As long as there is an amorphous silicon layer, a variety of back contact batteries can also be applied to the battery structure with an amorphous structure at the edge and a crystallized structure in the middle region in the present application to improve battery efficiency.

[0016] In some possible implementation manners, along the second direction, the crystallization rate of at least one first strip-shaped portion near the edge of the first surface is the same as that of the second portion. With such a setting, for the strip-shaped first strip-shaped portions, multiple first strip-shaped portions are arranged along the second direction. In the arrangement direction, the crystallization rate of the entire region of at least one first strip-shaped portion near the edge of the first surface is the same as that of the second portion, that is, at least one first strip-shaped portion near the edge does not undergo laser crystallization treatment, while the remaining first strip-shaped portions only form amorphous second portions at both ends of the extending direction, realizing the setting of the edge amorphous structure of the first semiconductor layer.

[0017] In some possible implementation manners, the contact resistance of the first portion is less than that of the second portion. Since the first portion can have a crystallized structure and the second portion is an amorphous structure, therefore, the effective doping of the crystallized structure of the first portion increases. Compared with the second portion, the contact resistance of the first portion can be reduced, thereby reducing the energy loss in the current collection process of the first portion and improving the battery efficiency.

[0018] In some possible implementation manners, the first strip-shaped portion has an overlapping portion stacked on the second strip-shaped portion, and the first portion does not include the overlapping portion; and / or, the solar cell further includes a first transparent conductive layer covering part of the first portion, and the projection of the middle portion on the first transparent conductive layer is at least located within the boundary of the first transparent conductive layer. With such a setting, by providing the transparent conductive layer, the carrier transport ability of the first semiconductor layer is improved, good ohmic contact can be formed with the electrode, the conductivity is improved, and the middle portion with a crystallized structure does not exceed the boundary of the first transparent conductive layer, realizing the reduction of the contact resistance within the effective conductive region of the first transparent conductive layer, improving the conductivity, and improving the battery efficiency.

[0019] In some possible implementation manners, the solar cell further includes a second transparent conductive layer and a third transparent conductive layer. The second transparent conductive layer covers part of the overlapping portion and part of the second strip-shaped portion; the third transparent conductive layer covers part of the second portion;

[0020] There is a PN isolation region between the adjacent first transparent conductive layer and the second transparent conductive layer;

[0021] There are edge isolation regions between the first transparent conductive layer and the third transparent conductive layer and between the second transparent conductive layer and the third transparent conductive layer.

[0022] In the case of adopting the above technical solution, electrical insulation between the P region and the N region is achieved through the PN isolation region, and electrical insulation between the middle region and the edge region is achieved through the edge isolation region. Moreover, the projection of the middle part of the first strip portion is located within the boundary of the first transparent conductive layer. Therefore, the middle part does not enter the boundary of the edge isolation region and / or does not enter the boundary of the PN isolation region, so the irradiation range of the laser does not enter the edge isolation region and the PN isolation region. Since there is no crystallization structure in the isolation region, the electrical insulation effect of the isolation region is ensured.

[0023] In some possible implementation manners, in the image obtained by the EL test of the solar cell, the brightness of the first part is greater than the brightness of the second part. When the EL test is performed on the solar cell under the same conditions, in the obtained image, the brightness of the first part is greater than the brightness of the second part, indicating that the contact resistance of the first part with the crystallization structure is smaller than that of the second part without the crystallization structure. When the solar cell is energized for testing, the electroluminescence brightness of the first part with a smaller contact resistance is greater, and the electroluminescence brightness of the second part is smaller.

[0024] In some possible implementation manners, the solar cell further includes a first grid line electrode extending along a first direction. The first grid line electrode is conductively disposed on a first part of the first semiconductor layer and extends from the first part to the second part. The extending direction of the first grid line electrode is consistent with the extending direction of the first semiconductor layer, and can collect the carriers of both the first part and a part of the second part. Therefore, the carrier collection ability of the first grid line electrode for the first semiconductor layer can be improved.

[0025] In some possible implementation manners, along the direction from the first part to the second part and perpendicular to the side length of the semiconductor substrate, the width of the second part is 0.3 mm to 12 mm. That is, an edge region of 0.3 mm to 12 mm is reserved on the semiconductor substrate without laser crystallization treatment. If the width of the second part is too wide, the area of the first part of the overall solar cell is small, the reduction of the series resistance is small, and the loss during current collection is large; if the width of the second part is too small, on the one hand, due to the limitation of the coating process at the edge of the first semiconductor layer, the first semiconductor layer in the edge region is relatively thin, and on the other hand, when laser irradiation is performed at the edge of the solar cell, the angle is relatively large, and the energy distribution in the laser spot is deviated, and it is easy for part of the laser energy density to be too large and cause damage to the passivation of the first semiconductor layer in the edge region. Therefore, considering the reduction of the overall contact resistance of the solar cell and the reduction of damage to the passivation, the width of the second part is selected to be 0.3 mm to 12 mm.

[0026] In a second aspect, the present invention further provides a solar cell, including:

[0027] A semiconductor substrate having opposite first and second surfaces;

[0028] A first semiconductor layer disposed on the first surface, the first semiconductor layer including an intermediate portion located in the middle region of itself and an edge portion located in the peripheral region of the intermediate portion, wherein the edge portion surrounds the intermediate portion; the intermediate portion includes amorphous silicon and nanocrystalline silicon, and the edge portion is amorphous silicon.

[0029] In the case of adopting the above technical solution, only a crystallization structure is formed in the intermediate portion located in the middle region of the first semiconductor layer, so that both nanocrystalline silicon and amorphous silicon are present in the intermediate portion, while the edge portion located in the peripheral region of the intermediate portion of the first semiconductor layer is not crystallized and retains the original amorphous silicon, so that the overall crystallization rate of the intermediate portion of the first semiconductor layer is greater than the overall crystallization rate of the edge portion. The nanocrystalline silicon in the intermediate portion is formed by laser irradiating amorphous silicon. Due to the non-uniformity of the full amplitude of the laser and the non-uniformity of the thickness of the first semiconductor layer, when the laser acts on the edge of the first semiconductor layer, the laser will damage the passivation of the edge portion of the first semiconductor layer, thereby increasing the recombination of the edge portion. Therefore, in this application, nanocrystalline silicon is not formed by laser in the edge portion, and the amorphous silicon of the edge portion of the first semiconductor layer is retained, thereby ensuring the passivation effect of the edge portion close to the edge of the semiconductor substrate, reducing the recombination of the edge portion, and having a relatively large crystallization rate in the intermediate portion of the first semiconductor layer, reducing the contact resistance. Therefore, by reasonably setting the region with a crystallization structure on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0030] In some possible implementation manners, the first semiconductor layer covers the entire first surface, and the edge portion is an annular shape between the intermediate portion and the edge of the first surface. With such a setting, the entire first surface of the solar cell is covered with the first semiconductor layer, which can form one side of a double-sided solar cell and can be used as a P region or an N region, and a heterojunction structure can be formed on the first semiconductor layer on this surface. As long as the first semiconductor layer in this application is provided, the double-sided solar cell can also be applied to the cell structure in this application where the edge is amorphous silicon and the intermediate portion has amorphous silicon and nanocrystalline silicon to improve the cell efficiency.

[0031] In some possible implementation manners, the solar cell further includes a third semiconductor layer disposed on the second surface, and the third semiconductor layer includes at least one of a polysilicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer. With such a setting, a double-sided solar cell is formed, and the semiconductor layers on the first surface and the second surface can be the same or different. As long as the first semiconductor layer in this application is provided, the double-sided cell is applicable to the cell structure in this application where the edge is amorphous silicon and the intermediate portion has amorphous silicon and nanocrystalline silicon to improve the cell efficiency.

[0032] In some possible implementation manners, the solar cell further includes a second semiconductor layer disposed on the first surface. The first semiconductor layer and the second semiconductor layer are both in a long strip shape extending along the first direction, and are disposed adjacent to each other along the second direction. The first semiconductor layer includes an overlapping portion stacked on the second semiconductor layer; the first semiconductor layer and the second semiconductor layer have different conductivity types, the first direction and the second direction intersect, and the middle portion does not include the overlapping portion.

[0033] In the case of adopting the above technical solution, the long strip-shaped first semiconductor layer and the second semiconductor layer are disposed adjacent to each other along the second direction. The first semiconductor layer includes an overlapping portion stacked on the second semiconductor layer, and the middle portion having amorphous silicon and nanocrystalline silicon does not include the overlapping portion. Therefore, the first semiconductor layer and the second semiconductor layer with different conductivity types have good insulation in the overlapping portion, reducing leakage current.

[0034] In some possible implementation manners, the solar cell further includes a first transparent conductive layer covering the first semiconductor layer. The projection of the middle portion on the semiconductor substrate is completely located within the projection of the first transparent conductive layer on the semiconductor substrate. With such a setting, by providing the first transparent conductive layer, the carrier transport ability of the first semiconductor layer is improved, a good ohmic contact can be formed with the electrode, the conductivity is improved, and the middle portion having amorphous silicon and nanocrystalline silicon does not exceed the boundary of the first transparent conductive layer, realizing a reduction in contact resistance within the effective conductive region of the first transparent conductive layer, improving the conductivity, and improving the cell efficiency.

[0035] In some possible implementation manners, the semiconductor substrate includes a recessed portion on the first surface. The recessed portion is recessed in the direction of the second surface relative to the rest of the first surface. The middle portion is located within the recessed portion. With such a setting, the recessed portion is formed by etching to the surface of the semiconductor substrate and usually has a textured structure. Setting the middle portion with a relatively high crystallization rate in the recessed portion can increase the contact area of the middle portion, which is beneficial to current collection.

[0036] In some possible implementation manners, along the first direction, there is a first distance between the boundary of the middle portion and the boundary of the first semiconductor layer; along the second direction, there is a second distance between the boundary of the middle portion and the boundary of the first semiconductor layer; wherein, the first distance is greater than the second distance. Since the portion of the first semiconductor layer close to the edge of the semiconductor substrate has large defects, poor passivation effect, large leakage current, and serious recombination, the first distance between the middle portion and the boundary of the first semiconductor layer is set to be larger to avoid edge defects, and the second distance only needs to ensure that the middle portion with a relatively high crystallization rate does not include the overlapping portion, and the second distance is reduced as much as possible to increase the area of the middle portion, reduce the contact resistance, and improve the current collection ability.

[0037] In some possible implementations, the first spacing is 0.2 mm to 12 mm, and / or the second spacing is less than or equal to 100 μm. If the width of the first spacing is too wide, the middle part of the overall solar cell is small, resulting in a small reduction in series resistance and large losses during current collection. If the width of the first spacing is too small, there are large edge defects, poor passivation effect, large recombination, and large leakage current. Therefore, considering the reduction of the overall contact resistance of the solar cell and avoiding edge defects, the first spacing is selected to be 0.2 mm to 12 mm. If the second spacing is too large, the middle part will be small and the current collection loss will be large. Therefore, the second spacing is less than or equal to 100 μm.

[0038] In some possible implementations, the solar cell further includes a first grid electrode disposed on the first semiconductor layer and extending along the first direction, and the first grid electrode extends from above the middle part to above the edge part. The extending direction of the first grid electrode is the same as the extending direction of the first semiconductor layer, and can collect the carriers in both the middle part and the edge part. Therefore, the carrier collection ability of the first grid electrode for the first semiconductor layer can be improved.

[0039] In some possible implementations, the solar cell further includes a first grid electrode disposed on the first semiconductor layer and extending along the first direction; along the second direction, the ratio of the width of the first grid electrode to the width of the middle part is 10%-120%. Reasonably setting the ratio of the width of the first grid electrode to the width of the middle part can ensure that the first grid electrode is located above the middle part within the process error range, thereby improving the current collection efficiency. At the same time, compared with the middle part, a first grid electrode that is too narrow will result in incomplete current collection in the second direction, while a first grid electrode that is too wide will cause waste of materials and may cause the first grid electrode to climb into the PN isolation area resulting in leakage.

[0040] In some possible implementations, the solar cell further includes a first grid electrode disposed on the first transparent conductive layer and extending along the first direction; along the second direction, the width of the first grid electrode is less than or equal to the width of the first transparent conductive layer, and the width of the first transparent conductive layer is greater than the width of the middle part. With such a setting, the first grid electrode can be disposed opposite to the middle part, and the width of the first transparent conductive layer is greater than the width of the middle part to improve the current collection ability.

[0041] In a third aspect, the present invention further provides a photovoltaic module, including a solar cell, and the solar cell is the solar cell described in any one of the above.

[0042] Since the photovoltaic module uses the solar cell of the first aspect and any one of the above, the photovoltaic module has the same beneficial effects as the first aspect and will not be elaborated here.

[0043] In a fourth aspect, the present invention further provides a method for manufacturing a solar cell, including:

[0044] providing a semiconductor substrate having opposite first and second surfaces;

[0045] forming a first semiconductor layer on the first surface, the first semiconductor layer having a middle portion located in the middle region of itself and an edge portion located in the peripheral region of the middle portion;

[0046] irradiating the middle portion with a laser so that the crystallization rate of the middle portion is greater than that of the edge portion; wherein the edge portion surrounds the middle portion, and the first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

[0047] In the case of adopting the above technical solution, the middle portion located in the middle region of the first semiconductor layer is crystallized by using a laser, so that the crystallization rate is increased, while the edge portion located in the peripheral region of the middle portion of the first semiconductor layer is not irradiated with a laser and retains an amorphous structure. Due to the non-uniformity of the full area of the laser and the non-uniformity of the thickness of the first semiconductor layer, when the laser acts on the edge portion of the first semiconductor layer, the laser will damage the passivation of the edge portion, thereby increasing the recombination of the edge portion. Therefore, in this application, a crystalline structure is not formed by laser at the edge portion, and the amorphous structure of the edge portion of the first semiconductor layer is retained, thereby ensuring the passivation effect at the edge portion, reducing the recombination at the edge, and forming a middle portion by laser crystallization in the middle region of the first semiconductor layer, reducing the contact resistance. Therefore, by reasonably controlling the laser irradiation area on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved. When the first semiconductor layer includes an amorphous silicon layer and / or a nanocrystalline silicon layer, the crystallization rate can be increased by laser irradiation.

[0048] In some possible implementation manners, the first surface has a first side and a second side oppositely arranged along a first direction;

[0049] irradiating the middle portion with a laser includes:

[0050] starting to irradiate with a laser at a position at a first distance from the first side, and passing through the middle portion along the first direction and stopping irradiating at a position at a second distance from the second side.

[0051] In the case of adopting the above technical solution, the laser irradiates the first semiconductor layer in the direction from the first side to the second side. The starting point of the irradiation of the middle part is at a first distance from the first side, and the ending point of the irradiation of the middle part is at a second distance from the second side. Only the middle part of the first semiconductor layer is irradiated, and the laser irradiation stops at the edge parts on both sides of the middle part. The irradiation can be repeated multiple times in the first direction so that the range perpendicular to the first direction in the middle part is irradiated by the laser.

[0052] In some possible implementation manners, the first distance and / or the second distance is 0.2 mm to 12 mm. That is, an unirradiated edge part of the first semiconductor layer is reserved. If the edge part is too wide, the area of the middle part of the overall solar cell is small, the reduction of the series resistance is small, and the loss during current collection is large. If the width of the edge part of the first semiconductor layer is too small, on the one hand, due to the limitation of the coating process, the edge part of the first semiconductor layer is relatively thin. On the other hand, when laser irradiation is performed at the edge of the solar cell, the angle is relatively large, and the energy distribution in the laser spot is deviated, and it is easy for part of the laser energy density to be too high, causing damage to the passivation of the edge part of the first semiconductor layer. Therefore, considering the reduction of the overall contact resistance of the solar cell and the reduction of damage to passivation, the first distance and / or the second distance is selected to be 0.2 mm to 12 mm.

[0053] In some possible implementation manners, the first semiconductor layer includes an amorphous silicon layer. After the middle part is irradiated with the laser, part of the amorphous silicon layer crystallizes to form nanocrystals. When the first semiconductor layer adopts an amorphous silicon layer, the unirradiated part has a better passivation effect and a better insulation effect in the isolation region.

[0054] In some possible implementation manners, the wavelength of the laser is 325 nm to 532 nm; and / or, the energy density of the laser is 200 mJ / cm 2 ~6000 mJ / cm 2 . By setting this wavelength range, it can be absorbed by the amorphous semiconductor layer, which is beneficial to realizing the crystallization of the amorphous semiconductor layer. If the laser energy density is too high, the high-temperature range will expand, and the temperature at the top of the textured structure will be too high, thus affecting the passivation of the top region of the textured structure. If the laser energy density is too small, the energy accumulation time is too long, affecting the production efficiency, and the energy may not reach the energy required for crystallization. Therefore, by selecting the laser energy density in this range, it can be realized that only the top of the textured structure reaches a high temperature, the morphological change is realized, and a crystallized structure is formed. Description of the Drawings

[0055] The accompanying drawings described herein are used to provide a further understanding of the present invention and form a part of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0056] Figure 1 It is a schematic diagram of the structure of the first side of a solar cell provided by an embodiment of the present invention without electrodes;

[0057] Figure 2 It is a schematic diagram of the structure of the first side of a solar cell provided by an embodiment of the present invention with electrodes;

[0058] Figure 3 is Figure 2 a partial enlarged schematic diagram in;

[0059] Figure 4 It is a schematic diagram of the partial layout of the transparent conductive layer on the first side of a solar cell provided by an embodiment of the present invention;

[0060] Figure 5 is Figure 4 a cross-sectional schematic diagram of the A-A section in;

[0061] Figure 6 is Figure 4 a cross-sectional schematic diagram of the B-B section in;

[0062] Figure 7 is Figure 2 a partial enlarged schematic diagram in;

[0063] Figures 8 - 19 It is a schematic diagram of the process flow of each step of a method for manufacturing a solar cell provided by an embodiment of the present invention;

[0064] Figure 20 It is a schematic diagram of the comparison of EL test images of the solar cell provided by an embodiment of the present invention and the existing solar cell without an amorphous region;

[0065] Figure 21 It is a schematic diagram of the comparison of the P-region contact resistance of the solar cell provided by an embodiment of the present invention and the existing solar cell without an amorphous region;

[0066] Figure 22 It is a schematic diagram of the crystallization at the top of the pyramid provided by an embodiment of the present invention.

[0067] Reference numerals: 100 is the first semiconductor layer, 1 is the first strip portion, 11 is the first part, 12 is the second part, 13 is the intrinsic amorphous silicon layer, 14 is the p-type amorphous silicon layer, 15 is the stacked portion, 2 is the second semiconductor layer, 21 is the tunneling oxide layer, 22 is the n-type doped polysilicon layer, 3 is the edge isolation region, 4 is the first gate line electrode, 5 is the second gate line electrode, 6 is the semiconductor substrate, 7 is the transparent conductive layer, 71 is the first transparent conductive layer, 72 is the second transparent conductive layer, 73 is the third transparent conductive layer, 8 is the passivation layer, 9 is the antireflection layer, 10 is the PN isolation region. Detailed implementation manners

[0068] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present invention clearer and more understandable, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0069] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0070] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, the meaning of "a plurality" is two or more, unless otherwise specifically defined. The meaning of "several" is one or more, unless otherwise specifically defined.

[0071] In the description of the present invention, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "front", "rear", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present invention.

[0072] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "installed", "connected", and "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the communication inside two components or the interaction relationship between two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0073] As Figures 1 - 7 shown, an embodiment of the present invention provides a solar cell, including a semiconductor substrate 6 and a first semiconductor layer 100; wherein, the semiconductor substrate 6 has opposite first and second surfaces; the first semiconductor layer 100 is disposed on the first surface of the semiconductor substrate 6, and the first semiconductor layer 100 has a first portion 11 located in the middle region of the first surface and a second portion 12 located in the edge region of the first surface. The crystallization rate of the first portion 11 is greater than that of the second portion 12. The edge region surrounds the middle region and is adjacent to the edge of the first surface. The projected area of the middle region on the first surface accounts for more than 90% of the area of the first surface, and the edge region has a substantially rectangular annular structure. The first semiconductor layer 100 includes at least one of amorphous silicon and nanocrystalline silicon, that is, the first semiconductor layer 100 may be an amorphous silicon layer, a nanocrystalline silicon layer, or a combination of nanocrystalline silicon and amorphous silicon. After laser crystallization, the crystallization rate can be improved. Exemplarily, when the first semiconductor layer 100 is an amorphous silicon layer, in the laser-crystallized part, some crystallization will occur inside the amorphous silicon layer to form nanocrystals. When the first semiconductor layer 100 is a nanocrystalline silicon layer or a combination of amorphous silicon and nanocrystals, in the laser-crystallized part, the crystallinity or crystallization rate of the first semiconductor layer 100 will increase.

[0074] In the actual application process, the embodiment of the present invention does not specifically limit the material and conductivity type of the semiconductor substrate 6. Exemplarily, the above semiconductor substrate 6 may be a silicon substrate. Alternatively, the above semiconductor substrate 6 may also be a substrate of any semiconductor material such as a germanium-silicon substrate, a germanium substrate, or a gallium arsenide substrate. The conductivity type of the semiconductor substrate 6 may be an N-type semiconductor substrate, a P-type semiconductor substrate, or an intrinsic semiconductor substrate.

[0075] Secondly, the first surface of the above semiconductor substrate 6 corresponds to the backlight surface of the solar cell, and the second surface of the semiconductor substrate 6 corresponds to the light-facing surface of the solar cell, that is, the front surface.

[0076] In the case of adopting the above technical solution, only the first part 11 located in the middle region of the semiconductor substrate 6 in the first semiconductor layer 100 forms a crystallization structure, so that there are both a crystallized part and another non-crystallized part in the first part 11. The first part 11 is not entirely a crystallization structure, but mostly an amorphous structure, and only part of it forms a crystallization structure, such as nanocrystals. The second part 12 of the first semiconductor layer 100 located in the edge region of the semiconductor substrate 6 is not crystallized and retains the original amorphous structure (it should be noted that when the first semiconductor layer 100 includes nanocrystalline silicon, the crystallization rate or crystallinity of the nanocrystalline silicon in the second part 12 remains unchanged), so that the overall crystallization rate of the first part 11 of the first semiconductor layer 100 is greater than the overall crystallization rate of the second part 12. The crystallization structure in the first part 11 is formed by laser irradiation. Due to the non-uniformity of the full laser beam and the non-uniform thickness of the first semiconductor layer 100, when the laser acts on the edge of the semiconductor substrate 6, the laser will damage the passivation of the first semiconductor layer 100 at the edge position, thereby increasing the recombination at the edge position. Therefore, in this application, a crystallization structure is not formed by laser at the edge of the first semiconductor layer 100, and the amorphous structure at the edge of the first semiconductor layer 100 is retained, leaving the second part 12 at the edge, thereby ensuring the passivation effect of the second part 12 located at the edge, reducing the recombination at the edge, and forming the first part 11 with a crystallization structure in the middle region of the first semiconductor layer 100. The crystallization structure in the first part 11 reduces the contact resistance. At the same time, the amorphous structure in the first part 11 also has a good passivation effect. Therefore, by setting reasonable crystallization regions and amorphous regions on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized and the cell efficiency is improved.

[0077] It can be understood that in the case where at least part of the first surface of the semiconductor substrate 6 is a textured surface, a plurality of pseudo-pyramids are formed on the textured surface. As Figure 22 shown, the first semiconductor layer 100 is conformally disposed on the textured surface, and the crystallization degree of the part of the first semiconductor layer 100 covering at least part of the tops of the pseudo-pyramids is greater than the crystallization degree of the other part of the first semiconductor layer 100 covering the bases of the pseudo-pyramids. During the process of observing the crystallization degree of the first semiconductor layer 100, if the observed area is too small and only the area within the base region of the pseudo-pyramid is observed, the crystallization degree of the first semiconductor layer 100 cannot be accurately obtained. Therefore, the observed area should at least include one pseudo-pyramid. Preferably, the observed area should be greater than or equal to 5*5 μm 2 to prevent the crystallization degree of the first semiconductor layer 100 from not being accurately obtained when only observing the area within the base region of the pseudo-pyramid.

[0078] In some possible implementation manners, the contact resistance of the first part 11 is less than that of the second part 12. Since the first part 11 has a crystallized structure or a higher crystallization rate, and the second part 12 is an amorphous structure or has a lower crystallization rate, the effective doping of the first part 11 increases. Compared with the second part 12, the contact resistance of the first part 11 can be reduced, thereby reducing the energy loss during the current collection process of the first part 11 and improving the battery efficiency. Exemplarily, as Figure 21 shown, when the first semiconductor layer 100 is disposed in the P region, by comparing the P-region contact resistances of the battery without a crystallized region and the battery with a crystallized region, it can be seen that the overall contact resistance of the solar cell with the first semiconductor layer 100 having the first part 11 is less than the overall contact resistance of the solar cell without the first semiconductor layer 100 having the first part 11.

[0079] This embodiment provides a solar cell. The first semiconductor layer 100 entirely covers the first surface. The first part 11 is in a rectangular shape, and the second part 12 is in an annular shape. That is, the first semiconductor layer 100 is a continuous integral surface structure covering the entire first surface, roughly in a rectangular shape. The first part 11 located in the middle region corresponds to a rectangular shape, and the second part 12 located in the edge region corresponds to a rectangular ring shape. The first semiconductor layer 100 can form one side of a double-sided solar cell and can be used as a P region or an N region. Since the first semiconductor layer 100 includes amorphous silicon and / or nanocrystalline silicon, the first semiconductor layer 100 can form a heterojunction structure.

[0080] On this basis, a third semiconductor layer having a conductivity type opposite to that of the first semiconductor layer 100 is disposed on the second surface. The third semiconductor layer includes a polysilicon layer or an amorphous silicon layer. For example, if the second surface is entirely covered with an amorphous silicon layer, the third semiconductor layer can also form a heterojunction structure. The structure of the third semiconductor layer can be similar to that of the first semiconductor layer 100, and also has a first part and a second part, and the crystallization rate of the first part is greater than that of the second part.

[0081] In one example, when the conductivity type of the first semiconductor layer is P type and the conductivity type of the third semiconductor layer is N type, the first semiconductor layer includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface. The first intrinsic amorphous silicon layer is disposed close to the first surface. The third semiconductor layer includes a third intrinsic amorphous silicon layer and an n-type amorphous silicon layer stacked on the second surface. The third intrinsic amorphous silicon layer is disposed close to the second surface, forming a double-sided heterojunction battery. Of course, the conductivity type of the first semiconductor layer can also be N type and the conductivity type of the third semiconductor layer can be P type, which will not be elaborated here.

[0082] In another example, if a polysilicon layer is provided on the second surface, the third semiconductor layer may form a tunneling passivation contact structure. Specifically, if the conduction type of the first semiconductor layer is P-type and the conduction type of the third semiconductor layer is N-type, the first semiconductor layer includes a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer stacked on the first surface, with the first intrinsic amorphous silicon layer being close to the first surface. The third semiconductor layer includes an N-type doped polysilicon layer provided on the second surface, and a tunneling oxide layer is further provided between the N-type doped polysilicon layer and the second surface. The tunneling oxide layer and the N-type doped polysilicon layer form a tunneling passivation contact structure. The third semiconductor layer may be partially provided on the second surface. For example, it may be provided in multiple strip shapes, forming a poly-finger structure at this time, and doping field regions may be selectively formed on the substrate between the poly-fingers; alternatively, the third semiconductor layer may be formed entirely on the second surface, except that the metallization contact region has a thicker part, while the third semiconductor layer has a thinner part in the non-metallized region. The first semiconductor layer may be a heterojunction structure, forming a double-sided hybrid solar cell. Of course, the conduction type of the first semiconductor layer may also be N-type and the conduction type of the third semiconductor layer may be P-type, which will not be elaborated here.

[0083] As long as there are amorphous silicon layers and / or nanocrystalline silicon layers, double-sided heterojunction cells and double-sided hybrid solar cells can also be applicable to the cell structure in this application where the edge is an amorphous structure and the middle region has a crystallized structure, so as to improve the cell efficiency.

[0084] As Figure 1 shown, this embodiment provides another solar cell. The solar cell further includes a second semiconductor layer 2 provided on the first surface. The first semiconductor layer 100 includes a plurality of first strip-shaped portions 1 extending along the first direction, and the second semiconductor layer 2 includes a plurality of second strip-shaped portions extending along the first direction. The first strip-shaped portions 1 and the second strip-shaped portions are alternately arranged along the second direction, and the conduction types of the first semiconductor layer 100 and the second semiconductor layer 2 are different, with the first direction and the second direction intersecting. For the case where the first semiconductor layer 100 is provided on the first surface, in order to realize the arrangement of the P region and the N region on the first surface, the first semiconductor layer 100 is one of the P region and the N region, and the second semiconductor layer 2 is the other of the P region and the N region. For the strip-shaped first strip-shaped portions 1, a first part 11 is located in the middle region of the extension direction of the first strip-shaped portions 1, and a second part 12 is located at the two end edge regions of the extension direction. The edge amorphous structure of the first semiconductor layer 100 is realized.

[0085] As Figure 6 and Figure 7As shown, in some embodiments, for the first strip-shaped portion 1, the first portion 11 includes a middle portion extending in a strip shape along the first direction and edge portions in a strip shape arranged on both sides of the middle portion along the second direction, and the lengths of the middle portion and the edge portions along the first direction may be the same, wherein the crystallization rate of the middle portion is greater than the crystallization rate of the edge portion, and the crystallization rate of the edge portion may be the same as the crystallization rate of the second portion 12. That is, along the second direction, the first portion 11 is divided into two parts, the middle portion and the edge portion, and the entire second portion 12 is an amorphous structure. In the second direction, not all regions of the first portion 11 are crystallized, but only the middle portion is crystallized, and both sides of the middle portion and the second portion 12 are amorphous structures, and no laser crystallization is performed. Since the first portion 11 has a crystallized structure and the second portion 12 is an amorphous structure, the overall crystallization rate of the middle portion is greater than the crystallization rates of the edge portion and the second portion 12. By such arrangement, the middle part with a relatively high crystallinity rate does not include the overlapping part 15 where the first strip part 1 overlaps the second strip part, so that the first strip part 1 and the second strip part of different conductivity types have better insulation in the overlapping part 15, thereby reducing leakage.

[0086] Furthermore, in this embodiment, the width of the edge portion on one side of the middle portion in the first strip portion 1 along the second direction is less than or equal to 100 μm. In this way, the width of the edge portion is reduced as much as possible to increase the area of ​​the middle portion, reduce the contact resistance, and improve the current collection capacity.

[0087] like Figure 1 As shown, in some possible implementations, along the second direction, the crystallization rate of at least one first strip portion 1 near the edge of the first surface is the same as the crystallization rate of the second portion 12. In this way, for the strip-shaped first strip portions 1, multiple first strip portions 1 are arranged along the second direction, and in the arrangement direction, the entire area of ​​at least one first strip portion 1 near the edge of the first surface has the same crystallization rate as the second portion 12, that is, at least one first strip portion 1 near the edge is not subjected to laser crystallization treatment, and the remaining first strip portions 1 only form amorphized second portions 12 at the two end edges in the extension direction, thereby realizing the setting of the edge amorphization structure of the first semiconductor layer 100.

[0088] For example, in the second direction, the crystallization rate of the entire area of ​​the two strip-shaped portions 1 respectively located on the two edges of the first surface is the same as the crystallization rate of the second portion 12, or two, three or more first strip-shaped portions 1 having the same crystallization rate as the second portion 12 are reserved near the edge of each first surface.

[0089] In some embodiments, along the direction from the first part 11 to the second part 12 and perpendicular to the side length of the semiconductor substrate 6, the width of the second part 12 is 0.3 mm to 12 mm. That is, a peripheral edge region of 0.3 mm to 12 mm is reserved around the first semiconductor layer 100 of the semiconductor substrate 6 without laser crystallization treatment. If the width of the second part 12 is too wide, the area of the first part 11 with a crystallized structure in the overall solar cell is small, the reduction of the series resistance is small, and the loss during current collection is large; if the width of the second part 12 is too small, on the one hand, due to the limitation of the coating process at the edge of the first semiconductor layer 100, the first semiconductor layer 100 in the edge region is relatively thin, and on the other hand, when laser irradiation is performed at the edge of the solar cell, the angle is relatively large, resulting in a deviation in the energy distribution within the laser spot, and it is easy for part of the laser energy density to be too large, causing damage to the passivation of the first semiconductor layer 100 at the edge. Therefore, considering the reduction of the overall contact resistance of the solar cell and the reduction of damage to passivation, the width of the second part 12 is selected to be 0.3 mm to 12 mm.

[0090] Further, the width of the second part 12 is 0.3 mm to 3 mm. To further increase the area of the first part 11 of the first semiconductor layer 100, reduce the contact resistance, and improve the cell efficiency. Specifically, the width of the second part 12 can be 0.3 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, etc.

[0091] Exemplarily, for the first semiconductor layer 100 including a plurality of first strip portions 1, along the extension direction (the first direction) of the first strip portion 1, the extension lengths of the second part 12 at both ends of the first strip portion 1 are 1 mm, 1.2 mm, 1.5 mm, etc. Along the arrangement direction (the second direction) of the plurality of first strip portions 1, the crystallization rates of the two first strip portions 1 on the two side edges close to the first surface are the same as the crystallization rate of the second part 12.

[0092] In some embodiments, when the first semiconductor layer 100 and the second semiconductor layer 2 are provided on the first surface of the solar cell, that is, when the solar cell is a back contact cell, the second semiconductor layer 2 may include amorphous silicon and / or nanocrystalline silicon. The second semiconductor layer 2 has a structure similar to that of the first semiconductor layer 100, except for the different conduction types, that is, the second semiconductor layer 2 also has a first part in the middle region on the first surface and a second part in the edge region on the first surface. The first part of the second semiconductor layer 2 may be entirely a laser crystallization region or not entirely a laser crystallization region. Referring to the description of the first part 11 of the first semiconductor layer 100 above, it will not be elaborated here.

[0093] Exemplarily, taking the case where the first semiconductor layer corresponds to the P region and the second semiconductor layer corresponds to the N region as an example, the first semiconductor layer may include a first intrinsic amorphous silicon layer and a p-type amorphous silicon layer arranged in a stacked manner, and the second semiconductor layer may include a second intrinsic amorphous silicon layer and an n-type amorphous silicon layer arranged in a stacked manner. Both the first intrinsic amorphous silicon layer and the second intrinsic amorphous silicon layer are disposed close to the semiconductor substrate. Of course, the conduction types of the first semiconductor layer and the second semiconductor layer can be interchanged, which will not be elaborated herein.

[0094] With such an arrangement, for the first semiconductor layer and the second semiconductor layer with different conduction types disposed on the first surface, both the first semiconductor layer and the second semiconductor layer can form a heterojunction structure, forming a heterojunction back-contact cell having a P-region heterojunction structure and an N-region heterojunction structure on the back surface, which has the advantages of good passivation effect, high conversion efficiency, long service life, and low preparation energy consumption of the heterojunction structure. As long as there is an amorphous silicon layer and / or a nanocrystalline silicon layer, the heterojunction back-contact cell can also be applicable to the cell structure with an amorphous structure at the edge and a crystalline structure in the middle region in the present application to improve the cell efficiency.

[0095] As Figures 1 - 7 shown, in some embodiments, when the first surface of the solar cell has the first semiconductor layer 100 and the second semiconductor layer 2, that is, when the solar cell is a back-contact cell, the second semiconductor layer 2 can be at least one of a polysilicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer. The first semiconductor layer 100 can be a heterojunction structure. When the second semiconductor layer 2 is a polysilicon layer, a tunneling passivation contact structure can be formed, and the conduction types of the second semiconductor layer 2 and the first semiconductor layer 100 are different.

[0096] Exemplarily, the second semiconductor layer 2 may include a tunneling oxide layer 21 and a doped polysilicon layer arranged in a stacked manner on the first surface. The tunneling oxide layer 21 is disposed close to the semiconductor substrate 6. Taking the case where the second semiconductor layer 2 corresponds to the N region and the first semiconductor layer 100 corresponds to the P region as an example, the doped polysilicon layer of the second semiconductor layer 2 is an n-type doped polysilicon layer 22; the first semiconductor layer 100 includes an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 arranged in a stacked manner on the first surface, and the intrinsic amorphous silicon layer 13 is disposed close to the semiconductor substrate 6. Of course, when the second semiconductor layer 2 corresponds to the P region and the first semiconductor layer 100 corresponds to the N region, the doped polysilicon layer is a p-type doped polysilicon layer, and the doped amorphous silicon layer in the first semiconductor layer 100 is an n-type amorphous silicon layer.

[0097] With such a setting, by providing a second semiconductor layer 2 and a first semiconductor layer 100 with different conduction types on the first surface, a hybrid back-contact cell with a tunneling passivation contact structure and a heterojunction structure on the back surface is formed. Among them, the first semiconductor layer 100 is a heterojunction structure. This cell simultaneously has the advantages of high conversion efficiency, good stability, low Auger recombination of the tunneling passivation contact structure, and good passivation effect, high conversion efficiency, long service life, and low preparation energy consumption of the heterojunction structure. As long as there is an amorphous silicon layer and / or a nanocrystalline silicon layer, the hybrid back-contact cell can also be applied to the cell structure with an amorphous structure at the edge and a crystalline structure in the middle region in this application to improve the cell efficiency. Of course, when the second semiconductor layer 2 is other semiconductor layers, such as microcrystalline silicon or nanocrystalline silicon, a heterojunction structure can also be formed. By selecting different materials for the second semiconductor layer 2, back-contact cells with different structures in the P region and the N region can be formed.

[0098] As Figure 1 , Figures 4 - 7 shown, in some possible implementation manners, the first strip portion 1 has an overlapping portion 15 stacked on the second strip portion, and the first portion 11 does not include the overlapping portion 15; and / or, the solar cell further includes a first transparent conductive layer 71 covering part of the first portion 11, and the projection of the middle portion of the first portion 11 on the first transparent conductive layer 71 is at least located within the boundary of the first transparent conductive layer 71. With such a setting, by providing the first transparent conductive layer 71, the carrier transport ability of the first semiconductor layer 100 is improved, a good ohmic contact can be formed with the electrode, and the conductivity is improved. The middle portion with a crystalline structure does not exceed the boundary of the first transparent conductive layer 71, so as to reduce the contact resistance within the effective conductive region of the first transparent conductive layer 71, improve the conductivity, and improve the cell efficiency.

[0099] As Figures 5 - 7 shown, further, in some embodiments, the solar cell further includes a second transparent conductive layer 72 and a third transparent conductive layer 73. The second transparent conductive layer 72 covers part of the overlapping portion 15 and part of the second strip portion; the third transparent conductive layer 73 covers part of the second portion 12, mainly covering the position near the edge of the semiconductor substrate 6 of the second portion 12; wherein, there is a PN isolation region 10 between the adjacent first transparent conductive layer 71 and the second transparent conductive layer 72; there are edge isolation regions 3 between the first transparent conductive layer 71 and the third transparent conductive layer 73 and between the second transparent conductive layer 72 and the third transparent conductive layer 73.

[0100] In the case of adopting the above technical solution, the PN isolation region 10 realizes electrical insulation between the P region and the N region, and the edge isolation region realizes electrical insulation between the PN region in the middle region and the dead region in the edge region. It should be noted that the dead region may include a stack of a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is stacked on the second semiconductor layer, and the first semiconductor layer in the dead region belongs to the edge region of the second part. The third transparent conductive layer 73 is disposed on the first semiconductor layer in the dead region. The projection of the middle part of the first strip portion is located within the boundary of the first transparent conductive layer. Therefore, the middle part does not enter the boundary of the edge isolation region and / or does not enter the boundary of the PN isolation region, so the irradiation range of the laser does not enter the edge isolation region and the PN isolation region. Since there is no crystallization structure or the crystallization rate is low in the isolation region, the electrical insulation effect of the isolation region is ensured.

[0101] Exemplarily, as Figure 6 and Figure 7 shown, the first semiconductor layer 100 has an overlapping portion 15 stacked on the second semiconductor layer 2 in the second direction. For example, when the second semiconductor layer 2 includes a stacked tunneling oxide layer 21 and an n-type doped polysilicon layer 22, and the first semiconductor layer 100 includes a stacked intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14, at the junction of the first semiconductor layer 100 and the second semiconductor layer 2, the first semiconductor layer 100 overlaps on the second semiconductor layer 2 to form an overlapping portion 15. At this time, the PN isolation region 10 straddles part of the overlapping portion 15 and part of the non-overlapping portion of the first semiconductor layer 100. As Figure 5 shown, the edge isolation region 3 straddles part of the stack of the first semiconductor layer 100 and the second semiconductor layer 2 and part of the second part 12. Specifically, it straddles the side wall and part of the bottom wall of the recessed portion of the semiconductor substrate.

[0102] On the basis of having the PN isolation region 10 and the edge isolation region 3, along the second direction, as Figure 6 shown, the distance between the boundary of the middle part (i.e., the crystallized region) on the first semiconductor layer 100 and the boundary of the PN isolation region 10 is greater than or equal to zero; and / or, as Figure 5 shown, along the first direction and / or the second direction, the distance between the boundary of the middle part (i.e., the crystallized region) of the first part 11 on the first semiconductor layer 100 and the boundary of the edge isolation region 3 is greater than or equal to zero. That is, the middle part does not enter the boundary of the edge isolation region 3 and / or does not enter the boundary of the PN isolation region 10, so the irradiation range of the laser does not enter the edge isolation region 3 and the PN isolation region 10. Since the first semiconductor layer 100 in the edge isolation region 3 and the PN isolation region 10 is still in an amorphous structure or has a low crystallization rate, the electrical insulation effect of the edge isolation region 3 and the PN isolation region 10 is ensured.

[0103] As shown Figures 5 - 7 in FIG. 1, further, the first transparent conductive layer 71, the second transparent conductive layer 72, and the third transparent conductive layer 73 may be at least one of fluorine-doped tin oxide, aluminum-doped zinc oxide, indium tin oxide, indium tungsten oxide, indium molybdenum oxide, indium cerium oxide, and indium hydroxide. The transparent conductive layer may be a single-layer film or a stacked film.

[0104] As shown Figure 20 in FIG. 2, in this embodiment, the EL (Electroluminescent) test of the solar cell is a method for detecting internal defects of the solar cell. In the image obtained by the EL test, the brightness of the first part 11 with a relatively high crystallization rate is greater than the brightness of the second part 12 with a relatively low crystallization rate. When the EL test is performed on the solar cell under the same conditions, in the obtained image, the brightness of the first part 11 is greater than the brightness of the second part 12, indicating that the contact resistance of the first part 11 is smaller than the contact resistance of the second part 12. When the solar cell is energized for testing, the electroluminescent brightness of the first part 11 with a small contact resistance is relatively high, and the electroluminescent brightness of the second part 12 is relatively low. As can be seen from Figure 20 the image of the solar cell B in FIG. 3, the solar cell B has a first part 11 in the middle region and a second part 12 in the edge region, and the brightness of the first part 11 in the middle region is greater than the brightness of the second part 12 in the edge region. By comparing with the image of the solar cell C, it can be seen that the solar cell C does not have the first part 11 in the middle region. Therefore, the brightness of the entire surface of the solar cell C is consistent, and compared with the solar cell B, the overall brightness is low, indicating that the overall contact resistance of the solar cell C is large.

[0105] As shown Figure 2 and Figure 3 in FIGS. 4 and 5, in some possible implementation manners, the solar cell further includes a first grid line electrode 4 extending along a first direction. The first grid line electrode 4 is conductively disposed on the first part 11 of the first semiconductor layer 100 and extends from the first part 11 to the second part 12, and extends from the middle part of the first part 11 to the second part 12, and the first grid line electrode 4 does not extend into the edge isolation region 3. The extending direction of the first grid line electrode 4 is the same as the extending direction of the first strip portion 1, and can collect the carriers of both the first part 11 and a part of the second part 12 on the same first semiconductor layer 100. Therefore, the carrier collection ability of the first grid line electrode 4 for the first semiconductor layer 100 can be improved.

[0106] For a solar cell having a second semiconductor layer 2, the solar cell further includes a second grid electrode 5 conductively disposed on the second semiconductor layer 2. The extending direction of the second grid electrode 5 is along a first direction and is consistent with the extending direction of the second semiconductor layer 2. In the case of having a first transparent conductive layer 71 and a second transparent conductive layer 72, the first grid electrode 4 is disposed on the first transparent conductive layer 71, and the second grid electrode 5 is disposed on the second transparent conductive layer 72.

[0107] In some embodiments, the surface of the semiconductor substrate provided with the amorphous semiconductor layer has a velvet surface structure. The amorphous semiconductor layer is conformal with the velvet surface structure. The velvet surface structure has a light trapping effect, which increases the collection of light, and the velvet surface structure can achieve good contact with the electrode. When laser crystallizing the first part of the first semiconductor layer, the laser irradiates on the velvet surface structure of the first part, and can reach the crystallization temperature, so that a crystallized microcrystalline structure or nanocrystalline structure is formed in a local area of the first part. Thus, the crystallized region has both an amorphous structure and a crystallized structure. The crystallized structure reduces the contact resistance, but reduces the passivation effect, and the recombination may increase, which is not beneficial to the photoelectric efficiency. Therefore, by forming a crystallized structure in a local area of a part of the velvet surface structure, the two factors of contact resistance and passivation effect can be balanced, so that the cell efficiency is optimized.

[0108] This embodiment only describes the structure of a solar cell from the perspective of the first semiconductor layer. Similarly, taking Figures 1 - 7 as an example, the solar cell includes a semiconductor substrate 6 and a first semiconductor layer 100. The semiconductor substrate 6 has opposite first and second surfaces; the first semiconductor layer 100 is disposed on the first surface. The first semiconductor layer 100 includes a middle part located in the middle area of itself and an edge part located in the peripheral area of the middle part. The middle part includes amorphous silicon and nanocrystalline silicon, and the edge part is amorphous silicon; wherein the edge part surrounds the middle part. It should be noted that the edge part here does not refer to the edge of the semiconductor substrate 6, and there is still a certain distance between the edge part of the first semiconductor layer 100 and the edge of the semiconductor substrate 6.

[0109] Since a crystallization structure is formed only in the middle part of the middle region of the first semiconductor layer, both nanocrystalline silicon and amorphous silicon exist in the middle part. However, the edge part of the first semiconductor layer located in the peripheral region of the middle part is not crystallized and remains the original amorphous silicon, so that the overall crystallization rate of the middle part of the first semiconductor layer is greater than that of the edge part. The nanocrystalline silicon in the middle part is formed by irradiating the amorphous silicon with a laser. Due to the non-uniformity of the full width of the laser and the non-uniformity of the thickness of the first semiconductor layer, when the laser acts on the edge part of the first semiconductor layer, the laser will damage the passivation of the edge part of the first semiconductor layer, thereby increasing the recombination at the edge part. Therefore, in this application, nanocrystalline silicon is not formed by laser in the edge part, and the amorphous silicon in the edge part of the first semiconductor layer is retained, thus ensuring the passivation effect of the edge part close to the edge of the semiconductor substrate, reducing the recombination in the edge part, and having a relatively large crystallization rate in the middle part of the first semiconductor layer, reducing the contact resistance. Therefore, by reasonably setting the region with a crystallization structure on the first semiconductor layer, the overall cell efficiency of the solar cell is optimized, and the cell efficiency is improved.

[0110] In some embodiments, the first semiconductor layer entirely covers the first surface, and the edge part has an annular shape between the middle part and the edge of the first surface. With such a setting, the entire first surface of the solar cell is covered by the first semiconductor layer, which can form one side of a bifacial solar cell and can be used as a P region or an N region. The first semiconductor layer on this surface can form a heterojunction structure. As long as the first semiconductor layer in this application is provided, the bifacial solar cell can also be applicable to the cell structure in this application where the edge is amorphous silicon and the middle part has amorphous silicon and nanocrystalline silicon to improve the cell efficiency.

[0111] In some possible implementation manners, the solar cell further includes a third semiconductor layer disposed on the second surface, and the third semiconductor layer includes at least one of a polysilicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer. With such a setting, a bifacial solar cell is formed. The semiconductor layers on the first surface and the second surface can be the same or different. As long as the first semiconductor layer in this application is provided, the bifacial cell is applicable to the cell structure in this application where the edge part is amorphous silicon and the middle part has amorphous silicon and nanocrystalline silicon to improve the cell efficiency.

[0112] With Figure 1 , Figure 2 and Figure 7Taking the shown structure as an example, in some embodiments, when a first semiconductor layer 100 is disposed on the first surface, the solar cell further includes a second semiconductor layer 2 disposed on the first surface. Both the first semiconductor layer 100 and the second semiconductor layer 2 are in the shape of long strips extending along the first direction, and are adjacent to each other along the second direction. The first semiconductor layer 100 includes an overlapping portion 15 stacked on the second semiconductor layer 2; the first semiconductor layer 100 and the second semiconductor layer 2 have different conduction types, the first direction and the second direction intersect, and the middle portion does not include the overlapping portion 15.

[0113] In the case of adopting the above technical solution, the long-strip-shaped first semiconductor layer 100 and the second semiconductor layer 2 are adjacent to each other along the second direction. The first semiconductor layer 100 includes an overlapping portion 15 stacked on the second semiconductor layer 2, and the middle portion having amorphous silicon and nanocrystalline silicon does not include the overlapping portion 15, that is, the overlapping portion 15 is amorphous silicon. Therefore, the first semiconductor layer 100 and the second semiconductor layer 2 with different conduction types have good insulation at the overlapping portion 15, reducing leakage current.

[0114] As Figure 4 and Figure 6 shown, in some possible implementation manners, the solar cell further includes a first transparent conductive layer 71 covering the first semiconductor layer 100, and the projection of the middle portion on the semiconductor substrate 6 is completely located within the projection of the first transparent conductive layer 71 on the semiconductor substrate 6. By setting the first transparent conductive layer 71 in this way, the carrier transport ability of the first semiconductor layer 100 is improved, good ohmic contact can be formed with the electrode, the conductivity is improved, and the middle portion having amorphous silicon and nanocrystalline silicon does not exceed the boundary of the first transparent conductive layer 71, realizing a reduction in the contact resistance within the effective conductive region of the first transparent conductive layer 71, improving the conductivity, and improving the battery efficiency.

[0115] As Figure 5 and Figure 6 shown, in some embodiments, the semiconductor substrate 6 includes a recessed portion on the first surface. The recessed portion includes a side wall and a bottom wall. The recessed portion is recessed in the direction of the second surface relative to the rest of the first surface, and the middle portion is located within the recessed portion. By setting it in this way, the recessed portion is formed by etching to the surface of the semiconductor substrate 6 and usually has a textured structure. Setting the middle portion having amorphous silicon and nanocrystalline silicon in the recessed portion can increase the contact area of the middle portion, which is beneficial to current collection.

[0116] As Figure 5 and Figure 6As shown, in some possible implementation manners, along the first direction, there is a first spacing L1 between the boundary of the middle portion and the boundary of the first semiconductor layer 100; along the second direction, there is a second spacing L2 between the boundary of the middle portion and the boundary of the first semiconductor layer 100; wherein, the first spacing L1 is greater than the second spacing L2. Since the portion of the first semiconductor layer 100 close to the edge of the semiconductor substrate 6 has large defects, poor passivation effect, large leakage current, and severe recombination, therefore, the first spacing L1 between the middle portion and the boundary of the first semiconductor layer 100 is set to be larger to avoid edge defects, while the second spacing L2 is not close to the edge of the semiconductor substrate 6. Therefore, as long as the middle portion having amorphous silicon and nanocrystalline silicon does not include an overlapping portion, the second spacing L2 is reduced as much as possible to increase the area of the middle portion, so as to reduce the contact resistance and improve the current collection ability.

[0117] In some possible implementation manners, the first spacing L1 is 0.2 mm to 12 mm, and / or, the second spacing L2 is less than or equal to 100 μm. If the width of the first spacing L1 is too wide, the middle portion of the overall solar cell is small, the reduction of the series resistance is small, and the loss during current collection is large; if the width of the first spacing L1 is too small, the defects closer to the edge are larger, the passivation effect is poor, the recombination is large, and the leakage current is large. Therefore, considering the reduction of the overall contact resistance of the solar cell and avoiding edge defects, the first spacing L1 is selected to be 0.2 mm to 12 mm. If the second spacing L2 is too large, the middle portion is small and the current collection loss is large. Therefore, the second spacing L2 is less than or equal to 100 μm.

[0118] As Figure 2 and Figure 3 As shown, in some possible implementation manners, the solar cell further includes a first grid electrode 4 disposed on the first semiconductor layer 100 and extending along the first direction. The first grid electrode 4 extends from above the middle portion to above the edge portion. The extending direction of the first grid electrode 4 is the same as the extending direction of the first semiconductor layer 100, and can collect the carriers of both the middle portion and the edge portion. Therefore, the carrier collection ability of the first grid electrode 4 for the first semiconductor layer 100 can be improved.

[0119] Further, in this embodiment, along the second direction, the ratio of the width of the first gate line electrode 4 to the width of the middle part is 10% - 120%, specifically, it can be 10%, 30%, 50%, 80%, 100%, 120%, etc. According to the material and carrier transport ability of the first semiconductor layer 100, the ratio of the width of the first gate line electrode 4 to the width of the middle part is selected. If the carrier transport ability of the first semiconductor layer 100 is weak, the ratio of the width of the first gate line electrode 4 to the width of the middle part is increased to increase the contact area between the first gate line electrode 4 and the middle part and reduce the contact resistance. Conversely, the ratio of the width of the first gate line electrode 4 to the width of the middle part can be reduced to save electrode materials while meeting current collection requirements.

[0120] Exemplarily, the width of the first gate line electrode 4 can be 30μm - 600μm: Specifically, when the first gate line electrode 4 is prepared by screen printing process, the width of the first gate line electrode 4 is 30μm - 80μm; when the first gate line electrode 4 is prepared by deposition methods such as electroplating, the width of the first gate line electrode 4 is 100μm - 600μm. The width of the middle part is 200μm - 700μm. The appropriate width of the first gate line electrode 4 is selected according to the width of the middle part and the electrode preparation process.

[0121] Further, in the case where the solar cell includes the first transparent conductive layer 71, the first gate line electrode 4 extends along the first direction and is disposed on the first transparent conductive layer 71; along the second direction, the width of the first gate line electrode 4 is less than or equal to the width of the first transparent conductive layer 71, and the width of the first transparent conductive layer 71 is greater than the width of the middle part. Exemplarily, the width of the first transparent conductive layer 71 is 120μm - 800μm, the width of the middle part is 200μm - 700μm, and the ratio of the width of the first transparent conductive layer 71 to the width of the middle part is 1.2 - 1.5. The appropriate width of the first transparent conductive layer 71 is selected according to the width of the middle part, and the appropriate width of the first gate line electrode 4 is selected according to the width of the middle part, the first transparent conductive layer 71, and the electrode preparation process. With such a setting, the first gate line electrode 4 can be disposed opposite to the middle part, and the width of the first transparent conductive layer 71 is greater than the width of the middle part to improve the current collection ability.

[0122] Based on the solar cell described in any of the above embodiments, the embodiment of the present invention further provides a photovoltaic module, including the solar cell described in any of the above embodiments.

[0123] Since the photovoltaic module uses the solar cell described in any of the above embodiments, the photovoltaic module has the same beneficial effects as the above solar cell, which will not be elaborated here.

[0124] An embodiment of the present invention further provides a method for manufacturing a solar cell, which can fabricate a solar cell as described in Figures 1 - 7 , and the solar cell described in any of the above embodiments. The method for manufacturing the solar cell includes the following steps:

[0125] Step S100: Provide a semiconductor substrate 6, which has opposite first and second surfaces.

[0126] Step S200: Form a first semiconductor layer 100 on the first surface of the semiconductor substrate 6. The first semiconductor layer 100 has an intermediate portion located in the middle region of itself and an edge portion located in the peripheral region of the intermediate portion.

[0127] Step S300: Use a laser to irradiate the intermediate portion so that the crystallization rate of the intermediate portion is greater than that of the edge portion; wherein the edge portion surrounds the intermediate portion, and the first semiconductor layer 100 includes at least one of amorphous silicon and nanocrystalline silicon.

[0128] In the case of adopting the above technical solution, the intermediate portion located in the middle region of the first semiconductor layer 100 is crystallized by using a laser, so that the crystallization rate is increased, while the edge portion located in the peripheral region of the intermediate portion of the first semiconductor layer 100 is not irradiated by the laser and retains the amorphous structure. Due to the non-uniformity of the full area of the laser and the non-uniform thickness of the first semiconductor layer 100, when the laser acts on the edge portion of the first semiconductor layer 100, the laser will cause damage to the passivation of the edge portion, thereby increasing the recombination of the edge portion. Therefore, in this application, a crystallized structure is not formed by the laser at the edge portion, and the amorphous structure of the edge portion of the first semiconductor layer 100 is retained, thereby ensuring the passivation effect of the edge portion, reducing the recombination of the edge portion, and forming a crystallized structure by laser crystallization in the middle portion of the first semiconductor layer 100, reducing the contact resistance. Therefore, by reasonably controlling the laser irradiation area on the first semiconductor layer 100, the overall cell efficiency of the solar cell is optimized, and the cell efficiency is improved.

[0129] Further, the first surface has a first side and a second side that are oppositely arranged along a first direction. Then, the step of using a laser to irradiate the intermediate portion in step S300 specifically includes the following steps:

[0130] Step S301: Use a laser to start irradiating from a position at a first distance from the first side, and pass through the intermediate portion along the first direction, and stop irradiating at a position at a second distance from the second side.

[0131] In the case of adopting the above technical solution, the laser irradiates the first semiconductor layer along the direction from the first side to the second side. The starting point of the middle part where the irradiation begins is at a first distance from the first side, and the ending point of the middle part where the irradiation ends is at a second distance from the second side. Only the middle part of the first semiconductor layer is irradiated, and the laser irradiation stops at the edge parts on both sides of the middle part. The irradiation can be repeated multiple times along the first direction so that the range of the middle part perpendicular to the first direction is irradiated by the laser. In the width direction of the first semiconductor layer, there is a spacing between the irradiation area of the laser on the first semiconductor layer and the boundary of the width of the first semiconductor layer, so that the formed middle part does not enter the PN isolation region for isolating the P region and the N region, ensuring the electrical insulation effect of the PN isolation region.

[0132] Further, the first distance and / or the second distance is 0.2 mm to 12 mm. That is, an unirradiated edge part of the first semiconductor layer is reserved. If the edge part is too wide, the area of the middle part of the overall solar cell is small, the reduction of the series resistance is small, and the loss during current collection is large; if the width of the edge part of the first semiconductor layer is too small, on the one hand, due to the limitation of the coating process, the edge part of the first semiconductor layer is relatively thin, and on the other hand, when the laser irradiates at the edge of the solar cell, the angle is relatively large, and the energy distribution in the laser spot is deviated, and it is easy for part of the laser energy density to be too large and cause damage to the passivation of the edge part of the first semiconductor layer. Therefore, considering the reduction of the overall contact resistance of the solar cell and the reduction of damage to the passivation, the first distance and / or the second distance is selected to be 0.2 mm to 12 mm.

[0133] In some possible implementation manners, the first semiconductor layer includes an amorphous silicon layer. After the middle part is irradiated with the laser, part of the amorphous silicon layer crystallizes to form nanocrystals. If the first semiconductor layer adopts an amorphous silicon layer, the unirradiated part has a better passivation effect and a better insulation effect in the isolation region.

[0134] In some embodiments, the wavelength of the laser is 325 nm to 532 nm. Specifically, the wavelength of the laser can be 325 nm, 450 nm, 532 nm, etc.; and / or, the energy density of the laser is 200 mJ / cm 2 ~6000 mJ / cm 2 . Specifically, the energy density of the laser can be 200 mJ / cm 2 , 500 mJ / cm 2 , 1000 mJ / cm 2 , 2000 mJ / cm 2 , 3000 mJ / cm 2 , 5000 mJ / cm 2 , 6000 mJ / cm2 etc. The pulse width of the laser can be in the order of picoseconds to nanoseconds. By setting this wavelength range, the laser can be absorbed by the first semiconductor layer 100, which is conducive to the crystallization of the first semiconductor layer 100. If the laser energy density is too high, the high-temperature range will expand, and the temperature at the top of the textured structure will be too high, thus affecting the passivation of the top region of the textured structure. If the laser energy density is too small, the energy accumulation time will be too long, affecting the production efficiency, and the energy may not reach the energy required for crystallization. Therefore, by selecting the laser energy density in this range, only the top of the textured structure can reach a high temperature, achieving a morphological change and forming a crystallized structure.

[0135] such as Figures 8 - 19 As shown, this embodiment provides a specific manufacturing process of a solar cell. Taking the preparation of a hybrid back contact battery with a tunneling passivation contact structure and a heterojunction structure on the back as an example, the preparation process of this back contact battery is as follows:

[0136] The first step: As Figure 8 shown, polish and clean the silicon wafer. Specifically, put the silicon wafer into a tank-type polishing and cleaning machine for polishing to remove the cutting damage layer of the silicon wafer, and control the temperature, time, and chemical solution concentration to adjust the polishing morphology on both sides. The obtained silicon wafer is used as the semiconductor substrate 6, and the semiconductor substrate 6 can be an n-type, p-type, or intrinsic silicon substrate.

[0137] The second step: As Figure 9 shown, sequentially form a tunneling oxide layer 21 and an intrinsic polysilicon layer 23 on the backlight side of the semiconductor substrate 6. Among them, the tunneling oxide layer 21 is a SiOx layer. The tunneling oxide layer 21 and the intrinsic polysilicon layer 23 can be formed by one or more processes such as low-pressure chemical vapor deposition, plasma chemical vapor deposition, physical chemical vapor deposition, or plasma-enhanced atomic layer deposition. In addition, the tunneling oxide layer 21 can be formed by the high-temperature reaction of oxygen with the semiconductor substrate 6, or by wet chemical methods, such as the reaction of silicon with ozone, the oxidation reaction of silicon with nitric acid, etc. The thickness of the tunneling oxide layer 21 is 1 nm to 4 nm, optionally, the thickness is 1.4 nm, and the thickness of the intrinsic polysilicon layer 23 is 30 nm to 250 nm, optionally, the thickness is 120 nm.

[0138] The third step: As Figure 10 shown, dope the intrinsic polysilicon layer 23 by high-temperature diffusion to form an n-type doped polysilicon layer 22, and generate a layer of phosphorus-containing oxide layer, that is, a phosphosilicate glass layer 24. The doping concentration of the n-type doped polysilicon layer 22 is 1×10 19 cm -3 ~5×10 20 cm -3 .

[0139] The fourth step: As Figure 11As shown, the phosphosilicate glass layer 24 formed after phosphorus diffusion is removed by HF solution.

[0140] Step 5: As Figure 12 shown, a silicon nitride mask layer 25 is deposited on the n-type doped polysilicon layer 22. One function of the silicon nitride mask layer 25 is to serve as a hydrogen source to provide hydrogen atoms for the interface between the crystalline silicon and the tunneling oxide layer 21, passivate the dangling bonds, and also passivate some defects in the crystalline silicon body. Another function is to serve as a mask to protect the N-region film layer during subsequent P-region patterning.

[0141] Step 6: As Figure 13 shown, the P-region is patterned using a laser process. The laser ablates all P-region film layers until the semiconductor substrate 6. The laser can use a 532nm laser, and the pulse width can be selected from nanosecond-level and picosecond-level lasers. Optionally, a 532 picosecond laser is used.

[0142] Step 7: As Figure 14 shown, the semiconductor substrate 6 exposed in the P-region is textured through a wet etching process to obtain a textured surface structure, such as a pyramid structure. Then, the silicon nitride mask layer 25 is removed. One function of this wet etching process is to remove the damaged layer of the semiconductor substrate 6 in the P-region after laser treatment for interface cleaning; the other is to remove the silicon nitride mask layer 25 deposited in the N-region.

[0143] Step 8: As Figure 15 shown, an intrinsic amorphous silicon layer 13 and a p-type amorphous silicon layer 14 are sequentially deposited on the backlight surface of the entire semiconductor substrate 6 to form a P-region emitter. Among them, the thickness of the intrinsic amorphous silicon layer 13 is 2nm - 20nm, optionally 8nm; the thickness of the p-type amorphous silicon layer 14 is 5nm - 50nm, optionally 15nm. At the same time, a passivation layer 8 and an antireflection layer 9 are sequentially deposited on the textured surface of the front of the semiconductor substrate 6. The antireflection layer 9 is any combination of one or more of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer. The passivation layer 8 can be an intrinsic amorphous silicon layer or an aluminum oxide layer.

[0144] Step 9: As Figure 16 shown, the N-region is patterned using a laser process. The intrinsic amorphous silicon layer 13 and the p-type amorphous silicon layer 14 on the n-type doped polysilicon layer 22 are removed, exposing the n-type doped polysilicon layer 22, and an oxide layer will be generated on the n-type doped polysilicon layer 22 and removed by a subsequent wet etching process. Among them, the laser can use 355nm and 532nm lasers, and the pulse width can be selected from nanosecond-level and picosecond-level lasers. Optionally, a 532 picosecond laser is used. The wet etching process can use a chain device. The semi-finished product is placed face up, protected by a water film. The back is in contact with the HF solution to remove the oxide layer and the silicon nitride deposited on the back by overplating.

[0145] Step 10: As shown in Figure 16 , use a laser process to irradiate the middle area of the p-type amorphous silicon layer 14 in the P region, so that the middle area of the p-type amorphous silicon layer 14 forms a first part 11 with a crystallized structure, while the positions of the p-type amorphous silicon layer 14 near the edge of the semiconductor substrate 6 are not irradiated by the laser and retain the original amorphous structure to form a second part 12. Among them, the laser can use 355nm and 532nm lasers, and the pulse width can select nanosecond-level and picosecond-level lasers. Optionally, a 532 picosecond laser is used. Specifically, the pulsed laser spot moves along the extension direction of the p-type amorphous silicon layer 14 for irradiation. Ideally, the width of the laser treatment range is the same as the width of the P region (p-type amorphous silicon layer 14), maximizing the laser treatment area. Even if the laser action range exceeds the P region and reaches the isolation region, it will not affect the battery performance. However, considering production capacity, the laser treatment area should be minimized, and it is recommended that the laser action area does not exceed the P region range. The laser treatment range avoids the range of 0.3mm to 3mm from the edge of the semiconductor substrate 6. For the two outermost p-type amorphous silicon layers 14 among the multiple p-type amorphous silicon layers 14, the width is about 1mm, and all are not subjected to laser treatment. For the two end edges of the remaining p-type amorphous silicon layers 14, about 1mm is not subjected to laser treatment. It should be noted that the laser processes in Step 9 and Step 10 can be carried out in the same step and do not need to be in a specific order. In order to save laser treatment time, after the P region is patterned by the laser, irradiation is carried out for crystallization treatment.

[0146] Step 11: As shown in Figure 17 , deposit a transparent conductive layer 7 on the backlight surface of the semiconductor substrate 6, which can be one or more of fluorine-doped tin oxide, aluminum-doped zinc oxide, indium tin oxide, indium tungsten oxide, indium molybdenum oxide, indium cerium oxide, and indium hydroxide, in a stacked or single-layer form. Optionally, an indium tin oxide film layer is used.

[0147] Step 12: As shown in Figure 18 , disconnect the transparent conductive layer 7 on the N region and the P region to form a PN isolation region, so that the transparent conductive layer 7 forms a first transparent conductive layer 71 on the P region and a second transparent conductive layer 72 on the N region, realizing insulation between the P region and the N region. The transparent conductive layer 7 is disconnected at the positions near the edge of the semiconductor substrate 6 in the N region and the P region to form a third transparent conductive layer on the edge. The PN isolation region between the P region and the N region straddles the overlapping region between the N region and the P region and a part of the p region to achieve better insulation.

[0148] Step 13: As shown in Figure 19 , deposit and form a first gate line electrode 4 and a second gate line electrode 5 on the first transparent conductive layer 71 in the P region and the second transparent conductive layer 72 in the N region respectively. Among them, both ends of the first gate line electrode 4 extend respectively as shown in Figure 1On the second part 12 on both sides as shown. The material of the first gate line electrode 4 and the second gate line electrode 5 can be one or a combination of silver, copper, and aluminum.

[0149] In the description of the above embodiments, specific features, structures, materials, or characteristics can be combined in a suitable manner in any one or more embodiments or examples.

[0150] As described above, it is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; A first semiconductor layer is arranged on the first surface, the first semiconductor layer has a first portion located in a middle area of ​​the first surface and a second portion located in an edge area of ​​the first surface, the crystallization rate of the first portion is greater than the crystallization rate of the second portion; wherein the edge area surrounds the middle area and is adjacent to the edge of the first surface, the first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

2. The solar cell according to claim 1, characterized in that The first semiconductor layer entirely covers the first surface, the first portion is in a rectangular shape, and the second portion is in a ring shape.

3. The solar cell according to claim 2, characterized in that: The solar cell further includes a third semiconductor layer disposed on the second surface, the third semiconductor layer includes a polycrystalline silicon layer or an amorphous silicon layer, and the third semiconductor layer has a different conductivity type from that of the first semiconductor layer.

4. The solar cell according to claim 1, characterized in that The third semiconductor layer is a polysilicon layer, and the semiconductor layer is arranged on the second surface in a strip shape, or the third semiconductor layer is entirely arranged on the second surface, and the third semiconductor layer includes a thicker portion arranged in a strip shape and a thinner portion except the thicker portion.

5. The solar cell according to claim 1, characterized in that: The solar cell also includes a second semiconductor layer arranged on the first surface, the first semiconductor layer includes a plurality of first strip portions extending along a first direction, the second semiconductor layer includes a plurality of second strip portions extending along the first direction, the first strip portions and the second strip portions are alternately arranged along a second direction, the first semiconductor layer and the second semiconductor layer have different conductivity types, and the first direction and the second direction intersect.

6. The solar cell according to claim 5, characterized in that: In the first strip-shaped portion, the first portion includes a strip-shaped middle portion extending along a first direction and strip-shaped edge portions arranged on both sides of the middle portion along a second direction, and a crystallization rate of the middle portion is greater than a crystallization rate of the edge portion.

7. The solar cell according to claim 6, characterized in that: In the first strip-shaped portion, a width of the edge portion on one side of the middle portion along the second direction is less than or equal to 100 μm.

8. The solar cell according to claim 5, characterized in that: The second semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer, and a microcrystalline silicon layer.

9. The solar cell according to claim 5, characterized in that: Along the second direction, a crystallization rate of at least one of the first strip portions close to an edge of the first surface is the same as a crystallization rate of the second portion.

10. The solar cell according to claim 1, characterized in that: A contact resistance of the first portion is smaller than a contact resistance of the second portion.

11. The solar cell according to claim 6, characterized in that: The first strip-shaped portion has an overlapping portion overlapping the second strip-shaped portion, and the first portion does not include the overlapping portion; and / or the solar cell further includes a first transparent conductive layer covering a portion of the first portion, A projection of the middle portion on the first transparent conductive layer is at least located within a boundary of the first transparent conductive layer.

12. The solar cell according to claim 11, characterized in that: It also includes a second transparent conductive layer and a third transparent conductive layer, wherein the second transparent conductive layer covers part of the overlapping portion and part of the second strip-shaped portion; and the third transparent conductive layer covers part of the second portion; A PN isolation region is provided between the adjacent first transparent conductive layer and the second transparent conductive layer; An edge isolation region is provided between the first transparent conductive layer and the third transparent conductive layer and / or between the second transparent conductive layer and the third transparent conductive layer.

13. The solar cell according to claim 1, characterized in that In the image obtained by the EL test of the solar cell, the brightness of the first part is greater than the brightness of the second part.

14. The solar cell according to claim 1, characterized in that It also includes a first gate line electrode extending along the first direction. The first gate line electrode is conductively disposed on a first portion of the first semiconductor layer and extends from the first portion to the second portion.

15. The solar cell according to claim 1, characterized in that Along the direction from the first portion to the second portion and perpendicular to the side length of the semiconductor substrate, the width of the second portion is 0.3 mm to 12 mm.

16. A solar cell, characterized in that: include: A semiconductor substrate having a first surface and a second surface opposite to each other; A first semiconductor layer is arranged on the first surface, and the first semiconductor layer includes a middle part located in the middle area of ​​the first semiconductor layer and an edge part located in the peripheral area of ​​the middle part, wherein the edge part surrounds the middle part; the middle part includes amorphous silicon and nanocrystalline silicon, and the edge part is amorphous silicon.

17. The solar cell according to claim 16, characterized in that: The first semiconductor layer entirely covers the first surface, and the edge portion is in a ring shape between the middle portion and the edge of the first surface.

18. The solar cell according to claim 16, characterized in that: The invention also includes a third semiconductor layer disposed on the second surface, wherein the third semiconductor layer includes at least one of a polycrystalline silicon layer, an amorphous silicon layer, a nanocrystalline silicon layer and a microcrystalline silicon layer.

19. The solar cell according to claim 16, characterized in that: Also includes a second semiconductor layer disposed on the first surface, the first semiconductor layer and the second semiconductor layer are both in the shape of long strips extending along a first direction, and are adjacently disposed along a second direction, the first semiconductor layer includes an overlapping portion overlapping the second semiconductor layer; the first semiconductor layer and the second semiconductor layer have different conductivity types, and the first direction and the second direction intersect; Wherein, the middle portion does not include the overlapping portion.

20. The solar cell according to claim 19, characterized in that It also includes a first transparent conductive layer covering the first semiconductor layer, and the projection of the middle part on the semiconductor substrate is completely located within the projection of the first transparent conductive layer on the semiconductor substrate.

21. The solar cell according to claim 19, characterized in that The semiconductor substrate includes a concave portion on the first surface, the concave portion is concave relative to the rest of the first surface toward the second surface, and the middle portion is located within the concave portion.

22. The solar cell according to claim 19, characterized in that Along the first direction, there is a first distance between the boundary of the middle part and the boundary of the first semiconductor layer; along the second direction, there is a second distance between the boundary of the middle part and the boundary of the first semiconductor layer; wherein the first distance is greater than the second distance. 23 . The solar cell according to claim 22 , wherein the first spacing is 0.2 mm to 12 mm, and / or the second spacing is less than or equal to 100 μm.

24. The solar cell according to claim 19, characterized in that The invention also includes a first gate line electrode which is disposed on the first semiconductor layer and extends along the first direction, wherein the first gate line electrode extends from above the middle portion to above the edge portion.

25. The solar cell according to claim 19, characterized in that It also includes a first gate line electrode disposed on the first semiconductor layer and extending along the first direction; along the second direction, the ratio of the width of the first gate line electrode to the width of the middle part is 10%-120%.

26. The solar cell according to claim 20, characterized in that It also includes a first gate line electrode disposed on the first transparent conductive layer and extending along the first direction; along the second direction, the width of the first gate line electrode is less than or equal to the width of the first transparent conductive layer, and the width of the first transparent conductive layer is greater than the width of the middle part.

27. A photovoltaic module, comprising a solar cell, characterized in that: The solar cell is the solar cell according to any one of claims 1 to 26.

28. A method for manufacturing a solar cell, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate having a first surface and a second surface opposite to each other; forming a first semiconductor layer on the first surface, wherein the first semiconductor layer has a middle portion located in a middle region of the first semiconductor layer and an edge portion located in a peripheral region of the middle portion; The middle portion is irradiated with laser so that a crystallization rate of the middle portion is greater than a crystallization rate of the edge portion; wherein the edge portion surrounds the middle portion, and the first semiconductor layer includes at least one of amorphous silicon and nanocrystalline silicon.

29. The method for manufacturing a solar cell according to claim 28, characterized in that: The first surface has a first side and a second side arranged opposite to each other along a first direction; The irradiating the middle portion with laser light comprises: The laser is used to start irradiation at a position at a first distance from the first side, pass through the middle portion along a first direction, and stop irradiation at a position at a second distance from the second side.

30. The method for manufacturing a solar cell according to claim 29, characterized in that: The first distance and / or the second distance is / are between 0.2 mm and 12 mm.

31. The method for manufacturing a solar cell according to claim 28, characterized in that: The first semiconductor layer includes an amorphous silicon layer. After the middle portion is irradiated with the laser, a portion of the amorphous silicon layer is crystallized to form nanocrystalline grains.

32. The method for manufacturing a solar cell according to claim 28, characterized in that: The wavelength of the laser is 325nm to 532nm; And / or, the energy density of the laser is 200 mJ / cm 2 ~6000mJ / cm 2 .

Images