Method of repairing display panel and repairing apparatus performing the same

Abstract

The invention relates to a method of repairing a display panel and a repairing apparatus performing the same. The method of repairing the display panel includes: inspecting a defect of a first pattern of the display panel; irradiating a first laser with a first pulse width to the defect area with the defect; and irradiating a second laser having a second pulse width different from the first pulse width to the defect region.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0174694 filed in the Korean Intellectual Property Office on December 5, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method for repairing a display panel and a repairing device for performing the method. More specifically, the present disclosure relates to a method for repairing a display panel using laser and a repairing device for performing the method. Background Art

[0004] A display device is a device that displays moving images and / or still images, and includes a liquid crystal display (LCD) and / or an organic light emitting diode (OLED) display, etc. Display devices are used in various electronic devices such as mobile phones, navigation devices, digital cameras, e-books, portable game consoles, and / or various terminals. The display device includes a display panel for providing visual information such as images or pictures to a user.

[0005] Whether the display panel is defective can be determined during manufacturing or after the manufacturing process. At this time, when a defect occurs, various methods can be used to repair the defect of the display panel. Summary of the invention

[0006] Aspects and features of embodiments of the present disclosure provide a method for repairing a display panel by using different lasers. Other aspects and features of embodiments of the present disclosure provide a repairing device for repairing a display panel.

[0007] According to one or more embodiments of the present disclosure, a method for repairing a display panel may include: inspecting a defect of a first pattern of the display panel; irradiating a first laser having a first pulse width to a defective area where the defect occurs; and irradiating a second laser having a second pulse width different from the first pulse width to the defective area.

[0008] In one or more embodiments, the first pattern may be a multi-layer pattern.

[0009] In one or more embodiments, the first pattern may include a first layer including aluminum and a second layer on the first layer and including titanium.

[0010] In one or more embodiments, the second layer may be removed by the first laser, and the first layer may be removed by the second laser.

[0011] In one or more embodiments, the first pattern may further include a third layer between the first layer and the second layer and including titanium nitride.

[0012] In one or more embodiments, the first pattern may include gate lines of the display panel.

[0013] In one or more embodiments, the first pattern may be located on the second pattern, and the second pattern may include a channel region of a transistor of the display panel.

[0014] In one or more embodiments, the first pulse width may be smaller than the second pulse width.

[0015] In one or more embodiments, the peak power of the first laser may be greater than the peak power of the second laser.

[0016] In one or more embodiments, the first laser may be a femtosecond laser.

[0017] In one or more embodiments, the second laser may be a nanosecond laser.

[0018] In one or more embodiments, the first laser may be irradiated in a scanning method.

[0019] In one or more embodiments, the second laser may be irradiated in a stepping method.

[0020] According to one or more embodiments of the present disclosure, a repair device for repairing a display panel may include: a laser irradiator, configured to irradiate a first laser having a first pulse width and a second laser having a second pulse width different from the first pulse width to a defective area where a defect of the display panel occurs; and a controller, configured to control the laser irradiator.

[0021] In one or more embodiments, the repairing apparatus may further include: a photographing unit configured to photograph the display panel to generate image data and provide the image data to the controller, and the controller may be configured to check for defects based on the image data.

[0022] In one or more embodiments, the first pulse width may be smaller than the second pulse width.

[0023] In one or more embodiments, the peak power of the first laser may be greater than the peak power of the second laser.

[0024] In one or more embodiments, the first laser may be a femtosecond laser and the second laser may be a nanosecond laser.

[0025] In one or more embodiments, the laser irradiator may be configured to irradiate the first laser in a scanning method.

[0026] In one or more embodiments, the laser irradiator may be configured to irradiate the second laser in a stepping method.

[0027] The method of repairing a display panel according to an embodiment of the present disclosure may effectively repair a plurality of layers using different lasers.

[0028] However, the effects, aspects, and features of the embodiments of the present disclosure are not limited to the above-described effects, aspects, and features, and may be variously extended within a range not departing from the spirit and scope of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other aspects and features of the embodiments of the present disclosure will become more apparent by describing embodiments thereof in more detail with reference to the accompanying drawings, in which:

[0030] Figure 1 is a schematic perspective view of an electronic device according to one or more embodiments;

[0031] Figure 2 is a perspective view of a display device included in an electronic device according to one or more embodiments;

[0032] Figure 3 yes Figure 2 A cross-sectional view of a display device;

[0033] Figure 4 is a schematic plan view illustrating a connection relationship between components of a display device according to one or more embodiments;

[0034] Figure 5 It is a graphic Figure 4 A plan view of an embodiment of one of the pixels;

[0035] Figure 6 It is along Figure 5 A schematic cross-sectional view taken along line II' of ;

[0036] Figure 7 It is a graphic Figure 4 A plan view of a portion of the display area;

[0037] Figure 8 is a plan view illustrating an example in which a defect occurs in a conductive pattern;

[0038] Fig. 9 It is a graphic Figure 8 A cross-sectional view of an example of a conductive pattern;

[0039] Fig.10 is a flow chart illustrating a method of repairing a display panel according to one or more embodiments of the present disclosure;

[0040] Fig.11 It is a graphical execution Fig.10 A block diagram of a repairing device of a method for repairing a display panel;

[0041] Fig.12 and Fig.13 It is a graphic Fig.10 FIG. 100 of step S200; and

[0042] Fig.14 and Fig.15 It is a graphic Fig.10 FIG. 10 is a diagram of step S300. DETAILED DESCRIPTION

[0043] Hereinafter, embodiments according to the present disclosure are described in detail with reference to the accompanying drawings. It should be noted that in the following description, only the parts necessary for understanding the operation according to the present disclosure are described, and the description of other parts is omitted so as not to blur the subject matter of the present disclosure. In addition, the present disclosure may be embodied in other forms and is not limited to the embodiments described herein. However, the embodiments described herein are provided to describe the present disclosure in sufficient detail so that those skilled in the art to which the present disclosure belongs can realize the technical spirit and scope of the present disclosure.

[0044] Throughout this disclosure, when a part is "connected" to another part, the situation includes not only the situation that the part is "directly connected", but also the situation that the part is "indirectly connected" and another element is interposed therebetween. The terms used in this article are used to describe specific embodiments and are not intended to limit this disclosure. Throughout this disclosure, when a specific part "includes", unless otherwise stated, the situation means that the part may further include another component without excluding another component. "At least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted as any combination of one X, one Y, one Z or two or more of X, Y and Z (for example, XYZ, XY, YZ and XZ). Here, "and / or" includes all combinations of one or more of the corresponding structures.

[0045] Here, terms such as "first" and "second" can be used to describe various components, but the components are not limited to these terms. These terms are used to distinguish one component from another component. Therefore, a first component can refer to a second component within a range without departing from the spirit and scope of the present disclosure.

[0046] Spatially relative terms such as "under..." and "on..." can be used for descriptive purposes to describe the relationship between an element or feature and another (some) element or feature as shown in the drawings. In addition to the directions depicted in the drawings, spatially relative terms are intended to also include other directions in use, operation and / or manufacture. For example, when the device shown in the figure is reversed, the element depicted as being "under" other elements or features is located in the direction "on" other elements or features. Therefore, in one or more embodiments, the term "under..." can include both upper and lower directions. In addition, the device can face other directions (e.g., rotated 90 degrees or in other directions), and the spatially relative terms used in this article are therefore interpreted accordingly.

[0047] Various embodiments are described with reference to the accompanying drawings that schematically illustrate idealized embodiments. Accordingly, it is expected that the shapes may vary, for example, depending on tolerances and / or manufacturing techniques. Therefore, the embodiments disclosed herein should not be construed as limited to the specific shapes shown, but should be construed to include changes in shape that occur, for example, due to manufacturing. As described above, the shapes shown in the drawings may not show the actual shape of the area of ​​the device, and the present disclosure is not limited to this.

[0048] Hereinafter, the present disclosure is described in more detail with reference to the accompanying drawings.

[0049] Figure 1 is a schematic perspective view of an electronic device according to one or more embodiments.

[0050] refer to Figure 1 The electronic device 1 may be an electronic device that provides a display screen capable of displaying moving images and / or still images in a third direction DR3, and for example, a television, a notebook computer, a monitor, a billboard, an IoT device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, a game console, a digital camera and / or a camcorder, etc. that provide a display screen may be included in the electronic device 1.

[0051] The electronic device 1 may include a cover window WIN and a housing HM, and Figure 2 The display device 10 shown in FIG. 1 may be located inside the cover window WIN and the housing HM. Therefore, the cover window WIN and the housing HM may be combined to constitute the appearance of the electronic device 1.

[0052] The cover window WIN may include an insulating panel. For example, the cover window WIN may be formed of glass, plastic, or a combination thereof. In one or more embodiments, the cover window WIN may include a touch sensor capable of sensing a touch.

[0053] The front surface of the cover window WIN may define the front surface of the electronic device 1 .

[0054] The housing HM may be combined with the cover window WIN. The cover window WIN may be provided on the front surface of the housing HM. The housing HM may be combined with the cover window WIN to provide a desired accommodation space (e.g., a predetermined accommodation space). The display device 10 may be accommodated in a desired accommodation space (e.g., a predetermined accommodation space) provided between the housing HM and the cover window WIN.

[0055] The housing HM may include a material having relatively high rigidity. For example, the housing HM may include a plurality of frames and / or plates including glass, plastic, and / or metal or a combination thereof. The housing HM may have a rear surface and a side surface, and a cover window WIN may be provided on the housing HM, which may stably protect the structure of the display device 10 accommodated in the internal space formed by the housing HM and the cover window WIN from external impact.

[0056] The electronic device 1 may include a display device (refer to Figure 2 10). As a display device included in the electronic device 1, various display devices such as an inorganic light-emitting display device, an organic light-emitting display device, and / or a quantum dot light-emitting display device may be provided. Hereinafter, the present disclosure is described based on a case where a light-emitting display device including an organic light-emitting element (e.g., OLED) is applied as an example of a display device, but the present disclosure is not limited thereto, and when the same technical idea is applicable, the same technical idea may be applied to another display device.

[0057] The shape of the electronic device 1 may be modified in various ways. For example, the electronic device 1 may have a shape such as a rectangle whose horizontal length is long, a rectangle whose vertical length is long, a square, a quadrilateral whose corner portions (e.g., corners) are rounded, other polygons, and / or a circle in a plan view. The shape of the display area DA of the electronic device 1 may also be similar to the overall shape of the electronic device 1. Figure 1 , the electronic device 1 having a relatively long rectangular shape in the second direction DR2 is shown, but the present disclosure is not limited thereto.

[0058] The electronic device 1 may include a display area DA and a non-display area NDA around the display area DA along an edge or periphery of the display area DA. Figure 1The display area DA and the non-display area NDA shown in the figure may correspond to the display area DA and the non-display area NDA of the display device 10. The display area DA is an area where an image is displayed, and the non-display area NDA is an area where no image is displayed. The display area DA may generally occupy most of the area based on the center of the electronic device 1, and the non-display area NDA may have a structure surrounding the periphery of the display area DA.

[0059] The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 may be areas where components such as sensors and / or cameras for adding various functions to the electronic device 1 are provided on the rear surface (e.g., a surface located at the lower part of the third direction DR3), and the second display area DA2 and the third display area DA3 may correspond to the component areas. The second display area DA2 and the third display area DA3 may be surrounded by the first display area DA1. For example, the first display area DA1 may be around the second display area DA2 and the third display area DA3. In addition to the first display area DA1, the second display area DA2 and the third display area DA3 may also display images. According to one or more embodiments, the positions and quantities of the second display area DA2 and the third display area DA3 may be variously changed.

[0060] In the following, through Figure 2 A structure of a display device which is an example of a display device is described.

[0061] Figure 2 is a perspective view of a display device included in an electronic device according to one or more embodiments.

[0062] refer to Figure 2 , the electronic device 1 according to one or more embodiments may include a display device 10. The display device 10 may display an image in the electronic device 1, and may sense and / or photograph the front surface of the electronic device 1. The display device 10 may have a planar shape similar to the planar shape of the electronic device 1. For example, the display device 10 may have a shape similar to a quadrilateral having sides extending in a first direction DR1 and sides extending in a second direction DR2 in a plan view. The corner where the sides extending in the first direction DR1 and the sides extending in the second direction DR2 intersect may be rounded to have a curvature, but is not limited thereto, and may also be formed at a right angle. The planar shape of the display device 10 is not limited to a quadrilateral, and may be formed similarly to another polygon, a circle, and / or an ellipse.

[0063] The display device 10 may include a display panel 100 , a display driver 200 , a circuit board 300 , and a touch driver 400 .

[0064] The display panel 100 may include a main area MA and a sub-area SBA.

[0065] The main area MA may include a display area DA including pixels displaying an image and a non-display area NDA disposed around the display area DA along an edge or periphery of the display area DA. The display area DA may include a first display area DA1, a second display area DA2, and a third display area DA3. The second display area DA2 and the third display area DA3 may include pixels, components such as sensors and / or cameras may be disposed in a lower portion in the third direction DR3, and the second display area DA2 and the third display area DA3 may correspond to the component area.

[0066] The display area DA may emit light in a third direction DR3 from a plurality of emission regions corresponding to the plurality of light emitting elements. For example, the display panel 100 may include a light emitting element, a pixel circuit unit including a transistor, and a pixel defining layer having an opening defining an emission region of the light emitting element. Here, the light emitting element may include at least one of an organic light emitting element including an organic light emitting layer (e.g., an organic light emitting diode (OLED)), a quantum dot light emitting element including a quantum dot light emitting layer (e.g., a quantum dot LED), an inorganic light emitting element including an inorganic semiconductor (e.g., an inorganic LED), and a micro light emitting element (e.g., a micro LED), but is not limited thereto.

[0067] The non-display area NDA is an area outside the display area DA and surrounding the display area DA. The non-display area NDA may be defined as an edge area of ​​the main area MA of the display panel 100. The non-display area NDA may include a gate driver supplying a gate signal to a gate line and a fan-out line connecting the display driver 200 and the display area DA.

[0068] The sub-area SBA may be an area extending from one side of the main area MA. The sub-area SBA may include a flexible material capable of bending, folding and / or curling, etc. For example, when the sub-area SBA is bent, the sub-area SBA may overlap with the main area MA in the thickness direction (e.g., the third direction DR3). The sub-area SBA may include a display driver 200 and a pad unit connected to the circuit board 300. In one or more embodiments, the sub-area SBA may be omitted, and the display driver 200 and the pad unit may be disposed in the non-display area NDA.

[0069] The display driver 200 may output a signal and a voltage for driving the display panel 100. The display driver 200 may supply a data voltage to a data line. The display driver 200 may supply a power voltage to a power line and may supply a gate control signal to a gate driver. The display driver 200 may be formed by an integrated circuit (IC) and may be mounted on the display panel 100 in a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic welding method. For example, the display driver 200 may be disposed in the sub-area SBA and may overlap with the main area MA in a thickness direction (e.g., a third direction DR3) by bending of the sub-area SBA. As another example, the display driver 200 may be mounted on a circuit board 300.

[0070] The circuit board 300 may be attached to the pad unit of the display panel 100 using an anisotropic conductive film (ACF). The leads of the circuit board 300 may be electrically connected to the pad unit of the display panel 100. The circuit board 300 may be a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0071] The touch driver 400 may be mounted on the circuit board 300. The touch driver 400 may be electrically connected to a touch sensor included in the electronic device 1. The touch driver 400 may supply a touch drive signal to a plurality of sensing electrodes of the touch sensor, and sense the amount of change in capacitance between the plurality of sensing electrodes. For example, the touch drive signal may be a pulse signal having a desired frequency (e.g., a predetermined frequency). The touch driver 400 may determine whether a touch is input, and calculate the touch input coordinates based on the amount of change in capacitance between the plurality of sensing electrodes. The touch driver 400 may be formed as an integrated circuit (IC).

[0072] In the following, through Figure 3 A cross-sectional structure of the display device 10 is described.

[0073] Figure 3 yes Figure 2 A cross-sectional view of a display device.

[0074] refer to Figure 3 , the display panel 100 may include a display layer DU and an external light reducing layer CFL. The display layer DU may include a substrate SUB, a driving element layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL.

[0075] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded and / or curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. In one or more embodiments, the substrate SUB may include a glass material and / or a metal material.

[0076] The driving element layer TFTL may be disposed on the substrate SUB. The driving element layer TFTL may include a plurality of transistors and capacitors constituting a pixel circuit unit that outputs current and transmits current to a light-emitting element. The driving element layer TFTL may further include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 and the pad unit. Each transistor may include a semiconductor including a channel region, a source region, and a drain region, and a gate electrode located on one side of the semiconductor. Here, the source region and the drain region of the semiconductor may serve as a source electrode (e.g., a first electrode) and a drain electrode (e.g., a second electrode) of the transistor, respectively. In addition, when the gate driver is formed on one side of the non-display area NDA of the display panel 100, the gate driver may include a transistor.

[0077] The driving element layer TFTL may be disposed in the display area DA, the non-display area NDA, and the sub-area SBA. The transistors, gate lines, data lines, and power lines of the driving element layer TFTL may be disposed in the display area DA. The gate control lines and fan-out lines of the driving element layer TFTL may be disposed in the non-display area NDA. The lead lines of the driving element layer TFTL may be disposed in the sub-area SBA.

[0078] The light emitting element and the emission region corresponding thereto may be located in the light emitting element layer EML, and the light emitting element layer EML may be disposed on the driving element layer TFTL. The light emitting element layer EML may include a plurality of light emitting elements and a pixel defining layer, the light emitting element including a first electrode, a second electrode and a light emitting layer emitting light, and the pixel defining layer having an opening defining the emission region (hereinafter, also referred to as a pixel opening). The plurality of light emitting elements of the light emitting element layer EML may be disposed in the display area DA.

[0079] In one or more embodiments, the light-emitting layer may be an organic light-emitting layer including an organic material. A functional layer including at least one of an electron injection layer, an electron transport layer, a hole transport layer, and a hole injection layer may be located on both sides of the light-emitting layer. Here, the light-emitting layer and the functional layer together may be referred to as an intermediate layer. When the first electrode receives a voltage through the transistor of the driving element layer TFTL and the second electrode receives a driving low voltage, holes and electrons may move through the hole transport layer and the electron transport layer, respectively, and holes and electrons may recombine with each other in the organic light-emitting layer to emit light. Here, one of the first electrode and the second electrode may be an anode, and the other may be a cathode.

[0080] In one or more embodiments, the light emitting element may be a quantum dot light emitting element including a quantum dot light emitting layer, an inorganic light emitting element including an inorganic semiconductor, or a micro light emitting element.

[0081] The encapsulation layer TFEL may cover the upper and side surfaces of the light emitting element layer EML and may prevent external moisture and air from entering the light emitting element layer EML. The encapsulation layer TFEL may include at least one inorganic layer and at least one organic layer for encapsulating the light emitting element layer EML.

[0082] The external light reduction layer CFL may be disposed on the encapsulation layer TFEL. The external light reduction layer CFL may include a plurality of color filters corresponding to a plurality of corresponding emission regions. In addition, the shading member may be located between the color filters adjacent to each other in the external light reduction layer CFL or in an overlapping portion where the adjacent color filters overlap. The shading member may be located on or below the color filter in the third direction DR3, or may be located on both sides based on the color filter.

[0083] Because the external light reduction layer CFL is directly disposed on the encapsulation layer TFEL, the display device 10 may not require a separate substrate for the external light reduction layer CFL. In addition, a polarizing plate is not attached to the external light reduction layer CFL. As a result, the thickness of the display device 10 may be relatively small. In addition, because the display device 10 does not include a polarizing plate, although direct reflection of external light may occur, the reflection of external light may be reduced by a color filter and / or a light shielding member included in the external light reduction layer CFL. That is, because the color filter selectively transmits light of a specific wavelength and blocks and / or absorbs light of another wavelength, and the light shielding member absorbs external light, the amount of external light flowing into the display device 10 may be reduced, the amount of reflected light may also be reduced, and thus the reflection of external light may be reduced.

[0084] According to one or more embodiments, the display device 10 may further include an optical device 500. The optical device 500 may be disposed on the rear surface of the second display area DA2 or the third display area DA3. The optical device 500 may emit and / or receive light in infrared, ultraviolet, and visible light bands. For example, the optical device 500 may be an optical sensor such as a proximity sensor, an illumination sensor, a camera sensor, and / or an image sensor that senses light incident on the display device 10.

[0085] In the following, through Figure 4 The connection relationship of the components included in the display device 10 is described in detail.

[0086] Figure 4 is a schematic plan view illustrating a connection relationship between components of a display device according to one or more embodiments.

[0087] refer to Figure 4 , the display layer DU of the display device 10 may include a display area DA and a non-display area NDA.

[0088] The display area DA may be disposed at the center of the display panel 100. A plurality of unit pixels (or pixels) PX, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of power lines VL may be disposed in the display area DA. Each of the plurality of unit pixels PX may be a minimum unit for emitting light, and includes a pixel circuit unit including a transistor and a capacitor, and a light emitting element receiving current from the pixel circuit unit.

[0089] Each unit pixel PX may be connected to a gate line GL, a data line DL, and a power line VL, and each of the gate line GL and the power line VL may include a plurality of lines.

[0090] The plurality of gate lines GL may supply the plurality of unit pixels PX with gate signals received from the gate driver 210. The plurality of gate lines GL may extend in a first direction DR1 and may be spaced apart from each other in a second direction DR2 crossing the first direction DR1.

[0091] The plurality of data lines DL may supply the plurality of unit pixels PX with data voltages received from the display driver 200. The plurality of data lines DL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0092] The plurality of power lines VL may supply a power voltage received from the display driver 200 to the plurality of unit pixels PX. Here, the power voltage may be at least one of a driving voltage, an initialization voltage, a reference voltage, and a driving low voltage, and a plurality of these power voltages may be transmitted to the unit pixels PX. The plurality of power lines VL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0093] The non-display area NDA may surround the display area DA. The gate driver 210, the fan-out line FOL, and the gate control line GCL may be disposed in the non-display area NDA.

[0094] The gate driver 210 may generate a plurality of gate signals based on the gate control signal and sequentially supply the plurality of gate signals to the plurality of gate lines GL in a set order.

[0095] The fan-out line FOL may extend from the display driver 200 to the display area DA. The fan-out line FOL may supply a data voltage received from the display driver 200 to the plurality of data lines DL.

[0096] The gate control line GCL may extend from the display driver 200 to the gate driver 210. The gate control line GCL may supply a gate control signal received from the display driver 200 to the gate driver 210.

[0097] refer to Figure 4 , the display device 10 may further include a sub-area SBA.

[0098] The sub-area SBA may include the display driver 200 , the pad area PA, and first and second touch pad areas TPA1 and TPA2 .

[0099] The display driver 200 may output a signal and a voltage for driving the display panel 100 to the fan-out line FOL. The display driver 200 may supply a data voltage to the data line DL through the fan-out line FOL. The data voltage may be supplied to a plurality of unit pixels PX, and the brightness of the plurality of unit pixels PX may be controlled. The display driver 200 may supply a gate control signal to the gate driver 210 through the gate control line GCL.

[0100] The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be arranged at the edge of the sub-area SBA. The pad area PA may include a plurality of display pad units DP. The plurality of display pad units DP may be connected to the graphics system through the circuit board 300. The plurality of display pad units DP may be connected to the circuit board 300 to receive digital video data, and supply the digital video data to the display driver 200. The first touch pad area TPA1 and the second touch pad area TPA2 may include a plurality of touch pads TP1 and a plurality of touch pads TP2, respectively, and may be connected to the touch driver 400 located on the circuit board 300, so that the display device 10 can sense touch. The pad area PA, the first touch pad area TPA1, and the second touch pad area TPA2 may be electrically connected to the circuit board 300 using an anisotropic conductive film and / or a material such as a self-assembled anisotropic conductive adhesive (SAP).

[0101] Figure 5 It is a graphic Figure 4 A plan view of an embodiment of one of the pixels.

[0102] refer to Figure 4 and Figure 5 , the pixel PX may include first to third sub-pixels SP1 to SP3 arranged along the first direction DR1.

[0103] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0104] The first emission region EMA1 may be formed from the light emitting element layer EML (refer to Figure 6 ) may be an area where light is emitted from a portion of the light-emitting element layer EML corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the light-emitting element layer EML corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the light-emitting element layer EML corresponding to the third sub-pixel SP3. The emission areas EMA1 to EMA3 may be understood as openings of the pixel defining layer PDL corresponding to the first to third sub-pixels SP1 to SP3.

[0105] However, the arrangement or arrangement of the sub-pixels SP1 to SP3 is not limited to Figure 5 The arrangement or arrangement shown in .

[0106] Figure 6 It is along Figure 5 Schematic cross-sectional view taken along line II'.

[0107] Figure 6 A cross section through the first emission area EMA1, the second emission area EMA2 and the third emission area EMA3 is shown.

[0108] The display panel 100 of the display device 10 may include a display layer DU and an external light reduction layer CFL. The display layer DU may include a substrate SUB, a driving element layer TFTL, a light emitting element layer EML, and an encapsulation layer TFEL. In the display panel 100, the external light reduction layer CFL disposed on the encapsulation layer TFEL may include a light shielding member BM and color filters CF1, CF2, and CF3, and the color filters CF1, CF2, and CF3 may be located on the light shielding member BM. Here, the light shielding member BM overlaps with the overlapping portion of the color filters CF1, CF2, and CF3.

[0109] The substrate SUB may be a base substrate or a base member. The substrate SUB may be a flexible substrate that can be bent, folded and / or curled, etc. For example, the substrate SUB may include a polymer resin such as polyimide (PI), but is not limited thereto. As another example, the substrate SUB may include a glass material and / or a metal material.

[0110] The driving element layer TFTL may include a first buffer layer BF1, a lower metal layer BML, a second buffer layer BF2, a transistor TFT, a gate insulating layer GI, a first interlayer insulating layer ILD1, a capacitor electrode CPE, a second interlayer insulating layer ILD2, a first connection electrode CNE1, a first protection layer PAS1, a second connection electrode CNE2, and a second protection layer PAS2.

[0111] The first buffer layer BF1 may be disposed on the substrate SUB. The first buffer layer BF1 may include an inorganic layer that may prevent penetration of air or moisture. For example, the first buffer layer BF1 may include a plurality of inorganic layers alternately stacked. According to one or more embodiments, the first buffer layer BF1 may be omitted.

[0112] The lower metal layer BML may be disposed on the first buffer layer BF1. For example, the lower metal layer BML may be formed as a single layer or a plurality of layers formed of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), and / or an alloy thereof.

[0113] The second buffer layer BF2 may cover the first buffer layer BF1 and the lower metal layer BML. The second buffer layer BF2 may include an inorganic layer that may prevent penetration of air or moisture. For example, the second buffer layer BF2 may include a plurality of inorganic layers alternately stacked.

[0114] The transistor TFT may be disposed on the second buffer layer BF2, and the transistor TFT may be a driving transistor or a switching transistor of the pixel circuit unit. The transistor TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0115] The semiconductor layer ACT may be located on the second buffer layer BF2. The semiconductor layer ACT may overlap the lower metal layer BML and the gate electrode GE in the thickness direction (e.g., the third direction DR3) of the substrate SUB, and may be insulated from the gate electrode GE by the gate insulating layer GI. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may be conductive, and thus a source electrode SE and a drain electrode DE may be formed. The semiconductor layer ACT may include an undoped channel layer located between the source electrode SE and the drain electrode DE.

[0116] The gate electrode GE may be disposed on the gate insulating layer GI. The gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer GI interposed therebetween.

[0117] The gate insulating layer GI may be disposed on the semiconductor layer ACT and the second buffer layer BF2. For example, the gate insulating layer GI may cover the semiconductor layer ACT and the second buffer layer BF2 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer GI may include a contact hole through which the first connection electrode CNE1 passes.

[0118] The first interlayer insulating layer ILD1 may cover the gate electrode GE and the gate insulating layer GI. The first interlayer insulating layer ILD1 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer ILD1 may be connected to the contact hole of the gate insulating layer GI and the contact hole of the second interlayer insulating layer ILD2.

[0119] The capacitor electrode CPE may be disposed on the first interlayer insulating layer ILD1. The capacitor electrode CPE may overlap the gate electrode GE in a thickness direction of the substrate SUB (eg, in the third direction DR3). The capacitor electrode CPE and the gate electrode GE may form a capacitor.

[0120] The second interlayer insulating layer ILD2 may cover the capacitor electrode CPE and the first interlayer insulating layer ILD1. The second interlayer insulating layer ILD2 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer ILD2 may be connected to the contact hole of the first interlayer insulating layer ILD1 and the contact hole of the gate insulating layer GI.

[0121] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer ILD2. The first connection electrode CNE1 may electrically connect the drain electrode DE of the transistor TFT and the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole formed in the second interlayer insulating layer ILD2, the first interlayer insulating layer ILD1, and the gate insulating layer GI to contact the drain electrode DE of the transistor TFT.

[0122] The first protection layer PAS1 may cover the first connection electrode CNE1 and the second interlayer insulating layer ILD2. The first protection layer PAS1 may protect the transistor TFT. The first protection layer PAS1 may include a contact hole through which the second connection electrode CNE2 passes.

[0123] The second connection electrode CNE2 may be disposed on the first protection layer PAS1. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 and the pixel electrode AE ​​(hereinafter, also referred to as the anode or the first electrode) of the light emitting element ED. The second connection electrode CNE2 may be inserted into a contact hole formed in the first protection layer PAS1 to contact the first connection electrode CNE1.

[0124] The second protection layer PAS2 may cover the second connection electrode CNE2 and the first protection layer PAS1. The second protection layer PAS2 may include a contact hole through which the pixel electrode AE ​​of the light emitting element ED passes.

[0125] The light emitting element layer EML may be disposed on the driving element layer TFTL. The light emitting element layer EML may include a light emitting element ED and a pixel defining layer PDL. The light emitting element ED may include a pixel electrode AE, a light emitting layer EL, and a common electrode CE (hereinafter, also referred to as a second electrode or cathode). The light emitting element ED may further include a functional layer FL, and the functional layer FL may include at least one layer of a hole injection layer, a hole transport layer, an electron injection layer, and an electron transport layer, and may be located on both sides of the light emitting layer EL.

[0126] The pixel electrode AE ​​may be disposed on the second protection layer PAS2. The pixel electrode AE ​​may be disposed to overlap each of the pixel openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL. The pixel electrode AE ​​may be electrically connected to the drain electrode DE of the transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2.

[0127] The light-emitting layer EL may be disposed on the pixel electrode AE. For example, the light-emitting layer EL may be an organic light-emitting layer formed of an organic material, but is not limited thereto. The functional layer FL may be located on both sides of the light-emitting layer EL, the functional layer FL located between the light-emitting layer EL and the pixel electrode AE ​​may include a hole injection layer and / or a hole transport layer, and the functional layer FL located between the light-emitting layer EL and the common electrode CE may include an electron transport layer and / or an electron injection layer. In the case where the light-emitting layer EL corresponds to the organic light-emitting layer, when the transistor TFT applies a predetermined voltage to the pixel electrode AE ​​of the light-emitting element ED and the common electrode CE of the light-emitting element ED receives a common voltage or a driving low voltage, holes and electrons may move to the light-emitting layer EL through the hole transport layer and the electron transport layer, respectively, current may flow through the light-emitting element ED, and holes and electrons may recombine with each other in the light-emitting layer EL to emit light.

[0128] The common electrode CE may be disposed on the light emitting layer EL. For example, the common electrode CE may be implemented in the form of an electrode common to all pixels, rather than being distinguished for each of the plurality of pixels. The common electrode CE may be disposed on the light emitting layer EL in the first to third emission areas EMA1, EMA2, and EMA3, and may be disposed on the pixel defining layer PDL in areas other than the first to third emission areas EMA1, EMA2, and EMA3. The functional layer FL may be located between the pixel defining layer PDL and the common electrode CE.

[0129] The common electrode CE may receive a common voltage or a driving low voltage. When the pixel electrode AE ​​receives a voltage corresponding to the data voltage and the common electrode CE receives the driving low voltage, a potential difference is formed between the pixel electrode AE ​​and the common electrode CE, current flows, and thus the light emitting layer EL emits light.

[0130] The pixel defining layer PDL may be disposed on a portion of the pixel electrode AE ​​and the second protective layer PAS2. The pixel defining layer PDL may expose a portion of the pixel electrode AE. As described above, the pixel defining layer PDL may define the first emission area EMA1 to the third emission area EMA3, and their areas or sizes may be different from each other. The pixel defining layer PDL may separate and insulate the pixel electrode AE ​​of each of the plurality of light emitting elements ED. The pixel defining layer PDL may be a black pixel defining layer including a light absorbing material to prevent reflection of external light. For example, the pixel defining layer PDL may include a polyimide (PI)-based binder and a mixture of red, green and / or blue pigments. Alternatively, the pixel defining layer PDL may include a mixture of a cardo-based binder resin, a lactam-based black pigment and / or a blue pigment. Alternatively, the pixel defining layer PDL may include carbon black.

[0131] For ease of description, Figure 6 The pixel defining layer PDL is shown in a trapezoidal shape, and the shape of the pixel defining layer PDL is not limited thereto.

[0132] The encapsulation layer TFEL may be disposed on the common electrode CE to cover the plurality of light emitting elements ED. The encapsulation layer TFEL may include at least one inorganic layer and may prevent oxygen and / or moisture from penetrating into the light emitting element layer EML. The encapsulation layer TFEL may include at least one organic layer and may protect the light emitting element layer EML from foreign matter such as dust.

[0133] Figure 6 The encapsulation layer TFEL may include a first encapsulation layer TFE1, a second encapsulation layer TFE2, and a third encapsulation layer TFE3. The first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be inorganic encapsulation layers, and the second encapsulation layer TFE2 disposed between the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may be an organic encapsulation layer.

[0134] Each of the first encapsulation layer TFE1 and the third encapsulation layer TFE3 may include one or more inorganic insulating materials. The inorganic insulating materials may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and / or silicon oxynitride.

[0135] The second encapsulation layer TFE2 may include a polymer material. The polymer material may include an acrylic resin, an epoxy resin, a polyimide and / or polyethylene, etc. For example, the second encapsulation layer TFE2 may include an acrylic resin such as polymethyl methacrylate and / or polyacrylic acid. The second encapsulation layer TFE2 may be formed by curing a monomer and / or applying a polymer.

[0136] The external light reducing layer CFL located on the encapsulation layer TFEL includes a light blocking member BM and color filters CF1, CF2, and CF3. The color filters CF1, CF2, and CF3 may be located on the light blocking member BM. Here, the light blocking member BM overlaps with the overlapping portions of the color filters CF1, CF2, and CF3.

[0137] The shading member BM may be disposed on the encapsulation layer TFEL. The shading member BM may include a light absorbing material. For example, the shading member BM may include an inorganic black pigment and / or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black, and the present disclosure is not limited thereto. The shading member BM may improve the color reproduction rate of the display device 10 by preventing visible light from intruding and mixing colors between the first to third emission areas EMA1, EMA2, and EMA3.

[0138] The color filters CF1, CF2, and CF3 of the external light reduction layer CFL may be disposed on the light shielding member BM. Different color filters CF1, CF2, and CF3 may be disposed to correspond to different emission areas EMA1, EMA2, and EMA3 or pixel openings OPE1, OPE2, and OPE3 of the pixel defining layer PDL and light shielding openings OPT1, OPT2, and OPT3 of the light shielding member BM, respectively. For example, the first color filter CF1 may be disposed to correspond to the first emission area EMA1, the second color filter CF2 may be disposed to correspond to the second emission area EMA2, and the third color filter CF3 may be disposed to correspond to the third emission area EMA3.

[0139] The external light reduction layer CFL may further include a planarization layer OC, and the planarization layer OC may be disposed on the color filters CF1, CF2, and CF3 to planarize the upper ends of the color filters CF1, CF2, and CF3. The planarization layer OC may be a colorless light-transmitting layer having no color in the visible light band. For example, the planarization layer OC may include a colorless, light-transmitting organic material such as an acrylic resin.

[0140] Figure 7 It is a graphic Figure 4 a plan view of a portion of the display area, and Figure 8 is a plan view illustrating an example in which a defect occurs in a conductive pattern.

[0141] For ease of description, Figure 7 and Figure 8 Only the gate electrode GE (see Figure 6 ) or grid line GL (reference Figure 4 ) of the conductive pattern CP and forming a semiconductor layer ACT (reference Figure 6 )'s active pattern.

[0142] refer to Figure 4 , Figure 6 and Figure 7 , a conductive pattern CP forming a gate electrode GE or a gate line GL may be disposed in the display area DA. An active pattern forming a channel region (or channel layer) of a transistor TFT may be disposed in the display area DA. For example, a first conductive pattern CP1 may form a gate electrode GE, and may form a transistor TFT together with the active pattern. For example, a second conductive pattern CP2 may form a gate line GL.

[0143] refer to Figure 8 , defects may occur in the process of forming the conductive pattern CP. Figure 8 As shown in FIG. 1 , there may be a contact between the first conductive pattern CP1 and the second conductive pattern CP2 or a different gate line GL may be formed (refer to FIG. 1 ). Figure 4 )’s contact defect between the second conductive pattern CP2.

[0144] When a defect is found during the manufacturing process of the display panel, a process of repairing the defect area RA where the defect occurs is required to remove the defect. For example, the repair process may be a process of removing the defect area RA.

[0145] The defective area RA refers to the area that is repaired by the repair device 20 (refer to Fig.11 In the present embodiment, the defect area RA is illustrated as a quadrilateral shape, but the present disclosure is not limited to the shape of the defect area RA.

[0146] The defects according to the present disclosure refer only to defects that need to be removed, and the shape of the defects is not limited.

[0147] In the following, reference Figures 9 to 15 Describe the repair process in detail.

[0148] Fig. 9 It is a graphic Figure 8 A cross-sectional view of an example of a conductive pattern.

[0149] refer to Fig. 9, the conductive pattern CP may be formed as a multilayer pattern. In order to reduce the resistance of the gate line GL, the conductive pattern CP needs to be formed of a material having a low resistance (e.g., aluminum (Al)). However, in the case of a material that is susceptible to cleaning damage by heat and chemicals (e.g., aluminum (Al)), it may be difficult to use the material alone as the conductive pattern CP. Therefore, the conductive pattern CP may be formed as a multilayer pattern including different materials.

[0150] For example, the conductive pattern CP may include a first layer L1 including aluminum (Al), a first layer L2 including titanium nitride (TiN), and a second layer L3 including titanium nitride (Ti). x N y ) and a second layer L2 containing titanium (Ti) and a third layer L3.

[0151] However, the present disclosure is not limited to the type and amount of materials forming the multi-layered conductive pattern CP.

[0152] Fig.10 is a flowchart illustrating a method of repairing a display panel according to one or more embodiments of the present disclosure.

[0153] refer to Fig.10 , the method for repairing a display panel may include inspecting a defect of a pattern of the display panel (step S100), irradiating a first laser having a first pulse width to a defective area where the defect occurs (step S200), and irradiating a second laser having a second pulse width different from the first pulse width to the defective area (step S300).

[0154] In the following, reference Figures 11 to 15 The present disclosure is described in detail.

[0155] Fig.11 It is a graphical execution Fig.10 A block diagram of a repairing device of a method for repairing a display panel.

[0156] refer to Fig.11 The repair device may include a laser irradiator 21, a controller 22 and a shooting unit 23.

[0157] The laser irradiator 21 may receive a first control signal CON1 from the controller 22 and irradiate the laser light LA. The first control signal CON1 may include a pulse width, an irradiation time, an irradiation position, and / or an irradiation method of the laser light LA, and the like.

[0158] The photographing unit 23 can photograph the display panel 100 (refer to Figure 2 ) to generate image data IMG, and provide the image data IMG to the controller 22. The photographing unit 23 can photograph the display panel 100 (reference numeral 23) by receiving the second control signal CON2 from the controller 22. Figure 2). The second control signal CON2 may include a shooting position and / or a shooting angle, etc.

[0159] The controller 22 may check the display panel 100 (refer to Figure 2 ) defect. In addition, when a defect occurs, the controller 22 can control the laser irradiator 21 so that the laser irradiator 21 removes the defect area RA (reference Figure 8 ).

[0160] Fig.12 and Fig.13 It is a graphic Fig.10 FIG. 100 of step S200, and Fig.14 and Fig.15 It is a graphic Fig.10 FIG. 10 is a diagram of step S300.

[0161] refer to Figure 8 and Figures 12 to 15 , the second layer L2 and the third layer L3 of the conductive pattern CP of the defect area RA may be removed by the first laser LA1, and the first layer L1 of the conductive pattern CP of the defect area RA may be removed by the second laser LA2.

[0162] As described above, the conductive pattern CP may be formed as a multi-layer pattern. For example, the first layer L1 may include aluminum (Al), and the second layer L2 may include titanium nitride (Ti). x N y ), and the third layer L3 may include titanium (Ti).

[0163] The first pulse width of the first laser LA1 may be narrower than the second pulse width of the second laser LA2, and the peak power of the first laser LA1 may be greater than the peak power of the second laser LA2. For example, the first laser LA1 may be an ultrafast laser. For example, the first laser LA1 may be a picosecond laser, a femtosecond laser, and / or an attosecond laser. For example, the second laser LA2 may be a nanosecond laser.

[0164] refer to Fig.12 , a laser with a relatively narrow pulse width may be used as the first laser LA1. When the pulse width of the first laser LA1 is wide, heat may be gradually generated and diffused after irradiation, and the first layer L1 may melt and shrink due to the heat. Therefore, an ultrafast laser with a relatively narrow pulse width may be used as the first laser LA1.

[0165] refer to Fig.13 , the peak power of the first laser LA1 may be higher than the peak power of the second laser LA2. Therefore, when the first laser LA1 is irradiated in a stepping method, the lower layer (eg, active pattern) may be damaged. Therefore, the first laser LA1 may be irradiated in a scanning method.

[0166] like Fig.13 As shown in FIG. 1 , the scanning method is to scan a specific area (e.g., Fig.13 A method of sequentially irradiating laser light with a line in the image. Fig.15 As shown in , the step method is a method of irradiating laser light to the entire defect area RA concurrently (eg, simultaneously). However, the present disclosure is not limited to the shape of the above-mentioned specific area.

[0167] refer to Fig.14 , a laser with a relatively wide pulse width can be used as the second laser LA2. When the pulse width of the first laser LA1 is narrow, a large amount of residual particles may be generated due to high peak power, and the lower layer (eg, active pattern) may be damaged. Therefore, a nanosecond laser can be used as the second laser LA2.

[0168] refer to Fig.15 , the peak power of the second laser LA2 may be lower than the peak power of the first laser LA1. Therefore, when the second laser LA2 is irradiated in a scanning method, the defect area RA may not be completely removed because of weak energy. Therefore, the second laser LA2 may be irradiated in a stepping method.

[0169] However, the present disclosure is not limited to the order of irradiating the laser. For example, the order of irradiating the laser may be changed according to the material of the pattern.

[0170] In addition, the present disclosure is not limited to the method of irradiating laser light (eg, a step method and / or a scanning method, etc.) For example, the method of irradiating laser light may be changed depending on the material of the pattern.

[0171] Although specific embodiments and application examples are described herein, these specific embodiments and application examples are provided only to facilitate a more comprehensive understanding of the present disclosure. The present disclosure is not limited to the above embodiments, and a person skilled in the art to which the present disclosure belongs may make various corrections and modifications to such descriptions.

[0172] Therefore, the spirit and scope of the present disclosure should not be limited to the described embodiments, and all modifications of the claims and equivalents or equivalents to the claims may fall within the scope of the spirit of the present disclosure.

[0173] The present disclosure may be applied to a display device and an electronic device including a display device. For example, the present disclosure may be applied to a digital TV, a 3D TV, a mobile phone, a smart phone, a tablet computer, a VR device, a PC, a home electronic device, a notebook computer, a PDA, a PMP, a digital camera, a music player, a portable game console and / or a navigation system, etc.

[0174] Although described with reference to the above embodiments, it will be understood that those skilled in the art may make various modifications and changes to the present disclosure without departing from the spirit and scope of the present disclosure as described in the claims.

Claims

1. A method for repairing a display panel, the method comprising: inspecting a first pattern of the display panel for defects; irradiating a first laser having a first pulse width onto a defective area where the defect occurs; as well as A second laser having a second pulse width different from the first pulse width is irradiated to the defective region.

2. The method according to claim 1, wherein: The first pattern is a multi-layer pattern.

3. The method according to claim 2, wherein: The first pattern includes a first layer including aluminum and a second layer on the first layer and including titanium.

4. The method according to claim 3, wherein: The second layer is removed by the first laser, and The first layer is removed by the second laser.

5. The method according to claim 3, wherein: The first pattern further includes a third layer located between the first layer and the second layer and including titanium nitride.

6. The method according to claim 1, wherein: The first pattern includes gate lines of the display panel.

7. The method according to claim 6, wherein: The first pattern is located on the second pattern, and Wherein, the second pattern includes a channel region of a transistor of the display panel.

8. The method according to claim 1, wherein: The first pulse width is smaller than the second pulse width.

9. The method according to claim 1, wherein: The peak power of the first laser is greater than the peak power of the second laser.

10. The method according to claim 1, wherein: The first laser is a femtosecond laser.

11. The method according to claim 1, wherein: The second laser is a nanosecond laser.

12. The method according to any one of claims 1 to 10, wherein: The first laser light is irradiated in a scanning method.

13. The method according to any one of claims 1 to 10, wherein: The second laser is irradiated in a stepping method.

14. A repairing device for repairing a display panel, comprising: a laser irradiator configured to irradiate a first laser having a first pulse width and a second laser having a second pulse width different from the first pulse width to a defective area where a defect of the display panel occurs; as well as A controller is configured to control the laser irradiator.

15. The repair device according to claim 14, further comprising: a photographing unit configured to photograph the display panel to generate image data and provide the image data to the controller, Wherein, the controller is configured to inspect the defect based on the image data.

16. The repair device according to claim 14, wherein: The first pulse width is smaller than the second pulse width.

17. The repair device according to claim 14, wherein: The peak power of the first laser is greater than the peak power of the second laser.

18. The repair device according to claim 14, wherein: The first laser is a femtosecond laser, and Wherein, the second laser is a nanosecond laser.

19. The repair device according to any one of claims 14 to 18, wherein: The laser irradiator is configured to irradiate the first laser in a scanning method.

20. The repair device according to any one of claims 14 to 18, wherein: The laser irradiator is configured to irradiate the second laser in a stepping method.

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