Operating method for memory

Abstract

The invention discloses an operation method for a plurality of memories and a controller thereof, and the method comprises the following steps: outputting a selection signal to a first group of memories in the plurality of memories, but not outputting the selection signal to a second group of memories different from the first group of memories in the plurality of memories; outputting a clock signal to a third group of memories in the plurality of memories, but not outputting the clock signal to a fourth group of memories different from the third group of memories in the plurality of memories; outputting an instruction to a fifth group of memories in the plurality of memories, but not outputting the instruction to a sixth group of memories different from the fifth group of memories in the plurality of memories; and selecting one of the plurality of memories according to the selection signal, the clock signal and the instruction.

Description

Technical Field

[0001] The present invention relates to an operating method for a memory, and in particular to an operating method capable of accessing a memory in a light-emitting diode (LED) display. Background Art

[0002] In recent years, direct view LED displays that use light-emitting diode (LED) arrays as actual display pixels have gradually emerged. In large-scale direct view LED displays, the screen is formed by connecting a large number of LED light boxes, each of which includes a display screen with multiple light boards, and each light box also includes a control board that carries an LED controller for transmitting display data to each light board to generate the image to be displayed in the display area of ​​each light board. A flash memory can be set on each light board to store the compensation information required for the LED pixels on the light board.

[0003] The light board is the display unit of the LED screen. In a large-size LED display, if any display pixel or area is damaged, it needs to be repaired as a unit of the light board. That is, the LED screen can be repaired by replacing the light board with damaged pixels with a new light board. The new light board has new LED pixels, which may have different compensation information, and the compensation data of these new LED pixels should be carried in the flash memory corresponding to the new light board. Therefore, the original flash memory should be updated or replaced by the new flash memory. In this way, the LED controller can directly read the correct compensation data for the new light board from the corresponding flash memory, avoiding the extra labor required to manually update the compensation data.

[0004] However, in the prior art, the LED controller is required to control a large number of light panels, so a large number of control ports are required to access the flash memory to obtain compensation data. A large number of control ports requires a considerable circuit cost, especially as the number of light panels in the LED display is gradually increasing. Summary of the invention

[0005] Therefore, the main purpose of the present invention is to provide a new operation method for accessing a flash memory to solve the above problems.

[0006] An embodiment of the present invention discloses an operation method for multiple memories, which includes the following steps: outputting a selection signal to a first group of memories among the multiple memories, but not outputting the selection signal to a second group of memories among the multiple memories that is different from the first group of memories; outputting a clock signal to a third group of memories among the multiple memories, but not outputting the clock signal to a fourth group of memories among the multiple memories that is different from the third group of memories; outputting an instruction to a fifth group of memories among the multiple memories, but not outputting the instruction to a sixth group of memories among the multiple memories that is different from the fifth group of memories; and selecting one of the multiple memories according to the selection signal, the clock signal and the instruction.

[0007] Another embodiment of the present invention discloses a controller for controlling a plurality of memories. The controller includes a plurality of selection ports, a plurality of clock ports, and a plurality of signal ports. The plurality of selection ports are respectively coupled to a first plurality of groups of memories among the plurality of memories. The plurality of clock ports are respectively coupled to a second plurality of groups of memories among the plurality of memories. The plurality of signal ports are respectively coupled to a third plurality of groups of memories among the plurality of memories. The controller outputs a selection signal through one of the plurality of selection ports, outputs a clock signal through one of the plurality of clock ports, and outputs an instruction through one of the plurality of signal ports. The controller selects one of the plurality of memories according to the selection signal, the clock signal, and the instruction. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of an exemplary direct-view light-emitting diode display.

[0009] Figure 2 A simplified structure of an LED light box is shown.

[0010] Figure 3 A control port of a light emitting diode controller is shown for controlling a flash memory.

[0011] Figure 4 Figure 2 is a waveform diagram of the control signals of the serial peripheral interface in a read operation.

[0012] Figure 5 Figure 2 is a waveform diagram of the control signals of the serial peripheral interface during a write operation.

[0013] Fig. 6A An exemplary implementation of connecting a light emitting diode controller to a flash memory according to an embodiment of the present invention is shown.

[0014] Figure 6B A flash memory bank is shown connected to a light emitting diode controller.

[0015] Figure 7 Schematic diagram of the system structure in which the LED controller is connected to 12 flash memories.

[0016] Figure 8 The waveform diagram of a chip select port that is not selected.

[0017] Fig. 9 FIG. 4 is a waveform diagram of an unselected clock port.

[0018] Fig.10 FIG. 4 is a waveform diagram of an unselected slave input port.

[0019] Fig.11 This is the waveform diagram of another slave input port that is not selected.

[0020] Fig.12 An exemplary implementation of flash memory grouping is shown.

[0021] Fig.13 Another exemplary implementation of flash memory grouping is shown.

[0022] Fig.14 The figure is a flow chart of the operation process of the first embodiment of the present invention.

[0023] The reference numerals are described as follows:

[0024] 10 LED Display

[0025] 100 LED screen

[0026] 110 LED light box

[0027] 120 Light Board

[0028] 130 Control Panel

[0029] 122 LED Driver

[0030] 132,600 LED controller

[0031] 140 Connectors

[0032] CS_0~CS_11、CS、CS_A、CS_B、CS_C chip select port

[0033] CLK, CLK_A, CLK_B, CLK_C clock ports

[0034] SI, SI_A, SI_B, SI_C slave input port

[0035] SO_0~SO_11, SO slave output port

[0036] BUF_1~BUF_4, BUF buffer

[0037] A23~A0 Address

[0038] D7~D0 data

[0039] FLASH_0~FLASH_11 Flash memory

[0040] G1_A, G1_B, G1_C, G2_A, G2_B, Group G2_C, G3_A, G3_B, G3_C

[0042] 1400 Operation Flow

[0043] Steps 1402-1408 DETAILED DESCRIPTION

[0044] Figure 1 FIG. 1 is a schematic diagram of an exemplary direct view LED display 10. The LED display 10 may be a large-size display, wherein an LED screen 100 is composed of a plurality of LED light boxes 110, and each LED light box 110 includes a plurality of light panels 120 and a control panel 130.

[0045] In detail, each light board 120 can be used as a display unit to construct the LED screen 100. The light board 120 can be formed by a printed circuit board (PCB) on which an LED array and a plurality of LED drivers 122 are disposed. The LED driver 122 can be used to provide a driving current to the corresponding LEDs to drive the LEDs to emit light. The light board 120 can be connected to the control board 130 through the connector 140, so that the LEDs on the light board 120 form a pixel array as a partial segment of the LED screen 100. Each LED light box 110 can also include one or more LED controllers 132, which are disposed on the control board 130 and are configured to receive video data and related instructions from a video source, so as to determine the image range to be displayed by the LED pixels in the corresponding LED light box 110 according to the instructions, and transmit the display data to the corresponding light board 120 accordingly. The LED controller 132 is also responsible for appropriately compensating the received video data. Generally speaking, due to process variation (or other factors), the light-emitting characteristics of different LED pixels may be inconsistent, which should be compensated in the display operation to improve the display quality. In some embodiments, the LED light box 110 may also include a power supply device or a power integrated circuit (Power Integrated Circuit, Power IC) (not shown for simplicity), and these power supply devices may also be disposed on the control board 130.

[0046] Figure 2 The simplified structure of the LED light box 110 is shown, wherein the control board 130 is connected to 12 light boards 120 via connectors 140, and each light board 120 may include a flash memory or be coupled to a flash memory (not shown). The flash memory may be used to store compensation data for the LED pixels on the corresponding light board 120, and the purpose of the compensation data is to compensate for the inconsistency of the light emission characteristics (such as brightness and / or chromaticity). In display operation, the LED controller 132 may access the flash memory to obtain the compensation data, and then use the compensation data to modify the display data.

[0047] In this case, the LED controller 132 of the LED light box 110 is required to control multiple flash memories. Figure 2 The LED light box 110 shown includes only one LED controller, which needs to perform read and write operations on 12 flash memories on 12 light boards 120 .

[0048] The LED controller 132 usually controls the flash memory through a serial peripheral interface (SPI), which can be used by a host device (i.e., the LED controller 132) to control multiple slave devices (i.e., the flash memory). The serial peripheral interface may include several chip select ports (CS), a clock port (CLK), a master-out-slave-in port (hereinafter referred to as a slave input port (SI)), and multiple master-in-slave output ports (hereinafter referred to as slave output ports (SO)). Each chip select port can be used as a selection port for the LED controller 132 to select a specific flash memory. The clock port is a control port that transmits a clock signal to synchronize the timing of the slave device and the host device. The slave input port is the output port of the LED controller 132 (because it is a master output slave input port), wherein the LED controller 132 can use the slave input port to output instructions or data to the flash memory. Each slave output port is an input port of the LED controller 132 (because it is a master-input slave output port), wherein the LED controller 132 can use the slave output port to receive data from the flash memory.

[0049] Figure 3 The LED controller 132 is shown as a control port for controlling the flash memory, including chip select ports CS_0 to CS_11 of the serial peripheral interface, a clock port CLK, a slave input port SI, and a slave output port SO_0 to SO_11. Assuming that the LED controller 132 is used to control 12 flash memories, its ports include 12 chip select ports CS_0 to CS_11 respectively coupled to the 12 flash memories. The 12 flash memories can receive the same clock signal, so only one clock port CLK is needed to allow the LED controller 132 to supply the clock signal.

[0050] The slave input port SI can be used to transmit any signal or data from the LED controller 132 to the flash memory. For example, during the use of the LED screen 100, each LED pixel on the light board 120 may experience different degrees of aging, resulting in different degrees of brightness efficiency decay, thereby generating additional brightness inconsistency. Therefore, the LED controller 132 needs to update the compensation data for the LED pixels and write the updated compensation data to the flash memory through the slave input port SI. Generally speaking, a flash memory can only receive instructions or data when the chip select ports CS_0~CS_11 are enabled, so only one flash memory is enabled at the same time. In this case, only one slave input port SI is sufficient for the LED controller 132 to transmit instructions or data.

[0051] The slave output ports SO_0-SO_11 can be used to transmit any signal or data from the flash memory to the LED controller 132. For example, when the LED controller 132 receives display data of an LED pixel from the video source, the compensation data corresponding to the LED pixel can be read from the flash memory to modify / compensate the display data using the compensation data. Since the 12 flash memories are controlled by the LED controller 132, the LED controller 132 can have 12 slave output ports SO_0-SO_11 respectively coupled to the 12 flash memories.

[0052] It is worth noting that the LED controller 132 is coupled to the flash memory located on different lamp boards 120, and each control signal should be transmitted through the connection line between the control board 130 and the lamp board 120 and the connector 140 therebetween. In this case, the control signal needs to be transmitted over a considerable distance. Generally speaking, the output driving device of the LED controller 132 is usually implemented in an integrated circuit, which may not have sufficient driving capability. To solve this problem, one or more buffers can be set on the control board 130 or the lamp board 120 to couple between the LED controller 132 and the flash memory. Therefore, the control signal or data output by the control port of the LED controller 132 can be transmitted to the flash memory through the buffer.

[0053] For example, if Figure 3As shown, the chip select signal outputted by the chip select ports CS_0-C_11 is transmitted through a buffer BUF_1, the clock signal outputted by the clock port CLK is transmitted through a buffer BUF_2, and the instruction or data outputted by the slave input port SI is transmitted through a buffer BUF_3. In addition, the data (such as compensation data) read out from the flash memory can also be transmitted through a buffer BUF_4. The buffers BUF_1-BUF_4 can also provide the control port with sufficient driving capability to drive multiple output devices.

[0054] In another embodiment, if the LED controller 132 has sufficient driving capability to drive the flash memory, the buffer may be omitted without affecting the operation of accessing the flash memory.

[0055] like Figure 3 As shown, if an LED controller 132 is responsible for controlling 12 flash memories through a serial peripheral interface, it needs 26 ports to transmit related control signals, including 12 chip selection ports CS_0 to C_11, 1 clock port CLK, 1 slave input port SI, and 12 slave output ports SO_0 to SO_11. A large number of control ports requires a considerable circuit cost. Therefore, the present invention proposes a new operation method, which allows the LED controller to access multiple flash memories through a small number of control ports.

[0056] The following is a brief description of the operating principle of the serial peripheral interface. Figure 4 The waveform diagram of the control signal of the serial peripheral interface in the read operation. When the light-emitting diode controller wants to read the compensation data from a specific flash memory, the chip select port CS corresponding to the flash memory can be pulled low, and the clock port CLK starts to switch at a preset clock frequency. When the clock starts to output, the slave input port SI can transmit an instruction in the first bit group, and then transmit the address (such as A23~A0) in the subsequent several bit groups (3 bit groups in this example, or equivalent to 24 clock cycles). The instruction "03" output by the slave input port SI indicates the enablement of the read operation. The address represents the flash memory location of the data to be read. Then, during the subsequent data output period, the data stored at the specific address (such as D7~D0) is output to the light-emitting diode controller through the slave output port SO. When the required data is completely read out, the corresponding chip select port CS can be restored to a high level (not shown).

[0057] Figure 5The waveform diagram of the control signal of the serial peripheral interface in the write operation. When the LED controller wants to write the compensation data into a specific flash memory, the chip select port CS corresponding to the flash memory can be pulled low, and the clock port CLK starts to switch at a preset clock frequency, and at the same time, a command "06h" is transmitted through the slave input port SI to indicate the enablement of the write operation. When the command transmission is completed, the corresponding chip select port CS will return to a high level. During the write operation, the LED controller does not need to read data from the flash memory, and the corresponding slave output port SO can be maintained in a high impedance (High-Z) state.

[0058] It can be seen that the read or write operation of the serial peripheral interface should meet three conditions: the chip select port enters a low level, the clock port is switched appropriately, and the slave input port transmits a valid instruction. Therefore, in order to access a target flash memory, the light-emitting diode controller can use multiple chip select ports for selection. In addition, two or more clock ports can be coupled to two or more groups of flash memories, wherein the correct clock signal can be provided to one group, while no clock signal is provided to the other groups. In addition, different slave input ports can be coupled to multiple groups of flash memories, wherein valid and correct instructions are selected only through the output of one of the slave input ports.

[0059] Correspondingly, the flash memory can be divided into a first plurality of groups in a first manner, each of which is used to receive a selection signal from one of the chip select ports. The flash memory can also be divided into a second plurality of groups in a second manner (which is different from the first manner), each of which is used to receive a clock signal from one of the clock ports. The flash memory can also be divided into a third plurality of groups in a third manner (which is different from the first manner and the second manner), each of which is used to receive a command from one of the slave input ports.

[0060] Under the above grouping method, each flash memory belongs to one of the first plurality of groups, one of the second plurality of groups, and one of the third plurality of groups. In addition, each flash memory and another flash memory belong to at least one different group. Therefore, in order to select access to a target flash memory, the LED controller can output a correct selection signal to a group of the first plurality of groups including the target flash memory, output a clock signal to a group of the second plurality of groups including the target flash memory, and output a valid instruction (such as a read or write enable instruction) to a group of the third plurality of groups including the target flash memory. In this case, the target flash memory can be selected according to the combination of the selection signal, the clock signal and the instruction.

[0061] Fig. 6AAn exemplary implementation of a light emitting diode controller 600 connected to a flash memory according to an embodiment of the present invention is shown. In this example, the light emitting diode controller 600 is used to control 12 flash memories numbered from 0 to 11 (i.e., FLASH_0 to FLASH_11). The light emitting diode controller 600 includes two chip select ports CS_A and CS_B, two clock ports CLK_A and CLK_B, and three slave input ports SI_A, SI_B, and SI_C as its output ports. The light emitting diode controller 600 also includes 12 slave output ports SO_0 to SO_11 as its input ports.

[0062] Figure 6B It is shown that the flash memories FLASH_0-FLASH_11 are grouped and connected to the light emitting diode controller 600. In detail, the flash memories FLASH_0-FLASH_11 can be divided into two groups G1_A and G1_B, wherein the group G1_A includes the flash memories FLASH_0 / 2 / 4 / 6 / 8 / 10 and is coupled to the chip selection port CS_A, and the group G1_B includes the flash memories FLASH_1 / 3 / 5 / 7 / 9 / 11 and is coupled to the chip selection port CS_B. The flash memories FLASH_0-FLASH_11 can also be divided into two groups G2_A and G2_B in different ways, wherein the group G2_A includes the flash memories FLASH_0 / 1 / 4 / 5 / 8 / 9 and is coupled to the clock port CLK_A, and the group G2_B includes the flash memories FLASH_2 / 3 / 6 / 7 / 10 / 11 and is coupled to the clock port CLK_B. The flash memories FLASH_0-FLASH_11 can be divided into three groups G3_A, G3_B and G3_C in another different way, wherein the group G3_A includes the flash memories FLASH_0 / 1 / 2 / 3 and is coupled to the slave input port SI_A, the group G3_B includes the flash memories FLASH_4 / 5 / 6 / 7 and is coupled to the slave input port SI_B, and the group G3_C includes the flash memories FLASH_8 / 9 / 10 / 11 and is coupled to the slave input port SI_C. Therefore, each of the flash memories FLASH_0-FLASH_11 can be coupled to the LED controller 600 through one of the two chip select ports CS_A and CS_B, one of the two clock ports CLK_A and CLK_B, and one of the three slave input ports SI_A, SI_B and SI_C. Every two flash memories are connected differently in at least one of the chip selection port, the clock port and the slave input port, so that the target flash memory for performing the read / write operation can be selected according to the output of the selection signal, the clock signal and the instruction.

[0063] The overall system structure of the LED controller 600 connected to 12 flash memories FLASH_0 to FLASH_11 is shown in FIG. Figure 7 Please refer to Figure 7 Matching Fig. 6A and 6B As shown, each chip select port CS_A and CS_B is coupled to 6 flash memories, each clock port CLK_A and CLK_B is coupled to 6 flash memories, and each slave input port SI_A, SI_B and SI_C is coupled to 4 flash memories. In this case, the operation of controlling the 12 flash memories FLASH_0 to FLASH_11 can be achieved using only 19 ports, including 2 chip select ports, 2 clock ports, 3 slave input ports, and 12 slave output ports. Compared to Figure 3 Compared with the conventional serial peripheral interface implementation with 26 control ports shown in the figure, this embodiment can achieve significant improvement.

[0064] Similarly, the control signals output from the chip select ports CS_A and CS_B, the clock ports CLK_A and CLK_B, and the slave input ports SI_A, SI_B, and SI_C can all be transmitted through the buffer (BUF). Figure 3 The explanation of the relevant paragraphs will not be repeated here.

[0065] In order to select a target flash memory, the LED controller 600 can output a selection signal through one of the chip selection ports (CS_A or CS_B), output a clock signal through one of the clock ports (CLK_A or CLK_B), and output a command through one of the slave input ports (SI_A, SI_B or SI_C). Therefore, the LED controller 600 can select one of the flash memories FLASH_0 to FLASH_11 according to the selection signal, the clock signal and the command.

[0066] For example, when the LED controller 600 communicates with the flash memories FLASH_0 to FLASH_11 through the serial peripheral interface, according to the specifications of the serial peripheral interface, the LED controller 600 can pull down one of the chip select ports (CS_A or CS_B), output an appropriate clock signal through one of the clock ports (CLK_A or CLK_B), and output a read or write enable instruction through one of the slave input ports (SI_A, SI_B, or SI_C). The flash memory can only operate normally when the corresponding chip select port is pulled down, the corresponding clock port is switched appropriately, and the corresponding slave input port provides a valid instruction (that is, the three conditions are met at the same time). In this way, Fig. 6A , Figure 6B and Figure 7 Under the port connection mode, only one flash memory can operate correctly, that is, through the combination of the selection signal, the clock signal and the instruction, only one flash memory can be selected and accessed by the LED controller 600.

[0067] For example, if the LED controller 600 wants to perform a write operation on the flash memory FLASH_0, it can output the correct control signals through the ports CS_A, CLK_A and SI_A. For example, the chip select port CS_A is pulled low, the clock port CLK_A is switched appropriately, and the slave input port SI_A provides a valid instruction of the serial peripheral interface. In this case, the flash memory FLASH_0 can be enabled by the low chip select signal to decode the received instruction according to the received clock signal, such as Figure 5 The operation shown.

[0068] In other words, by grouping the selection ports, the flash memory FLASH_0 belongs to the group G1_A, which can receive the selection signal from the chip selection port CS_A. By grouping the clock ports, the flash memory FLASH_0 belongs to the group G2_A, which can receive the clock signal from the clock port CLK_A. By grouping the signal ports, the flash memory FLASH_0 belongs to the group G3_A, which can receive the valid instruction from the slave input port SI_A. Since the flash memory FLASH_0 belongs to these groups, the light emitting diode controller 600 can select the flash memory FLASH_0 based on the control signal provided by its control port.

[0069] For the flash memories FLASH_1 / 3 / 5 / 7 / 9 / 11, their corresponding chip select ports CS_B are maintained at a high level. Therefore, regardless of whether the clock signal and the instruction are received correctly, these flash memories cannot operate normally. Figure 8 As shown, although the flash memory FLASH_1 is provided with a correct clock signal and a valid write enable command "06h", it still cannot operate normally to receive the command because its chip select signal (CS signal) is maintained at a high level.

[0070] For the flash memories FLASH_2 / 3 / 6 / 7 / 10 / 11, their corresponding clock ports CLK_B are not switched, so no matter whether the chip select signal and the command are received correctly, these flash memories cannot operate normally. Fig. 9 As shown in FIG. 1 , although the flash memory FLASH_2 is provided with the correct chip select signal and the valid write enable command “06h”, it still cannot correctly decode the command because it does not receive the clock signal. Fig. 9As shown, the unselected clock port CLK can be maintained at a high level or a low level. As long as the clock port CLK is not switched, the corresponding flash memory cannot operate normally.

[0071] For the flash memories FLASH_4 to FLASH_11, their corresponding slave input ports SI_B and SI_C do not transmit valid commands. Therefore, regardless of whether the chip select signal and the clock signal are correctly received, these flash memories cannot operate normally. Fig.10 As shown, although the flash memory FLASH_4 or FLASH_8 is provided with a correct chip selection signal (CS signal) and a clock signal (CLK signal), it still cannot perform a correct operation because it does not receive a valid instruction.

[0072] like Fig.10 As shown, the unselected slave input port SI can provide a signal "00h", which means that the slave input port SI is maintained at a low level in the instruction bit group. The signal "00h" represents a no operation (NoOperation, NOP) instruction in the serial peripheral interface specification. The flash memory that receives the no operation instruction does not perform any valid operations, such as data reading or writing. In another embodiment, the unselected slave input port SI can provide another signal "FFh", at which time the slave input port SI is maintained at a high level in the instruction bit group. The signal "FFh" is also a no operation instruction (or undefined instruction, such as Fig.11 shown).

[0073] In a similar manner, if the light-emitting diode controller 600 wants to perform a read / write operation on the flash memory FLASH_3, it can output the correct control signal through the ports CS_B, CLK_B and SI_A, wherein the chip select port CS_B is pulled low, the clock port CLK_B is switched appropriately, and the slave input port SI_A provides a valid read or write enable instruction. Other unselected control ports cannot output signals normally, so that other flash memories will not be enabled to perform normal operations. For example, the chip select port CS_A is maintained at a high level, the clock port CLK_A is maintained at a high level or a low level, and the slave input ports SI_B and SI_C provide no operation instructions. In this case, among all the flash memories FLASH_0 to FLASH_11, only the selected flash memory FLASH_3 can operate normally.

[0074] In a similar manner, if the LED controller 600 wants to perform a read / write operation on the flash memory FLASH_6, it can output the correct control signal through the ports CS_A, CLK_B and SI_B, wherein the chip select port CS_A is pulled low, the clock port CLK_B is switched appropriately, and the slave input port SI_B provides a valid read or write enable instruction. Other unselected control ports cannot output signals normally, so that other flash memories will not be enabled to perform normal operations. For example, the chip select port CS_B is maintained at a high level, the clock port CLK_A is maintained at a high level or a low level, and the slave input ports SI_A and SI_C provide no operation instructions. In this case, among all the flash memories FLASH_0 to FLASH_11, only the selected flash memory FLASH_6 can operate normally.

[0075] In a similar manner, if the light-emitting diode controller 600 wants to perform a read / write operation on the flash memory FLASH_10, it can output the correct control signal through the ports CS_A, CLK_B and SI_C, wherein the chip select port CS_A is pulled low, the clock port CLK_B is switched appropriately, and the slave input port SI_C provides a valid read or write enable instruction. Other unselected control ports cannot output signals normally, so that other flash memories will not be enabled to perform normal operations. For example, the chip select port CS_B is maintained at a high level, the clock port CLK_A is maintained at a high level or a low level, and the slave input ports SI_A and SI_B provide no operation instructions. In this case, among all the flash memories FLASH_0 to FLASH_11, only the selected flash memory FLASH_10 can operate normally.

[0076] It is worth noting that the purpose of the present invention is to propose a new operating method for selecting and accessing multiple memories. Those skilled in the art can modify or change accordingly, but are not limited to this. For example, in the above embodiment, the light emitting diode controller is used to control 12 flash memories. In another embodiment, a host device (such as a light emitting diode controller) can be used to control any number of slave devices (such as flash memories), and the number of control ports can be set accordingly. In addition, the operating method of the present invention can be applied to a light emitting diode panel control system, in which a light emitting diode controller is used to control multiple flash memories. In another embodiment, the host device can be any other control device, such as a memory controller, a touch controller, a central processing unit (CPU), a microprocessor, or a microcontroller unit (MCU), but is not limited thereto. Alternatively or additionally, the slave device can be another type of memory, or can be any other controllable device, such as a sensor or a driver chip, but is not limited thereto.

[0077] In an embodiment of the present invention, a target slave device (such as a flash memory) is selected based on the output of a chip select port, a clock port, and a slave input port of a serial peripheral interface. Since the slave device is connected to the host device through different control ports, a combination of a selection signal (through a chip select port), a clock signal (through a clock port), and an instruction (through a slave input port) can be used as a decoder. In other words, a decoding function is built into the combination of a chip select port, a clock port, and a slave input port, so that the host device can output appropriate signals through these control ports to select a target slave device. These control ports can be allocated in any appropriate manner to achieve the selection of the slave device, and the relevant implementation is not limited to the description in the above paragraph.

[0078] For example, in another embodiment, through the serial peripheral interface, a light emitting diode controller can be coupled to 12 flash memories FLASH_0 to FLASH_11 through three chip select ports CS_A, CS_B and CS_C, two clock ports CLK_A and CLK_B, and two slave input ports SI_A and SI_B. The flash memories FLASH_0 to FLASH_11 can be divided into three groups G1_A, G1_B and G1_C, which receive a selection signal from the chip select ports CS_A, CS_B and CS_C respectively. The flash memories FLASH_0 to FLASH_11 can also be divided into two groups G2_A and G2_B, which receive a clock signal from the clock ports CLK_A and CLK_B respectively. The flash memories FLASH_0 to FLASH_11 can also be divided into two groups G3_A and G3_B in different ways to receive a command from the slave input ports SI_A and SI_B respectively. An exemplary implementation of grouping the flash memories FLASH_0 to FLASH_11 is shown in FIG. Fig.12 .

[0079] Specifically, the chip select port CS_A is coupled to the four flash memories FLASH_0 / 1 / 2 / 3 in the group G1_A, the chip select port CS_B is coupled to the four flash memories FLASH_4 / 5 / 6 / 7 in another group G1_B, and the chip select port CS_C is coupled to the four flash memories FLASH_8 / 9 / 10 / 11 in another group G1_C. The clock port CLK_A is coupled to the six flash memories FLASH_0 / 2 / 4 / 6 / 8 / 10 in the group G2_A, and the clock port CLK_B is coupled to the six flash memories FLASH_1 / 3 / 5 / 7 / 9 / 11 in another group G2_B. The slave input port SI_A is coupled to the six flash memories FLASH_0 / 1 / 4 / 5 / 8 / 9 in group G3_A, and the slave input port SI_B is coupled to the six flash memories FLASH_2 / 3 / 6 / 7 / 10 / 11 in another group G3_B. To select a target flash memory, the LED controller can pull down one of the chip select ports (CS_A, CS_B or CS_C), output the correct clock signal through one of the clock ports (CLK_A or CLK_B), and output a valid command through one of the slave input ports (SI_A or SI_B).

[0080] In another embodiment, through a serial peripheral interface, a light emitting diode controller can be coupled to 12 flash memories FLASH_0 to FLASH_11 through two chip select ports CS_A and CS_B, three clock ports CLK_A, CLK_B and CLK_C, and two slave input ports SI_A and SI_B. The flash memories FLASH_0 to FLASH_11 can be divided into two groups G1_A and G1_B, which receive a selection signal from the chip select ports CS_A and CS_B respectively. The flash memories FLASH_0 to FLASH_11 can also be divided into three groups G2_A, G2_B and G2_C, which receive a clock signal from the clock ports CLK_A, CLK_B and CLK_C respectively. The flash memories FLASH_0 to FLASH_11 can also be divided into two groups G3_A and G3_B in different ways to receive a command from the slave input ports SI_A and SI_B respectively. An exemplary implementation of grouping the flash memories FLASH_0 to FLASH_11 is shown in FIG. Fig.13 .

[0081] Specifically, the chip select port CS_A is coupled to the six flash memories FLASH_0 / 1 / 4 / 5 / 8 / 9 in the group G1_A, and the chip select port CS_B is coupled to the six flash memories FLASH_2 / 3 / 6 / 7 / 10 / 11 in another group G1_B. The clock port CLK_A is coupled to the four flash memories FLASH_0 / 1 / 2 / 3 in the group G2_A, the clock port CLK_B is coupled to the four flash memories FLASH_4 / 5 / 6 / 7 in another group G2_B, and the clock port CLK_C is coupled to the four flash memories FLASH_8 / 9 / 10 / 11 in another group G2_C. The slave input port SI_A is coupled to the six flash memories FLASH_0 / 2 / 4 / 6 / 8 / 10 in the group G3_A, and the slave input port SI_B is coupled to the six flash memories FLASH_1 / 3 / 5 / 7 / 9 / 11 in another group G3_B. To select a target flash memory, the LED controller can pull down one of the chip select ports (CS_A or CS_B), output the correct clock signal through one of the clock ports (CLK_A, CLK_B or CLK_C), and output a valid command through one of the slave input ports (SI_A or SI_B).

[0082] The above embodiment uses a serial peripheral interface as an example, wherein the chip select port, the clock port, and the slave input port are used together to realize the selection of the slave device. It should be noted that the application of the serial peripheral interface is only one of many embodiments of the present invention. In another embodiment, another transmission interface having multiple selection ports, multiple clock ports, and / or multiple signal ports may also be used, wherein each slave device may be coupled to one of the selection ports, one of the clock ports, and one of the signal ports. By applying a correct selection signal to one of the selection ports, outputting a correct clock through one of the clock ports, and outputting a valid data or command signal through one of the signal ports, the target slave device can be selected.

[0083] Thus, the operating method of the present invention can be applied to any control system having a host device that can access multiple slave devices through any and suitable transmission interface, which is not limited to the LED controller, flash memory, and / or serial peripheral interface described in this specification. The selection of the slave device can be realized by using the built-in decoding function of the combination of different control ports, thereby reducing the number of ports of the transmission interface.

[0084] The above operations of the host device accessing the slave device can be summarized into an operation flow 1400, such as Fig.14 Operation process 1400 may be implemented in a light emitting diode controller (such as Fig. 6A or Figure 7 The light emitting diode controller 600 in FIG. 1 is used to control a plurality of memories (such as Fig. 6A or Figure 7 The flash memory FLASH_0~FLASH_11 in the Fig.14 As shown, the operation flow 1400 includes the following steps:

[0085] Step 1402: Output a selection signal to a first group of memories among a plurality of memories, but do not output a selection signal to a second group of memories among the plurality of memories that is different from the first group of memories.

[0086] Step 1404: Output a clock signal to a third group of memories among the plurality of memories, but do not output a clock signal to a fourth group of memories among the plurality of memories that is different from the third group of memories.

[0087] Step 1406: Output a command to a fifth memory group among the plurality of memories, but do not output the command to a sixth memory group among the plurality of memories that is different from the fifth memory group. Step 1408: Select one of the plurality of memories according to the selection signal, the clock signal and the command.

[0088] In the operation flow 1400, steps 1402 to 1406 may be executed sequentially or simultaneously. That is, the selection signal, the clock signal, and the instruction may be output in a predetermined order or simultaneously, and the related transmission sequence shall not be regarded as a limitation of the present invention. Based on the grouping and output of the control signal, the target memory may be selected. The detailed implementation and operation of the operation flow 1400 may be referred to the description in the above paragraphs, which will not be repeated here.

[0089] In summary, the present invention proposes a novel operation method for accessing multiple memories, which may be flash memories included in an LED display, wherein each flash memory may be configured with an LED light board to record compensation data for the corresponding light board. The LED display may also include an LED controller for selecting to access the flash memory to read out the compensation data stored in the flash memory or write data into the flash memory. The LED controller may be coupled to the flash memory through multiple control ports, which include a chip selection port, a clock port, and a slave input port, respectively used to transmit a selection signal, a clock signal, and an instruction. The flash memory may be grouped in different ways, so that each flash memory may be coupled to the LED controller through one of the chip selection ports, one of the clock ports, and one of the slave input ports. To select a target flash memory, the LED controller may output a selection signal through one of the chip selection ports, output a clock signal through one of the clock ports, and output an instruction through one of the slave input ports. The combination of the selection signal, the clock signal, and the instruction may serve as a decoder, so that the LED controller may access the selected flash memory according to these control signals.

[0090] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for operating multiple memories, characterized in that: include: Outputting a selection signal to a first group of memories among the plurality of memories, but not outputting the selection signal to a second group of memories among the plurality of memories that is different from the first group of memories; Output a clock signal to a third group of memories among the plurality of memories, but do not output the clock signal to a fourth group of memories among the plurality of memories that is different from the third group of memories; output a command to a fifth group of memories among the plurality of memories, but do not output the command to a sixth group of memories among the plurality of memories that is different from the fifth group of memories; as well as One of the memories is selected according to the selection signal, the clock signal and the instruction.

2. The operating method according to claim 1, characterized in that: The step of selecting one of the plurality of memories according to the selection signal, the clock signal and the instruction comprises: According to a combination of the selection signal, the clock signal and the command, one of the plurality of memories is selected for access.

3. The operating method according to claim 1, characterized in that: The step of selecting one of the plurality of memories according to the selection signal, the clock signal and the instruction comprises: When a first memory among the plurality of memories belongs to the first group, the third group, and the fifth group, the first memory is selected.

4. The operating method according to claim 1, characterized in that: The selection signal is output to the first group of memories through a first buffer, the clock signal is output to the third group of memories through a second buffer, and the instruction is output to the fifth group of memories through a third buffer.

5. The operating method according to claim 1, characterized in that: Each memory in the plurality of memories belongs to at least one different group from another memory in the plurality of memories.

6. The operating method according to claim 1, characterized in that: The multiple memories are divided into first multiple groups including the first group and the second group in a first manner, divided into second multiple groups including the third group and the fourth group in a second manner different from the first manner, and divided into third multiple groups including the fifth group and the sixth group in a third manner different from the first manner and the second manner.

7. The operating method according to claim 1, characterized in that: The multiple memories are controlled by a serial peripheral interface, and the selection signal, the clock signal and the instruction are transmitted through the serial peripheral interface.

8. The operating method according to claim 1, characterized in that: The multiple memories are flash memories respectively arranged on multiple lamp boards of a light emitting diode display.

9. A controller for controlling a plurality of memories, characterized in that: The controller includes: A plurality of selection ports, used to be respectively coupled to the first plurality of memory groups in the plurality of memories; A plurality of clock ports, respectively coupled to a second plurality of memory groups in the plurality of memories; and A plurality of signal ports, respectively coupled to a third plurality of memory groups in the plurality of memories; The controller outputs a selection signal through one of the plurality of selection ports, outputs a clock signal through one of the plurality of clock ports, and outputs a command through one of the plurality of signal ports; The controller selects one of the multiple memories according to the selection signal, the clock signal and the instruction.

10. The controller according to claim 9, characterized in that The controller is arranged on a control board of a light emitting diode display, and the multiple memories are flash memories respectively arranged on multiple lamp boards of the light emitting diode display.

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