Memory controller, storage device and host-storage system

Abstract

A memory controller, a memory device, and a host-memory system are provided. The memory controller includes a cache manager configured to receive a logical block address (LBA) from a host and separate the LBA into a plurality of logical page numbers (LPNs), the plurality of LPNs including at least a first LPN and a second LPN, a physical striper configured to output a first signal, and a second signal configured to output a second signal. The first signal corresponds the first LPN to a first page of the non-volatile memory device and the second LPN to a second page of the non-volatile memory device, where the second page is different from the first page, and a logic writer configured to receive the first LPN and the second LPN from the cache manager, receive the first signal from the physical stripe device, and receive the second signal from the physical stripe device. And store data to the non-volatile memory device by performing a write operation based on the first signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0172967 filed in the Korean Intellectual Property Office on December 4, 2023, and all benefits arising therefrom, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a memory controller, a storage device, and a host-storage system. Background Art

[0004] Semiconductor memory devices are memory devices implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), etc. Semiconductor memory devices are mainly classified into volatile memory devices and nonvolatile memory devices.

[0005] A volatile memory device is a memory device in which the stored data is not maintained (e.g., erased) when the power is interrupted. Examples of volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM). A non-volatile memory device is a memory device that retains the stored data even when the power is interrupted. Examples of non-volatile memory devices include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory devices, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FeRAM or FRAM). Compared to volatile memory devices, read and write operations of non-volatile memory devices are generally slower.

[0006] Meanwhile, if the time required to read data stored in a nonvolatile memory device is uneven, the read performance of the corresponding nonvolatile memory device may be poorly evaluated, resulting in reduced reliability in terms of the read performance of the nonvolatile memory device. Summary of the invention

[0007] Aspects of the present disclosure provide a memory controller that enhances data read performance of a memory device.

[0008] Aspects of the present disclosure also provide a storage device having improved reliability in data reading performance.

[0009] Aspects of the present disclosure also provide a host-storage system including a storage device having improved reliability in data reading performance.

[0010] However, aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0011] According to aspects of the present disclosure, there is provided a memory controller including: a cache manager configured to receive a logical block address (LBA) from a host and separate the LBA into a plurality of logical page numbers (LPNs), the plurality of LPNs including at least a first LPN and a second LPN; a physical striper configured to output a first signal, the first signal corresponding the first LPN to a first page of a nonvolatile memory device and the second LPN to a second page of the nonvolatile memory device, wherein the second page is different from the first page; and a logical writer configured to receive the first LPN and the second LPN from the cache manager, receive the first signal from the physical striper, and store data to the nonvolatile memory device by performing a write operation based on the first signal, wherein the write operation includes a first write operation for first data at a first address of the nonvolatile memory device corresponding to the first LPN, and then a second write operation for second data at a second address of the nonvolatile memory device corresponding to the second LPN, and wherein the data is stored such that a read operation of the host includes a first read operation for the first data stored at the first address, and then a second read operation for the second data stored at the second address.

[0012] According to an aspect of the present disclosure, a storage device is provided, the storage device comprising a nonvolatile memory device and a memory controller, the nonvolatile memory device comprising a memory cell array, the memory controller being configured to receive a write request signal and data from a host and control the nonvolatile memory device to write the received data into the memory cell array, wherein the nonvolatile memory device comprises a first page to a third page, the memory controller comprising a cache manager, the cache manager being configured to receive a logical block address (LBA) from the host and separate the LBA into a plurality of logical page numbers (LPNs), the plurality of LPNs comprising at least a first LP N to sixth LPNs, a physical striper configured to perform a grouping operation so that a first group including first to third LPNs and a second group including fourth to sixth LPNs are generated, the first to third LPNs respectively corresponding to the first page to the third page and the fourth to sixth LPNs respectively corresponding to the first page to the third page, and a logical writer configured to receive the LPNs from the cache manager and sequentially write first to sixth data corresponding to the first to sixth LPNs, respectively, among the received data to a nonvolatile memory device by performing a write operation based on the grouping operation.

[0013] According to one aspect of the present disclosure, a host-storage system is provided, the host-storage system comprising: a host configured to send a write request signal, data and a logical block address (LBA); a non-volatile memory device comprising a memory cell array and a plurality of word lines connected to the memory cell array; and a memory controller configured to receive the write request signal, the data and the LBA and control a write operation to write the data to a memory cell corresponding to the LBA of the non-volatile memory device, wherein the memory controller comprises: a cache manager configured to separate the LBA into logical page numbers (LPNs), a logical writer, and a logical page number (LPN). A logical writer is configured to receive one or more LPNs and generate a program unit by collecting the LPNs page by page, and a physical striper configured to group some of the LPNs into a first LPN group and group some of the remaining portion of the LPNs into a second LPN group, such that the first LPN group corresponds to a first page and the second LPN group corresponds to a second page different from the first page, and wherein, when a write operation to the nonvolatile memory device is performed based on the program unit, the logical writer is configured to initiate the write operation for the first page and then initiate the write operation for the first page before completing the write operation for the first page.

[0014] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be clear from the following description.

[0015] Specific details of other embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and other aspects and features of the present disclosure will become more apparent by describing in detail example embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0017] Figure 1 is a schematic diagram of a host-storage system according to some embodiments of the inventive concept.

[0018] Figure 2 yes Figure 1 Schematic diagram of the memory controller.

[0019] Figure 3 yes Figure 1 Schematic diagram of a non-volatile memory device.

[0020] Figure 4 yes Figure 1 Schematic diagram of a memory controller and non-volatile memory devices.

[0021] Figure 5 yes Figure 1 and Figure 2 Schematic diagram of a memory controller, memory interface, and non-volatile memory devices.

[0022] Figure 6 is a schematic diagram of a memory cell array according to some embodiments of the inventive concept.

[0023] Figure 7 is a schematic diagram for explaining a sequential write operation for a nonvolatile memory device according to some embodiments of the inventive concept.

[0024] Figure 8 and Fig. 9 is a schematic diagram for explaining a mapping table showing a correspondence between a logical address and a physical address in a nonvolatile memory device according to some embodiments of the inventive concept during a write operation.

[0025] Fig.10 is a schematic diagram for explaining threshold voltage distributions of different numbers of bits that can be stored in a memory cell of a nonvolatile memory device according to some embodiments of the inventive concept.

[0026] Fig.11 It is used to explain Figure 2 Schematic diagram of the memory controller.

[0027] Fig.12 It is used to explain Fig.11 An example flow chart of a write operation of a memory controller.

[0028] Figures 13 to 16 is used to explain Fig.11 The program unit generated by the logic writer and by Fig.11 Schematic diagram of the grouping operations performed by the physical striper.

[0029] Fig.17 and Fig.18 is a schematic diagram for explaining how to write data to a nonvolatile memory device in the HSP scheme.

[0030] Fig.19 and Fig. 20 is a schematic diagram for explaining groups generated by a grouping operation performed by a physical striper according to some embodiments of the inventive concept.

[0031] Figure 21 to Figure 24 is a schematic diagram for explaining how to write data in a memory device in a 2-8 HSP scheme according to some embodiments of the inventive concept.

[0032] Fig.25is a schematic diagram for explaining a system to which a storage device according to some embodiments of the inventive concept is applied. DETAILED DESCRIPTION

[0033] A memory controller, a memory device, and a host-memory system according to some embodiments of the present disclosure will be described below with reference to the accompanying drawings.

[0034] In the present disclosure, any of the disclosed elements and / or function blocks (including those elements and / or function blocks containing "unit", "... device (er) / ... device (or)", "logic", etc.) can be used to represent a unit having at least one function or operation and implemented by a processing circuit including hardware, software, or a combination of hardware and software. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuit may include an electrical component such as at least one of a transistor, a resistor, a capacitor, etc. and / or an electronic circuit including the component. In addition, the line connections or connecting members between the elements depicted in the drawings represent functional connections and / or physical or circuit connections by way of example, and in actual applications, they may be replaced or embodied as various additional functional connections, physical connections, or circuit connections.

[0035] Figure 1 is a schematic diagram of a host-storage system according to some embodiments of the inventive concept.

[0036] refer to Figure 1 , the host-storage system 1 may include a host 100 and a storage device 10. The host 100 and the storage device 10 may be configured to communicate via an electrical (and / or similar) connection. For example, the host 100 and the storage device 10 may be electrically connected. The host 100 may provide a logical block address (LBA) “LBA” and a request signal REQ to the storage device 10, and the host 100 and the storage device 10 may exchange data DATA based on the signal received from the host 100. For example, the host 100 may be connected to and / or communicate with a memory controller 200.

[0037] The host 100 may include, for example, a personal computer (PC), a laptop computer, a mobile phone, a smart phone, a tablet PC, a server, etc. The host 100 may include a host controller 110 and a host memory 120 .

[0038] The host controller 110 may be configured to manage operations such as storing data from the host memory 120 (eg, write data) in the nonvolatile memory device 300 and / or storing data from the nonvolatile memory device 300 (eg, read data) in the host memory 120 .

[0039] The host memory 120 may be configured to function as a buffer memory for temporarily storing data DATA to be transmitted to the storage device 10 or data DATA received from the storage device 10 .

[0040] In some embodiments, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in other embodiments, the host controller 110 and the host memory 120 may be integrated on the same semiconductor chip. For example, the host controller 110 may be one of a plurality of modules provided in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 120 may be an embedded memory within the application processor or a volatile memory or memory module placed outside the application processor.

[0041] The storage device 10 may include a memory controller 200 and a non-volatile memory device 300. The storage device 10 may be integrated into a single semiconductor device. For example, the storage device 10 may include an embedded universal flash storage (UFS) memory device, an embedded multimedia card (eMMC), a solid state drive (SSD), etc. In addition, for example, the storage device 10 may include a removable UFS memory card, a compact flash (CF) card, a secure digital (SD) card, a micro SD card, a mini SD card, an extreme end digital (eXtreme Digital, xD) card, and / or a memory stick. If the storage device 10 can comply with the Non-Volatile Memory express (NVMe) standard, for example, when the storage device 10 is an SSD.

[0042] The nonvolatile memory device 300 may include a NAND flash memory, but the present disclosure is not limited thereto. The nonvolatile memory device 300 may also include a NOR flash memory and / or a resistive memory such as PRAM, MRAM, FeRAM, and / or RRAM.

[0043] The memory controller 200 is connected to the nonvolatile memory device 300 and may be configured to control the nonvolatile memory device 300. For example, the memory controller 200 may provide an address ADDR, a command CMD, and a control signal CTRL to the nonvolatile memory device 300 in response to an LBA “LBA” and a request signal REQ received from the host 100. In other words, the memory controller 200 may provide a signal to the nonvolatile memory device 300, and thereby may control data to be written to and / or read from the nonvolatile memory device 300. In addition, the memory controller 200 and the nonvolatile memory device 300 may exchange data DATA.

[0044] Figure 2 yes Figure 1 Schematic diagram of a memory controller 200 .

[0045] refer to Figure 2 , the memory controller 200 may include a processor 210, a host interface 220, a memory interface 230, a flash translation layer (FTL) 240, a write buffer 250, a cache controller 260, a logical writer 270, and a physical striper 280. The memory controller 200 may further include Figure 2 Other components than those depicted in .

[0046] The processor 210 may include a central processing unit (CPU), a controller, an application specific integrated circuit (ASIC), etc. The processor 210 may be configured to control the overall operation of the memory controller 200. The processor 210 may execute firmware loaded into the FTL 240 to control the memory controller 200.

[0047] The host interface 220 may be configured to Figure 1 The host 100 sends and receives packets. The packets sent from the host 100 to the host interface 220 may include the packets to be written to Figure 1 The packet transmitted from the host interface 220 to the host 100 may include a response to a command or data read from the nonvolatile memory device 300.

[0048] The memory interface 230 may be configured to send data to be written to the nonvolatile memory device 300 and / or receive data read from the nonvolatile memory device 300. The memory interface 230 may be implemented to comply with standard protocols such as Toggle and / or Open NAND Flash Interface (ONFI).

[0049] The FTL 240 may be configured to include system software that manages write, read, and erase operations of the nonvolatile memory device 300. For example, the FTL 240 may include firmware. The firmware in the FTL 240 may be executed by the processor 210. The FTL 240 may include software and / or hardware.

[0050] The FTL 240 may be configured to perform various functions, such as address mapping, wear-leveling, garbage collection, etc. Address mapping is a process involving converting a logical address (such as a Figure 1 The LBA (“LBA”) or logical page number (LPN) is converted into a physical address for the operation of actually storing data within the non-volatile memory device 300.

[0051] Wear leveling is a technique that aims to prevent (and / or reduce) excessive wear of specific blocks within the nonvolatile memory device 300 by ensuring uniform use of blocks in the nonvolatile memory device 300, and may be implemented, for example, by firmware techniques that balance erase counts of physical blocks. Garbage collection is a technique for reclaiming available capacity within the nonvolatile memory device 300 by copying valid data from existing blocks to new blocks and then erasing the existing blocks.

[0052] The write buffer 250 may be configured to store code data required for the initial startup of the storage device 10. The write buffer 250 may buffer the LBA "LBA", the request signal REQ, the data DATA, and the command received from the host 100. The signal buffered in the write buffer 250 may be sent to the non-volatile memory device 300 through the memory interface 230, and then may be utilized. For example, the data DATA buffered in the write buffer 250 may be programmed into the non-volatile memory device 300. In other words, the write buffer 250 may be a volatile memory device for temporarily storing the data DATA. In addition, the write buffer 250 may also be a cache memory.

[0053] The cache controller 260 may be configured to control the write buffer 250. The cache controller 260 may regulate the overall operation of the write buffer 250 and control the cache operation for the data DATA to be written to the non-volatile memory device 300. The cache controller 260 may include a cache manager 261. The cache manager 261 may be configured to manage the cache operation of the write buffer 250. For example, the cache manager 261 may control the data to be stored in the write buffer 250. In addition, the cache manager 261 may receive an LBA "LBA" from the host 100 and divide the received LBA "LBA" into one or more LPNs. In other words, the cache manager 261 may classify (or separate) the received LBA "LBA" into a plurality of LPNs. This will be referred to later. Figure 8 and Fig. 9 The relationship between the LPN and the LBA "LBA" generated by the cache manager 261 is described in detail.

[0054] The logical writer 270 may be configured to receive an LPN from the cache manager 261 and collect the received LPNs to create a program unit for performing a write operation on the nonvolatile memory device 300. For example, if one LPN is 4K and one program unit is 16K, the logical writer 270 may collect 4 LPNs to create one program unit. The logical writer 270 may then perform a write operation on the nonvolatile memory device 300 based on the generated program unit. The program unit may consist of a collection of multiple pages within the nonvolatile memory device 300. The logical writer 270 may be configured to perform a write operation on the nonvolatile memory device 300 on a program unit-by-program unit basis.

[0055] The physical striper 280 is configured to send a signal to the non-volatile memory device 300 in response to a signal received from the logical writer 270. The signal sent by the physical striper 280 may contain information about the correspondence between the received LPNs and the pages within the non-volatile memory device 300. Considering the read mode of the host 100 for the non-volatile memory device 300, the physical striper 280 may correspond each LPN to one of the pages within the non-volatile memory device 300. The logical writer 270 may create a program unit based on the signal received from the physical striper 280. This will be referred to later. Fig.12 The operations of logical writer 270 and physical striper 280 are described in detail.

[0056] Figure 3 yes Figure 1 Schematic diagram of a non-volatile memory device.

[0057] refer to Figure 3 The nonvolatile memory device 300 may include a control logic circuit 320, a memory cell array 330, a page buffer unit 340, a voltage generator 350, and a row decoder 360. The nonvolatile memory device 300 may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc. In at least one embodiment, the nonvolatile memory device 300 may also include Figure 2 A memory interface 230 is provided.

[0058] The control logic circuit 320 may be configured to generally control various operations within the nonvolatile memory device 300. The control logic circuit 320 may output various control signals, for example, in response to a command CMD and / or an address ADDR from the memory interface 230. For example, the control logic circuit 320 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR corresponding to the command CMD and / or the address ADDR. The voltage control signal CTRL_vol may include a program signal or an erase signal.

[0059] The memory cell array 330 may include a plurality of memory blocks BLK1 to BLKz (where z is a positive integer), and each of the memory blocks BLK1 to BLKz may include a plurality of memory cells. The memory cell array 330 may be connected to the page buffer unit 340 through the bit lines BL, and may also be connected to the row decoder 360 through the word lines WL, the string selection lines SSL, and the ground selection lines GSL.

[0060] In at least one example embodiment, the memory cell array 330 may include a three-dimensional (3D) memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each of the NAND strings may include a memory cell connected to a corresponding word line WL vertically stacked on a substrate. In other example embodiments, the memory cell array 330 may include a two-dimensional (2D) memory cell array, and the 2D memory cell array may include a plurality of NAND strings arranged in rows and columns.

[0061] The page buffer unit 340 may include a plurality of page buffers PB1 to PBn (where n is an integer greater than or equal to 3), and each of the page buffers PB1 to PBn may be connected to the memory cell through a bit line BL. The page buffer PB1 will be described below as an example, and its description may be directly applicable to other page buffers PB2 to PBn.

[0062] The page buffer PB1 may be configured to select one of the bit lines BL in response to the column address Y-ADDR. Depending on the operation mode, the page buffer PB1 may operate as a write driver or a sense amplifier. For example, during a programming operation, the page buffer PB1 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line BL, and during a read operation, the page buffer PB1 may sense the current or voltage of the selected bit line BL to detect the data stored in the corresponding memory cell.

[0063] The voltage generator 350 may be configured to generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol from the control logic circuit 320. For example, the voltage generator 350 may generate a program voltage, a read voltage, a program verification voltage, and an erase voltage as the word line voltage VWL.

[0064] The row decoder 360 may be configured to select one of the word lines WL and one of the string selection lines SSL in response to the row address X-ADDR. For example, during a program operation, the row decoder 360 may apply a program voltage and a program verification voltage to the selected word line WL, and during a read operation, the row decoder 360 may apply a read voltage to the selected word line WL.

[0065] The control logic circuit 320 may be connected to the voltage generator 350, the row decoder 360, and the page buffer unit 340. The control logic circuit 320 may be configured to control the operation of the nonvolatile memory device 300. For example, the control logic circuit 320 may be responsive to a signal from a Figure 1 The memory controller 200 operates based on a control signal CTRL and a command CMD (eg, a write command and a read command) provided by the memory controller 200.

[0066] Figure 4 yes Figure 1 Schematic diagram of a memory controller and non-volatile memory devices.

[0067] refer to Figure 4 , the storage device 10 may include a memory controller 200 and a nonvolatile memory device 300. The storage device 10 may support a plurality of first to m-th channels CH1 to CHm, and the memory controller 200 and the nonvolatile memory device 300 may be connected through the first to m-th channels CH1 to CHm. For example, the storage device 10 may be implemented as a storage device such as an SSD.

[0068] The nonvolatile memory device 300 may include a plurality of nonvolatile memories NVM11 to NVMmn. Each of the nonvolatile memories NVM11 to NVMmn may be connected to one of the first channel CH1 to the mth channel CHm in a corresponding manner. For example, the nonvolatile memories NVM11 to NVM1n may be connected to the first channel CH1 through the paths W11 to W1n, and the nonvolatile memories NVM21 to NVM2n may be connected to the second channel CH2 through the paths W21 to W2n. In at least one example embodiment, each of the nonvolatile memories NVM11 to NVMmn may be implemented as a memory cell configured to operate in response to a separate command from the memory controller 200. For example, each of the nonvolatile memories NVM11 to NVMmn may be implemented as a chip or die, but the present disclosure is not limited thereto. In at least one embodiment, each of the nonvolatile memories NVM11 to NVMmn may include a memory cell array ( Figure 3 and / or Figure 6 of “330”).

[0069] The memory controller 200 may be configured to transmit signals to and / or receive signals from the nonvolatile memory device 300 through the first to m-th channels CH1 to CHm. For example, the memory controller 200 may transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the nonvolatile memory device 300 through the first to m-th channels CH1 to CHm, or receive data DATAa to DATAm from the nonvolatile memory device 300 through the first to m-th channels CH1 to CHm.

[0070] The memory controller 200 may be configured to select one of the nonvolatile memories NVM11 to NVMmn and transmit and receive signals to and from the selected nonvolatile memory device through the corresponding channel. For example, the memory controller 200 may select the nonvolatile memory NVM11 connected to the first channel CH1 and may transmit a command CMDa, an address ADDRa, and data DATAa to the nonvolatile memory NVM11 through the first channel CH1 or receive data DATAa from the nonvolatile memory NVM11 through the first channel CH1.

[0071] The memory controller 200 may be configured to send signals to and / or receive signals from the nonvolatile memory device 300 in parallel through different channels. For example, while sending a command CMDa to the nonvolatile memory device 300 through the first channel CH1, the memory controller 200 may simultaneously send a command CMDb to the nonvolatile memory device 300 through the second channel CH2. Similarly, for example, while receiving data DATAa from the nonvolatile memory device 300 through the first channel CH1, the memory controller 200 may receive data DATAb from the nonvolatile memory device 300 through the second channel CH2.

[0072] The memory controller 200 may be configured to control the overall operation of the nonvolatile memory device 300. The memory controller 200 may control each of the nonvolatile memories NVM11 to NVMmn connected to the first to m-th channels CH1 to CHm by transmitting signals to the first to m-th channels CH1 to CHm. For example, the memory controller 200 may transmit a command CMDa and an address ADDRa through the first channel CH1, and thereby may control one selected from the nonvolatile memory devices NVM11 to NVM1n.

[0073] Each of the nonvolatile memories NVM11 to NVMmn may be configured to operate under the control of the memory controller 200. For example, the nonvolatile memory NVM11 may program data DATAa based on a command CMDa, an address ADDRa, and data DATAa provided through the first channel CH1. Similarly, for example, the nonvolatile memory NVM21 may be configured to read data DATAb from the second channel CH2 based on a command CMDb and an address ADDRa, and may transmit the read data DATAb to the memory controller 200.

[0074] Therefore, since the memory controller 200 and the nonvolatile memory device 300 can transmit and receive data DATAa to DATAm in parallel through the first channel CH1 to the m-th channel CHm, the read performance of the nonvolatile memory device 300 by the host 100 can be enhanced. For example, the memory controller 200 can use the channel resources simultaneously by performing operations such as receiving data DATAa from the nonvolatile memories NVM11 to NVM1n through the first channel CH1, receiving data DATAb from the nonvolatile memories NVM21 to NVM2n through the second channel CH2, and receiving data DATAm from the nonvolatile memories NVM1m to NVMmn through the m-th channel CHm in parallel. Therefore, compared with the case where the host 100 performs a read operation using only a subset of the channel resources, the read performance of the data stored in the nonvolatile memory device 300 by the host 100 can be improved.

[0075] Figure 4 The nonvolatile memory device 300 is shown to communicate with the memory controller 200 through m channels and includes n nonvolatile memories for each of the m channels, but the number of channels and the number of nonvolatile memories connected to each channel may vary.

[0076] Figure 5 yes Figure 1 and Figure 2 Schematic diagram of a memory controller, memory interface, and non-volatile memory devices.

[0077] The nonvolatile memory device 300 may include first to eighth pins P11 to P18 , a memory interface 230 b , a control logic circuit 320 , and a memory cell array 330 .

[0078] The memory interface 230b may receive a chip enable signal nCE from the memory controller 200 through the first pin P11. The memory interface 230b may be configured to send and receive signals to and from the memory controller 200 through the second pin P12 to the eighth pin P18 in response to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (or has a high level), the memory interface 230b may send and receive signals to and from the memory controller 200 through the second pin P12 to the eighth pin P18.

[0079] The memory interface 230b can receive a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal nWE from the memory controller 200 through the second pin P12 to the fourth pin P14. The memory interface 230b can also receive a data signal DQ from the memory controller 200 through the seventh pin P17, or send a data signal DQ to the memory controller 200 through the seventh pin P17. The command CMD, the address ADDR, and the data DATA can be sent through the data signal DQ. For example, the data signal DQ can be sent through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the data signal lines.

[0080] The memory interface 230b can obtain the command CMD for the command latch enable signal CLE from the data signal DQ received during the enable period (or high level period) of the command latch enable signal CLE based on the switching timing of the write enable signal nWE. Similarly, the memory interface 230b can obtain the address ADDR from the data signal DQ received during the enable period (e.g., high level period) of the address latch enable signal ALE based on the switching timing of the write enable signal nWE.

[0081] In some embodiments, the write enable signal nWE may maintain a static state (e.g., a high level or a low level) and then may switch between a high level and a low level. For example, the write enable signal nWE may switch during the transmission of the command CMD or the address ADDR. Therefore, the memory interface 230b may acquire the command CMD or the address ADDR based on the switching timing of the write enable signal nWE.

[0082] The memory interface 230b may receive a read enable signal nRE from the memory controller 200 through a fifth pin P15. The memory interface 230b may receive a data strobe signal DQS from the memory controller 200 and / or transmit the data strobe signal DQS to the memory controller 200 through a sixth pin P16.

[0083] During the data output operation of the nonvolatile memory device 300, the memory interface 230b may receive a switching read enable signal nRE from the nonvolatile memory device 300 through the fifth pin P15 before outputting the data DATA. The memory interface 230b may be configured to generate a switching data strobe signal DQS based on the switching of the read enable signal nRE. For example, the memory interface 230b may generate a data strobe signal DQS that starts switching after a predetermined delay (e.g., "tDQSRE") after the switching of the read enable signal nRE begins. The memory interface 230b may send a data signal DQ including data DATA based on the switching timing of the data strobe signal DQS. Therefore, the data DATA may be sent to the memory controller 200 aligned with the switching timing of the data strobe signal DQS.

[0084] During the data input operation of the nonvolatile memory device 300, when the data signal DQ including the data DATA is received from the memory controller 200, the memory interface 230b may receive the switching data strobe signal DQS and the data DATA from the memory controller 200. The memory interface 230b may acquire the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS. For example, the memory interface 230b may acquire the data DATA by sampling the data signal DQ at the rising edge and the falling edge of the data strobe signal DQS.

[0085] The memory interface 230b may be configured to send a ready / busy output signal nR / B to the memory controller 200 through the eighth pin P18. For example, the memory interface 230b may send the state information of the nonvolatile memory device 300 to the memory controller 200 through the ready / busy output signal nR / B. When the nonvolatile memory device 300 is in a busy state (e.g., when the internal operation of the nonvolatile memory device 300 is in progress), the memory interface 230b may send the ready / busy output signal nR / B indicating the busy state to the memory controller 200. When the nonvolatile memory device 300 is in a ready state (e.g., when the internal operation of the nonvolatile memory device 300 is not in progress or has been completed), the memory interface 230b may send the ready / busy output signal nR / B indicating the ready state to the memory controller 200.

[0086] For example, the memory interface 230b may be configured to send a ready / busy output signal nR / B indicating a busy state (e.g., a low level state) to the memory controller 200 when the nonvolatile memory device 300 reads data DATA from the memory cell array in response to a page read command. For example, when the nonvolatile memory device 300 programs data DATA to the memory cell array 330 in response to a program command, the memory interface 230b may send a ready / busy output signal nR / B indicating a busy state to the memory controller 200.

[0087] The control logic circuit 320 may be configured to generally control various operations of the nonvolatile memory device 300. The control logic circuit 320 may receive a command / address (CMD / ADDR) obtained from the memory interface 230 b. The control logic circuit 320 may generate a control signal in response to the received command / address CMD / ADDR to control other components of the nonvolatile memory device 300. For example, the control logic circuit 320 may be configured to generate various control signals to program data DATA into the memory cell array 330 or read data DATA from the memory cell array 330.

[0088] The memory cell array 330 may be configured to store data DATA acquired from the memory interface 230b under the control of the control logic circuit 320. The memory cell array 330 may also output the stored data DATA to the memory interface 230b under the control of the control logic circuit 320.

[0089] The memory cell array 330 may include a plurality of memory cells. For example, the memory cell may be a flash memory cell, but the present disclosure is not limited thereto. Alternatively, the memory cell may be an RRAM cell, a FRAM cell, a PRAM cell, a thyristor random-access memory (TRAM) cell, or an MRAM cell. For convenience, the memory cell is described below as a NAND flash memory cell.

[0090] The memory controller 200 may include first to eighth pins P21 to P28 and a controller interface 230 a . The first to eighth pins P21 to P28 may correspond to first to eighth pins P11 to P18 of the nonvolatile memory device 300 .

[0091] The controller interface 230a may be configured to transmit a chip enable signal nCE to the nonvolatile memory device 300 through the first pin P21. The controller interface 230a may transmit and receive signals to and from the nonvolatile memory device 300 selected by the chip enable signal nCE through the second to eighth pins P22 to P28.

[0092] The controller interface 230a can be configured to: send the command latch enable signal CLE, the address latch enable signal ALE and the write enable signal nWE to the non-volatile memory device 300 through the second pin P22 to the fourth pin P24; and / or the controller interface 230a can send the data signal DQ to the non-volatile memory device 300 and / or receive the data signal DQ from the non-volatile memory device 300 through the seventh pin P27.

[0093] The controller interface 230a may be configured to transmit the data signal DQ including the command CMD or the address ADDR together with the toggle write enable signal nWE to the nonvolatile memory device 300. The controller interface 230a may transmit the data signal DQ including the command CMD to the nonvolatile memory device 300 by transmitting the enabled command latch enable signal CLE. Similarly, the controller interface 230a may transmit the data signal DQ including the address ADDR to the nonvolatile memory device 300 by transmitting the enabled address latch enable signal ALE.

[0094] The controller interface 230a may be configured to send a read enable signal nRE to the nonvolatile memory device 300 through a fifth pin P25. The controller interface 230a may also receive and / or send a data strobe signal DQS from and / or to the nonvolatile memory device 300 through a sixth pin P26.

[0095] During the data output operation of the nonvolatile memory device 300, the controller interface 230a may be configured to generate a read enable signal nRE that initiates switching and send the switching read enable signal nRE to the nonvolatile memory device 300. For example, the controller interface 230a may generate a switching read enable signal nRE that changes from a fixed state (e.g., a high level state or a low level state) to a switching state before outputting the data DATA. Therefore, a data strobe signal DQS that is switched based on the switching read enable signal nRE is generated in the nonvolatile memory device 300. The controller interface 230a may receive a data signal DQ including data DATA and the switched data strobe signal DQS from the nonvolatile memory device 300. The controller interface 230a may obtain data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0096] During the data input operation of the nonvolatile memory device 300, the controller interface 230a may generate a switched data strobe signal DQS. For example, the controller interface 230a may generate a data strobe signal DQS that changes from a fixed state (e.g., a high level state or a low level state) to a switched state before transmission of the data DATA. The controller interface 230a may transmit a data signal DQ including data DATA to the nonvolatile memory device 300 based on the switching timing of the data strobe signal DQS.

[0097] The controller interface 230a may receive the ready / busy output signal nR / B from the nonvolatile memory device 300 through the eighth pin P28. The controller interface 230a may determine the state of the nonvolatile memory device 300 based on the ready / busy output signal nR / B.

[0098] Figure 6 is a schematic diagram of a memory cell array according to some embodiments.

[0099] refer to Figure 6 , a plurality of cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may be arranged on a substrate in a first direction x and a second direction y. Cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may extend in a third direction z. Cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may be commonly connected to a common source line CSL formed on or in the substrate. Figure 6 It is shown that the common source line CSL is connected to the lowest part of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23 and NS33 in the third direction z. However, it is sufficient that the common source line CSL is electrically connected only to the lowest part of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23 and NS33 in the third direction z, and the common source line CSL may not necessarily be located at the bottom of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23 and NS33. In addition, Figure 6 The cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 arranged in a 3×3 array are shown, but the arrangement and number of cell strings provided in the memory cell array 330 are not particularly limited.

[0100] Cell strings NS11, NS12, and NS13 may be connected to a first ground selection line GSL1. Cell strings NS21, NS22, and NS23 may be connected to a second ground selection line GSL2. Cell strings NS31, NS32, and NS33 may be connected to a third ground selection line GSL3.

[0101] In addition, cell strings NS11, NS12, and NS13 may be connected to a first string selection line SSL1. Cell strings NS21, NS22, and NS23 may be connected to a second string selection line SSL2. Cell strings NS31, NS32, and NS33 may be connected to a third string selection line SSL3.

[0102] Each of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may include a string selection transistor SST connected to a corresponding string selection line. Each of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may also include a ground selection transistor GST connected to a corresponding ground selection line.

[0103] Each of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may be connected to a corresponding ground selection transistor once. In addition, a plurality of memory cells may be sequentially stacked in a third direction z between the ground selection transistor and the string selection transistor of each of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33. Although not specifically described, a dummy cell may also be included between the ground selection transistor and the string selection transistor of each of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33. In addition, the number of string selection transistors included in each of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 is not particularly limited.

[0104] For example, the cell string NS11 may include a ground selection transistor GST11, a plurality of memory cells M11_1 to M11_8, and a string selection transistor SST11, the ground selection transistor GST11 is located at the lowest part of the cell string NS11 in the third direction z, the plurality of memory cells M11_1 to M11_8 are sequentially stacked on top of the ground selection transistor GST11 in the third direction z, and the string selection transistor SST11 is stacked on top of the memory cell M11_8 in the third direction z. Similarly, the cell string NS21 may include a ground selection transistor GST21 and a plurality of memory cells M21_1 to M21_8, and a string selection transistor SST21, the ground selection transistor GST21 is located at the lowest point of the cell string NS21 in the third direction z, the plurality of memory cells M21_1 to M21_8 are sequentially stacked on top of the ground selection transistor GST21 in the third direction z, and the string selection transistor SST21 is stacked on top of the memory cell M21_8 in the third direction z. In addition, the cell string NS31 may include a ground selection transistor GST31, a plurality of memory cells M31_1 to M31_8, and a string selection transistor SST31, the ground selection transistor GST31 is located at the lowest point in the third direction z of the cell string NS31, the plurality of memory cells M31_1 to M31_8 are sequentially stacked on top of the ground selection transistor GST31 in the third direction z, and the string selection transistor SST31 is stacked on top of the memory cell M31_8 in the third direction z. Other cell strings may also have similar configurations.

[0105] The memory cells or their corresponding ground selection transistors located at the same height from the substrate in the third direction z can be electrically connected through their corresponding word lines. For example, the memory cells M11_1, M21_1, and M31_1 can be connected to the first word line WL1. Similarly, the memory cells M11_2, M21_2, and M31_2 can be connected to the second word line WL2. The memory cells connected to each of the word lines WL3 to WL8 may also have a similar configuration, and therefore a detailed description thereof will be omitted.

[0106] One end of the string selection transistor of each of the cell strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, and NS33 may be connected to one of the first to third bit lines BL1 to BL3. For example, the string selection transistors SST11, SST21, and SST31 may be connected to the first bit line BL1 extending in the second direction y. Similarly, the other string selection transistors may be connected to their corresponding bit lines, and thus their description will be omitted.

[0107] Memory cells corresponding to the same string (or ground) selection line and the same word line can form a page. Write or read operations can be performed page by page. The memory cells of each page can each store two or more bits. The bits written to the memory cells in each page can form a logical page.

[0108] The memory cell array 330 may be provided as a 3D memory array. The 3D memory array may be monolithically formed on one or more physical levels of a substrate and / or a memory cell array having an active region placed on a circuit associated with the operation of the memory cell. The circuit associated with the operation of the memory cell may be located on or within the substrate. The expression "monolithically formed" means that each level of the layers of the 3D memory array may be deposited directly on their corresponding underlying levels. Alternatively, the circuit associated with the operation of the memory cell may be connected to the uppermost contact portion in a third direction z.

[0109] Figure 7 is a schematic diagram for explaining a sequential write operation for a nonvolatile memory device according to some embodiments of the inventive concept.

[0110] refer to Figure 7 , in some embodiments, Figure 1 The logical writer of the memory controller 200 ( Figure 2 270) can perform a sequential write operation on the nonvolatile memory device 300. Figure 7 , a zone can conceptually refer to a region from Figure 1 The memory block of the non-volatile memory device 300 ( Figure 3 Some physically sequential parts of "BLK1" to "BLKz" of the memory cell array 330. For example, the memory controller 200 and the non-volatile memory device 300 may support the non-volatile memory express (NVMe) zoned namespace (Zoned NameSpace, ZNS) standard. Within a memory cell array 330, there may be multiple zones, for example, the first zone to the Nth zone (where N is an arbitrary natural number). For better understanding, Figure 7 The logical area and the physical area of ​​each of the first to N-th areas are shown.

[0111] Referring to the logical area, the memory controller 200 may manage the first area to the Nth area. The first area to the Nth area may be managed independently. For example, Figure 1The host 100 can run a first application and a second application. The first application can manage data included in the first area. The second application can manage data included in the second area. That is, data managed by the same application with similar purposes and usage cycles can be managed in the same area.

[0112] Each of the first to Nth regions may include a plurality of LBAs. For example, the first region may include a first LBA LBA1 to an mth LBA LBAm (where m is a natural number). The first to mth LBAs LBA1 to LBAm may be logically sequential.

[0113] The logical area may include a logical address that can be identified by the host 100. The physical area may include the location or address of the memory block BLK within the non-volatile memory device 300. There may be a mapping relationship between the logical area and the physical area. The address mapping operation of converting the host identifiable logical address into a physical address within the non-volatile memory device 300 may be performed by the FTL 240.

[0114] The host 100 may transmit the first LBA LBA1 to the mth LBA LBAm to the storage device 10. The first LBA LBA1 to the mth LBA LBAm may be logically sequential.

[0115] The memory controller 200 may sequentially store data in the memory cell array 330. For example, data corresponding to the first LBA LBA1 and the second LBA LBA2 may be sequentially written to the memory cell array 330. Figure 2 When the data corresponding to the third LBA LBA3 is stored in the memory cell array 330, the data corresponding to the third LBA LBA3 may be written to the memory cell array 330.

[0116] Referring to the physical region, the memory cell array 330 may include a plurality of memory blocks BLK. The memory blocks BLK may be classified into the first region to the Nth region. The memory blocks BLK within the first region may be physically sequential first memory blocks BLK1 to the mth memory blocks BLKm. The first memory blocks BLK1 to the mth memory blocks BLKm of the first region may correspond to the first LBA LBA1 to the mth LBA LBAm of the first region, respectively. The memory controller 200 may manage the data received from the host 100 to be logically and physically sequentially stored within the memory cell array 330. That is, the memory controller 200 may support sequential writes.

[0117] Figure 7It is shown that one LBA can correspond to one memory block BLK, but the inventive concept is not limited thereto. For example, one LBA can correspond to one of a plurality of sequential sub-memory blocks within a memory block BLK while maintaining its logical sequence relative to other LBAs. Alternatively, one LBA can correspond to one of a plurality of sequential program units while maintaining its logical sequence relative to other LBAs. A program unit represents a unit that performs programming (e.g., a write operation) on a memory cell, and can correspond to a set of logical pages.

[0118] Figure 8 and Fig. 9 is a schematic diagram for explaining a mapping table showing a correspondence between a logical address and a physical address in a nonvolatile memory device according to some embodiments of the inventive concept during a write operation.

[0119] refer to Figure 8 , the mapping table 400_1 may include Figure 1 The LBAs and their corresponding physical block addresses (PBAs) within the nonvolatile memory device 300 of the host 100 may correspond to the LPNs of the host 100. Similarly, the PBAs may correspond to the physical page numbers (PPNs) of the nonvolatile memory device 300.

[0120] In other words, when the FTL 240 performs mapping at a page level, which means that a read or write operation of the host 100 is performed in units of pages, the LBA and the PBA may correspond to the LPN and the PPN, respectively.

[0121] For example, when Figure 1 When the memory controller 200 receives a write request signal for data corresponding to LBA0 from the host 100 , the memory controller 200 may store the received data at PPN 2 within the nonvolatile memory device 300 with reference to the mapping table 400_1 .

[0122] refer to Fig. 9 , the mapping table 400_2 may include LBAs within the nonvolatile memory device 300 and their corresponding PBAs. For example, the LBA may be an LBN of the host 100. Similarly, the PBA may correspond to a physical block number (PBN) of the nonvolatile memory device 300. Each of the LBNs may include the following: Figure 8 Concept of two or more LPNs shown.

[0123] In other words, when the FTL 240 performs mapping at the block level, the host 100 performs a read or write operation in units of blocks, and the LBA and the PBA may correspond to the LBN and the PBN, respectively.

[0124] For example, when Figure 1 When the memory controller 200 receives a write request signal for data corresponding to LBA0 from the host 100 , the memory controller 200 may store the received data at PBA 7 within the nonvolatile memory device 300 with reference to the mapping table 400_2 .

[0125] Fig.10 is a schematic diagram for explaining threshold voltage distributions of different numbers of bits that can be stored in a memory cell of a nonvolatile memory device according to some embodiments of the inventive concept.

[0126] refer to Fig.10 , the horizontal axis of each graph represents the magnitude of the threshold voltage, and the vertical axis of each graph represents the number of memory cells. When the memory cell is a single-level cell (SLC) capable of storing 1-bit data, the memory cell may have a threshold voltage Vth corresponding to one of a first programming state P1 and a second programming state P2. The read voltage Va1 may be a voltage for distinguishing the first programming state P1 from the second programming state P2. The memory cell having the first programming state P1 has a threshold voltage Vth lower than the read voltage Va1 and can be read as an on cell. The memory cell having the second programming state P2 has a threshold voltage Vth higher than the read voltage Va1 and can be read as an off cell.

[0127] When the memory cell is a multi-level cell (MLC) capable of storing 2-bit data, the memory cell may have a threshold voltage Vth corresponding to one of the first to fourth programming states P1 to P4. The first to third read voltages Vb1 to Vb3 may be voltages for distinguishing the first to fourth programming states P1 to P4.

[0128] When the memory cell is a triple-level cell (TLC) capable of storing 3-bit data, the memory cell may have a threshold voltage Vth corresponding to one of the first to eighth programming states P1 to P8. The first to seventh read voltages Vc1 to Vc7 may be voltages for distinguishing the first to eighth programming states P1 to P8.

[0129] When the memory cell is a quadruple-level cell (QLC) capable of storing 4-bit data, the memory cell may have a threshold voltage Vth corresponding to one of the first to sixteenth programming states P1 to P16. The first to fifteenth read voltages Vd1 to Vd15 may be voltages for distinguishing the first to sixteenth programming states P1 to P16.

[0130] In some embodiments, Figure 1 The nonvolatile memory device 300 may perform a high-speed programming (HSP) operation to quickly program data into the MLC. For example, when the nonvolatile memory device 300 programs data into the TLC, the HSP operation may include programming the data into the MLC by using Figure 3 The row decoder 360 applies a gradually increasing program voltage to the word line WL to program 3-bit data all at once to sequentially form the first to eighth program states P1 to P8.

[0131] refer to Figure 6 , when 2 or more bits of data are stored in a memory cell, two or more pages may correspond to one word line WL of the memory cell array 330. For example, when the memory cell is an MLC, 2-bit data (e.g., most significant bit (MSB) data and least significant bit (LSB) data) may be stored in each memory cell. Here, the MSB data may correspond to the MSB page, and the LSB data may correspond to the LSB page. In this case, two pages may correspond to one word line WL of the memory cell array 330.

[0132] Alternatively, when the memory cell is TLC, three bits of data (e.g., including MSB data, center significant bit (CSB) data, and LSB data) may be stored in each memory cell. Here, the MSB data may correspond to an MSB page, the CSB data may correspond to a CSB page, and the LSB data may correspond to an LSB page. In this case, three pages may correspond to one word line WL of the memory cell array 330.

[0133] Fig.11 It is used to explain Figure 2 The schematic diagram of the memory controller of the above reference will be omitted. Figure 2 Description of the content that the description overlaps.

[0134] The host interface 220 may include a host direct memory access (DMA) module 221. The host interface 220 may be configured to receive Figure 2The host 100 receives the LBA "LBA", the write request signal WREQ and / or the data DATA. Here, the host interface 220 can receive and convert the LBA "LBA", the write request signal WREQ and the data DATA according to the NVMe standard. The host DMA module 221 can input the data DATA to the memory controller 200 using the LBA "LBA", the write request signal WREQ and the data DATA. The host DMA module 221 can manage the DMA of the data DATA. In other words, the host DMA module 221 can manage the data to be directly input to the write buffer 250 without passing through Figure 2 The data DATA of the processor 210 is transmitted, but the present disclosure is not limited thereto.

[0135] The write buffer 250 may include a memory 251. Here, the memory 251 may be a buffer memory. The write buffer 250 may buffer data DATA received from the host 100. That is, the write buffer 250 may temporarily store the data DATA in the memory 251 according to the write request signal WREQ. For example, the memory 251 may cache the data DATA. The memory 251 may temporarily store the data DATA based on the cache identifier C_ID. Here, the cache identifier C_ID may correspond to the address of the memory 251 storing the data DATA. Here, the write buffer 250 may be a volatile memory. In other words, the write buffer 250 may store the data DATA only during and / or before programming the data DATA to the nonvolatile memory device 300, and may remove the data DATA after programming the data DATA to the nonvolatile memory device 300. In addition, the write buffer 250 may provide the buffered data DATA to the memory interface 230 or the nonvolatile memory device 300 in response to a request from the memory interface 230 or the nonvolatile memory device 300.

[0136] The write buffer 250 may be configured to be controlled by the cache controller 260. In addition, the write buffer 250 may provide the cache identifier C_ID1 of the memory 251 to the cache controller 260.

[0137] The cache controller 260 may be configured to register the LBA “LBA” and the cache identifier C_ID. The cache controller 260 may control the overall operation of the write buffer 250 and manage a cache operation of the data DATA. The cache controller 260 may include a cache manager 261 .

[0138] The cache manager 261 may be configured to manage a cache operation of the write buffer 250. For example, the cache manager 261 may control data DATA to be stored in the write buffer 250. The cache manager 261 may store the data DATA to correspond to the LBA "LBA" and the cache identifier C_ID. That is, in response to receiving a write request WREQ for the LBA "LBA" from the host 100, the cache manager 261 may identify the cache identifier C_ID of the write buffer 250. In addition, when an address in the write buffer 250 in which the data DATA is stored is updated, the cache manager 261 may store the updated address.

[0139] The FTL 240 may receive the LPN or LBA from the cache controller 260. Here, the FTL 240 may correspond to a working memory and may operate as firmware. The FTL 240 may convert the LPN into a physical address ADDR with reference to a mapping table. The FTL 240 may temporarily store the LPN and the corresponding address ADDR. The address ADDR may correspond to a physical address in the nonvolatile memory device 300.

[0140] The memory interface 230 may receive a write command WCMD, an address ADDR, and data DATA. Here, the memory interface 230 may receive the address ADDR from the FTL 240 and receive the data DATA from the write buffer 250. The write buffer 250 may be configured to provide the buffered data DATA to the memory interface 230. In addition, the memory interface 230 may access the data DATA stored in the memory 251. The flash DMA module 231 included in the memory interface 230 may control the access of the data DATA between the memory controller 200 and the non-volatile memory device 300. In other words, the flash DMA module 231 may allow the data DATA stored in the memory 251 to be input to the non-volatile memory device 300.

[0141] Fig.12 It is used to explain Fig.11 An example flow chart of a write operation of a memory controller of FIG. Fig.12 A write operation of the memory controller 200 is described and may be referred to as including a grouping operation performed by a physical striper.

[0142] refer to Fig.12 , the host 100 may provide the LBA, the write request signal, and the data to the memory controller 200 (S100). That is, the host 100 may provide the LBA, the write request signal, and the data to the host interface 220.

[0143] The host interface 220 may send the LBA to the cache controller 260, and send the write request signal and the data to the write buffer 250. The cache manager 261 may receive the LBA from the host interface 220 (S101) and may divide the LBA into LPNs (S102). Here, the LPN may correspond to a logical address corresponding to a physical address in the nonvolatile memory device 300, where the data DATA is to be written by the host 100. Thereafter, the cache manager 261 may send the LPN to the logical writer 270 (S103).

[0144] The logical writer 270 may receive the LPN from the cache manager 261 (S104). Thereafter, the logical writer 270 may transmit the first signal S1 to the physical striper 280 (S105). Here, the first signal S1 may be a signal for querying which page of the nonvolatile memory device 300 the LPN received by the logical writer 270 corresponds to.

[0145] The number of pages of the nonvolatile memory device 300 may be determined depending on the type of memory cells included in the memory cell array 330 of the nonvolatile memory device 300. For example, when the memory cells in the memory cell array 330 are MLC, the number of pages of the nonvolatile memory device 300 may be two (e.g., MSB and LSB pages). Alternatively, when the memory cells in the memory cell array 330 are TLC, the number of pages of the nonvolatile memory device 300 may be three (e.g., MSB, CSB, and LSB pages).

[0146] That is, the logical writer 270 may query the physical striper 280 through the first signal S1 in which page of the nonvolatile memory device 300 the data corresponding to the received LPN will be stored. Here, one LPN may correspond to one data, but the present disclosure is not limited thereto. Alternatively, two or more LPNs may correspond to one data depending on the mapping operation of the FTL 240.

[0147] The physical striper 280 may receive a first signal S1 from the logical writer 270 (S106). In response to the first signal S1, the physical striper 280 may perform a grouping operation on the received LPN (S107). The physical striper 280 may generate a second signal S2 including a correspondence relationship between the LPN received by the logical writer 270 and the page of the nonvolatile memory device 300 through the grouping operation. Figures 13 to 15 Describes the grouping operation.

[0148] Thereafter, the physical striper 280 may transmit the second signal S2 to the logical writer 270 (S108), and the logical writer 270 may receive the second signal S2 (S109) and generate a program unit based on the second signal S2 (S110). Thereafter, the logical writer 270 may perform a write operation on the nonvolatile memory device 300 based on the program unit (S111). Therefore, the nonvolatile memory device 300 may store data corresponding to the LPN included in the program unit (S112).

[0149] Figures 13 to 16 is used to explain Fig.11 The program unit generated by the logic writer and by Fig.11 Schematic diagram of the grouping operations performed by the physical striper.

[0150] The memory cells in the memory cell array 330 will be described below as, for example, TLC, but the present disclosure is not limited thereto. For example, the following description may also be applicable to a case where the memory cells in the memory cell array 330 are MLC.

[0151] refer to Fig.13 , the nonvolatile memory device 300 may include three pages, for example, MSB, CSB, and LSB pages. The nonvolatile memory device 300 may receive the first data DATA1 to the twelfth data DATA12 from the memory controller 200 through the first channel CH1 to the fourth channel CH4. The number of channels between the memory controller 200 and the nonvolatile memory device 300 is not particularly limited and may vary. That is, the number of channels between the memory controller 200 and the nonvolatile memory device 300 may be greater than or less than four. As previously described with reference to Figure 7 As explained, the nonvolatile memory device 300 may perform sequential write operations for the first to twelfth data DATA12. For example, the nonvolatile memory device 300 may first write the first data DATA1, then sequentially write the second to eleventh data DATA2 to eleventh data DATA11, and finally write the twelfth data DATA12.

[0152] In some embodiments, the first to twelfth data DATA1 to DATA12 may correspond to the first to twelfth LPNs LPN1 to LPN12, respectively. For example, the first data DATA1 may be stored at an address in the nonvolatile memory device 300 corresponding to the first LPN LPN1 among the physical addresses in the nonvolatile memory device 300. Similar explanations are directly applicable to other data and their corresponding LPNs, for example, the second to twelfth data DATA2 to DATA12 and the second to twelfth LPNs LPN2 to LPN12, and will be omitted here.

[0153] The grouping operation performed by the physical striper 280 may involve assigning each of the first LPN LPN1 to the twelfth LPN LPN12 received by the logical writer 270 to one of the MSB, CSB, or LSB pages to create a plurality of groups, for example, the first group Group1 to the fourth group Group4. Figure 1 In the read mode of the host 100, the physical striper 280 may perform a grouping operation.

[0154] For example, when the nonvolatile memory device 300 performs a sequential write operation with respect to first to twelfth data DATA1 to DATA12 , the host 100 may sequentially read the first to twelfth data DATA1 to DATA12 from the nonvolatile memory device 300 .

[0155] Therefore, since the first data DATA1 is to be written first, the host 100 may first read the first data DATA1 from the nonvolatile memory device 300. Similarly, since the twelfth data DATA12 is written last, the host 100 may last read the twelfth data DATA12 from the nonvolatile memory device 300.

[0156] In some embodiments, the physical striper 280 may allocate the LPN of the first data DATA1 (e.g., the first LPN LPN1) to (e.g., the MSB page), and then allocate the LPN of the second data DATA2 (e.g., the second LPN LPN2) to another page (e.g., the CSB page), but the present disclosure is not limited thereto. When the second LPN LPN2 is allocated to the CSB page, the physical striper 280 may allocate the LPN of the third data DATA3 (e.g., the fourth LPN LPN3) to the LSB page, and then allocate the LPN of the fourth data DATA4 (e.g., the fourth LPN LPN4) back to the MSB page.

[0157] In this manner, assuming that the host 100 sequentially reads corresponding data, the physical striper 280 may allocate LPNs of the first to twelfth data DATA1 to DATA12 between pages of the nonvolatile memory device 300 so that a plurality of data to be sequentially written may be allocated to different pages.

[0158] The logical writer 270 may create program units “Program Unit” for the first group Group1 to the fourth group Group4 based on the grouping operation performed by the physical striper 280 .

[0159] Fig.13 It is shown that first to third data DATA1 to DATA3 to be sequentially written are first sent to the nonvolatile memory device 300 through one channel (e.g., the first channel CH1), and then fourth to sixth data DATA4 to DATA6 to be sequentially written are sent to the nonvolatile memory device 300 through a subsequent channel (e.g., the second channel CH2), but the present disclosure is not limited to this.

[0160] For example, refer to Fig.14 , when the physical striper 280 corresponds the first LPN LPN 1 to the twelfth LPN LPN 12 to the MSB, CSB, and LSB pages, the memory controller 200 may consider performing a striping operation for the nonvolatile memory device 300. That is, the memory controller 200 may provide data to the nonvolatile memory device 300 in a distributed manner to enhance the performance (e.g., write and / or read performance) of the memory device 10, and may allow the physical striper 280 to control the nonvolatile memory device 300 using the first channel CH1 to the fourth channel CH4 at the same time, so that the data provided in a distributed manner may be programmed at the same time.

[0161] Therefore, with the above reference Fig.13 Conversely to what is described, the physical striper 280 may transmit the first data DATA1 having the first LPN LPN1 allocated to the MSB page to the nonvolatile memory device 300 through the first channel CH1, and may then transmit the data written next to the first data DATA1 (e.g., the second data DATA2 having the second LPN LPN2 allocated to the CSB page) through another channel (e.g., the second channel CH2) to the nonvolatile memory device 300. Thereafter, the physical striper 280 may transmit the data written next to the second data DATA2 (e.g., the third data DATA3 having the third LPN LPN3 allocated to the LSB page) to the nonvolatile memory device 300 through yet another channel (e.g., the third channel CH3).

[0162] Therefore, considering the read mode of the host 100, the physical striper 280 may perform a grouping operation in such a manner that a plurality of data to be sequentially written (eg, first to twelfth data DATA12) may be distributed between pages and channels as much as possible.

[0163] In this manner, the logical writer 270 may create the program unit Program Unit_A for the first group Group1_A to the fourth group Group4_A obtained through the grouping operation performed by the physical striper 280 .

[0164] in other words, Fig.13 It is shown that data transmitted to the nonvolatile memory device 300 through the same channel is included in the same group, and Fig.14 It is shown that the first data DATA1 , the fifth data DATA5 , and the ninth data DATA9 transmitted to the nonvolatile memory device 300 through the first channel CH1 may be included in different groups; however, the present disclosure is not limited thereto.

[0165] Fig.13 and Fig.14 It is shown that data to be written one by one (eg, first data DATA1 and second data DATA2 ) are respectively allocated to different pages, eg, MSB and CSB pages, but the present disclosure is not limited thereto.

[0166] In some embodiments, the LPNs of two or more data to be sequentially written first may correspond to one page, and the LPNs of two or more data to be sequentially written next may correspond to another page. Fig.15, the LPNs of the first data DATA1 and the second data DATA2 to be sequentially written first (e.g., the first LPN LPN1 and the second LPN LPN2) may both correspond to the MSB page, and the LPNs of the third data DATA3 and the fourth data DATA4 to be sequentially written next (e.g., the third LPN LPN3 and the fourth LPN LPN4) may both correspond to a page different from the first LPN LPN1 and the second LPN LPN2, for example, a CSB page. In this case, as a result of the striping operation performed by the memory controller 200, the first data DATA1 and the second data DATA2 may be transmitted to the nonvolatile memory device 300 through the first channel CH1 and the second channel CH2, respectively, and the third data DATA3 and the fourth data DATA4 may be transmitted to the nonvolatile memory device 300 through the third channel CH3 and the fourth channel CH4, respectively. Similarly, other data and their corresponding LPNs (e.g., fifth data DATA5 to twelfth data DATA12 and fifth LPNs LPN5 to twelfth LPNs LPN12) may correspond to one of the MSB, CSB, and LSB pages of the nonvolatile memory device 300, and the fifth data DATA5 to twelfth data DATA12 may be transmitted to the nonvolatile memory device 300 through one of the first to fourth channels CH1 to CH4.

[0167] In this manner, the logical writer 270 may create the program unit Program Unit_B for the first group Group1_B to the fourth group Group4_B obtained through the grouping operation performed by the physical striper 280 .

[0168] The following will describe Figures 13 to 15 Program units Program Unit, Program Unit_A and ProgramUnit_B.

[0169] Fig.16 is a schematic diagram for explaining a program unit generated by a logic writer according to some embodiments of the inventive concept.

[0170] refer to Fig.16 , the program unit "Program Unit" can be Figures 13 to 15 The program unit "ProgramUnit" will be described as any one of the program units "ProgramUnit", Program Unit_A and Program Unit_B. Fig.14 Program unit "Program Unit_A" of the

[0171] In some embodiments, a program unit "Program Unit" may consist of three pages (eg, MSB, CSB, and LSB pages), and the MSB, CSB, and LSB pages may be programmed to Figure 6 The logical writer 270 may perform a write operation on a program unit-by-program unit basis (e.g., using a write operation including a grouping operation performed by a physical striper), and may simultaneously program three bits of data (e.g., MSB, CSB, and LSB data) through an HSP operation.

[0172] Fig.17 and Fig.18 is a schematic diagram for explaining how to write data to a nonvolatile memory device in the HSP scheme.

[0173] refer to Fig.17 , when data is written to the nonvolatile memory device 300 in the HSP scheme, variations in the sensing count and the data read time t_Read may occur between different pages.

[0174] The data read time t_Read may represent the amount of time taken from when the memory cell array 330 is activated to when data is read from the memory cells of the memory cell array 330 and the data arrives at the page buffer unit 340. In other words, the data read time t_Read may mean the duration from when a read command and an address in the memory interface 230 are received to when data is read from the memory cell array 330 and delivered to the page buffer unit 340.

[0175] For example, when reading data stored in the MSB page, sensing may be performed twice, resulting in a data read time t_Read of 37 microseconds (μs). Similarly, when reading data stored in the CSB page, sensing may be performed three times, resulting in a data read time t_Read of 50 μs. Likewise, when reading data stored in the LSB page, sensing may be performed twice, resulting in a data read time t_Read of 35 μs. However, the sensing counts and data read times of different pages are not limited to Fig.17 Those shown in and may vary.

[0176] When the data read time t_Read differs from one page to another, as described above, the execution of the read operation may vary depending on in which page the data currently being read is stored when reading data stored in the nonvolatile memory device 300 .

[0177] For example, refer to Fig.18In some comparative examples, the memory cell array 330 may include a first page Page1, a second page Page2, and a third page Page3, in which case the data read time T3 of the third page Page3 may be longer than the data read time T1 of the first page Page1, and the data read time T1 of the first page Page1 may be longer than the data read time T2 of the second page Page2.

[0178] The length of the data read time may be inversely proportional to the data read performance. For example, when reading data from a page with the shortest data read time T2 (eg, the second page Page2), Figure 1 The read performance of the storage device 10 may be rated as the highest. Conversely, when data is read from a page with the longest data read time T3 (e.g., the third page Page3), the read performance of the storage device 10 may be rated as the lowest. Therefore, if the evaluation of the performance of the storage device 10 changes depending on which page of the memory cell array 330 is being read, the reliability of the performance of the storage device 10 may deteriorate.

[0179] Fig.19 and Fig. 20 is a schematic diagram for explaining groups generated by a grouping operation performed by a physical striper according to some embodiments of the inventive concept.

[0180] The following describes the first group Group1_A to the fourth group Group4_A ( Fig.14 ) and the program unit Program Unit_A ( Fig.14 ) as an example, describing Fig.19 and 20 However, Fig.19 and Fig. 20 The following description of the embodiments can be applied not only to Fig.13 The first group Group1 to the fourth group Group4 and the program unit "Program Unit" can also be applied to Fig.15 The first group Group1_B to the fourth group Group4_B and the program unit Program Unit_B.

[0181] Fig.19 The horizontal axis of represents the data read time t_Read of each of the first to twelfth data DATA1 to DATA12. Fig.14 , Fig.17 and Fig.19, the data read time t_Read of the MSB page is represented as t1, the data read time t_Read of the CSB page is represented as t2, and the data read time t_Read of the LSB page is represented as t3. The first data DATA1 to the twelfth data DATA12 are data written sequentially and can also be read sequentially. For example, the data belonging to the first group Group1_A (for example, the first data DATA1 to the third data DATA3) are read sequentially, and then, the data belonging to the second group Group2_A (for example, the fourth data DATA4 to the sixth data DATA6) can be read sequentially, and finally, the data belonging to the third group Group3_A (for example, the seventh data DATA7 to the ninth data DATA9) can be read sequentially.

[0182] In this case, since the data belonging to each of the first to fourth groups Group1_A to Group4_A are stored in different types of pages, the sum of the data read time t_Read of the pages of each of the first to fourth groups Group1_A to Group4_A may be almost similar. For example, the data belonging to the first group Group1_A (e.g., the first to third data DATA1 to DATA3) are not stored in the same page, but are respectively stored in different pages, such as MSB, CSB, and LSB pages, and similarly, the data belonging to the second group Group2_A (e.g., the fourth to sixth data DATA4 to DATA6) are also respectively stored in different pages, such as MSB, CSB, and LSB pages. Therefore, the total data read time of the first group Group1_A may be similar to the total data read time of the second group Group2_A.

[0183] Therefore, reference Fig. 20 , and the previous reference Fig.18 Contrary to what has been described, the data reading performance of the memory device 10 can be kept consistent regardless of which page of the memory cell array 330 is being read. Therefore, the reliability of the performance of the memory device 10 can be improved.

[0184] Figure 21 to Figure 24 is a schematic diagram for explaining how to write data in a memory device in a 2-8 HSP scheme according to some embodiments of the inventive concept.

[0185] refer to Fig.21 , and the previous reference Fig.16 Contrary to what has been described, three pages (eg, MSB, CSB, and LSB pages) forming a programming unit may be programmed in Figure 6Between two word lines WL(N) and WL(N-1) within the memory cell array 330. For example, the MSB page may be programmed on the word line WL(N-1), and the CSB and LSB pages may be programmed on the word line WL(N) adjacent to the word line WL(N-1).

[0186] In addition, the previous page PD may correspond to the word line WL(N-2). Other pages except the previous page PD may also correspond to the word line WL(N-2).

[0187] The following will refer to Fig. 22 and Fig.23 Description Fig.21 , a 2-8 HSP approach is shown for programming three pages (eg, MSB, CSB, and LSB pages) of a program unit between two word lines (eg, word lines WL(N) and WL(N-1)) within a memory cell array 330. In the example of FIG.

[0188] For convenience, the description assumes that in the current programming operation, word line WL(N-1) may be the selected word line, while word line WL(N) is the unselected word line, and word line WL(N-1) has stored the previous page PD. For example, before the programming operation of word line WL(N-1), the programming operation of word line WL(N-2) may be performed. In the programming operation of word line WL(N-2), word line WL(N-2) is the selected word line, while word line WL(N-1) is the unselected word line, and at least one of the pages corresponding to word line WL(N-2) (e.g., the previous page PD) may be non-selectively programmed onto word line WL(N-1). That is, at the start of the programming operation of word line WL(N-1), word line WL(N-1) may have stored the previous page PD that was non-selectively programmed during the previous programming operation. However, the present disclosure is not limited thereto.

[0189] Figure 1 The nonvolatile memory device 300 may receive the MSB, CSB, and LSB pages corresponding to the word line WL(N-1). In at least one example embodiment, the received MSB, CSB, and LSB pages may be stored in the nonvolatile memory device 300 ( Figure 3 The nonvolatile memory device 300 may program one of the MSB, CSB, and LSB pages corresponding to the word line WL(N-1) onto an unselected word line (e.g., word line WL(N)) (e.g., perform an unselected program operation PGM_unsel).

[0190] For example, refer to Fig.23, the nonvolatile memory device 300 may perform an unselected program operation PGM_unsel for the word line WL(N) so that the memory cells connected to the word line WL(N) may be placed in the erase state E or the unselected program state P01. In at least one example embodiment, during the unselected program operation PGM_unsel, an unselected verification voltage VF01 may be used to verify the unselected program state P01. When the unselected program operation PGM_unsel for the word line WL(N) is completed, the word line WL(N) has stored a page corresponding to the word line WL(N-1), and the word line WL(N-1) has stored a previous page PD.

[0191] Thereafter, the nonvolatile memory device 300 may perform a previous page read operation RD_pre with respect to the word line WL(N-1) to read the previous page PD. Fig.23 As shown, each memory cell in the word line WL(N-1) storing the previous page PD may have an erase state E or an unselected program state P01. The nonvolatile memory device 300 may read the previous page PD by performing a previous page read operation RD_pre using a read voltage VRD01.

[0192] In at least one example embodiment, the previous page PD read by the previous page read operation RD_pre may be stored in a specific latch in the page buffer unit 340 of the nonvolatile memory device 300. The specific latch may refer to a data latch in which a page (e.g., an MSB page) is programmed to an unselected word line. That is, after the previous page read operation RD_pre, the page buffer unit 340 of the nonvolatile memory device 300 may store the LSB and CSB pages corresponding to the word line WL(N-1) and the previous page PD corresponding to the word line WL(N-2).

[0193] Thereafter, the nonvolatile memory device 300 may perform the selected program operation PGM_sel for the word line WL(N-1) based on the LSB and CSB pages and the previous page PD. For example, as described above, after the previous page read operation RD_pre is completed, the page buffer unit 340 of the nonvolatile memory device 300 may store the LSB and CSB pages and the previous page PD. Then, the nonvolatile memory device 300 may perform the selected program operation PGM_sel for the word line WL(N-1) based on the LSB and CSB pages and the previous page PD stored in the page buffer unit 340.

[0194] As a result of the execution of the selected program operation PGM_sel, the memory cells in the word line WL(N-1) previously in the erase state E may have the erase state E and one of the first to third program states P1 to P3, and the memory cells in the word line WL(N-1) previously in the unselected program state P01 may have one of the fourth to seventh program states P4 to P7. During the selected program operation PGM_sel, the first to seventh program states P1 to P7 may be verified using the first to seventh verification voltages VF1 to VF7. This type of programming method may be referred to as a 2-8HSP scheme, and the technical concepts of the present disclosure may be applicable to the 2-8HSP scheme.

[0195] For example, refer to Fig.24 , and the previous reference Fig.17 Compared with the HSP scheme described in the previous section, the 2-8HSP scheme can show a larger variation in sense counts and data read time t_Read between pages. Fig.17 Compared with the HSP scheme depicted in , the 2-8HSP scheme may further impair the reliability of the read performance of the storage device 10. Therefore, when programming data in the non-volatile memory device 300 according to the 2-8HSP scheme, the physical striper 280 may perform a grouping operation to ensure that a plurality of data sequentially written according to the previous embodiment are allocated to different pages. Based on the result of the grouping operation, the logical writer 270 may collect LPNs to generate program units.

[0196] Fig.25 is a schematic diagram for explaining a system to which a storage device according to some embodiments of the inventive concept is applied.

[0197] refer to Fig.25 , the system 1000 may be a mobile system such as a portable communication terminal, a mobile phone, a smart phone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IoT) device, but the present disclosure is not limited thereto. Alternatively, the system 1000 may also be a PC, a laptop computer, a server, a media player, or an automotive device (e.g., a navigation device).

[0198] The system 1000 may include a main processor 1100, memories 1200a and 1200b, and storage devices 1300a and 1300b. In addition, the system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0199] The main processor 1100 may be configured to control the overall operation of the system 1000, and in particular, the operations of various other components forming the system 1000. The main processor 1100 may be implemented as a general-purpose processor, a special-purpose processor, or an application processor.

[0200] The main processor 1100 may include at least one CPU core 1110, and may also include a controller 1120 for controlling memories 1200a and 1200b and / or storage devices 1300a and 1300b. In some embodiments, the main processor 1100 may include a dedicated accelerator 1130 for high-speed data processing, such as artificial intelligence (AI) data processing. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and may be implemented as an independent chip separate from other components of the main processor 1100.

[0201] Memories 1200a and 1200b may be configured as main memories of system 1000, and may include volatile memories such as static random access memory (SRAM) and / or dynamic random access memory (DRAM), but may also include non-volatile memories such as flash memory, phase change random access memory (PRAM) and / or resistive random access memory (RRAM). Memories 1200a and 1200b may also be implemented in the same package as main processor 1100.

[0202] The storage devices 1300a and 1300b may be configured to be used as non-volatile storage devices for storing data independently of the power state, and may have a relatively large storage capacity compared to the memories 1200a and 1200b. The storage devices 1300a and 1300b may include controllers 1310a and 1310b, respectively, and non-volatile memories 1320a and 1320b that store data under the control of the controllers 1310a and 1310b, respectively. The non-volatile memories 1320a and 1320b may include two-dimensional (2D) or three-dimensional (3D) V-NAND flash memory, but may also include other types of non-volatile memories, such as PRAM and RRAM.

[0203] The storage devices 1300a and 1300b may be included in the system 1000 while being physically separated from the main processor 1100 or implemented in the same package as the main processor 1100. In addition, the storage devices 1300a and 1300b may be implemented in the form of an SSD or a memory card, and may be detachably connected to other components of the system 1000 through an interface such as a connection interface 1480 to be described later. The storage devices 1300a and 1300b may correspond to Figure 1The storage device 10, and the controllers 1310a and 1310b and the non-volatile memories 1320a and 1320b may correspond to Figure 1 A memory controller 200 and a nonvolatile memory device 300 are provided.

[0204] Image capture device 1410 may be configured to capture optical data, such as still images and / or video; and may be, for example, a camera, a camcorder, a webcam, etc.

[0205] The user input device 1420 may be configured to receive various types of data input from a user of the system 1000 and may be, for example, a touch pad, a keypad, a keyboard, a mouse, a microphone, or the like.

[0206] The sensor 1430 may detect various types of physical quantities that may be acquired from the external environment of the system 1000, and may convert the detected physical quantities into electrical signals. The sensor 1430 may include a temperature sensor, a pressure sensor, a light sensor, a positioning sensor, an acceleration sensor, a biosensor, a gyroscope, and the like.

[0207] The communication device 1440 may be configured to send and receive signals between the system 1000 and other devices outside the system 1000 according to various communication protocols. The communication device 1440 may be (and / or be configured to include), for example, an antenna, a transceiver, a modem, and the like.

[0208] Display 1450 and speaker 1460 may be used as output devices to provide visual and auditory information, respectively, to a user of system 1000 .

[0209] The power supply device 1470 may be configured to convert power supplied from an embedded battery (not shown) and / or an external power source to power components of the system 1000 .

[0210] The connection interface 1480 may be configured as a connection between the system 1000 and an external device connected to the system 1000 to exchange data with the system 1000. The connection interface 1480 may be implemented using various interface methods, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnection (PCI), PCI express (PCIe), NVMe, IEEE 1394, Universal Serial Bus (USB), SD, Multimedia Card (MMC), Embedded MMC (eMMC), UFS, Embedded UFS (eUFS), and CF.

[0211] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the embodiments of the present disclosure are not limited to the above-described embodiments, but can be implemented in various different forms. It will be appreciated by those skilled in the art that the present disclosure can be practiced in other specific forms without changing the technical spirit or basic features of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive, but illustrative in all aspects.

Claims

1. A memory controller, comprising: a cache manager configured to receive a logical block address LBA from a host and separate the LBA into a plurality of logical page numbers LPN, the plurality of LPNs including at least a first LPN and a second LPN; a physical striper configured to output a first signal that corresponds the first LPN to a first page of a nonvolatile memory device and corresponds the second LPN to a second page of the nonvolatile memory device, wherein the second page is different from the first page; and a logical writer configured to receive the first LPN and the second LPN from the cache manager, receive the first signal from the physical striper, and store data to the nonvolatile memory device by performing a write operation based on the first signal, wherein the write operation comprises a first write operation for first data at a first address of the nonvolatile memory device corresponding to the first LPN and a second write operation for second data at a second address of the nonvolatile memory device corresponding to the second LPN after the first write operation, and The data is stored such that a read operation of the host includes a first read operation for the first data stored at the first address and a second read operation for the second data stored at the second address after the first read operation.

2. The memory controller according to claim 1, wherein: A first data read time for the first data and a second data read time for the second data are different from each other.

3. The memory controller according to claim 1, wherein: The first data and the second data are written in a high speed programming (HSP) scheme.

4. The memory controller according to claim 1, wherein The nonvolatile memory device includes one or more word lines, and The logical writer is configured to collect the LPN to generate a program unit for performing the write operation based on the collected LPN.

5. The memory controller according to claim 4, wherein: The memory controller is configured to write a plurality of data corresponding to the program unit to memory cells connected to a corresponding one of the word lines of the nonvolatile memory device.

6. The memory controller according to claim 4, wherein The nonvolatile memory device includes a first word line and a second word line adjacent to the first word line, The plurality of LPNs further includes a third LPN, The physical striper is configured to correspond the third LPN to a third page of the non-volatile memory device, and The logic writer is configured to generate the program unit by collecting the first LPN, the second LPN, and the third LPN to write some of the data corresponding to the program unit to a first memory cell connected to the first word line, and to write some of the remaining data corresponding to the program unit to a second memory cell connected to the second word line.

7. The memory controller according to claim 6, wherein The logic writer is configured to perform a third write operation for a third address of the nonvolatile memory device corresponding to the third LPN after the second write operation, and in, The data is stored such that the read operation of the host includes a third read operation for third data stored at the third address after the second read operation.

8. The memory controller according to claim 7, wherein: A third data read time for the third data is different from a first data read time for the first data, and the third data read time is different from a second data read time for the second data.

9. A storage device comprising: A non-volatile memory device comprising an array of memory cells; as well as a memory controller configured to receive a write request signal and data from a host, and control the nonvolatile memory device to write the received data into the memory cell array, The non-volatile memory device includes a first page to a third page. The memory controller includes a cache manager configured to receive a logical block address LBA from the host and separate the LBA into a plurality of logical page numbers LPN, the plurality of LPNs including at least first to sixth LPNs, a physical striper configured to perform a grouping operation so that a first group including the first to third LPNs and a second group including the fourth to sixth LPNs are generated, the first to third LPNs respectively corresponding to the first to third pages, and the fourth to sixth LPNs respectively corresponding to the first to third pages, and A logical writer is configured to receive the LPN from the cache manager and sequentially write first to sixth data respectively corresponding to the first to sixth LPNs among the received data to the nonvolatile memory device by performing a write operation based on the grouping operation.

10. The storage device according to claim 9, wherein: The first to sixth data are written so that a read operation of the host sequentially reads the first to sixth data stored at the nonvolatile memory device.

11. The storage device according to claim 9, wherein The memory controller and the non-volatile memory device are configured to communicate with each other via a plurality of channels, and The memory controller is configured to: sending the first data to the non-volatile memory device through a first channel, sending the second data to the nonvolatile memory device through a second channel different from the first channel, and The third data is sent to the nonvolatile memory device through a third channel different from both the first channel and the second channel.

12. The storage device according to claim 9, wherein The nonvolatile memory device includes at least an Nth word line and an N+1th word line, and The first to sixth data are written to memory cells connected to the Nth word line.

13. The storage device according to claim 9, wherein The memory cell array includes at least an Nth word line and an N+1th word line, The first data, the second data, the fourth data, and the fifth data are written to a first memory cell connected to the Nth word line, and The third data and the sixth data are written to the second memory cell connected to the (N+1)th word line.

14. The storage device according to claim 9, wherein The logical writer is configured to send a first signal to the physical striper in response to receiving the LPN from the cache manager, In response to receiving the first signal, the physical striper is configured to perform the grouping operation and send a second signal to the logical writer, and The second signal includes a correspondence relationship between the first to sixth LPNs and the first to third pages.

15. The storage device according to claim 9, wherein: A data read time for the first data is the same as a data read time for the fourth data, and is different from a data read time for the second data.

16. A host-storage system, comprising: The host is configured to send a write request signal, data and a logical block address LBA; A nonvolatile memory device comprising a memory cell array and a plurality of word lines connected to the memory cell array; as well as a memory controller configured to receive the write request signal, the data, and the LBA, and control a write operation to write the data to a memory cell of the nonvolatile memory device corresponding to the LBA, Wherein, the memory controller comprises: a cache manager configured to separate the LBAs into logical page numbers LPN, a logic writer configured to receive the LPN and generate a program unit by collecting the LPN page by page, and a physical striper configured to group some of the LPNs into a first LPN group and group some of the remaining portion of the LPNs into a second LPN group, such that the first LPN group corresponds to a first page and the second LPN group corresponds to a second page different from the first page, and Wherein, when the write operation to the non-volatile memory device is performed based on the program unit, the logical writer is configured to initiate a write operation for the first page, and then initiate a write operation for the second page before completing the write operation for the first page.

17. The host-storage system of claim 16, wherein The first LPN group includes a first LPN corresponding to the first data and a second LPN corresponding to the second data, the second LPN group includes a third LPN corresponding to third data, The memory controller and the non-volatile memory device are configured to communicate with each other via at least a first channel and a second channel, The memory controller is configured to send the first data to the nonvolatile memory device via the first channel and to send the second data and third data to the nonvolatile memory device via the second channel, and The logical writer is configured to perform a write operation for the third data after the write operation for the first data is initiated and before the write operation for the second data is completed.

18. The host-storage system of claim 17, wherein A data reading time for the first data is the same as a data reading time for the second data and is different from a data reading time for the third data, and The host is configured to perform a read operation on the third data after performing a read operation on the first data and before performing a read operation on the second data.

19. The host-storage system of claim 16, wherein The logical writer is configured to generate a program unit based on a correspondence between the LPN generated by the physical striper and the first page and the second page, and The data included in the program unit is written to the first and second pages in a high speed programming (HSP) scheme.

20. The host-storage system of claim 19, wherein The memory cell array includes a first word line and a second word line, the first word line and the second word line are connected to the first memory cell and the second memory cell, respectively, The data of the first page included in the program unit is written to the first memory unit, and The data of the second page is written to the second memory cell.

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