Read-write method of embedded Flash, embedded Flash and electronic equipment

Abstract

The invention provides a read-write method of an embedded Flash, the embedded Flash and electronic equipment, and belongs to the technical field of semiconductors, the embedded Flash comprises a plurality of spliced IP modules; the reading channel is provided with an independent address signal line and a chip selection signal; the write channel has control signals required by all IP modules and multiplexes read enable signals; a Flash storage area is divided into two Banks, one Bank is used for storing data of a currently read intellectual property module, the other Bank is used for storing data of all other intellectual property modules, and when an embedded Flash is accessed through a Flash controller and write operation is carried out on one IP module, any other IP module can be read at the same time. The function of writing while reading is achieved in the Flash controller, the method can be applied to various application scenes, and the access efficiency of a chip storage area is high.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to an embedded Flash reading and writing method, an embedded Flash and an electronic device. Background Art

[0002] With the continuous development of semiconductor process technology, the processor capability is constantly enhanced, but the development of embedded Flash has not kept pace with it. Therefore, the read speed of embedded Flash has become a key factor restricting the computing power of the chip. Improving the read speed of embedded Flash is the main direction to solve the computing bottleneck of the existing von Neumann architecture embedded Flash chip. Considering the constraints of the development of embedded Flash process technology, Read-While-Write (RWW, read while writing) technology has become the best solution to improve the read and write speed of embedded Flash in current chip design.

[0003] Currently, the following three methods are commonly used to implement the RWW function: The first method is to use the underlying driver to pre-move some key code or data to other storage media (such as RAM) on the chip, thereby indirectly implementing the RWW function. Although this method can simulate the effect of RWW to a certain extent, it is not a true RWW function. It relies on additional memory to temporarily store code and data, which is limited by memory capacity and how to reasonably divide the code to ensure that the key parts can run in memory.

[0004] The second way is to use the Harvard architecture storage method, which stores instructions and data in different physical memories. Accessing these memories through independent buses can realize the reading and writing of instructions and data. However, the design of the Harvard architecture is not suitable for all scenarios. Under the Harvard architecture, due to the existence of independent instruction cache and data cache, this may cause cache consistency problems; and because the instruction memory is separated from the data memory, the Harvard architecture does not allow instructions to be executed directly from the data memory, so the implementation of self-modifying code requires additional steps to synchronize changes in the instruction memory, which increases the complexity of the system.

[0005] The third method is for IP (Intellectual Property) manufacturers to physically partition the Flash storage array and implement the RWW function by adding detection circuits or encoding and decoding circuits. However, this method requires complex architecture design, which not only increases the complexity of chip design, but also leads to increased production costs. In addition, not all IP manufacturers support the RWW function.

[0006] Therefore, how to improve the application scenarios of the read-while-write function of embedded Flash and reduce the production cost of Flash chips has become a technical problem that needs to be solved urgently. Summary of the invention

[0007] The present invention provides an embedded Flash reading and writing method, an embedded Flash and an electronic device, so as to solve the defects in the prior art that the RWW function is limited in scenarios when implemented by Harvard architecture, and is dependent on IP manufacturers and has high costs when implemented by Flash hardware.

[0008] The present invention provides a method for reading and writing an embedded Flash, wherein the embedded Flash comprises a plurality of spliced ​​intellectual property modules; a read channel of the embedded Flash has an independent address signal line and a chip select signal for each of the intellectual property modules; a write channel of the embedded Flash has control signals required by all the intellectual property modules and multiplexes a read enable signal; the method for reading and writing the embedded Flash comprises: The Flash storage area is divided into two memory banks, each of which performs read and write operations independently. The logical address of each bank changes dynamically. One bank is used to store the data of the intellectual property module currently being read, and the other bank is used to store the data of all other intellectual property modules. This allows the embedded Flash to be accessed through the Flash controller, and any other intellectual property module can be read simultaneously when a write operation is performed on one intellectual property module.

[0009] According to a method for reading and writing an embedded Flash provided by the present invention, the channel selection signal of the intellectual property module is switched to the write channel by default, and the method for reading and writing an embedded Flash further includes: When the read operation is enabled, the intellectual property module that needs to be switched to the read channel is determined based on the read address; When the write operation is enabled, the IP module that needs to switch to the read channel is determined based on the write address.

[0010] According to an embedded Flash reading and writing method provided by the present invention, the chip selection signal of the current intellectual property module is determined based on the following steps: If the current read / write operation is for the current intellectual property module, the initial chip select signal of the controller is assigned to the chip select signal of the current intellectual property module; If the current read / write operation is not for the current intellectual property module, the chip select signal of the current intellectual property module is set to a high level.

[0011] According to a method for reading and writing an embedded Flash provided by the present invention, output data output to the controller is determined based on the following steps: If the channel selection signal of any intellectual property module is at a high level, the IP indication bit of the output data chip selection signal is determined based on the read address, wherein the IP indication bit is a bit used to indicate the selected intellectual property module; If the channel selection signals of all intellectual property modules are at low level, the IP indicator bit of the output data chip selection signal is determined based on the write address; If the value of the IP indicator is the same as the intellectual property module number corresponding to the current read / write operation, then determining that the output data is the output of the intellectual property module corresponding to the IP indicator; If the value of the IP indicator bit is different from the intellectual property module number corresponding to the current read / write operation, the output data is cleared.

[0012] According to a method for reading and writing an embedded Flash provided by the present invention, the method for reading and writing an embedded Flash further includes: The addresses issued by the processor are remapped so that the CODE areas of each intellectual property module are logically connected continuously, the DATA areas of each intellectual property module are logically connected continuously, and the NVR areas of each intellectual property module are logically connected continuously.

[0013] According to an embedded Flash reading and writing method provided by the present invention, the address of the CODE area is remapped based on the following steps: Shift the 16th to 19th bits of the received system access address one bit to the left to obtain a bit subset; The bit subset is sequentially concatenated with bits 0 to 15 of the system access address to obtain a new CODE area address.

[0014] According to an embedded Flash reading and writing method provided by the present invention, the address of the DATA area is remapped based on the following steps: The 19th bit of the received system access address, the 15th to 16th bits of the system access address, the first preset value and the 0th to 14th bits of the system access address are concatenated to obtain a new DATA area address, wherein the first preset value is "10".

[0015] According to an embedded Flash reading and writing method provided by the present invention, the address of the NVR area is remapped based on the following steps: The 10th to 12th bits of the received system access address, the second preset value and the 0th to 9th bits of the system access address are concatenated to obtain a new NVR area address, where the second preset value is "0000000".

[0016] The present invention also provides an embedded Flash, which includes a plurality of spliced ​​intellectual property modules; the read channel of the embedded Flash has an independent address signal line and a chip select signal for each of the intellectual property modules; the write channel of the embedded Flash has control signals required by all the intellectual property modules and multiplexes a read enable signal; the embedded Flash uses any of the above-mentioned embedded Flash read and write methods to read and write data.

[0017] The present invention also provides an electronic device, comprising the embedded Flash as described above, or using any of the embedded Flash reading and writing methods as described above to read and write data.

[0018] The present invention provides an embedded Flash reading and writing method, an embedded Flash and an electronic device, wherein the embedded Flash comprises a plurality of spliced ​​intellectual property modules; the read channel of the embedded Flash has an independent address signal line and a chip select signal for each of the intellectual property modules; the write channel of the embedded Flash has control signals required by all the intellectual property modules and multiplexes a read enable signal; the Flash storage area is divided into two memory banks Bank, each of the Banks performs read and write operations independently, the logical address of each Bank changes dynamically, one Bank is used for data storage of the intellectual property module currently being read, and the other Bank is used for data storage of all other intellectual property modules, so that when the embedded Flash is accessed through a Flash controller, when a write operation is performed on an intellectual property module, any other intellectual property module can be read simultaneously. The present invention realizes the read-while-write function inside the Flash controller by splicing multiple embedded Flash intellectual property modules, and supports Harvard architecture and von Neumann architecture at the same time, and can be applied to various application scenarios; the RWW function is realized inside the controller, and there is no need to add additional short-circuit detection or encoding and decoding circuits for Flash, thereby reducing the Flash production cost and being independent of IP manufacturers. When the IP itself does not support the RWW function, this solution can be used to realize the read-while-write of the embedded Flash, thereby improving the access efficiency of the chip storage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1It is a flow chart of the embedded Flash reading and writing method provided by the present invention; Figure 2 It is a schematic diagram of the division of the read and write channels provided by the present invention. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0022] It should be noted that in the description of the embodiments of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "include one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. The orientation or position relationship indicated by the terms "upper", "lower" and the like is based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention. Unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be a connection between two elements. For those skilled in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0023] The terms "first", "second", etc. in this application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" represents at least one of the connected objects, and the character " / " generally indicates that the objects associated with each other are in an "or" relationship.

[0024] Combine the following Figure 1-Figure 2 The embedded Flash reading and writing method, device, electronic device and storage medium provided in the embodiments of the present invention are described.

[0025] Figure 1 It is a flow chart of the embedded Flash reading and writing method provided by the present invention, such as Figure 1 As shown, the embedded Flash includes a plurality of spliced ​​intellectual property modules; the read channel of the embedded Flash has an independent address signal line and a chip select signal for each of the intellectual property modules; the write channel of the embedded Flash has control signals required by all the intellectual property modules and multiplexes a read enable signal; the read and write method of the embedded Flash includes: Step 100, divide the Flash storage area into two memory banks Bank, each Bank performs read and write operations independently, and the logical address of each Bank changes dynamically. One Bank is used to store the data of the intellectual property module currently being read, and the other Bank is used to store the data of all other intellectual property modules, so that when the embedded Flash is accessed through the Flash controller, when a write operation is performed on an intellectual property module, any other intellectual property module can be read at the same time.

[0026] In the embodiment of the present invention, multiple intellectual property (IP) modules are spliced ​​together. For ease of understanding, the following embodiments are described by taking the splicing of 6 IP modules as an example.

[0027] In the embodiment of the present invention, the processor accesses the intellectual property module through the Flash controller. When a write operation is performed on one of the intellectual property modules, any other intellectual property module can be read at the same time. When the intellectual property module being read is in the process of writing, it is necessary to wait for the completion of the ongoing write operation before reading the intellectual property module. The flexibility of Bank logic division is achieved through the dynamic multi-intellectual property module logic channel design. The logical address of the Bank is in dynamic change, which improves the effective utilization of the storage area compared with the fixed Bank division scheme. Specifically: The Flash storage area is logically divided into two banks, one bank (Bank1) is the intellectual property module currently being read, and the other bank (Bank2) is the remaining intellectual property modules. Taking the reading of IP0 as an example, the bank division is shown in Table 1 below.

[0028] Table 1 Bank division table

[0029] Figure 2Schematic diagram of the division of the read and write channels provided by the present invention, such as Figure 2 As shown in the figure, the read channel has independent address signal lines and chip select signals; the write channel has the control signals required by all intellectual property modules, and the address signal lines and chip select signals multiplex the read enable signal, that is, the multiplexed read enable signal is used to control the write channel. Combining bank division and write channel division, the Flash controller can have the RWW function, where the read channel corresponds to Bank1 and the write channel corresponds to Bank2.

[0030] The embodiment of the present invention provides a method for reading and writing an embedded Flash, wherein the embedded Flash includes a plurality of spliced ​​intellectual property modules; the read channel of the embedded Flash has an independent address signal line and a chip select signal for each of the intellectual property modules; the write channel of the embedded Flash has control signals required by all the intellectual property modules and multiplexes a read enable signal; the Flash storage area is divided into two memory banks, each of which performs read and write operations independently, and the logical address of each of the banks changes dynamically, one bank is used for data storage of the intellectual property module currently being read, and the other bank is used for data storage of all other intellectual property modules, so that when the embedded Flash is accessed through the Flash controller, when a write operation is performed on an intellectual property module, any other intellectual property module can be read at the same time. The present invention realizes the read-while-write function inside the Flash controller by splicing multiple embedded Flash intellectual property modules, and supports Harvard architecture and von Neumann architecture at the same time, and can be applied to various application scenarios; the RWW function is realized inside the controller, and there is no need to add additional short-circuit detection or encoding and decoding circuits for Flash, thereby reducing the Flash production cost and being independent of IP manufacturers. When the IP itself does not support the RWW function, this solution can be used to realize the read-while-write of the embedded Flash, thereby improving the access efficiency of the chip storage area.

[0031] In an optional embodiment, the channel selection signal of the intellectual property module is switched to the write channel by default, and the embedded Flash reading and writing method further includes: When the read operation is enabled, the intellectual property module that needs to be switched to the read channel is determined based on the read address; When the write operation is enabled, the IP module that needs to switch to the read channel is determined based on the write address.

[0032] In the embodiment of the present invention, the switching signal of the read-write channel is switched to the write channel by default, so that the unaccessed intellectual property module can be kept in the STANDBY state, avoiding the chip select signal of other unaccessed intellectual property modules from being pulled low and exiting the STANDBY state.

[0033] In the embodiment of the present invention, the channel selection signal can be determined by the read and write addresses. Each intellectual property module has a channel selection signal bank_sel. When the read operation is enabled, the intellectual property module that needs to be switched to the read channel is determined according to the read address. At the same time, the intellectual property module that needs to be written is switched to the write channel, and then the intellectual property module that needs to be written is determined according to the write address. Other IPs that have not been accessed are not chip selected and are switched to the write channel by default.

[0034] In the embedded Flash reading and writing method provided by the embodiment of the present invention, the switching signal of the reading and writing channel is switched to the writing channel by default, so that the intellectual property module that is not accessed is in the STANDBY state, thereby reducing the power consumption of the chip.

[0035] In an optional embodiment, the chip select signal of the current intellectual property module is determined based on the following steps: If the current read / write operation is for the current intellectual property module, the initial chip select signal of the controller is assigned to the chip select signal of the current intellectual property module; If the current read / write operation is not for the current intellectual property module, the chip select signal of the current intellectual property module is set to a high level.

[0036] Taking the splicing of 6 intellectual property modules as an example, the following hardware description statement can be used to implement the selection of multi-speed Flash IP chip select signal: CSN=(wr_addr[19:17]=IP_numb)|(RD&(rd_addr[19:17]=IP_numb))?CEb:1'b1; Among them, CSN is the chip select signal of the current intellectual property module, CEb is the initial chip select signal of the controller, IP_numb is the number of the IP module, here it is 0-5, RD is the read enable signal, wr_addr indicates the write address, and rd_addr indicates the read address. If any of the conditions wr_addr[19:17]=IP_numb and RD&(rd_addr[19:17]=IP_numb) is true, the initial chip select signal of the controller is assigned to the chip select signal of the current intellectual property module, otherwise the chip select signal of the current intellectual property module is set to a high level "1" (the chip select signal is valid at a low level). Among them, wr_addr[19:17]=IP_numb means that the values ​​of the 17th to 19th bits of the write address are the same as the number of the target IP module, indicating that the current write operation is for the current intellectual property module; RD&(rd_addr[19:17]=IP_numb) means that the read enable signal RD is high (that is, there is a read operation) and the values ​​of the 17th to 19th bits of the read address are the same as the number of the target IP module, indicating that the current read operation is for the current intellectual property module; 1'b1 represents a binary value with a bit width of 1 and a value of 1, where the first 1 represents the bit width of 1, b represents binary, and the second 1 represents the actual value.

[0037] The embedded Flash reading and writing method provided by the embodiment of the present invention assigns the initial chip select signal of the controller to the current intellectual property module only when the current operation is for the current intellectual property module, otherwise the chip select signal of the current intellectual property module is set to an invalid state to avoid incorrect selection of the intellectual property module.

[0038] In an optional embodiment, the output data output to the controller is determined based on the following steps: If the channel selection signal of any intellectual property module is at a high level, the IP indication bit of the output data chip selection signal is determined based on the read address, wherein the IP indication bit is a bit used to indicate the selected intellectual property module; If the channel selection signals of all intellectual property modules are at low level, the IP indicator bit of the output data chip selection signal is determined based on the write address; If the value of the IP indicator is the same as the intellectual property module number corresponding to the current read / write operation, then determining that the output data is the output of the intellectual property module corresponding to the IP indicator; If the value of the IP indicator bit is different from the intellectual property module number corresponding to the current read / write operation, the output data is cleared.

[0039] In the embodiment of the present invention, the following hardware description statement is used to implement the data output selection of multiple intellectual property modules: dout_cs[2:0] = |bank_sel[5:0]? rd_addr[19:17] : wr_addr[19:17]; DOUT[35:0] = (dout_cs[2:0]= IP_numb) ? DOUT_numb[35:0] : 36'b0; Among them, dout_cs[2:0] is a 3-bit wide signal, indicating the IP indicator bit of the output data chip select signal; DOUT_numb indicates the data output of the corresponding IP, and DOUT indicates the data output to the controller after multiple IPs are spliced. bank_sel indicates the channel selection signal, bank_sel[5:0] is a 6-bit wide signal, each bit corresponds to an intellectual property module. If the value of a certain bit is "1", it means that the IP module corresponding to the bit is selected. |bank_sel[5:0] is the result of the logical OR operation of all 6 bits of bank_sel. If any bit in bank_sel is 1, the value of the entire expression is 1, otherwise it is 0. Here, the value of bank_sel is used to select the high-order part of the read address rd_addr or the write address wr_addr as the value of dout_cs. If |bank_sel[5:0] is true (that is, at least one bit in bank_sel is 1), rd_addr[19:17] is selected as the value of dout_cs[2:0]; if |bank_sel[5:0] is false (that is, all bank_sel are 0), wr_addr[19:17] is selected as the value of dout_cs[2:0].

[0040] Here, when the lowest three bits of dout_cs are equal to IP_numb, it indicates that the value of the IP indicator bit is the same as the intellectual property module number corresponding to the current read / write operation, and the value of DOUT_numb is assigned to DOUT; if they are not equal, it indicates that the value of the IP indicator bit is different from the intellectual property module number corresponding to the current read / write operation, and DOUT is cleared.

[0041] The embedded Flash reading and writing method provided by the embodiment of the present invention outputs the data of the selected intellectual property module, thereby realizing accurate data output in the scenario of splicing multiple intellectual property modules.

[0042] In an optional embodiment, the embedded Flash reading and writing method further includes: The addresses issued by the processor are remapped so that the CODE areas of each intellectual property module are logically connected continuously, the DATA areas of each intellectual property module are logically connected continuously, and the NVR areas of each intellectual property module are logically connected continuously.

[0043] In the embodiment of the present invention, the solution for splicing multiple Flash IPs is to select the chip through the high-order address line. The Flash IP has a CODE area (used to store program code, i.e., execute the instruction set), a DATA area (used to store data that needs to be stored for a long time, such as user configuration, log files, etc.) and an NVR area (the Non-Volatile Register area is used to store key system configuration parameters, calibration data or other one-time programming information), so when splicing IPs, the three areas are spliced ​​continuously. The CODE area of ​​each IP is spliced ​​continuously, the DATA area is spliced ​​continuously, and the NVR area is spliced ​​continuously. The address issued by the processor is remapped to ensure that each area is spliced ​​continuously.

[0044] The embedded Flash reading and writing method provided by the embodiment of the present invention remaps the addresses of the CODE area, DATA area, and NVR area of ​​the intellectual property module respectively, realizes the continuous splicing of the CODE area, DATA area, and NVR area, thereby obtaining a logically continuous and physically independent Flash storage area.

[0045] In an optional embodiment, the address of the CODE area is remapped based on the following steps: Shift the 16th to 19th bits of the received system access address one bit to the left to obtain a bit subset; The bit subset is sequentially concatenated with bits 0 to 15 of the system access address to obtain a new CODE area address.

[0046] According to the Flash IP feature requirements, if the CODE area is accessed, the physical address flash_code_addr

[16] =1'b0 of the CODE area must be satisfied. In the embodiment of the present invention, the address of the CODE area is remapped using the following hardware description statement: flash_code_addr={sys_addr[19:16]<<1, sys_addr[15:0]}; Among them, sys_addr[19:16] extracts the 19th to 16th bits of the system access address, which is a 4-bit wide subset; sys_addr[19:16]<<1 shifts the extracted 4 bits one bit to the left, which actually expands the 4 bits to 5 bits, with the highest bit discarded and the lowest bit increased by one 0; sys_addr[15:0] extracts the 15th to 0th bits of the system access address, which are the lower 16 bits of the address bus and remain unchanged; {sys_addr[19:16]<<1, sys_addr[15:0]} concatenates the 5-bit high-order part after left shift with the unchanged 16-bit low-order part to form a new 21-bit wide address signal flash_code_addr, which is the physical address after remapping.

[0047] The embedded Flash reading and writing method provided by the embodiment of the present invention ensures that the 16th bit is 0, points to the access CODE area, realizes the remapping of the CODE area, and ensures that the CODE area is logically continuous and physically independent.

[0048] In an optional embodiment, the address of the DATA area is remapped based on the following steps: The 19th bit of the received system access address, the 15th to 16th bits of the system access address, the first preset value and the 0th to 14th bits of the system access address are concatenated to obtain a new DATA area address, wherein the first preset value is "10".

[0049] According to the Flash IP feature requirements, if the DATA area is accessed, the physical address of the DATA area flash_data_addr[16:15]=2'b10 must be satisfied. In the embodiment of the present invention, the address of the DATA area is remapped using the following hardware description statement: flash_data_addr={sys_addr

[19] ,sys_addr[16:15],2'b10,sys_addr[14:0]}; Among them, sys_addr

[19] extracts the 19th bit of the system access address, sys_addr[16:15] extracts the 16th to 15th bits of the system access address, 2'b10 ensures that flash_data_addr[16:15]=2'b10, and sys_addr[14:0] extracts the lower 15 bits of the system access address and remains unchanged; these parts are spliced ​​together to get the physical address flash_data_addr.

[0050] The embedded Flash reading and writing method provided by the embodiment of the present invention ensures that the 15th bit is 0 and the 16th bit is 1, points to access the DATA area, implements remapping of the DATA area, and ensures that the DATA area is logically continuous and physically independent.

[0051] In an optional embodiment, the address of the NVR area is remapped based on the following steps: The 10th to 12th bits of the received system access address, the second preset value and the 0th to 9th bits of the system access address are concatenated to obtain a new NVR area address, where the second preset value is "0000000".

[0052] In the embodiment of the present invention, the address of the NVR area is remapped using the following hardware description statement: flash_sysmem_addr={sys_addr[12:10],7'b0,sys_addr[9:0]};; Among them, sys_addr[12:10] extracts the 12th to 10th bits of the system access address, 7'b0 is "0000000", and sys_addr[9:0] extracts the 9th to 0th bits of the system access address; these parts are spliced ​​together to get the physical address flash_sysmem_addr.

[0053] The embedded Flash reading and writing method provided by the embodiment of the present invention realizes the remapping of the NVR area, and ensures that the NVR area is logically continuous and physically independent.

[0054] The present invention also provides an embedded Flash, which includes a plurality of spliced ​​intellectual property modules; the read channel of the embedded Flash has an independent address signal line and a chip select signal for each of the intellectual property modules; the write channel of the embedded Flash has control signals required by all the intellectual property modules and multiplexes a read enable signal; the embedded Flash uses the embedded Flash read and write method described in any of the above embodiments to read and write data.

[0055] The present invention further provides an electronic device, comprising the embedded Flash as described in the above embodiment, or using the embedded Flash reading and writing method as described in any of the above embodiments to read and write data.

[0056] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0057] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for reading and writing embedded Flash, characterized in that: The embedded Flash includes a plurality of spliced ​​intellectual property modules; the read channel of the embedded Flash has an independent address signal line and a chip select signal for each of the intellectual property modules; The write channel of the embedded Flash has the control signals required by all the intellectual property modules and multiplexes the read enable signal; The embedded Flash reading and writing method comprises: The Flash storage area is divided into two memory banks, each of which performs read and write operations independently. The logical address of each bank changes dynamically. One bank is used to store the data of the intellectual property module currently being read, and the other bank is used to store the data of all other intellectual property modules. This allows the embedded Flash to be accessed through the Flash controller, and any other intellectual property module can be read simultaneously when a write operation is performed on one intellectual property module.

2. The method for reading and writing embedded Flash according to claim 1, characterized in that: The channel selection signal of the intellectual property module is switched to the write channel by default, and the embedded Flash reading and writing method further includes: When the read operation is enabled, the intellectual property module that needs to be switched to the read channel is determined based on the read address; When the write operation is enabled, the IP module that needs to switch to the read channel is determined based on the write address.

3. The method for reading and writing embedded Flash according to claim 2, characterized in that: Determine the chip select signal of the current intellectual property module based on the following steps: If the current read / write operation is for the current intellectual property module, the initial chip select signal of the controller is assigned to the chip select signal of the current intellectual property module; If the current read / write operation is not for the current intellectual property module, the chip select signal of the current intellectual property module is set to a high level.

4. The method for reading and writing embedded Flash according to claim 3, characterized in that: The output data to be output to the controller is determined based on the following steps: If the channel selection signal of any intellectual property module is at a high level, the IP indication bit of the output data chip selection signal is determined based on the read address, wherein the IP indication bit is a bit used to indicate the selected intellectual property module; If the channel selection signals of all intellectual property modules are at low level, the IP indicator bit of the output data chip selection signal is determined based on the write address; If the value of the IP indicator is the same as the intellectual property module number corresponding to the current read / write operation, then determining that the output data is the output of the intellectual property module corresponding to the IP indicator; If the value of the IP indicator bit is different from the intellectual property module number corresponding to the current read / write operation, the output data is cleared.

5. The method for reading and writing embedded Flash according to claim 4, characterized in that: The embedded Flash reading and writing method further includes: The addresses issued by the processor are remapped so that the CODE areas of each intellectual property module are logically connected continuously, the DATA areas of each intellectual property module are logically connected continuously, and the NVR areas of each intellectual property module are logically connected continuously.

6. The method for reading and writing embedded Flash according to claim 5, characterized in that: The address of the CODE area is remapped based on the following steps: Shift the 16th to 19th bits of the received system access address one bit to the left to obtain a bit subset; The bit subset is sequentially concatenated with bits 0 to 15 of the system access address to obtain a new CODE area address.

7. The embedded Flash reading and writing method according to claim 5, characterized in that: The address of the DATA area is remapped based on the following steps: The 19th bit of the received system access address, the 15th to 16th bits of the system access address, the first preset value and the 0th to 14th bits of the system access address are concatenated to obtain a new DATA area address, wherein the first preset value is "10".

8. The method for reading and writing embedded Flash according to claim 5, characterized in that: The address of the NVR area is remapped based on the following steps: The 10th to 12th bits of the received system access address, the second preset value and the 0th to 9th bits of the system access address are concatenated to obtain a new NVR area address, where the second preset value is "0000000".

9. An embedded Flash, characterized in that: The embedded Flash includes multiple spliced ​​intellectual property modules; the read channel of the embedded Flash has independent address signal lines and chip select signals for each of the intellectual property modules; the write channel of the embedded Flash has control signals required by all the intellectual property modules and multiplexes the read enable signal; the embedded Flash uses the embedded Flash read and write method as described in any one of claims 1 to 8 to read and write data.

10. An electronic device, characterized in that: The method comprises the embedded Flash as claimed in claim 9, or uses the embedded Flash reading and writing method as claimed in any one of claims 1 to 8 to perform data reading and writing.

Images