A control method for a storage device and a storage device

Abstract

The present invention provides a control method for a storage device and a storage device. The control method includes the following steps: when data reading fails, perform a decoding process on the parity bits and information bits of the read data; in the decoding process, obtain and record the decoding iteration count; set a first iteration threshold, when the decoding iteration count reaches the first iteration threshold, while performing the next decoding iteration, change the read voltage and reread the data, wherein the reread data is temporarily stored in the storage device; set a second iteration threshold, if the decoding iteration count reaches the second iteration threshold, report that data reading fails, and perform a decoding process on the temporarily stored reread data; and loop the decoding process and the rereading process until the data is successfully read or until data reading still fails after traversing all read voltages. The present invention provides a control method for a storage device and a storage device, which can balance the reading efficiency of the storage device and the allocation and utilization efficiency of storage resources.

Description

Technical Field

[0001] The present invention relates to the field of storage technologies, and particularly to a control method for a storage device and a storage device. Background Art

[0002] Due to the change in the stored charge amount, the stored data in the flash memory is prone to errors. Therefore, when reading the data in the flash memory, error correction processing needs to be performed on the data in the flash memory. The error correction processing steps for the data stored in the flash memory involve a process of multiple iterative calculations to obtain the correct data. Multiple iterations will continuously occupy storage resources. When the number of iterations is too high and the correct result still cannot be obtained, the execution strategy of the iterative calculation decoding by the storage device will be related to the performance of the storage device. And how to balance the performance and latency performance of the storage device is a difficult problem in storage design. Summary of the Invention

[0003] The purpose of the present invention is to provide a control method for a storage device and a storage device, which can take into account the reading efficiency of the storage device and the allocation and utilization efficiency of storage resources.

[0004] To solve the above technical problems, the present invention is realized through the following technical solutions:

[0005] The present invention provides a control method for a storage device, including the following steps:

[0006] When the data reading fails, perform a decoding process on the check bits and information bits of the read data;

[0007] In the decoding process, obtain and record the decoding iteration count;

[0008] Set a first iteration threshold. When the decoding iteration count reaches the first iteration threshold, while performing the next decoding iteration, change the read voltage and reread the data, where the reread data is temporarily stored in the storage device;

[0009] Set a second iteration threshold. If the decoding iteration count reaches the second iteration threshold, report that the data reading fails, and perform a decoding process on the temporarily stored reread data; and

[0010] Loop the decoding process and the rereading process until the data is successfully read or until the data reading fails after traversing all the read voltages.

[0011] In an embodiment of the present invention, the step of setting the first iteration threshold includes:

[0012] When the storage device is idle, obtain the decoding iteration count when each storage block is decoded successfully, and obtain the decoding success rate of each storage block at each decoding iteration count;

[0013] Compare the decoding success rates of two adjacent decoding iteration times in sequence, and obtain the difference of the decoding success rates; and

[0014] When the difference of the decoding success rates first exceeds the allowable range, use the decoding iteration time corresponding to the larger decoding success rate as the first iteration threshold.

[0015] In an embodiment of the present invention, the step of setting the second iteration threshold includes:

[0016] When the storage device is idle, obtain the decoding iteration times when each storage block is decoded successfully, and obtain the decoding success rates of each storage block at each decoding iteration time; and

[0017] Set a near-zero threshold. When the decoding success rate is less than the near-zero threshold, set the decoding iteration time corresponding to the decoding success rate as the second iteration threshold.

[0018] In an embodiment of the present invention, the steps of the rereading process include:

[0019] When the decoding iteration time reaches the first iteration threshold, generate a warning signal;

[0020] Under the trigger of the warning signal, select another read voltage from the read voltmeter, and read the data according to the reselected read voltage; and

[0021] Store the reread data in the power-off volatile area of the storage device.

[0022] In an embodiment of the present invention, before performing the decoding iteration process on the reread data, determine whether the reread data passes the decoding verification. If it passes the decoding verification, directly upload the reread data to the host computer. If it does not pass the decoding verification, perform the decoding iteration process on the reread data.

[0023] In an embodiment of the present invention, the following steps are further included:

[0024] When the decoding process successfully decodes, if the storage device is in a busy state, terminate the rereading process;

[0025] When the decoding process successfully decodes, if the storage device is in a callable state, delete the reread data; and

[0026] When the decoding process successfully decodes, upload the successfully decoded data to the host computer.

[0027] In an embodiment of the present invention, in the step of setting the first iteration threshold and the second iteration threshold, the first iteration threshold and the second iteration threshold are preset data and are stored in a power-fail non-volatile area of the storage device.

[0028] In an embodiment of the present invention, in the decoding process, according to the parity bits, the error bits in the information bits are iteratively corrected by the LDPC code.

[0029] The present invention provides a storage device, including:

[0030] A flash memory chip;

[0031] A cache chip, electrically connected to the flash memory chip;

[0032] A decoding module, configured to perform a decoding process on the parity bits and information bits of the read data when the read data fails, and in the decoding process, the decoding module obtains and records the decoding iteration count;

[0033] A threshold setting module, configured to set a first iteration threshold and a second iteration threshold;

[0034] A reading module, configured to read data from the flash memory chip, and configured to, when the decoding iteration count reaches the first iteration threshold, while performing the next decoding iteration, change the read voltage and re-read the data, wherein the re-read data is temporarily stored in the cache chip;

[0035] A process control module, configured to report that the read data fails when the decoding iteration count reaches the second iteration threshold, and perform a decoding process on the temporarily stored re-read data; and

[0036] A loop control module, configured to loop the decoding process and the re-reading process until the data is successfully read or until the read data fails after traversing the read voltages.

[0037] In an embodiment of the present invention, the storage device includes a timing control module, the timing control module is connected to the reading module and the decoding module, and the timing control module is configured to output a first timing signal and a second timing signal simultaneously when the decoding iteration count reaches the first iteration threshold, wherein the first timing signal is used to trigger an increment of the decoding iteration count and trigger a new decoding iteration process, and the second timing signal is used to trigger the re-reading process.

[0038] As described above, the present invention uses timing control to trigger voltage rereading, combines double means of LDPC decoding iteration and voltage adjustment to improve the repair probability of complex storage errors, and based on the determination that the decoding success rate approaches zero, avoids invalid calculations, reports uncorrectable errors in a timely manner, and ensures the system's quick response to serious failures. Moreover, the present invention can improve the rationality of storage resource utilization, starts rereading only when reaching the first threshold, and temporarily stores the reread data in the power-off volatile area, which can avoid unnecessary data transfer. After successful decoding, redundant data is intelligently cleared according to the device status, reducing storage fragmentation. And the present invention avoids blind iteration and shortens the average decoding time through preset thresholds and real-time success rate analysis, can make a reasonable prediction of the status of the storage device in combination with the service life of the storage device. And the present invention processes rereading and decoding in parallel, which can improve the decoding efficiency of the storage device, can also obtain an optimal solution between error correction ability and computational overhead, and can also compensate for charge drift caused by temperature and aging, extending the life of the storage device.

[0039] Of course, any product implementing the present invention does not necessarily need to achieve all the above advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0041] Figure 1 It is a flowchart of the control method of the storage device in an embodiment of the present invention.

[0042] Figure 2 It is a flowchart of step S300 in an embodiment of the present invention.

[0043] Figure 3 It is a flowchart of step S310 in an embodiment of the present invention.

[0044] Figure 4 It is a flowchart of step S400 in an embodiment of the present invention.

[0045] Figure 5 It is a schematic structural diagram of the storage device in an embodiment of the present invention.

[0046] In the figure: 10, main controller; 11, decoding module; 12, threshold setting module; 13, reading module; 14, process control module; 15, loop control module; 16, timing control module; 20, cache chip; 30, flash chip; 40, memory. DETAILED DESCRIPTION OF THE INVENTION

[0047] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0048] The control method of the storage device provided by the present invention can be applied to improve the efficiency of reading data from the storage device. The storage medium of the storage device is a flash memory. Please refer to Figure 1 As shown, the present invention provides a control method for a storage device, including step S100 to step S500.

[0049] Step S100: When the data reading fails, perform a decoding process on the check bits and information bits of the read data.

[0050] Step S200: In the decoding process, obtain and record the number of decoding iterations.

[0051] Step S300: Set a first iteration threshold. When the number of decoding iterations reaches the first iteration threshold, while performing the next decoding iteration, change the read voltage and reread the data, where the reread data is temporarily stored in the storage device.

[0052] Step S400: Set a second iteration threshold. If the number of decoding iterations reaches the second iteration threshold, report that the data reading fails, and perform a decoding process on the temporarily stored reread data.

[0053] Step S500: Loop the decoding process and the rereading process until the data is successfully read or until the data reading fails after traversing all the read voltages.

[0054] Please refer to Figure 1As shown, in an embodiment of the present invention, when writing data to a storage device, the user data to be written is processed by LDPC codes to generate check data for the user data. Among them, the user data is written as the encoded information bits into the power-fail non-volatile area of the storage device, and the check data generated after encoding processing is also synchronously written into the power-fail non-volatile area of the storage device. In this embodiment, the check bits and the information bits can be written into the same storage page or storage block. Wherein, the storage block is the physical block (block) of the flash memory, and the storage page is the physical page (page) of the flash memory. When reading data from the storage device, a read voltage is set, and at the read voltage, the information bits and the check bits are read. In step S100, when the data reading fails, a decoding process is performed on the check bits and the information bits of the read data. In this embodiment, when the decoding iteration count reaches the second iteration threshold and still fails to decode successfully, it is determined that the data reading fails. It should be noted that, in this embodiment, when reading data for the first time, the data is verified and processed by means of Error Checking and Correction (ECC). If the ECC verification fails, the first data reading fails, and step S100 is executed. When switching the read voltage to start rereading the data, that is, when reading the current data for the second time, if the decoding iteration count reaches the second iteration threshold and the error correction has not been successful, it is determined that the data reading fails. In step S100, the decoding process is based on the check bits, and the error bits in the information bits are iteratively corrected by LDPC codes to finally restore the correct user data.

[0055] Please refer to Figure 1 As shown, in an embodiment of the present invention, it should be noted that, in the decoding process, iterative calculation means are used to correct the information bits. It is very difficult to solve complex errors directly in one calculation, especially when multiple bits are in error at the same time, while the iterative calculation method can optimize the result step by step. In the decoding process, the possible number of error bits in the information bits is guessed based on the check bits. Specifically, for example, some "0"s or some "1"s actually undergo bit flips. And the decoding process will guess which specific "0"s and "1"s are in error. Then, the algorithm is used to verify whether there are contradictions in the guessed error units. If there are no contradictions, the guess is correct and the decoding is successful. If there are contradictions, the process of guessing the number of error bits and algorithm verification is performed for the second time. In this embodiment, each process of proposing a guessed error point and verifying whether the guess is correct is a decoding iteration. Executing the decoding process means looping through the decoding iterations until the iteration stop condition is reached. Each decoding iteration will make the data of the information bits closer to the correct value, and when all contradictions disappear after several loops, it means that the data has been successfully corrected, that is, the decoding is successful. Among them, the selection of the guessed error points is random.

[0056] Please refer to Figure 1As shown, in an embodiment of the present invention, in step S200, the decoding process includes a process of multiple decoding iterations. In this embodiment, whenever a guess of the error point is made, a decoding iteration starts, and the number of decoding iterations is incremented by one. In this embodiment, the number of decoding iterations is recorded and stored. The way to obtain the number of decoding iterations can be achieved by setting a counter and a trigger to achieve stable calculation, or by counting through an algorithm to achieve with lower hardware resource occupancy.

[0057] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, in step S300, a first iteration threshold is used to determine whether to perform parallel decoding and rereading operations. The process of implementing step S300 is based on the simultaneous triggering of timing signals. In this embodiment, a first timing signal and a second timing signal are set. The triggering condition of the first timing signal is the failure of decoding iteration. And the first timing signal is used to trigger the increment of the number of decoding iterations by one and trigger a new decoding iteration process. The triggering condition of the second timing signal is that the current number of decoding iterations reaches the first iteration threshold. And the second timing signal is used to trigger the rereading process. Based on the stable control of the timing signals, the coordinated parallel operation of these two operations can be better coordinated. In other embodiments of the present invention, it can also be achieved by setting a task queue and establishing a task sequence to coordinate the new decoding iteration and rereading processes. In the present invention, step S300 includes steps S310 to step S3

[0058] Step S310: Set the first iteration threshold.

[0059] Step S320: When the number of decoding iterations reaches the first iteration threshold, continue to perform the next decoding iteration.

[0060] Step S330: While performing the next decoding iteration, change the read voltage and reread the data.

[0061] Step S340: When rereading the data and the decoding iteration has not been successful, store the reread data.

[0062] Step S350: When the decoding iteration is successful before rereading the data, terminate the rereading process.

[0063] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, the first iteration threshold can be a preset value or a value obtained by training in the offline state or idle state of the storage device. The preset value is input by the designer and is a fixed value, which can reduce the algorithm complexity of the storage device. In this embodiment, when the first iteration threshold is a value obtained by training, step S310 includes steps S311 to S313.

[0064] Step S311: When the storage device is idle, obtain the decoding iteration count when each storage block is successfully decoded, and obtain the decoding success rate of each storage block at each decoding iteration count.

[0065] Step S312: Compare the decoding success rates of two adjacent decoding iteration counts in sequence, and obtain the difference in the decoding success rates.

[0066] Step S313: When the difference in the decoding success rates first exceeds the allowable range, use the decoding iteration count corresponding to the larger decoding success rate as the first iteration threshold.

[0067] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, in step S311, the storage device being idle means that the storage device currently has no host computer tasks to execute. In this embodiment, the host computer tasks include data writing tasks and data reading tasks. Among them, the data reading task also includes multiple rounds of data rereading tasks in the rereading process. It should be noted that each time a decoding iteration is performed, it is not certain whether the current decoding iteration can be successfully decoded. And as the number of times the storage medium is used increases, the decoding iteration count will also change as the medium wears. In this embodiment, when the storage device fails to read data, the decoding information of the storage device is recorded. The decoding information includes the rereading count of each storage block or each storage page, and the decoding iteration count in a single rereading process. Among them, each time the read voltage is switched, a rereading process starts, so the rereading count is equal to the number of times the read voltage is switched. The rereading count can be recorded by the number of times of rereading the data, or the rereading count can be obtained by the number of times of switching the read voltage. In this embodiment, taking the decoding iteration count as the unit, the decoding success rate of each storage block at each decoding iteration count is statistically analyzed.

[0068] Please refer to Figures 1 to 3As shown, in an embodiment of the present invention, in step S311, for example, the total number of times the storage block performs decoding is 50 times, and the number of times data is read out in the first decoding iteration is 2 times. Then the decoding success rate of the first decoding iteration is 1 / 25. Another example is that the number of times data is read out in the fifth decoding iteration is 10 times. Then the decoding success rate of the fifth decoding iteration is 1 / 5. And so on, to obtain the decoding success rate corresponding to each decoding iteration number. It should be noted that the examples in the present invention are limited in number. When the storage device is actually used, accurate to the decoding times of each storage page and the decoding times in each storage block, the total amount of decoding times of the storage device is extremely large. Therefore, through big data statistics, a relatively accurate decoding success rate can be obtained. And in this embodiment, the initial decoding success rate of each decoding iteration number can be set. The initial decoding success rate is used as an initial value for the storage device. During the use of the storage device, the decoding success rate of each decoding iteration number can be continuously calibrated in the idle state to make the value of the decoding success rate conform to the actual state of the storage device.

[0069] Please refer to Figures 1 to 3 As shown, in an embodiment of the present invention, in step S312, the decoding success rates of two adjacent decoding iteration numbers are compared in sequence, and the difference in the decoding success rate is obtained. Among them, the maximum value of the decoding iteration number is limited by the second iteration threshold. In step S313, through the success rate difference between adjacent decoding iteration numbers, the position where the decoding success rate first shows a cliff-like drop is obtained. In this embodiment, a permitted range can be set to limit the upper limit of the drop in the success rate difference. For example, it is set to 35%, that is, when the success rate difference exceeds the permitted range, it is determined that the decoding success rate of the current decoding iteration shows a cliff-like drop. In this embodiment, among the two decoding iteration numbers with a cliff-like drop in the decoding success rate, the decoding iteration number corresponding to the larger decoding success rate is used as the first iteration threshold. For example, when the decoding is performed for the ninth time, the decoding success rate is 52%, when the decoding is performed for the tenth time, the decoding success rate is 50%, and when the decoding is performed for the eleventh time, the decoding success rate is 12%. Then the tenth time is the demarcation position of the decoding success rate, and the first iteration threshold can be set to 10. In this embodiment, the first iteration threshold can be stored in the non-volatile area of the storage device when the power is off, and the first iteration threshold is called from the storage device every time a judgment is made.

[0070] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, in steps S320 and S330, the decoding iteration process performed at the current read voltage is continuously carried out without being restricted by the first iteration threshold. Therefore, even if the number of decoding iterations reaches the first iteration threshold and the current decoding is not successful, the next decoding iteration is still continued. The increase in the number of decoding iterations can be used for the calculation of the first iteration threshold and the second iteration threshold. In this embodiment, if the verification of the current decoding iteration fails, it is determined that the current decoding iteration fails, and a first timing signal can be issued. It should be noted that the first timing signal can trigger an increment in the number of decoding iterations. However, due to device delay, in fact, the increment in the number of decoding iterations can occur when the current round of decoding iteration is determined to fail and the next round of decoding iteration has not yet started, or it can also occur when the next round of decoding iteration starts but the error guessing point has not yet been performed. Triggered by the first timing signal, the next decoding iteration starts. Specifically, a new round of error point guessing starts. In this embodiment, when the number of decoding iterations reaches the first iteration threshold, the occurrence of a second timing signal is triggered. Triggered by the second timing signal, the storage device can establish a reread task and start the reread task. It should be noted that the increase in the number of decoding iterations occurs before the start of the current round of decoding iteration behavior. Therefore, the occurrence of the second timing signal is before the start of the current round of decoding iteration behavior. In this embodiment, the reread process and the next decoding iteration process are independent of each other. After the reread task is established, the storage device switches the read voltage and rereads the data. In this embodiment, for the switching of the read voltage, a new unused read voltage can be selected from the read voltage table provided by the manufacturer. In another embodiment of the present invention, the switching of the read voltage can also be an automatic voltage adjustment. For example, the read voltage is adjusted step by step until the read voltage traverses the readable voltage range. For example, if the read voltage of the current round is 3V, with a step value of 0.1V, the new read voltage can be set to 2.9V or 3.1V. Among them, the second timing signal, as the timing signal for starting the reread process, can also be understood as a kind of warning signal.

[0071] Please refer to Figure 1 and Figure 2As shown, in an embodiment of the present invention, after the current decoding iteration ends, if the decoding iteration is successful, it is determined whether the storage device is busy at this time. If it is in a busy state, the storage device is still executing the rereading process at this time, and it can be determined that the reread data has not been completely read out. At this time, step S350 is executed to terminate the rereading process, thereby saving storage resources. Then, the decoded successful data is used as the read-out data and uploaded to the host computer. If the storage device is not in a busy state at this time, step S340 is executed. At this time, the reread data has been read out, and the reread data is automatically stored in the power-fail volatile area of the storage device, and then the reread data is deleted. In other embodiments of the present invention, it is also possible to use whether the reread data has been read out as a judgment criterion. For example, after the reread data is read out, the reread data is stored in the power-fail volatile area of the storage device, and at the same time, it is judged whether the decoding has been successful. If the decoding is successful, the data after successful decoding is directly uploaded and the reread data is deleted. If the decoding is still not successful, no operation is performed. It should be noted that it is impossible to know specifically which decoding iteration the decoding is successful in. Therefore, in this embodiment, taking the decoding iteration as the benchmark can save storage resources, and the judgment method is simple and the efficiency is higher.

[0072] Please refer to Figure 1 and Figure 2 As shown, in an embodiment of the present invention, when the number of decoding iterations of the current data reaches the first iteration threshold, before starting the rereading process, it is determined whether the available read voltages have been traversed. If the available read voltages have been traversed, the rereading process is stopped from starting, that is, although the first iteration threshold is reached, the reread data is not obtained.

[0073] Please refer to Figure 1 and Figure 4 As shown, in an embodiment of the present invention, in step S400, by setting a second iteration threshold, the number of decoding iterations is prevented from being too large and occupying too much storage resources. Wherein step S400 includes step S410 to step S430.

[0074] Step S410, set the second iteration threshold.

[0075] Step S420, if the number of decoding iterations of the current read data reaches the second iteration threshold, report that the read-out data fails.

[0076] Step S430, when judging to obtain the current failed data, determine whether the available read voltages have been traversed. If the available read voltages have been traversed, end the data read-out process.

[0077] Step S440, if the number of decoding iterations of the current read data reaches the second iteration threshold and the available read voltages have not been traversed, start the decoding iteration process for the reread data.

[0078] Please refer to Figure 1 、 Figure 4 and Figure 5 As shown, in an embodiment of the present invention, step S410 includes steps S411 to S412.

[0079] Step S411: When the storage device is idle, obtain the decoding iteration times when each storage block is decoded successfully, and obtain the decoding success rate of each storage block at each decoding iteration time.

[0080] Step S412: Set a near-zero threshold. When the decoding success rate is less than the near-zero threshold, set the decoding iteration times corresponding to the decoding success rate as the second iteration threshold.

[0081] Please refer to Figure 1 、 Figure 4 and Figure 5 As shown, in an embodiment of the present invention, step S411 is the same as step S311 and can be combined into the same step. In another embodiment of the present invention, the second iteration threshold can be a preset value, such as 30 times. In step S412, the near-zero threshold is, for example, 0 to 5%, and specifically, for example, 5%. When the decoding success rate is less than the near-zero threshold, it means that the possibility of successful decoding is already very low, and continuing to decode will only occupy more storage resources. In the case of a large number of sample trainings, when the decoding iteration times are greater than the first iteration threshold, as the decoding iteration times increase, the decoding success rate will also continuously decrease. Among them, the second iteration threshold is greater than the first iteration threshold. In step S420, when the decoding iteration times reach the second iteration threshold, it is directly determined that the data read out at the current read voltage is decoded failed, that is, report that the data read out this time is read failed. Before performing decoding iteration on the reread data, execute step S430 to determine whether it is already the last one among the available read voltages when obtaining the currently failed read data, that is, it can be determined whether the read voltages have been traversed currently. The available read voltages can be the read voltage data stored in the read voltage table, or the read voltage data that meets the offset voltage range configured by the upper-layer software. When all the voltages in the read voltage table have been tried, or the read voltages have traversed the preset offset range, then the read voltages are in the traversed state. In the case of traversing the read voltages, the reread data is empty, so the result of unread data can be directly uploaded to the host computer. If the read voltages have not been traversed yet, at this time, the storage device memory stores the reread data, and the decoding iteration can be performed on the reread data.

[0082] Please refer to Figures 1 to 4As shown, in an embodiment of the present invention, in step S500, the decoding process of the reread data repeats steps S100 to S400 until the data is successfully read out or the data readout fails to be reported to the host computer. Before executing the decoding iteration process of the reread data, the reread data is decoded to determine whether the data is successfully read out under the new read voltage. If the data is successfully read out, there is no need to execute the decoding iteration process, and the successfully read data can be directly uploaded to the host computer. If the data is not successfully read out, the decoding iteration process of the reread data is continued. And so on, steps S100 to S400 are looped until the data is successfully read out or it is determined that the data cannot be read out. In this embodiment, after the reread process is started, if the decoding process is successfully decoded, the successfully decoded data is uploaded to the host computer.

[0083] Please refer to Figures 1 to 4 As shown, it should be noted that although the first iteration threshold and the second iteration threshold need to be set in the control method of the present invention, the setting of the first iteration threshold and the second iteration threshold both occur in the idle stage of the storage device. When performing decoding iteration, the step of obtaining the first iteration threshold and the second iteration threshold refers to directly calling the values from the storage device. In this embodiment, the first iteration threshold and the second iteration threshold can be solidified in the power-off non-volatile area of the storage device, for example, stored in the metadata area of the flash memory. The first iteration threshold and the second iteration threshold can be loaded into the memory 40 for the algorithm to call when the system is started, or can be configured by the upper-layer software during operation to adapt to different error correction scenarios.

[0084] Please refer to Figures 1 to 5 As shown, the present invention also provides a storage device, where the storage device includes a flash memory chip 30, a cache chip 20, a memory 40, and a main controller 10. The cache chip 20 can be a Static Random-Access Memory (SRAM) and serves as the power-off volatile area of the storage device. The flash memory chip 30 can be a memory with a NAND flash memory as the storage medium and serves as the power-off non-volatile area of the storage device. The cache chip 20 is electrically connected to the flash memory chip 30. The main controller 10 is electrically connected to the flash memory chip 30, the cache chip 20, and the memory 40 respectively. The memory 40 can be a Read-Only Memory (ROM). The control method of the storage device provided by the present invention is stored in the memory 40 in the form of firmware. The main controller 10 can use a microprocessor, such as an ARM processor, as the processing core to call the firmware in the memory 40 to implement the control method of the storage device provided by the present invention.

[0085] Please refer to Figure 1 and Figure 5As shown, in an embodiment of the present invention, the main controller 10 includes a decoding module 11, a threshold setting module 12, a reading module 13, a process control module 14, and a loop control module 15. Among them, the decoding module 11 is used to execute a decoding process on the check bits and information bits of the read data when the read data fails. And during the decoding process, the decoding module 11 obtains and records the decoding iteration count of the decoding module 11. The threshold setting module 12 is used to set a first iteration threshold and a second iteration threshold. The reading module 13 is used to read data from the flash memory chip 30, and is used to change the read voltage and re-read the data while executing the next decoding iteration when the decoding iteration count reaches the first iteration threshold. The re-read data is temporarily stored in the cache chip 20. The process control module 14 is used to report that the read data fails when the decoding iteration count reaches the second iteration threshold, and execute a decoding process on the temporarily stored re-read data. The loop control module 15 is used to loop the decoding process and the re-reading process until the data is successfully read or until the read data still fails after traversing all the read voltages.

[0086] Please refer to Figure 1 and Figure 5 As shown, in an embodiment of the present invention, the main controller 10 further includes a timing control module 16. The timing control module 16 is electrically connected to the reading module 13 and the decoding module 11, and the timing control module 16 is used to output a first timing signal and a second timing signal simultaneously when the decoding iteration count reaches the first iteration threshold. Among them, the first timing signal is used to trigger an increment of the decoding iteration count and trigger the next decoding process, and the second timing signal is used to trigger the re-reading process of the data.

[0087] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the art can well understand and utilize the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A control method for a storage device, characterized in that, Including the following steps: When the data reading fails, perform a decoding process on the parity bits and information bits of the read data; In the decoding process, obtain and record the decoding iteration count; Set a first iteration threshold. When the decoding iteration count reaches the first iteration threshold, while performing the next decoding iteration, change the read voltage and reread the data, where the reread data is temporarily stored in the storage device; Set a second iteration threshold, where the second iteration threshold is greater than the first iteration threshold. If the decoding iteration count reaches the second iteration threshold, report that the data reading fails and perform a decoding process on the temporarily stored reread data; And Loop the decoding process and the rereading process until the data is successfully read or until the data reading fails after traversing all the read voltages; Wherein, in the steps of setting the first iteration threshold and the second iteration threshold, count the decoding success rate of each decoding iteration count. When the difference in the decoding success rate between adjacent decoding iteration counts first exceeds the allowable range, use the decoding iteration count corresponding to the larger decoding success rate as the first iteration threshold, and when the decoding success rate is less than the near-zero threshold, set the decoding iteration count corresponding to the decoding success rate as the second iteration threshold.

2. The control method of a storage device according to claim 1, wherein The step of setting the first iteration threshold includes: When the storage device is idle, obtain the decoding iteration count when each storage block is decoded successfully, and obtain the decoding success rate of each storage block at each decoding iteration count; Compare the decoding success rates of two adjacent decoding iteration counts in sequence and obtain the difference in the decoding success rate; and When the difference in the decoding success rate first exceeds the allowable range, use the decoding iteration count corresponding to the larger decoding success rate as the first iteration threshold.

3. The control method of a storage device according to claim 1, wherein, The step of setting the second iteration threshold includes: When the storage device is idle, obtain the decoding iteration count when each storage block is decoded successfully, and obtain the decoding success rate of each storage block at each decoding iteration count; and Set a near-zero threshold. When the decoding success rate is less than the near-zero threshold, set the decoding iteration count corresponding to the decoding success rate as the second iteration threshold.

4. A control method for a storage device according to claim 1, characterized in that, The steps of the rereading process include: When the decoding iteration count reaches the first iteration threshold, generate a warning signal; Under the trigger of the warning signal, select another read voltage from the read voltage table and read the data according to the reselected read voltage; and Store the reread data in the power-off volatile area of the storage device.

5. A control method for a storage device according to claim 1, characterized in that, Before performing the decoding iteration process on the reread data, determine whether the reread data passes the decoding verification. If it passes the decoding verification, directly upload the reread data to the host computer. If it fails to pass the decoding verification, perform the decoding iteration process on the reread data.

6. The control method of a storage device according to claim 1, wherein It further includes the following steps: When the decoding process decodes successfully, if the storage device is in a busy state, terminate the rereading process; When the decoding process decodes successfully, if the storage device is in a callable state, delete the reread data; And When the decoding process is successfully decoded, the successfully decoded data is uploaded to the host computer.

7. A control method for a storage device according to claim 1, characterized in that, In the step of setting the first iteration threshold and the second iteration threshold, the first iteration threshold and the second iteration threshold are preset data and are stored in the non-volatile area of the storage device when power is off.

8. A control method for a storage device according to claim 1, characterized in that, In the decoding process, according to the parity bits, the error bits in the information bits are iteratively corrected by the LDPC code.

9. A storage device, characterized in that, Including: Flash memory chip; Cache chip, electrically connected to the flash memory chip; Decoding module, used to execute the decoding process on the parity bits and information bits of the read data when the read data fails, and in the decoding process, the decoding module obtains and records the decoding iteration times; Threshold setting module, used to set the first iteration threshold and the second iteration threshold, where the second iteration threshold is greater than the first iteration threshold. In the step of setting the first iteration threshold and the second iteration threshold, the decoding success rate of each decoding iteration time is statistically calculated. When the difference in the decoding success rate of adjacent decoding iteration times first exceeds the allowable range, the decoding iteration time corresponding to the larger decoding success rate is used as the first iteration threshold, and when the decoding success rate is less than the near-zero threshold, the decoding iteration time corresponding to the decoding success rate is set as the second iteration threshold; Reading module, used to read data from the flash memory chip, and used to change the read voltage and reread the data while performing the next decoding iteration when the decoding iteration times reach the first iteration threshold, where the reread data is temporarily stored in the cache chip; Process control module, used to report that the read data fails when the decoding iteration times reach the second iteration threshold, and execute the decoding process on the temporarily stored reread data; And Loop control module, used to loop the decoding process and the rereading process until the data is successfully read or until the read data still fails after traversing the read voltage.

10. A storage device according to claim 9, characterized in that, The storage device includes a timing control module, the timing control module is connected to the reading module and the decoding module, and the timing control module is used to output a first timing signal and a second timing signal simultaneously when the decoding iteration times reach the first iteration threshold, where the first timing signal is used to trigger the decoding iteration times to increment by one and trigger a new decoding iteration process, and the second timing signal is used to trigger the rereading process.

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