A Performance Testing Method and System for LPCAMM2

Abstract

The present invention provides a performance testing method and system for LPCAMM2, which relates to the technical field of memory testing. The method includes: obtaining the refresh cycle of LPCAMM2; creating a test data array; performing a first test using the test data array to generate first test fault points; determining the fault expansion range of each first test fault point; obtaining the index addresses of each storage unit within the fault expansion range; generating a differentiated index address injection path; performing a second test on the fault expansion range according to the index address injection path using second test data, and outputting second test fault points; returning to regenerate a differentiated index address injection path; and outputting a test result. Through the determination of the fault expansion range and path planning, the testing duration is effectively reduced, the damage that may be caused to the LPCAMM2 hardware by long-term full-load testing is avoided, and at the same time, the accurate detection of critical faults is ensured.

Description

Technical Field

[0001] The present invention relates to the technical field of memory testing, and particularly to a performance testing method and system for LPCAMM2. Background Art

[0002] LPCAMM2 (Low Power Compressed Add-on Memory Module) is a low-power add-on memory module based on LPDDR5X technology. It is a high-performance memory chip, usually used in application fields that require large bandwidth and high performance, such as servers, data centers, and high-performance computing. It adopts advanced memory technology to improve the storage density and operating speed of the memory. The storage unit of LPCAMM2 is the smallest unit in this memory chip for storing data. Each storage unit can save a certain amount of binary data, usually 1 bit. These storage units are arranged in an array form, organized by rows and columns, to form the overall structure of the memory. In modern memory chips such as LPCAMM2, the storage unit usually adopts dynamic random access memory (DRAM) technology, relying on capacitors to store charges to represent "0" or "1" of the data. Since the charges will gradually leak, it is necessary to refresh regularly to maintain the stability of the data. The storage unit of LPCAMM2 supports high-density data storage and fast access through specific encoding, refreshing mechanisms, and efficient data writing technologies, meeting the requirements of large-scale computing and high-speed data processing.

[0003] The necessity of testing LPCAMM2 lies in that with the continuous progress of chip manufacturing technology, the density and complexity of memory chips are constantly increasing, which also brings more potential faults and errors. If memory faults are not detected in time, it may lead to system data loss, performance degradation, or system crashes. Therefore, through efficient testing means, faults in the memory can be detected and located in advance, ensuring the stability and reliability of the system. Especially in high-density and high-load working environments, it is particularly important to conduct tests in a timely manner.

[0004] However, currently, during the testing process of LPCAMM2, an undifferentiated global path scanning method is usually adopted. Conducting full-load tests for a long time may cause damage to the LPCAMM2 hardware, especially relying too much on high-load operations during the testing process. Therefore, the existing testing method fails to fully consider the high-density areas and high-fault-probability areas in the memory, resulting in a large number of ineffective test traversals. Especially in large-scale memory chips such as LPCAMM2, it increases the testing duration and cost, leading to low testing efficiency and easy omission of key fault points. Summary of the Invention

[0005] In view of the deficiencies of the above prior art, the purpose of the embodiments of the present invention is to provide a performance testing method and system for LPCAMM2, which can solve the technical problems existing in the prior art that in the current testing process of LPCAMM2, a non-discriminatory global path scanning method is usually adopted. Conducting full-load tests for a long time may cause damage to the LPCAMM2 hardware. Especially during the testing process, it is overly dependent on high-load operations. Therefore, the existing testing method fails to fully consider the high-density areas and high-failure-probability areas in the memory, resulting in a large number of ineffective test traversals. Especially in large-scale memory chips such as LPCAMM2, it increases the testing duration and testing cost, leading to low testing efficiency and easy omission of key fault points.

[0006] In the first aspect of the embodiments of the present invention, a performance testing method for LPCAMM2 is proposed, including:

[0007] S1: Obtain the refresh period of the LPCAMM2;

[0008] S2: Combine the pseudo-random coding technology to create a test data array that can be written into the LPCAMM2 once within a single refresh period;

[0009] S3: Use the test data array to conduct a test on the LPCAMM2 once to generate a set of test fault points;

[0010] S4: Combine the test working conditions of the LPCAMM2 to determine the fault expansion range of each set of test fault points;

[0011] S5: Obtain the index addresses of each storage unit within the fault expansion range;

[0012] S6: Combine the fault information and use the ant algorithm to plan each index address to generate a differentiated index address injection path;

[0013] S7: Randomly generate secondary test data from the test data array and use the secondary test data to conduct a secondary test on the fault expansion range according to the index address injection path, and output the secondary test fault points;

[0014] S8: Return to step S6 until the total secondary test duration is greater than the preset total secondary test duration, and output the fault storage units corresponding to the set of test fault points and the secondary test fault points;

[0015] S9: In the case where the number of fault storage units is less than the preset number of fault storage units, output that the LPCAMM2 test is normal; otherwise, output the index addresses of each fault storage unit to complete the test of the LPCAMM2.

[0016] In the second aspect of the embodiments of the present invention, a performance testing system for LPCAMM2 is proposed, including: a processor and a memory;

[0017] The memory stores programs or instructions that can run on the processor. When the programs or instructions are executed by the processor, the steps of the performance testing method for LPCAMM2 described in the first aspect are implemented.

[0018] The beneficial effects brought by the technical solutions provided by the embodiments of the present invention at least include:

[0019] In the embodiments of the present invention, by combining the pseudo-random coding technology and the ant algorithm to optimize the test path, it is possible to efficiently and accurately cover high-density and high-failure-probability areas, avoiding the ineffective testing and resource waste caused by indiscriminate global scanning. Through intelligent determination of the fault expansion range and path planning, the system effectively reduces the test duration, avoids the damage that may be caused to the LPCAMM2 hardware by long-term full-load testing, while ensuring the accurate detection of key faults, greatly improving the test efficiency and accuracy, and reducing the test cost. Description of the Drawings

[0020] The drawings are only for the purpose of showing specific embodiments and are not considered as a limitation of the present invention. Throughout the drawings, the same reference signs denote the same components. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0021] Figure 1 is a flowchart showing a performance testing method for LPCAMM2 provided by an embodiment of the present invention;

[0022] Figure 2 is a structural diagram of a performance testing system for LPCAMM2 provided by an embodiment of the present invention. Detailed Embodiments

[0023] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are some embodiments of the present invention, rather than all embodiments. It should be understood that these descriptions are only exemplary and are not used to limit the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0024] The following will, in conjunction with the accompanying drawings, elaborate in detail on the performance testing method of LPCAMM2 provided by the embodiments of the present invention through specific embodiments and their application scenarios.

[0025] Refer to the appended Figure 1 drawings, which show a schematic flowchart of a performance testing method for LPCAMM2 provided by an embodiment of the present invention.

[0026] The embodiments of the present invention provide a performance testing method for LPCAMM2, which may include the following steps:

[0027] S1: Obtain the refresh period of LPCAMM2.

[0028] Among them, in LPCAMM2, the refresh period means that the data stored in the memory needs to be refreshed regularly to maintain the stability and consistency of the data. Since DRAM (Dynamic Random Access Memory) stores data through capacitors, and the charge of the capacitors will gradually leak over time. If not refreshed regularly, the stored data may be lost. The role of the refresh period is to ensure that the capacitors in each storage unit can maintain the correct charge state, thereby preventing data loss. During one refresh period, all storage units in the memory are read and rewritten to restore the charging state of the capacitors and ensure the reliability of the data. In the test system of LPCAMM2, the role of obtaining the refresh period is to determine the time point when memory refresh occurs, so as to ensure that the tests performed within the refresh period are not affected by data loss and can complete fault detection at the correct moment.

[0029] In a possible implementation manner, S1 is specifically:

[0030] Obtain the refresh period through the memory controller of LPCAMM2.

[0031] It should be noted that the memory controller is responsible for managing the read and write operations of the memory and controlling the refresh period, so as to ensure that the data in the memory is refreshed at the correct time. By obtaining the refresh period, the system can accurately perform tests within each period, avoiding affecting the test results due to data loss or refresh errors.

[0032] S2: Combine the pseudo-random coding technology to create a test data array that can be written into LPCAMM2 once within a single refresh period.

[0033] Among them, pseudo-random encoding technology is a sequence of numbers generated by a pseudo-random number generator (PRNG). These sequences of numbers appear to be random statistically, but they are generated by an algorithm and are predictable and repeatable. This technology is often used to generate random data patterns to ensure the randomness and coverage of data during testing. The test data array is a two-dimensional matrix containing predetermined data for testing LPCAMM2 memory. Each memory cell is assigned a data value in the array, and the test data array is written to the LPCAMM2 at one time in a single refresh cycle. In this way, every memory cell in the memory is covered, ensuring that all data can be effectively tested and verified during the memory refresh cycle.

[0034] It should be noted that S2 uses pseudo-random encoding technology to generate a data array that can be written to the LPCAMM2 memory in a single refresh cycle. In this way, the system ensures that the test data can quickly and effectively cover each storage unit of the memory during the refresh cycle, while maximizing the memory bandwidth utilization and avoiding the frequent addressing switching and waiting time in traditional test methods.

[0035] In a possible implementation, S2 specifically includes:

[0036] Combined with the number of memory blocks of LPCAMM2, pseudo-random data of different storage units in each memory block are generated by a pseudo-random number generator.

[0037] The specific formula for generating pseudo-random data is:

[0038] ;

[0039] in, Represents the row and column coordinates of the storage unit, PRNG represents a pseudo-random number generator, Indicates rounding down. represents the memory block ID value, k represents the number of memory blocks, R represents the recursive perturbation factor of a prime number, mod represents the modular operation, Indicates that the row and column coordinates are A pseudo-random data value for a memory cell.

[0040] Optionally, the recursive perturbation factor can be set to 101. The value of each storage unit is a binary number generated by a pseudo-random number generator. Due to the randomness of the PRNG, it is possible to ensure that the value of each storage unit presents a pseudo-random distribution in the global range.

[0041] It should be noted that the data inside each block is quickly generated by a pseudo-random number generator to ensure that the data can be written continuously in a short time. Since the data is organized in blocks, the burst write mode can be used to write the data of a block to the memory at one time, thereby speeding up the writing speed. The data of the entire block is quickly written to the memory. In this way, the frequent addressing switching and waiting time in the traditional memory writing process can be avoided, and the writing efficiency of each block can be increased.

[0042] Furthermore, by combining the number of LPCAMM2 memory blocks, a pseudo-random number generator (PRNG) is used to generate pseudo-random data values ​​for each storage cell. This data generation formula ensures that the storage cell values ​​in each memory block are pseudo-random, which can avoid the regularity of the data and improve the sensitivity of fault detection. Through recursive perturbation factors and modular operations, the value of each storage cell presents a pseudo-random distribution, which effectively improves the randomness and coverage of the test data. Data is organized according to memory blocks and written all at once using the burst write mode, thereby accelerating the write process, avoiding frequent addressing switching and waiting in traditional tests, and improving write efficiency and test speed.

[0043] Generate disturbance data with linear disturbances for amplifying row and column drive faults.

[0044] The specific formula for generating perturbation data is:

[0045] ;

[0046] in, and denote the row perturbation coefficient and column perturbation coefficient respectively, Indicates that the row and column coordinates are The disturbed data value of the storage unit.

[0047] Among them, row and column drive failure refers to a failure in data transmission or storage due to a problem with the drive circuit of a row or column in the memory chip. For example, a row drive failure may be due to a failure in the drive circuit of a row, resulting in the inability of all storage cells in the row to read or write data correctly. Column short circuit refers to a short circuit in the electrical connection between column lines, which may cause interference or data loss between multiple columns of storage cells. The row perturbation coefficient and the column perturbation coefficient are parameters used to adjust the intensity of row and column perturbations. By adjusting these two coefficients, the degree of perturbation applied in the row and column directions can be controlled, thereby amplifying or reducing the anomalies caused by row and column drive failures. Specifically, the row perturbation coefficient and the column perturbation coefficient can take values ​​such as 0, 1, 2, etc., which are used to adjust the intensity of the perturbation according to the physical structure of the memory and the type of fault, so as to more effectively reveal potential fault problems in testing.

[0048] It should be noted that the generated perturbation data linearly perturbs the storage cells through the row perturbation coefficient and the column perturbation coefficient, so that any faults in the row and column directions (such as row drive faults or column short circuits) will cause abnormal perturbation values of the storage cells. This abnormality can amplify the fault signal and increase the sensitivity of fault detection. The formula of the perturbation data performs modulo operations on the row and column coordinates and adjusts the perturbation value of each storage cell through the perturbation coefficient, so as to more effectively expose the faults related to the rows and columns and improve the accuracy of fault detection. In this way, the system can more sensitively capture the memory faults caused by row and column problems.

[0049] The pseudo-random data is corrected according to the neighborhood weight matrix to obtain neighborhood-sensitive data.

[0050] The specific formula for generating the neighborhood-sensitive data is:

[0051] ;

[0052] where represents the neighborhood-sensitive data value of the storage cell with row and column coordinates , m and n respectively represent the traversal row index and traversal column index with values of -1, 0 or 1, represents the neighborhood weight matrix of the storage cell with row and column coordinates , represents the pseudo-random data value of the storage cell with row and column coordinates .

[0053] Optionally, the elements of the neighborhood weight matrix are specifically the central weight 0, the adjacent weight 1, and the diagonal weight 0.5.

[0054] It should be noted that the pseudo-random data is corrected by the neighborhood weight matrix to generate neighborhood-sensitive data, aiming to enhance the ability to detect faults between adjacent cells in the memory. Specifically, the neighborhood-sensitive data is calculated by weighted summing the pseudo-random data of neighboring storage cells. The neighborhood weight matrix defines the influence range of each storage cell, where the weight of the central cell is 0, the weight of the adjacent cells is 1, and the weight of the diagonal cells is 0.5. In this way, the system can amplify the interference signals between adjacent cells, such as short circuit or leakage faults, thereby improving the sensitivity and accuracy of fault detection and ensuring that potential faults in the memory can be detected in time.

[0055] The test data array is created by combining the pseudo-random data value, the perturbation data value, and the neighborhood-sensitive data value.

[0056] The specific formula for generating the test data array is:

[0057] ;

[0058] Among them, represents the test data array value of the storage unit with row and column coordinates , represents the exclusive OR operation.

[0059] It should be noted that the generation formula of the test data array performs an exclusive OR operation by combining pseudo-random data, row and column drive fault perturbation data, and neighborhood-sensitive data, ensuring the randomness of the test data and high sensitivity to faults. The test data array uses block recursive pseudo-random coding to ensure the randomness of the data and the sensitivity to faults, optimizing the memory access and refresh processes. During a refresh cycle, by using the block structure and pseudo-random number generation, it can ensure that all the data of the memory cells are quickly and effectively written into the memory during the refresh cycle, thereby improving the accuracy of memory fault detection and maximizing the memory bandwidth utilization efficiency. Such a design enables the test data array to efficiently cover the entire memory within a refresh cycle, avoiding misjudgment problems caused by not covering all the memory cells during the refresh cycle.

[0060] S3: Use the test data array to perform a test on LPCAMM2 to generate a test fault point for the first time.

[0061] Among them, a test fault point refers to the fault location or area that appears in the LPCAMM2 memory during the first test. During the test, the state of the memory cells is checked. If it is found that the data of the storage unit is inconsistent or lost, the system will mark this location as a fault point. A test fault point reflects possible hardware problems or data consistency problems in the memory.

[0062] S3 uses the created test data array to perform an initial test on LPCAMM2 to detect faults in the storage units. During the test, it checks the data of the memory cells one by one to find possible fault locations and generates a test fault point for the first time. This part of the content ensures effective detection during the memory refresh cycle, avoiding the charge leakage problem caused by incorrect refresh cycles, thereby improving the accuracy of storage unit fault detection. In this way, the system can accurately locate the faulty storage units in LPCAMM2.

[0063] In a possible implementation manner, S3 specifically includes:

[0064] Input the test data array into LPCAMM2 by memory block using the burst write protocol.

[0065] Generate a test fault point for the first time in LPCAMM2 through multi-phase dynamic sampling technology.

[0066] Among them, the Burst Write Protocol is a memory data writing mode used to improve the speed and efficiency of data writing. In the traditional memory writing process, each data write requires multiple addressings and waiting, resulting in a slow writing speed. The Burst Write Protocol packs multiple data units at once and writes them to the memory block in batches, reducing the number of addressing switches and thus accelerating the writing speed. The multi-phase dynamic sampling technology is an advanced sampling method used in memory testing. By sampling memory cells at different time points or multiple phases, it improves the accuracy and sensitivity of the test. This technology can detect memory faults more comprehensively by capturing the state of the memory at multiple moments, especially those tiny or transient faults that may not be detected in a single sampling phase.

[0067] It should be noted that the test data array is quickly written into each memory block of LPCAMM2 through the Burst Write Protocol to ensure the efficient loading of data. Subsequently, the multi-phase dynamic sampling technology is used to perform real-time sampling on LPCAMM2 to capture a test fault point in the memory. This method ensures the accurate detection of faults in the memory and promptly identifies possible hardware problems, improving the efficiency and accuracy of fault location.

[0068] S4: Combine the test conditions of LPCAMM2 to determine the fault expansion range of each primary test fault point.

[0069] Among them, the test conditions refer to the environmental parameters and conditions set during the LPCAMM2 test. These parameters may include the temperature, voltage, load, etc. of the memory chip, all of which will affect the memory performance during the test. By considering these external conditions, the test conditions help to more accurately simulate the actual usage environment, thereby improving the reliability and accuracy of the test. The fault expansion range refers to the area or range that a certain fault point may affect in the test. Due to the physical and electrical characteristics of the memory, a fault point may trigger faults in adjacent storage units or have a greater impact. Therefore, the fault expansion range is a prediction and delineation of the fault-affected area.

[0070] It should be noted that S4 combines the test conditions of LPCAMM2 to analyze the fault extension range of each primary test fault point. According to the actual environmental conditions in the test (such as temperature, voltage, etc.), the surrounding memory unit area to which the fault may extend is evaluated, and more accurate fault diagnosis information is provided for subsequent tests. Memory failures usually affect other units around a storage unit, especially in high-density memory, where a small failure may trigger a chain reaction in neighboring units. If the extension range of the fault is not considered, these joint failures may be missed, resulting in incomplete test results. By accurately judging the fault extension range, the fault area can be located more accurately, the accuracy of fault detection can be improved, and the health status of the entire memory chip can be fully evaluated. This process ensures that during the test, the system can identify and handle the overall impact of the fault area to avoid missing potential faults.

[0071] In addition, determining the fault extension range helps narrow the key areas of the test and avoids ineffective traversal testing. By clarifying the scope of possible fault impact, the test process can be more accurately focused on high fault probability areas, avoiding the inefficient operation of global scanning of the entire memory. This not only improves test efficiency, but also ensures that key fault areas are fully detected, thereby improving the accuracy and reliability of the test, while reducing unnecessary time and resource consumption.

[0072] In a possible implementation manner, the test condition includes the temperature and voltage of the LPCAMM2 in the test state.

[0073] It should be noted that parameters such as temperature and voltage will affect the performance and failure manifestations of memory chips. By considering these working conditions, the actual usage environment can be simulated more accurately, improving the reliability and accuracy of the test results.

[0074] In a possible implementation, S4 specifically includes:

[0075] Combined with temperature and voltage, the fault diffusion weight of each primary test fault point in different directions in the memory block to which it belongs is determined.

[0076] The calculation formula of fault diffusion weight is as follows:

[0077] ;

[0078] in, They represent the diffusion direction offsets that define the two-dimensional direction of fault extension, and Respectively represent the real-time temperature and real-time voltage of the memory block to which each fault point in a test belongs. and respectively represent the standard temperature and standard voltage of the memory block to which each single - test fault point belongs, 、 、 respectively represent the temperature weight, voltage weight and coupling weight, and | | represents taking the absolute value, represents and the capacitance coupling coefficient between adjacent memory cells provided by the LPCAMM2 layout data related to, represents the maximum capacitance coupling coefficient provided by the LPCAMM2 layout data, represents by the fault diffusion weights in different directions determined.

[0079] Optionally, the temperature weight, voltage weight and coupling weight can take values of 0.4, 0.3 and 0.3 respectively.

[0080] It should be noted that, combined with the real - time temperature and voltage of LPCAMM2, the influence range of faults is evaluated by calculating the fault diffusion weights in different directions. Specifically, the changes in temperature and voltage will affect the extent of memory faults. The fault diffusion weights consider the impact of these changes on fault propagation. By adjusting the temperature, voltage and coupling weights, combined with the layout data of LPCAMM2, the range of fault expansion can be accurately determined, and the fault diagnosis can be further optimized according to the capacitance coupling coefficients in different directions, thereby improving the accuracy and reliability of test results.

[0081] Based on the fault diffusion weights, the fault probability is mapped, and the memory cells with a fault probability greater than the preset fault probability are classified into the candidate area.

[0082] The specific calculation formula of the fault probability is:

[0083] ;

[0084] wherein, represents the natural constant, represents the slope factor, represents the fault diffusion weight threshold, represents the row - column coordinates as the fault probability at the place.

[0085] Optionally, the slope factor can be set to 10. The preset fault probability can be set to 0.7.

[0086] It should be noted that through this method of calculating the fault probability based on the fault diffusion weight, the diffusion range and probability of the storage unit fault can be predicted more accurately, taking into account various factors such as environmental conditions like temperature and voltage. This method can dynamically adjust the selection of the fault area, making the test more efficient and accurate, helping to quickly locate potential fault areas, optimize resource utilization, and improve the accuracy and reliability of fault detection.

[0087] It should be noted that those skilled in the art can set the size of the preset fault probability according to actual needs, and the present invention does not make any limitations here.

[0088] Obtain the metal line density within the candidate area based on the LPCAMM2 layout data.

[0089] Expand the candidate area in combination with the metal line density to determine the fault expansion range.

[0090] The constraint formula for the fault expansion range is specifically:

[0091] ;

[0092] Among them, represents the basic expansion radius, represents the metal line density sensitivity coefficient, represents the average metal line density of LPCAMM2, represents the metal line density in the direction determined by , represents the expansion value in the direction determined by .

[0093] Optionally, the metal line density sensitivity coefficient can be set to 0.8.

[0094] It should be noted that by combining the metal line density to adjust the fault expansion range, the diffusion of the fault in the storage unit can be simulated more precisely. The influence of the metal line density on the fault propagation is taken into account, which helps to reflect the expansion differences of the fault in different areas. This method can adjust the expansion range according to the actual circuit layout and physical characteristics, thereby improving the accuracy of fault prediction. By flexibly adjusting the expansion radius, the system can more effectively identify potential fault areas, optimize the test process, and enhance the reliability evaluation and fault location efficiency of the memory.

[0095] S5: Obtain the index addresses of each storage unit within the fault expansion range.

[0096] Among them, the index address refers to the unique identifier of the storage unit in the memory array, which is usually composed of the row number and the column number and is used to locate the specific position of the storage unit in the memory. Through the index address, the system can accurately access and operate each unit in the memory.

[0097] It should be noted that the index addresses of all affected storage units are obtained from within the fault expansion range. By determining the fault expansion area, each storage unit in these areas can be identified, and its corresponding index address can be obtained. This provides precise positioning information for subsequent testing and fault injection, ensuring that the system can perform effective secondary testing within the fault expansion range.

[0098] In a possible implementation, S5 is specifically used for:

[0099] Obtain the index address through the memory management unit of LPCAMM2.

[0100] It can be understood that by directly obtaining the index address of the storage unit through the memory management unit of LPCAMM2, the fault area in the memory can be accurately located. This helps to quickly identify and analyze faults, and optimize the testing efficiency.

[0101] S6 is used to combine the fault information and use the ant algorithm to plan each index address to generate a differentiated index address injection path.

[0102] Among them, the fault information refers to the data on the storage unit faults collected during the testing process, that is, the fault location. The ant algorithm is an optimization algorithm that simulates the foraging behavior of ants. By ants releasing pheromones on the path and adjusting the walking path according to the pheromone concentration, the optimal solution can be found. In this solution, the ant algorithm is used to optimize the testing path of the storage unit index address to ensure efficient and accurate coverage of the fault area. The index address injection path refers to the index addresses of each storage unit accessed in a specific order when performing fault injection in the memory. The path planning ensures that the fault points are effectively covered and avoids ineffective traversal.

[0103] It can be understood that by combining the collected fault information, the ant algorithm is used to optimize the path planning of the index addresses within the fault expansion range. Through intelligent path planning, it is ensured that the high-density and high-fault-probability areas are densely and accurately tested, thereby optimizing the testing efficiency and accuracy. By this method, the omission of key faults caused by "indiscriminate attacks" is avoided, and at the same time, the testing time is effectively reduced, and the reliability of the testing process is improved.

[0104] In a possible implementation, S6 specifically includes:

[0105] Take the fault probability and the metal wire density as the heuristic information of the ant algorithm.

[0106] Combine the fault feedback information and define the pheromone update rule for each index address based on the heuristic information.

[0107] The pheromone update rule is specifically as follows:

[0108] ;

[0109] Among them, represents the pheromone evaporation factor related to the fault feedback information, represents the pheromone increment, , respectively represent the wire density and the fault probability at the row and column coordinates , represents the pheromone concentration at the row and column coordinates , represents the update direction.

[0110] It should be noted that by dynamically adjusting the pheromone concentration in combination with the fault feedback information, the selection process of the index address can be optimized. The pheromone concentration reflects the priority of a specific location, so that based on the information feedback of the wire density and the fault probability, the test path can be adjusted, enabling more test resources to be allocated to the area where faults are concentrated. This method makes the test process adaptive and flexible, helping to improve the accuracy and efficiency of fault detection, and thus more accurately locate potential fault areas.

[0111] In a possible implementation manner, the update method of the pheromone evaporation factor is determined in combination with the fault density during the test process.

[0112] The specific update method of the pheromone evaporation factor is as follows:

[0113] ;

[0114] Among them, represents the reference pheromone evaporation rate without interference, t represents the time variable, tanh represents the arctangent function, represents the number of faults in the current test cycle, represents the total number of tests in the current test cycle, represents the wire density of the current test area, represents the fault density in the current test cycle, represents the fault density sensitivity coefficient, represents the fault density threshold, represents the attenuation smoothing coefficient of the dynamic decay factor, represents the initial amplitude of time decay, and λ represents the time decay rate constant.

[0115] Optionally, the reference evaporation rate can be set to 0.2. The fault density sensitivity coefficient can be set to 1.5. The decay smoothing coefficient can be set to 0.1 for a steep response or 0.5 for a gentle response. The time decay rate constant can be set to 0.07.

[0116] It should be noted that by combining the fault density to dynamically update the pheromone evaporation factor, the evolution of faults can be effectively reflected. As the number of faults and the density of regional metal lines change, the pheromone evaporation factor can be adaptively adjusted, making the testing process more flexible and accurate. When the fault density is high, the pheromone evaporation rate increases, and high-risk areas are preferentially selected for testing. This approach improves the targeting of testing, enabling the test path to focus on the areas most likely to have faults, optimizing the allocation of test resources, and accelerating the efficiency of fault location.

[0117] Determine the selection probability of each index address based on the pheromone update rule.

[0118] The specific calculation formula for the selection probability is:

[0119] ;

[0120] where represents the selection probability of the index address corresponding to the storage unit at the row and column coordinates , represents the heuristic factor related to the row and column coordinates , represents the straight-line distance from the current position to the row and column coordinates , represents the summation symbol, and β1 and β2 respectively represent the pheromone weight and the heuristic factor weight.

[0121] It should be noted that the method of calculating the selection probability by combining the pheromone concentration and the heuristic factor helps to dynamically adjust the test path according to the current fault information. The pheromone concentration reflects the probability of faults, and the heuristic factor provides additional guidance based on distance. Using this method, the testing process can preferentially select areas with a higher probability of potential faults, while also considering the influence of spatial location, making the test path more efficient and targeted. This calculation method improves the accuracy and speed of fault detection and can quickly and accurately locate the problem area.

[0122] Sort the corresponding index addresses in descending order of the selection probability to generate an index address injection path.

[0123] Specifically, by generating an index address injection path according to the selection probability ranking, storage units with a higher failure probability and a higher location priority can be preferentially tested. Such a ranking method ensures that the test resources are concentrated in the areas most likely to have failures, thereby improving the efficiency and accuracy of failure detection. By dynamically adjusting the path, it is possible to respond more flexibly to different failure modes, optimize the test process, and improve the accuracy of failure location.

[0124] S7 is used to randomly generate secondary test data from the test data array and perform a secondary test on the failure expansion range according to the index address injection path using the secondary test data, and output the secondary test failure points.

[0125] Among them, the secondary test failure points refer to the new or more serious memory failure locations found during the secondary test after being injected through a specific path within the failure expansion range. These failure points are detected during the further path injection and data change process after the first test, and are usually used to verify and confirm the failures that were not detected in the first test.

[0126] It should be noted that by performing tests within a smaller failure expansion range, accurate coverage of high-failure-probability areas is ensured. This can effectively avoid ineffective traversal, concentrate resources to quickly discover potential failures, thereby improving the test efficiency and accuracy, reducing the test time, and reducing the risk of damage to the hardware.

[0127] Specifically, the total data volume of the secondary test data is less than the total data volume of the test data array.

[0128] It can be understood that by setting the total data volume of the secondary test data to be less than the total data volume of the test data array, the test time and resource consumption can be effectively reduced, while ensuring the efficiency and pertinence of the test. This limitation helps to quickly focus on the failure area and avoid unnecessary repeated tests.

[0129] S8: Return to step S6 until the total secondary test duration is greater than the preset total secondary test duration, and output the failed storage units corresponding to the primary test failure points and the secondary test failure points.

[0130] It can be understood that according to the preset total secondary test duration, differential index address injection paths are repeatedly generated for secondary testing until the test time meets the requirements. Ensure that the test process fully covers the failure expansion area, while avoiding premature termination of the test to ensure accurate identification of failure points. Finally, the returned content helps to further locate and analyze memory failures by outputting the storage units corresponding to the primary test failure points and the secondary test failure points.

[0131] It should be noted that those skilled in the art can set the size of the preset total secondary test duration according to actual needs, and the present invention does not limit this here.

[0132] S9 is used to output that the LPCAMM2 test is normal when the number of fault storage units is less than the preset number of fault storage units; otherwise, it outputs the index addresses of each fault storage unit to complete the test of LPCAMM2.

[0133] It can be understood that the test result of LPCAMM2 is judged according to the number of fault storage units. If the number of fault storage units is less than the preset fault threshold, the system will consider that the LPCAMM2 test is normal. Otherwise, it will output the index addresses of all fault storage units to help locate the fault area and complete the test. This process ensures the accuracy of the test and timely feedback, and helps to quickly identify and repair potential problems.

[0134] It should be noted that those skilled in the art can set the size of the preset number of fault storage units according to actual needs, and the present invention does not make any limitations here.

[0135] While ensuring the rapid detection and location of fault storage units, it avoids hardware damage to LPCAMM2 caused by long-term full-load testing.

[0136] In the actual application process, the LPCAMM2 performance test system optimizes the memory fault detection process. Specifically, first, by obtaining the refresh cycle, it ensures that the test data will not be affected by charge leakage. Then, it uses the pseudo-random coding technology to generate a test data array and quickly writes it into the memory within a single refresh cycle. In S3, it performs preliminary fault detection and generates fault points, and then analyzes the fault expansion range. S7 performs a secondary test on the optimized path to ensure accurate coverage of high-fault areas. Before the secondary test, it uses the ant algorithm to plan the optimal test path to avoid invalid traversal. S8 ensures that the test duration meets the preset standard and outputs the index addresses of the fault storage units. Finally, it judges whether the test is normal according to the number of fault storage units, ensuring efficient and accurate detection and location of memory faults, while avoiding damage to the hardware. This solution not only improves the test efficiency, but also optimizes the accuracy of memory fault location.

[0137] Compared with the prior art, the present invention has at least the following beneficial technical effects:

[0138] In the embodiment of the present invention, by combining the pseudo-random coding technology and the ant algorithm to optimize the test path, it can efficiently and accurately cover high-density and high-fault-probability areas, avoiding the invalid tests and resource waste caused by indiscriminate global scanning. Through intelligent determination of the fault expansion range and path planning, the system effectively reduces the test duration, avoids the damage that long-term full-load testing may cause to the LPCAMM2 hardware, while ensuring accurate detection of key faults, greatly improving the test efficiency and accuracy, and reducing the test cost.

[0139] Refer to the attached specification Figure 2 , which shows a schematic structural diagram of a performance test system for LPCAMM2 provided by an embodiment of the present invention.

[0140] An embodiment of the present invention provides a performance test system 20 for LPCAMM2, including: a processor 201 and a memory 202;

[0141] The memory 202 stores programs or instructions that can run on the processor 201. When the programs or instructions are executed by the processor 201, the steps of the above-mentioned performance test method for LPCAMM2 are implemented, and the same technical effects can be achieved. To avoid repetition, the present invention will not be described in detail.

[0142] It should be understood that the processor 201 in the embodiment of the present invention may be a central processing unit (CPU), and this processor may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or this processor may also be any conventional processor, etc.

[0143] It should also be understood that the memory 202 in the embodiments of the present invention may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of random access memory are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synch link dynamic random access memory (SLDRAM), and direct rambus random access memory (DR RAM).

[0144] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware, or any combination thereof. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer programs are loaded or executed on a computer, the processes or functions described in the embodiments of the present invention are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wired (such as infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that contains one or more collections of available media. The available medium can be a magnetic medium (such as a floppy disk, hard disk, or magnetic tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0145] It should be understood that in various embodiments of the present invention, the order numbers of the above processes do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.

[0146] Those of ordinary skill in the art can realize that the units and algorithm steps of the examples described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0147] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the devices, apparatuses, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be described herein again.

[0148] In several embodiments provided by the present invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other can be through some interfaces. The indirect couplings or communication connections of the devices or units can be in electrical, mechanical, or other forms.

[0149] The units described as separate components may or may not be physically separated. The components displayed as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0150] In addition, in each embodiment of the present invention, the functional units can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit.

[0151] If the described functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in each embodiment of the present invention. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0152] The embodiments of the present invention provide a readable storage medium including: programs or instructions are stored on the readable storage medium. When the programs or instructions are executed by a processor, the steps of the above-mentioned performance test method of LPCAMM2 are implemented, and the same technical effects can be achieved. To avoid repetition, the present invention will not be described in detail.

[0153] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the embodiments of the present invention, rather than to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention. Any changes or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention.

Claims

1. A performance testing method for LPCAMM2, characterized in that, include: S1: Obtain the refresh cycle of the LPCAMM2; S2: creating a test data array that can be written into the LPCAM M2 once in a single refresh cycle by combining pseudo-random encoding technology; S3: Perform a test on the LPCAMM2 using the test data array to generate a test fault point; S4: Determine the fault extension range of each of the primary test fault points in combination with the test conditions of the LPCAMM2; S5: Obtaining the index address of each storage unit within the fault extension range; S6: combining the fault information, using the ant algorithm to plan each of the index addresses, and generating differentiated index address injection paths; S7: randomly generating secondary test data from the test data array, and performing a secondary test on the fault extension range according to the index address injection path using the secondary test data, and outputting a secondary test fault point; S8: Return to step S6, until the total duration of the secondary test is greater than the preset total duration of the secondary test, and output the fault storage unit corresponding to the primary test fault point and the secondary test fault point; S9: When the number of faulty storage units is less than the preset number of faulty storage units, output that the LPCAMM2 test is normal; otherwise, output the index address of each of the faulty storage units to complete the test of the LPCAMM2.

2. The performance testing method of LPCAMM2 according to claim 1, characterized in that, The S1 is specifically: The refresh cycle is obtained through the memory controller of the LPCAM M2.

3. The performance testing method of LPCAMM2 according to claim 1, characterized in that, The S2 specifically includes: In combination with the number of memory blocks of the LPCAMM2, pseudo-random data of different storage units in each memory block are generated by a pseudo-random number generator; generating disturbance data with linear disturbance for amplifying row and column driving faults; The pseudo-random data is modified according to a neighborhood weight matrix to obtain neighborhood sensitive data; The test data array is created by combining pseudo-random data values, perturbed data values, and neighborhood-sensitive data values.

4. The performance testing method of LPCAMM2 according to claim 1, characterized in that, The S3 specifically includes: Using a burst write protocol, the test data array is input into the LPCAMM2 according to the memory blocks; A primary test fault point in the LPCAMM2 is generated by a multi-phase dynamic sampling technique.

5. The performance testing method of LPCAMM2 according to claim 1, characterized in that, The test conditions include the temperature and voltage of the LPCAMM2 under the test state.

6. The performance testing method of LPCAMM2 according to claim 5, characterized in that, The S4 specifically includes: Determine the fault diffusion weight of each of the primary test fault points in different directions in the memory block to which it belongs, in combination with the temperature and the voltage; Based on the fault diffusion weight, a fault probability is mapped, and a storage unit whose fault probability is greater than a preset fault probability is classified into a candidate area; Acquire the metal line density in the candidate area based on LPCAMM2 layout data; The candidate area is expanded in combination with the metal wire density to determine the fault extension range.

7. The performance testing method of LPCAMM2 according to claim 1, characterized in that, The S5 specifically includes: The index address is obtained through the memory management unit of the LPCAMM2.

8. The performance testing method of LPCAMM2 according to claim 6, characterized in that, The S6 specifically includes: Using the failure probability and the metal wire density as heuristic information of the ant algorithm; In combination with the fault feedback information, defining the pheromone update rules of each of the index addresses based on the heuristic information; Determine the selection probabilities of each of the index addresses based on the pheromone update rule; Sort the corresponding index addresses in descending order of the selection probabilities to generate the index address injection path.

9. The performance testing method of LPCAMM2 according to claim 8, characterized in that, The S6 further includes: Determine the update method of the pheromone evaporation factor in combination with the fault density during the testing process.

10. A performance testing system for LPCAMM2, characterized in that, Includes: A processor and a memory; The memory stores a program or instructions that can run on the processor, and when the program or instructions are executed by the processor, the steps of the performance testing method of LPCAMM2 according to any one of claims 1 to 9 are implemented.

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