Bus bridging equipment test method, device and equipment and storage medium

Abstract

The invention discloses a bus bridging equipment testing method and device, equipment and a storage medium, and relates to the technical field of equipment testing, and the bus bridging equipment testing method comprises the steps: obtaining the equipment number and the equipment type of terminal equipment connected with the rear end of the bus bridging equipment; based on the device number, the device type and a support configuration mode of the bus bridging device, performing dynamic address configuration on each terminal device, and determining restriction information corresponding to each terminal device; and based on each dynamic address and each piece of limitation information, carrying out data transmission test on each piece of terminal equipment through the bus bridging equipment to obtain an equipment test result. According to the method and the device, the bus bridging equipment is subjected to comprehensive and systematic verification test, so that the stability and the reliability of the bus bridging equipment in practical application are ensured.

Description

Technical Field

[0001] The present application relates to the technical field of device testing, and in particular to a bus bridge device testing method, apparatus, device and storage medium. Background Art

[0002] In actual applications, after the design of the I3C Bridge (Improved Inter Integrated Circuit Bridge) is completed, designers usually only focus on whether the terminal device can successfully read data, but do not perform systematic testing on the I3C Bridge itself. The functions of the I3C Bridge are mainly implemented through software, such as implementing the bridge function through FPGA (Field-Programmable Gate Array) programming.

[0003] However, this implementation has the following problems: bus protocols such as I3C, I2C (Inter Integrated Circuit), SPI (Serial Peripheral Interface) and UART (Universal Asynchronous Receiver-Transmitter) have their own characteristics, data formats and transmission requirements. I3C Bridge needs to convert the data of one bus protocol into the data of another bus protocol. This process is prone to errors, which increases the complexity of the data transmission protocol. At the same time, because the function of I3C Bridge is implemented by software, designers may not verify the restrictions that I3C Bridge may encounter during the data conversion process. For example, I3CBridge may have a maximum data transmission rate limit, some terminal devices may have data reading delay requirements, and data write operations may have length limits, etc., causing designers to be unable to guarantee its ultimate stability and reliability.

[0004] Therefore, there is an urgent need for a systematic testing method that can fully verify the I3C Bridge function to ensure its stability and reliability in practical applications. Summary of the invention

[0005] The main purpose of this application is to provide a bus bridge device testing method, apparatus, device and storage medium, aiming to solve the problem that designers usually only focus on whether the terminal device can successfully read data, but do not perform systematic testing on the I3C Bridge itself.

[0006] To achieve the above object, the present application proposes a bus bridge device testing method, the method comprising:

[0007] Get the number and type of terminal devices connected to the back end of the bus bridge device;

[0008] Based on the number of devices, the device types, and the supported configuration mode of the bus bridge device, dynamically configure the address of each terminal device, and determine the restriction information corresponding to each terminal device;

[0009] Based on each of the dynamic addresses and each of the restriction information, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain a device test result.

[0010] In one embodiment, the dynamically configuring the address of each terminal device based on the number of devices, the device type, and the supported configuration mode of the bus bridge device, and determining the restriction information corresponding to each terminal device, includes:

[0011] Generate a dynamic address allocation instruction, and perform dynamic address configuration for each of the terminal devices based on the device type, the supported configuration mode of the bus bridge device, and the dynamic address allocation instruction;

[0012] Determine whether the number of allocated dynamic addresses is consistent with the number of devices;

[0013] If so, obtain a first value in the bus characteristic register, and determine the restriction information corresponding to each of the terminal devices based on the first value.

[0014] In one embodiment, after determining whether the number of allocated dynamic addresses is consistent with the number of devices, the method further includes:

[0015] If not, a value reading instruction is generated, and the second value is read according to the value reading instruction;

[0016] Based on the second value, determining whether to perform secondary dynamic address configuration on each of the terminal devices;

[0017] If not, the bus bridge device test process is terminated and a device test failure result is generated.

[0018] In one embodiment, based on each of the dynamic addresses and each of the restriction information, performing a data transmission test on each of the terminal devices through the bus bridge device to obtain a device test result includes:

[0019] Based on each of the dynamic addresses, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain data sending test data and data receiving test data, and the data sending test data and the data receiving test data are compared to obtain an accuracy test result;

[0020] Based on the dynamic addresses and the restriction information, obtaining restriction item test results;

[0021] The accuracy test result and the restriction item test result are associated and combined to generate the device test result.

[0022] In one embodiment, the restriction information includes a data read return time limit and a data write length limit;

[0023] The obtaining of restriction item test results based on each of the dynamic addresses and each of the restriction information includes:

[0024] Based on each of the dynamic addresses, the test data is sent to each of the terminal devices through the bus bridge device, and the total time of data transmission and reception is obtained by timing with a counter;

[0025] Obtaining a first test result according to the data read return time limit and the total data sending and receiving time;

[0026] Based on the data write length limit, performing a data write operation on the terminal device through the bus bridge device to obtain a second test result;

[0027] The first test result and the second test result are associated and combined to generate the restriction item test result.

[0028] In one embodiment, the method of performing a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information, before obtaining the device test result, further includes:

[0029] Generate an interrupt request, and send the interrupt request to the bus bridge device;

[0030] Detecting whether the bus bridge device receives the interrupt request;

[0031] If not, the bus bridge device test process is terminated and a device interrupt processing exception result is generated.

[0032] In one embodiment, the method of performing a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information, and obtaining a device test result, further includes:

[0033] Pushing the device test results to the client for device designers to view;

[0034] Obtaining a test optimization strategy of the device designer;

[0035] Based on the test optimization strategy, the bus bridge device test process is optimized.

[0036] In addition, to achieve the above-mentioned purpose, the present application also proposes a bus bridge device testing device, the bus bridge device testing device comprising:

[0037] An acquisition module is used to acquire the number and type of terminal devices connected to the back end of the bus bridge device;

[0038] A configuration module, configured to perform dynamic address configuration on each of the terminal devices based on the number of the devices, the type of the devices, and the supported configuration mode of the bus bridge device, and determine restriction information corresponding to each of the terminal devices;

[0039] The test module is used to perform a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information to obtain a device test result.

[0040] In addition, to achieve the above-mentioned purpose, the present application also proposes a bus bridge device testing device, which includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, and the computer program is configured to implement the steps of the bus bridge device testing method described above.

[0041] In addition, to achieve the above-mentioned purpose, the present application also proposes a storage medium, which is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the bus bridge device testing method described above are implemented.

[0042] In addition, to achieve the above-mentioned purpose, the present application also provides a computer program product, which includes a computer program, and when the computer program is executed by a processor, the steps of the bus bridge device testing method described above are implemented.

[0043] The present application provides a bus bridge device testing method, apparatus, equipment and storage medium. The bus bridge device testing method obtains the number and type of terminal devices connected to the back end of the bus bridge device, and then based on the number of devices, the type of devices and the supported configuration mode of the bus bridge device, dynamically configures the address of each terminal device and determines the restriction information corresponding to each terminal device, thereby performing a data transmission test on each terminal device through the bus bridge device based on each dynamic address and each restriction information, obtaining a device test result, and then realizing a comprehensive and systematic verification test of the bus bridge device to ensure the stability and reliability of the bus bridge device in practical applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0045] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0046] Figure 1 A schematic diagram of the connection between an I3C controller and an I3C bridge provided for the bus bridge device testing method of the present application;

[0047] Figure 2 A schematic diagram of a design of a bus bridge device testing device in one embodiment of a bus bridge device testing method provided in the present application;

[0048] Figure 3 A schematic diagram of a test topology structure of a bus bridge device test device in an embodiment of a bus bridge device test method provided in the present application;

[0049] Figure 4 A flowchart of the first embodiment of the bus bridge device testing method of the present application is provided;

[0050] Figure 5 An example flow chart of the test device address allocation and test process in one embodiment of the bus bridge device test method provided in the present application;

[0051] Figure 6 An example flow chart of an interrupt event verification process in an embodiment of the bus bridge device testing method provided in the present application;

[0052] Figure 7This is a schematic diagram of the module structure of the bus bridge device testing device according to an embodiment of the present application;

[0053] Figure 8 Schematic diagram of the device structure of the hardware operating environment involved in the bus bridge device testing method in the embodiment of the present application.

[0054] The purpose, features and advantages of this application will be further described in conjunction with the embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0055] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of the present application and are not used to limit the present application.

[0056] In order to better understand the technical solution of the present application, a detailed description will be given below in conjunction with the accompanying drawings and specific implementation methods.

[0057] MIPI (Mobile Industry Processor Interface) specification puts forward the concept of I3C Bridge. Through I3C Bridge, the connection between I3C bus and I2C, SPI and UART bus can be realized. Then I3C Controller can interact with I2C Slave (referring to the slave device in I2C (Inter-Integrated Circuit) bus communication), SPI Slave and devices with UART interface to realize data exchange, making the application of I3C more extensive. In this process, I3C Bridge is particularly important for the reliability of data conversion. You can refer to Figure 1 , Figure 1 A connection diagram of an I3C controller and an I3C bridge is provided for the bus bridge device testing method of the present application, wherein the number of I2C terminal devices and SPI terminal devices can be one or more, and the number of UART terminal devices is one.

[0058] However, in practical applications, after the design is completed (such as Figure 1 As shown in the figure, the designer only focuses on whether the terminal device data can be read successfully, and does not conduct systematic testing on the I3C Bridge. The I3CBridge mainly implements the function of the Bridge through software (such as FPGA implements the I3CBridge function through programming), that is, verifies whether the data transmission can meet the corresponding protocol requirements. There is no targeted verification of the restriction information described by the I3C Bridge, and the final stability and reliability of the design cannot be guaranteed.

[0059] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication and program running functions, such as a tablet computer, a personal computer, a mobile phone, etc., or an electronic device that can realize the above functions, a big data service platform, a bus bridge device test system, etc. The following takes the bus bridge device test system as an example. The bus bridge device test system is applied to the bus bridge device test device, which can be referred to Figure 2 , Figure 2 A design schematic diagram of a bus bridge device test device in one embodiment of the bus bridge device test method provided for the present application, wherein the test device can be implemented by selecting a field programmable gate array FPGA, that is, a data comparison module, an improved internal integrated circuit (I3C) control module, an internal integrated circuit (I2C) data transceiver module, a universal asynchronous (UART) data transceiver module, and a serial peripheral interface (SPI) data transceiver module are integrated inside the FPGA. The I3C control module is used to connect to the I3C interface of the I3C Bridgede and control the sending of I3C bus instructions and the sending and receiving of data; the I2C transceiver module, the UART transceiver module, and the I2C interface, UART interface, and SPI interface derived from the SPI transceiver module are respectively connected to the I3C Bridge for instruction reception and data reception and transmission; the data comparison module is used to compare the data sent or received by the I3C control module with the data received or sent by each transceiver module to confirm whether they are consistent. In addition, because all interfaces of I3Cbridge, such as I3C bus connected to I3CContollerde, and I2C, UART, and SPI buses connected to terminal devices, are low-speed signals, connectors or test points are usually reserved for low-speed signals. An optional topology is to connect these buses to the test equipment to form a loop so that the test equipment can compare the command data sent or received through I3C Bridge. For reference, Figure 3 , Figure 3 A schematic diagram of a test topology structure of a bus bridge device test device in an embodiment of the bus bridge device test method provided in the present application is provided. Taking a bus bridge device test system as an example, this embodiment and the following embodiments are described.

[0060] Based on this, the embodiment of the present application provides a bus bridge device testing method, referring to Figure 4 , Figure 4 A flowchart diagram of the first embodiment of the bus bridge device testing method of the present application is provided.

[0061] In this embodiment, the bus bridge device testing method includes steps S11 to S13:

[0062] Step S11, obtaining the number and type of terminal devices connected to the back end of the bus bridge device;

[0063] It should be noted that the bus bridge device refers to a hardware or software component used to connect different types of bus protocols or different bus segments to achieve data conversion and transmission, such as I3C Bridge, a device used to connect I3C bus and other buses (such as I2C (Inter Integrated Circuit), SPI (Serial Peripheral Interface), UART (Universal Asynchronous)).

[0064] It should be further explained that the terminal device refers to a device connected to the back end of the bus bridge device, which is usually used to perform specific functions (such as data acquisition, storage, communication, etc.), such as sensors (such as temperature sensors, accelerometers), storage devices (such as EEPROM, Flash memory), display screens or communication modules (such as Bluetooth modules, Wi-Fi modules), etc.

[0065] Furthermore, the number of devices refers to the total number of terminal devices connected to the back end of the bus bridge device, wherein the number of devices also includes the bus bridge device itself connected to the back end of the bus bridge device. The device type refers to the function or category of the terminal device, which is used to distinguish different types of devices.

[0066] Specifically, the number and type of terminal devices connected to the back end of the bus bridge device are obtained. In one embodiment, first, the bus bridge device (such as I3C Bridge) will start an initialization process to wake up and identify all terminal devices connected to its back end by sending specific commands or signals. In the I3C bus, this process involves a dynamic address allocation command (such as ENTDAA CCC), through which the bus bridge device scans the bus, detects the existence of each terminal device, and assigns a unique address to them. At the same time, the bus bridge device will read the bus characteristic register (BCR, Bus Characteristic Register) of each terminal device, and obtain the device type information therefrom, such as whether the device is a sensor, memory or other functional module, so that it can not only count the total number of terminal devices connected to its back end, but also clarify the specific type of each device, thereby providing basic information for subsequent communication and management.

[0067] Step S12, based on the number of devices, the device type and the supported configuration mode of the bus bridge device, dynamically configure the address of each terminal device and determine the restriction information corresponding to each terminal device;

[0068] It should be noted that the supported configuration mode refers to the configuration method or mode that the bus bridging device can support, which is used to dynamically adjust the operating parameters of the device, including but not limited to: Dynamic Address Allocation: automatically assigning addresses to devices; Fixed Address Configuration: the device uses a preset fixed address; Protocol Conversion Configuration: configure the bridging device to support conversion between different bus protocols; Power Management Configuration: configure the power mode of the device to optimize power consumption; Interrupt Configuration: configure the interrupt signal processing method of the device.

[0069] It should be further explained that the dynamic address refers to the address dynamically assigned to the terminal device by the bus bridge device during operation. Dynamic address allocation allows the device to automatically obtain a unique address after connecting to the bus without manual configuration. For example, in the I3C bus, a device can obtain a unique 7-bit or 10-bit address through the dynamic address allocation process.

[0070] Furthermore, the restriction information refers to specific conditions or restrictions that the terminal device needs to comply with during operation, which is used to optimize the operating performance and compatibility of the device, including but not limited to: Maximum Data Transfer Rate: the maximum data transfer rate supported by the device; Data Read Latency: the maximum delay time for device data reading; Data Write Length: the maximum data write length supported by the device; Power Mode Constraints: the power mode or power consumption limitation supported by the device; Interrupt Response Time: the maximum response time of the device to an interrupt signal.

[0071] Specifically, a dynamic address allocation instruction is generated, and a dynamic address configuration is performed for each of the terminal devices based on the device type, the supported configuration method of the bus bridging device, and the dynamic address allocation instruction, and then a determination is made as to whether the number of allocated dynamic addresses is consistent with the number of devices. If so, a first value in a bus characteristic register is obtained, and based on the first value, restriction information corresponding to each of the terminal devices is determined.

[0072] Step S13, based on each of the dynamic addresses and each of the restriction information, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain a device test result.

[0073] It should be noted that the device test results refer to the output data obtained after verifying the performance and functions of the terminal device through the test process, which is used to evaluate whether the device meets the design requirements and operating conditions, including data transfer accuracy (Data Transfer Accuracy): verifying whether the data transmission between devices is accurate; performance indicators (Performance Metrics): such as whether the data transmission rate, delay, etc. meet expectations; compatibility test results (Compatibility Test Results): whether the device is compatible with the bridge device; stability test results (Stability Test Results): the stability of the device under long-term operation or high-load conditions; error reports (Error Reports): any errors or abnormal conditions found during the test.

[0074] Specifically, based on each of the dynamic addresses, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain data sending test data and data receiving test data, and the data sending test data and the data receiving test data are compared to obtain an accuracy test result, and then based on each of the dynamic addresses and each of the restriction information, a restriction item test result is obtained, so that the accuracy test result and the restriction item test result are associated and combined to generate the device test result, and then an effective systematic test is performed on the bus bridge device to verify that its data transmission meets the corresponding bus requirements, and the conditions restricting the bus bridge device are specifically verified to ensure the ultimate stability and reliability of the design.

[0075] This embodiment obtains the number and type of terminal devices connected to the back end of the bus bridge device, and then performs dynamic address configuration on each terminal device based on the number of devices, the type of devices and the supported configuration method of the bus bridge device, and determines the restriction information corresponding to each terminal device, so as to perform data transmission test on each terminal device through the bus bridge device based on each dynamic address and each restriction information, and obtain device test results, thereby achieving a comprehensive and systematic verification test on the bus bridge device to ensure that each device can work normally within the support range of the bridge device, and optimize the performance configuration of the bridge device through the restriction information to ensure that the system runs in the best state, thereby ensuring the accuracy and integrity of data transmission and avoiding data loss or errors. At the same time, it verifies whether the bridge device can correctly handle the conversion between different protocols to ensure that the data transmission meets the protocol requirements, and finally ensures the stability and reliability of the bus bridge device in actual applications.

[0076] In a feasible implementation manner, the dynamically configuring the address of each terminal device based on the number of devices, the device type, and the supported configuration mode of the bus bridge device, and determining the restriction information corresponding to each terminal device, includes:

[0077] Step S21, generating a dynamic address allocation instruction, and performing dynamic address configuration for each of the terminal devices based on the device type, the supported configuration mode of the bus bridge device, and the dynamic address allocation instruction;

[0078] It should be noted that the dynamic address allocation command refers to a control command used to allocate a unique address to a terminal device in bus communication, which is usually generated by a bus controller or a bus bridge device to initialize the device and ensure the uniqueness of each device on the bus. In one embodiment, in the I3C bus protocol, the dynamic address allocation command is ENTDAA CCC (Enter Dynamic Address Assignment Common Command Code), which is used to start the dynamic address allocation process, allowing the I3C controller to allocate a unique 7-bit or 10-bit address to the device connected to the bus, so that at the beginning of the bus communication, a unique address is allocated to each terminal device, ensuring that multiple devices do not use the same address, thereby avoiding communication conflicts, and allowing devices to dynamically join or leave the bus at runtime without reconfiguring the entire system.

[0079] Specifically, a dynamic address allocation instruction is generated, that is, the test device sends the instruction ENTDAACCC to the terminal device connected to the 13CBridge to perform 13C dynamic address allocation. Further, based on the configuration mode supported by the bus bridge device and the dynamic address allocation instruction, dynamic address configuration is performed for each of the terminal devices. First, a suitable dynamic address allocation strategy is determined according to the supported configuration mode of the bus bridge device (such as supported bus protocols, address allocation range, etc.).

[0080] In one embodiment, the bus bridge device generates a dynamic address allocation instruction (such as the ENTDAACCC command in the I3C bus), wherein the dynamic address allocation instruction (such as the ENTDAACCC command in the I3C bus) is only for the I3C bus, and does not work for the bus at the back end of the bus bridge device. It can be understood that there are virtual I3C devices corresponding to the terminal devices inside the bus bridge device. The allocation of addresses to the terminal devices is actually to allocate addresses to these virtual devices, which further triggers the terminal devices to enter the dynamic address allocation mode and prepare to receive the allocated addresses. Then, the bus bridge device allocates a unique address to each terminal device one by one according to the device type and its own configuration capabilities. For example, for devices that support the I3C protocol, the bridge device can allocate a 7-bit or 10-bit dynamic address to it, while ensuring the uniqueness of the address on the bus. During the allocation process, the bridge device will communicate with each terminal device through the bus to confirm that the device has correctly received and stored the allocated address.

[0081] In another embodiment, since there are two configuration (I3C dynamic address allocation) schemes for the I3C Bridge device, that is, it can be performed using the ENTDAA CCC command or the SETBRGTGT CCC (Set Bridge Target Common Command Code) command, whose value is 0x93, wherein whether the SETBRGTGT CCC operation is required is determined based on the value in the I3C Bridge VTCAP1 (Virtual Target Capable) register, that is, the value of the VTCAP (Virtual Target Capable virtual target device characteristic description) of the I3CBridge is obtained, and by obtaining the value, it is determined whether the SETBRGTGT command is required for address allocation.

[0082] In addition, if the address cannot be allocated, it can be considered that the I3C Bridge function is abnormal, and the test is determined to have failed, the bus bridge device test process is terminated, and a device test failure result is generated.

[0083] Step S22, determining whether the number of allocated dynamic addresses is consistent with the number of devices;

[0084] Specifically, it determines whether the number of dynamic addresses after allocation is consistent with the number of detected devices to verify whether all terminal devices have successfully completed the address configuration, thereby ensuring the uniqueness of each device on the bus. It can also optimize the address allocation according to the device type and the configuration capability of the bridge device, thereby providing an accurate communication basis for subsequent data transmission and device management.

[0085] Step S23: If yes, obtain the first value in the bus characteristic register, and determine the restriction information corresponding to each of the terminal devices based on the first value.

[0086] It should be noted that the bus characteristic register (BCR) refers to a virtual register in the bus bridge device corresponding to the terminal device, which is used to describe the characteristics, functions and restrictions of the device. BCR is an important component of the I3C protocol, which is used to help the bus controller identify the device type and function. In the I3C protocol, BCR usually contains the following information: device type: identifies whether the device is a sensor, memory or other type; functional support: for example, whether interrupts are supported, whether high-bandwidth mode is supported, etc.; restriction information: such as maximum data transmission rate, data read delay, etc., so that the bus controller can identify the type and function of the device connected to the bus by reading the BCR, and based on the information in the BCR, the controller can optimize the communication parameters and configuration of the device, thereby ensuring the protocol compatibility between the device and the bus bridge device.

[0087] It should be further explained that the first value refers to a specific value read from the bus characteristic register (BCR), which is used to describe certain characteristics or restrictions of the terminal device, including the maximum data transmission rate: the maximum transmission rate supported by the device (such as 100kbps, 400kbps, etc.), data read delay time: the maximum data read delay time allowed by the device, device type flag: used to identify whether the device is an I3C device or a compatible I2C device and other restrictions, such as data write length limit, etc.

[0088] Specifically, if so, the first value in the bus characteristic register is obtained, and based on the first value, the restriction information corresponding to each of the terminal devices is determined. In one embodiment, for the restriction information, such as Bit0=1 in the BCR of a terminal device, that is, there is a restriction condition, the test device obtains the corresponding information by sending relevant instructions. For example, the test device additionally sends the instruction GETMXDS (its value is 0x94) to obtain the maximum data transmission rate; the test device additionally sends the instruction GETXTIME (its value is 0x99) to obtain the maximum data return time; the test device additionally sends the instruction GETMWL (Get MaxWrite Length, its value is 0x8B) to obtain the maximum length limit of the data during the write operation, and the test device can set the maximum data write length by sending the instruction SETMWL (Set Max Write Length, its value is 0x89).

[0089] This embodiment generates a dynamic address allocation instruction, and performs dynamic address configuration for each of the terminal devices based on the device type, the supported configuration method of the bus bridging device, and the dynamic address allocation instruction, and then determines whether the number of dynamic addresses after allocation is consistent with the number of devices. If so, the first value in the bus characteristic register is obtained, and based on the first value, the restriction information corresponding to each of the terminal devices is determined, thereby ensuring that all devices are correctly identified and assigned addresses to avoid omissions or repeated allocations. At the same time, the dynamic address allocation takes into account the device type and the supported configuration method of the bus bridging device, so that the system can flexibly adjust the address allocation strategy according to different device types and protocol requirements, and allow devices to join or leave the bus during operation without reconfiguring the entire system, thereby improving the scalability and flexibility of the system, and ensuring the protocol compatibility between the terminal device and the bus bridging device, avoiding communication errors caused by mismatched device characteristics, and thereby improving the overall stability of the system.

[0090] In a feasible implementation manner, after determining whether the number of allocated dynamic addresses is consistent with the number of devices, the method further includes:

[0091] Step S31, if not, generate a value reading instruction, and read the second value according to the value reading instruction;

[0092] It should be noted that the value reading instruction refers to a command for reading a specific register or status information from a terminal device to obtain the status, error information or other important data of the device. The second value refers to a specific value read from the register or status information of the terminal device, which is used to help the bridge device determine the status of the device or whether further operation is required.

[0093] Specifically, a numerical value reading instruction, such as a GETCAPSVTCAPS instruction, is generated, and the test device sends the instruction GETCAPSVTCAPS to read a second numerical value, such as an I3CBridgeVTCAP value, thereby determining whether it is necessary to perform I3C dynamic address allocation on the terminal device connected to the I3CBridge through the obtained I3CBridgeVTCAP1BIT[2:0].

[0094] Step S32, based on the second value, determining whether to perform secondary dynamic address configuration on each of the terminal devices;

[0095] Specifically, based on the second value, it is determined whether to perform secondary dynamic address configuration on each terminal device. Continuing with the above example, if Bit[2:0] in the I3C BridgeVTCAP1 value=3'd1, it is determined to perform secondary dynamic address configuration on each terminal device.

[0096] Furthermore, the test device sends the instruction ENTDAA CCC to allocate a 13C dynamic address to the I3CBridge, and then uses the SETBRGTGTCCC instruction to allocate a 13C dynamic address to the terminal device connected to the 13CBridge. If the number of allocated I3C dynamic addresses is inconsistent with the number of terminal devices, it indicates that the terminal device has failed to obtain the 13C address, and the test ends with a failure result.

[0097] In addition, if the number of allocated I3C dynamic addresses is consistent with the number of terminal devices, the BCR value of the terminal device connected to the 13C Bridge is used to determine whether there is restriction information to complete the confirmation of restriction information. Figure 5 , Figure 5 An example flowchart of the test device address allocation and test process in one embodiment of the bus bridge device testing method provided in the present application.

[0098] Step S33: if not, the bus bridge device test process is terminated and a device test failure result is generated.

[0099] It should be noted that the device test failure result refers to the final result of the test failure caused by some terminal devices failing to pass the dynamic address allocation or other test conditions during the device test process.

[0100] In this embodiment, if not, a numerical value reading instruction is generated, and a second numerical value is read according to the numerical value reading instruction, and then based on the second numerical value, it is determined whether a secondary dynamic address configuration is performed on each of the terminal devices. If not, the bus bridge device test process is terminated, and a device test failure result is generated, thereby achieving double verification. Through the number check after the first address allocation (determining whether the number of dynamic addresses is consistent with the number of devices), it is preliminarily confirmed whether the address allocation is successful. If inconsistency is found, a secondary verification is further performed. Therefore, the double verification mechanism effectively avoids address allocation failures caused by address conflicts, incorrect device response or communication failures, ensures that each terminal device is correctly configured with a dynamic address, and improves the accuracy and effectiveness of the test verification process.

[0101] In a feasible implementation manner, based on each of the dynamic addresses and each of the restriction information, performing a data transmission test on each of the terminal devices through the bus bridge device to obtain a device test result includes:

[0102] Step S41, based on each of the dynamic addresses, performing a data transmission test on each of the terminal devices through the bus bridge device to obtain data sending test data and data receiving test data, and comparing the data sending test data with the data receiving test data to obtain an accuracy test result;

[0103] It should be noted that the data sending test data refers to the test data sent by the bus bridge device (or test device) to the terminal device during the test process, which is used to verify the integrity and accuracy of the data transmission. The data receiving test data refers to the test data received by the terminal device from the bus bridge device during the test process, which is used to verify whether the terminal device correctly parses and responds to the sent test data.

[0104] It should be further explained that the accuracy test result refers to the test result obtained by comparing the sent test data (data sending test data) and the received test data (data receiving test data), which is used to evaluate the accuracy and completeness of data transmission.

[0105] Specifically, based on each of the dynamic addresses, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain data sending test data and data receiving test data, and the data sending test data and the data receiving test data are compared to obtain an accuracy test result.

[0106] In one embodiment, the test equipment reads and writes data to the corresponding terminal devices one by one at the maximum data transmission rate supported by each terminal device according to the 13C dynamic address allocated to the terminal device and the restriction information of each terminal device, and obtains data sending test data and data receiving test data. The test equipment determines whether the corresponding transceiver module can receive the data, and the received data is compared with the data sent by the I3C control module through the data comparison module. If the data of the two are inconsistent, the test fails and the test process is terminated.

[0107] Step S42, obtaining a restriction item test result based on each of the dynamic addresses and each of the restriction information;

[0108] It should be noted that the restriction item test result refers to the test result performed during the test based on the restriction information of the terminal device (such as maximum data transmission rate, delay time, data writing length, etc.), which is used to verify whether the terminal device can work normally within its performance limitation.

[0109] Specifically, based on each of the dynamic addresses, test data is sent to each of the terminal devices through the bus bridge device, and timing is performed through a counter to obtain the total time length for data transmission and reception, and then based on the data read return time limit and the total time length for data transmission and reception, a first test result is obtained, and then based on the data write length limit, data write operations are performed to the terminal devices through the bus bridge device to obtain a second test result, and then the first test result and the second test result are associated and combined to generate the restriction item test result.

[0110] Step S43: Associating and combining the accuracy test result and the restriction item test result to generate the device test result.

[0111] In this embodiment, based on each of the dynamic addresses, the bus bridge device performs a data transmission test on each of the terminal devices to obtain data sending test data and data receiving test data, and compares the data sending test data with the data receiving test data to obtain an accuracy test result, and then based on each of the dynamic addresses and each of the restriction information, obtains a restriction item test result, thereby associating and combining the accuracy test result and the restriction item test result to generate the device test result, and then directly verifies whether there is loss, error or damage in the data transmission process, generates a clear accuracy test result, helps to confirm whether the data transmission meets expectations, thereby ensuring the reliability of the system, and at the same time, based on the dynamic address and the device restriction information (such as maximum transmission rate, delay time, etc.), performs targeted performance tests on each terminal device to ensure that the device does not exceed its performance limit in actual operation, thereby not only verifying the accuracy of data transmission, but also evaluating whether the device can work normally under the specified restriction conditions, thereby realizing automation, providing more comprehensive test coverage, and reducing manual intervention, improving test efficiency and consistency, and ensuring the compatibility and stability of the system.

[0112] In a feasible implementation manner, the restriction information includes a data read return time limit and a data write length limit; and obtaining a restriction item test result based on each of the dynamic addresses and each of the restriction information includes:

[0113] Step S51, based on each of the dynamic addresses, sending test data to each of the terminal devices through the bus bridge device, and timing through a counter to obtain a total data transmission and reception time;

[0114] It should be noted that the test data refers to predefined data sent by the bus bridge device to the terminal device during the test process, which is used to verify the integrity and accuracy of data transmission. The counter refers to a hardware or software component used to measure a time interval.

[0115] It should be further explained that the total data transmission and reception time refers to the entire time interval from the bus bridge device sending the test data to the terminal device returning the response data, including the data transmission time and the data reception time.

[0116] Specifically, based on each of the dynamic addresses, the test data is sent to each of the terminal devices via the bus bridge device, and timing is performed via a counter to obtain a total duration of data transmission and reception.

[0117] Step S52, obtaining a first test result according to the data read return time limit and the total data sending and receiving time;

[0118] It should be noted that the data read return time limit refers to the maximum time limit that the terminal device must return data within the specified time after receiving the read instruction. The first test result refers to the test result obtained based on the total data transmission and reception time and the data read return time limit, which is used to evaluate whether the terminal device can complete data reading and returning within the specified time.

[0119] Specifically, in one embodiment, a test is performed for a data read return with a time delay item. For example, in this test, the test device (I3C control module) reads data from the terminal device (I2C data transceiver module). This process is that the physical link is for the test device to send a data read instruction to the I3C Bridge. After the I3C Bridge obtains the data from the I2C data transceiver module of the test device through the I2C link, it performs format conversion to meet the requirements of the I3C protocol transmission, and then sends it to the I3C control module in the test device. There will be a time delay when the I3C Bridge converts the data. Therefore, an optional time delay test method is designed, that is, the I3C control module of the test device starts timing through the timer in the test device after sending the data read command, and stops timing after obtaining the data returned by the I3C Bridge. If the returned data value is consistent with the value read by the I2C data transceiver module and the time is consistent with the preset value (less than the preset limit time), the test is determined to be passed, indicating that the I3C Bridge function is normal, otherwise this test item fails, indicating that the I3CBridge function is abnormal, and the I3C is completed in the same way. The UART and SPI interface tests of the Bridge eventually generate the first test results.

[0120] Step S53, based on the data write length limit, performing a data write operation on the terminal device through the bus bridge device to obtain a second test result;

[0121] It should be noted that the data write length limit refers to the maximum data write length that the terminal device can receive. The second test result refers to the test result obtained after performing a data write operation based on the data write length limit, which is used to evaluate whether the terminal device can correctly process the data write operation of the maximum length.

[0122] Specifically, based on the data write length limit, the data write operation is performed to the terminal device through the bus bridge device to obtain a second test result. In one embodiment, the test device sets the data write length to the maximum value through the I3C control module and performs a write operation to the I2C data transceiver module through the I3C Bridge. By comparing the data sent by the I3C control module in the test device with the data received by the I2C data transceiver module in the test device, if the two are consistent, the test passes, indicating that the I3C Bridge function is normal, otherwise the test item fails, indicating that the I3C Bridge function is abnormal. The test of the UART and SPI interfaces of the I3CBridge is completed in the same way, and finally the second test result is generated.

[0123] Step S54: Associating and combining the first test result and the second test result to generate the restriction item test result.

[0124] It should be noted that for data reading and writing, the entire data interaction process is based on the maximum data transmission rate supported by the terminal device (in this test, the I2C, UART, and SPI data transceivers in the test equipment test), so there is no need to consider it further.

[0125] Specifically, the first test result and the test results of other restriction items such as the second test result are associated and combined to generate a restriction item test result.

[0126] This embodiment sends test data to each of the terminal devices through the bus bridge device based on each of the dynamic addresses, and performs timing through a counter to obtain the total data transmission and reception time, and then obtains a first test result based on the data read return time limit and the total data transmission and reception time, and then performs a data write operation to the terminal device through the bus bridge device based on the data write length limit to obtain a second test result, and then associates and combines the first test result and the second test result to generate the restriction item test result, so as to accurately verify whether the device completes the data transmission within the specified time through accurate timing, ensure that the response speed of the device in actual application meets the design requirements, and verify whether the device can correctly process data of the maximum length, which helps to ensure the stability and reliability of the device under extreme conditions, more comprehensively reflect the performance of the device, and avoid problems that may be missed in single-dimensional testing, thereby improving the reliability and stability of the system, and improving testing efficiency and automation.

[0127] In a feasible implementation manner, the performing of a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information, before obtaining the device test result, further includes:

[0128] Step S61, generating an interrupt request, and sending the interrupt request to the bus bridge device;

[0129] It should be noted that the interrupt request refers to a signal generated by a terminal device or a test device and sent to a bus bridge device, which is used to request interrupt processing and to notify the bus bridge device that there is an emergency or important data that needs to be processed.

[0130] Specifically, for a terminal device that supports interrupts, an interrupt request is generated, and the interrupt request is sent to the bus bridge device. Figure 6 , Figure 6 The example flow chart of the interrupt event verification process in one embodiment of the bus bridge device testing method provided in the present application, the test device controls the ALERT signal to become low through the I2C data transceiver module, that is, sends an interrupt signal, and then the I3C control module receives the interrupt signal through SCL (Serial Clock Line, serial clock line) & SDA (Serial Data Line, serial data line) (that is, the I3C Bridge controls the SDA signal to become a low level when the I3C bus is idle (SCL & SDA signals are both high levels)).

[0131] Step S62, detecting whether the bus bridge device receives the interrupt request;

[0132] Specifically, it is detected whether the bus bridge device receives the interrupt request. Further, if so, the test device reads data from the I2C data transceiver module through the I3C control module through the I3CBridge, and releases the I2CALERT signal after the reading is completed. The data comparison module in the test device compares the read data with the data read by the I2C data transceiver module. If the data comparison is consistent, the test passes; if not, the bus bridge device test process is terminated and the device interrupt processing exception result is generated.

[0133] Step S63: if not, the bus bridge device test process is terminated and a device interrupt processing abnormal result is generated.

[0134] It should be noted that the device interrupt processing abnormal result refers to a test failure result generated during the test because the bus bridge device fails to correctly receive or process an interrupt request.

[0135] Specifically, if not, the bus bridge device test process is terminated and a device interrupt processing exception result is generated.

[0136] This embodiment generates an interrupt request and sends the interrupt request to the bus bridge device, thereby detecting whether the bus bridge device receives the interrupt request. If not, the bus bridge device test process is terminated, and a device interrupt processing exception result is generated, thereby verifying the interrupt processing capability, that is, verifying whether the bus bridge device can correctly receive and process the interrupt signal to ensure that the device can respond to emergency events or important communication requests in actual operation, and verifying whether the interrupt processing mechanisms between the bus bridge device and the terminal device are compatible to ensure that the two can work together, thereby improving the reliability and stability of the system and ensuring the real-time and responsiveness of the system.

[0137] In a feasible implementation manner, the performing of a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information, and obtaining a device test result, further includes:

[0138] Step S71, pushing the device test result to the client for the device designer to view;

[0139] Specifically, the device test results are pushed to the client for the device designer to view, wherein the results can be pushed via mobile devices such as mobile phones, tablets, computers, web pages, emails, public accounts, etc., without limitation.

[0140] Step S72, obtaining the test optimization strategy of the device designer;

[0141] It should be noted that the test optimization strategy refers to the specific methods and suggestions for improving the test process of the bus bridge device proposed by the equipment designer based on the test results.

[0142] Step S73: optimizing the bus bridge device test process based on the test optimization strategy.

[0143] Specifically, the test results are comprehensively analyzed to identify problems and bottlenecks in the test process, and then the equipment designers will make specific optimization suggestions, including but not limited to adjusting test parameters (such as data transmission rate, clock frequency, etc.), optimizing the test process (such as rearranging the test sequence, removing redundant test steps, and adding targeted test cases), improving test tools and methods (such as introducing automated testing tools and adopting new testing technologies), and troubleshooting and repairing the problems found (such as hardware improvements and software configuration optimization).

[0144] In addition, the comprehensiveness and practicality of the test can be enhanced by adding compatibility tests and simulating actual application scenarios. At the same time, the test documents and records should be improved to ensure the traceability of the test process and results. Finally, the test process should be adjusted and improved according to the optimization strategy to ensure that the test process is more efficient and accurate, and can better adapt to the characteristics and requirements of the device, thereby significantly improving the efficiency and quality of bus bridge device testing and providing strong guarantees for the stable operation and performance optimization of the device.

[0145] This embodiment pushes the device test results to the client for the device designer to view, and then obtains the test optimization strategy of the device designer, and optimizes the bus bridge device test process based on the test optimization strategy. Then, by pushing the test results to the device designers in a timely manner, they can quickly understand the performance and potential problems of the device, thereby reducing the test cycle and troubleshooting time, and quickly locate the problem and propose effective optimization strategies to improve the accuracy of the test. It can also dynamically adjust the test process to adapt to the characteristics and requirements of different devices, and continuously improve the test process according to the optimization strategy of the device designer to ensure that the test method is always in the best state and reduce development and maintenance costs.

[0146] It should be understood that the order of execution of the steps in the above embodiment does not necessarily mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiment of the present invention.

[0147] This application also provides a bus bridge device testing device, please refer to Figure 7 , the bus bridge device testing device comprises:

[0148] An acquisition module 71 is used to acquire the number and type of terminal devices connected to the back end of the bus bridge device;

[0149] A configuration module 72, configured to perform dynamic address configuration on each of the terminal devices based on the number of the devices, the type of the devices, and the supported configuration mode of the bus bridge device, and determine restriction information corresponding to each of the terminal devices;

[0150] The test module 73 is used to perform a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information to obtain a device test result.

[0151] The bus bridge device testing apparatus is also used for:

[0152] Generate a dynamic address allocation instruction, and perform dynamic address configuration for each of the terminal devices based on the device type, the supported configuration mode of the bus bridge device, and the dynamic address allocation instruction;

[0153] Determine whether the number of allocated dynamic addresses is consistent with the number of devices;

[0154] If so, obtain a first value in the bus characteristic register, and determine the restriction information corresponding to each of the terminal devices based on the first value.

[0155] The bus bridge device testing apparatus is also used for:

[0156] If not, a value reading instruction is generated, and the second value is read according to the value reading instruction;

[0157] Based on the second value, determining whether to perform secondary dynamic address configuration on each of the terminal devices;

[0158] If not, the bus bridge device test process is terminated and a device test failure result is generated.

[0159] The bus bridge device testing apparatus is also used for:

[0160] Based on each of the dynamic addresses, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain data sending test data and data receiving test data, and the data sending test data and the data receiving test data are compared to obtain an accuracy test result;

[0161] Based on the dynamic addresses and the restriction information, obtaining restriction item test results;

[0162] The accuracy test result and the restriction item test result are associated and combined to generate the device test result.

[0163] The bus bridge device testing apparatus is also used for:

[0164] Based on each of the dynamic addresses, the test data is sent to each of the terminal devices through the bus bridge device, and the total time of data transmission and reception is obtained by timing with a counter;

[0165] Obtaining a first test result according to the data read return time limit and the total data sending and receiving time;

[0166] Based on the data write length limit, performing a data write operation on the terminal device through the bus bridge device to obtain a second test result;

[0167] The first test result and the second test result are associated and combined to generate the restriction item test result.

[0168] The bus bridge device testing apparatus is also used for:

[0169] Generate an interrupt request, and send the interrupt request to the bus bridge device;

[0170] Detecting whether the bus bridge device receives the interrupt request;

[0171] If not, the bus bridge device test process is terminated and a device interrupt processing exception result is generated.

[0172] The bus bridge device testing apparatus is also used for:

[0173] Pushing the device test results to the client for device designers to view;

[0174] Obtaining a test optimization strategy of the device designer;

[0175] Based on the test optimization strategy, the bus bridge device test process is optimized.

[0176] The bus bridge device testing device provided by the present application adopts the bus bridge device testing method in the above embodiment, which can solve the technical problems in the background technology. Compared with the prior art, the beneficial effects of the bus bridge device testing device provided by the present application are the same as the beneficial effects of the bus bridge device testing method provided by the above embodiment, and other technical features in the bus bridge device testing device are the same as the features disclosed in the above embodiment method, which will not be repeated here.

[0177] The present application provides a bus bridge device testing device, which includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the bus bridge device testing method in the above-mentioned embodiment 1.

[0178] Reference below Figure 8, which shows a schematic diagram of the structure of a bus bridge device test device suitable for implementing the embodiment of the present application. The bus bridge device test device in the embodiment of the present application may include but is not limited to mobile terminals such as mobile phones, laptop computers, digital broadcast receivers, PDAs (Personal Digital Assistants), PADs (Portable Application Descriptions), PMPs (Portable Media Players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 8 The bus bridge device testing device shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0179] like Figure 8 As shown, the bus bridge device test device may include a processing device 1001 (such as a central processing unit, a graphics processor, etc.), which can perform various appropriate actions and processes according to the program stored in the read-only memory 1002 or the program loaded from the storage device 1003 to the random access memory 1004. In the random access memory 1004, various programs and data required for the operation of the bus bridge device test device are also stored. The processing device 1001, the read-only memory 1002 and the random access memory 1004 are connected to each other through the bus 1005. The input / output interface 1006 is also connected to the bus. Generally, the following systems can be connected to the input / output interface 1006: an input device 1007 including, for example, a touch screen, a touch pad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; an output device 1008 including, for example, a liquid crystal display (LCD: Liquid Crystal Display), a speaker, a vibrator, etc.; a storage device 1003 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1009. The communication device 1009 can allow the bus bridge device test device to communicate with other devices wirelessly or wired to exchange data. Although the bus bridge device test device with various systems is shown in the figure, it should be understood that it is not required to implement or have all the systems shown. More or fewer systems can be implemented or have alternatively.

[0180] In particular, according to the embodiments disclosed in the present application, the process described above with reference to the flowchart can be implemented as a computer software program. For example, the embodiments disclosed in the present application include a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network through a communication device, or installed from a storage device 1003, or installed from a read-only memory 1002. When the computer program is executed by the processing device 1001, the above-mentioned functions defined in the method of the embodiment disclosed in the present application are executed.

[0181] The bus bridge device testing device provided by the present application adopts the bus bridge device testing method in the above embodiment, which can solve the technical problems in the background technology. Compared with the prior art, the beneficial effects of the bus bridge device testing device provided by the present application are the same as the beneficial effects of the bus bridge device testing method provided by the above embodiment, and the other technical features in the bus bridge device testing device are the same as the features disclosed in the method of the previous embodiment, which will not be repeated here.

[0182] It should be understood that the various parts disclosed in this application can be implemented by hardware, software, firmware or a combination thereof. In the description of the above embodiments, specific features, structures, materials or characteristics can be combined in any one or more embodiments or examples in a suitable manner.

[0183] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

[0184] The present application provides a computer-readable storage medium having computer-readable program instructions (ie, computer programs) stored thereon, and the computer-readable program instructions are used to execute the bus bridge device testing method in the above-mentioned embodiment.

[0185] The computer-readable storage medium provided in the present application may be, for example, a USB flash drive, but is not limited to electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems or devices, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM: Random Access Memory), a read-only memory (ROM: Read Only Memory), an erasable programmable read-only memory (EPROM: Erasable Programmable Read Only Memory or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM: CD-Read Only Memory), an optical storage device, a magnetic storage device, or any suitable combination of the above. In this embodiment, the computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system or device. The program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (Radio Frequency: Radio Frequency), etc., or any suitable combination of the above.

[0186] The computer-readable storage medium may be included in the bus bridge device test device; or may exist independently without being assembled into the bus bridge device test device.

[0187] The computer-readable storage medium carries one or more programs. When the one or more programs are executed by the bus bridge device test device, the bus bridge device test device:

[0188] Get the number and type of terminal devices connected to the back end of the bus bridge device;

[0189] Based on the number of devices, the device types, and the supported configuration mode of the bus bridge device, dynamically configure the address of each terminal device, and determine the restriction information corresponding to each terminal device;

[0190] Based on each of the dynamic addresses and each of the restriction information, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain a device test result.

[0191] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0192] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a sequence different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0193] The modules involved in the embodiments described in this application may be implemented by software or hardware, wherein the name of the module does not constitute a limitation on the unit itself in some cases.

[0194] The readable storage medium provided by the present application is a computer-readable storage medium, which stores computer-readable program instructions (i.e., computer programs) for executing the above-mentioned bus bridge device testing method, and can solve the technical problems in the background technology. Compared with the prior art, the beneficial effects of the computer-readable storage medium provided by the present application are the same as the beneficial effects of the bus bridge device testing method provided by the above-mentioned embodiment, and will not be repeated here.

[0195] An embodiment of the present application provides a computer program product, including a computer program, which implements the steps of the bus bridge device testing method as described above when the computer program is executed by a processor.

[0196] The computer program product provided in this application can solve the technical problems in the background technology. Compared with the prior art, the beneficial effects of the computer program product provided in the embodiment of this application are the same as the beneficial effects of the bus bridge device testing method provided in the above embodiment, which will not be repeated here.

[0197] The above descriptions are only some embodiments of the present application, and are not intended to limit the patent scope of the present application. All equivalent structural changes made using the contents of the present application specification and drawings under the technical concept of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A bus bridge device testing method, characterized in that: include: Get the number and type of terminal devices connected to the back end of the bus bridge device; Based on the number of devices, the device types, and the supported configuration mode of the bus bridge device, dynamically configure the address of each terminal device, and determine the restriction information corresponding to each terminal device; Based on each of the dynamic addresses and each of the restriction information, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain a device test result.

2. The bus bridge device testing method according to claim 1, characterized in that: The dynamically configuring the address of each terminal device based on the number of devices, the type of devices, and the supported configuration mode of the bus bridge device, and determining the restriction information corresponding to each terminal device, includes: Generate a dynamic address allocation instruction, and perform dynamic address configuration for each of the terminal devices based on the device type, the supported configuration mode of the bus bridge device, and the dynamic address allocation instruction; Determine whether the number of allocated dynamic addresses is consistent with the number of devices; If so, obtain a first value in the bus characteristic register, and determine the restriction information corresponding to each of the terminal devices based on the first value.

3. The bus bridge device testing method according to claim 2, characterized in that: After determining whether the number of allocated dynamic addresses is consistent with the number of devices, the method further includes: If not, a value reading instruction is generated, and the second value is read according to the value reading instruction; Based on the second value, determining whether to perform secondary dynamic address configuration on each of the terminal devices; If not, the bus bridge device test process is terminated and a device test failure result is generated.

4. The bus bridge device testing method according to claim 1, characterized in that: The step of performing a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information to obtain a device test result includes: Based on each of the dynamic addresses, a data transmission test is performed on each of the terminal devices through the bus bridge device to obtain data sending test data and data receiving test data, and the data sending test data and the data receiving test data are compared to obtain an accuracy test result; Based on each of the dynamic addresses and each of the restriction information, obtaining a restriction item test result; The accuracy test result and the restriction item test result are associated and combined to generate the device test result.

5. The bus bridge device testing method according to claim 4, characterized in that: The restriction information includes a data read return time limit and a data write length limit; The obtaining of restriction item test results based on each of the dynamic addresses and each of the restriction information includes: Based on each of the dynamic addresses, the test data is sent to each of the terminal devices through the bus bridge device, and the total time of data transmission and reception is obtained by timing with a counter; Obtaining a first test result according to the data read return time limit and the total data sending and receiving time; Based on the data write length limit, performing a data write operation on the terminal device through the bus bridge device to obtain a second test result; The first test result and the second test result are associated and combined to generate the restriction item test result.

6. The bus bridge device testing method according to claim 1, characterized in that: Before performing a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information and obtaining a device test result, the method further includes: Generate an interrupt request, and send the interrupt request to the bus bridge device; Detecting whether the bus bridge device receives the interrupt request; If not, the bus bridge device test process is terminated and a device interrupt processing exception result is generated.

7. The bus bridge device testing method according to claim 1, characterized in that: After performing a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information and obtaining a device test result, the method further includes: Pushing the device test results to the client for device designers to view; Obtaining a test optimization strategy of the device designer; Based on the test optimization strategy, the bus bridge device test process is optimized.

8. A bus bridge device testing device, characterized in that: include: An acquisition module is used to acquire the number and type of terminal devices connected to the back end of the bus bridge device; A configuration module, configured to perform dynamic address configuration on each of the terminal devices based on the number of the devices, the type of the devices, and the supported configuration mode of the bus bridge device, and determine restriction information corresponding to each of the terminal devices; The test module is used to perform a data transmission test on each of the terminal devices through the bus bridge device based on each of the dynamic addresses and each of the restriction information to obtain a device test result.

9. A bus bridge device testing device, characterized in that: The bus bridge device testing device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the bus bridge device testing method according to any one of claims 1 to 7.

10. A storage medium, characterized in that: The storage medium is a computer-readable storage medium, and a computer program is stored on the storage medium. When the computer program is executed by a processor, the steps of the bus bridge device testing method according to any one of claims 1 to 7 are implemented.

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