Communication interface with calibration delay circuit

Abstract

The invention relates to a communication interface with a calibration delay circuit. In described examples, an apparatus (102) includes a transmitter (208), a receiver (212), and a control circuit (202, 209, and 210). A transmitter (208) transmits a clock signal and a receiver (212) receives a response signal. Control circuits (202, 209, 210) are coupled to the transmitter (208) and the receiver (212). The control circuit (202, 209, 210) causes the transmitter (208) to transmit a first clock signal having a first clock period and to transmit a second clock signal having a second clock period greater than the first clock period. The control circuit (202, 209 and 210) determines whether a first pattern of the signal responsive to the first clock signal is the same as a second pattern of the signal responsive to the second clock cycle. If the modes are the same, the control circuit (202, 209 and 210) delays the clock signal with a delay in response to the first clock cycle to generate a delayed clock signal. The receiver (212) samples the response signal using the delayed clock signal during normal operation of the device (102).

Description

Technical Field

[0001] The present application relates generally to communication interfaces, and more particularly to compensating for round-trip delays in short-range communication interfaces. Background Art

[0002] The Serial Peripheral Interface (SPI) is a serial communication interface used, for example, in embedded systems for short-range wired communication between integrated circuits (ICs). In some instances, microcontrollers use SPI to communicate with secure digital (SD) card readers, radio frequency identification (RFID) card readers, and 2.4 gigahertz (GHz) wireless transmitters and receivers. SPI enables high-speed synchronous communication, i.e., simultaneous communication from a master node to a subnode and from a subnode to a master node. Summary of the invention

[0003] In the described example, a device includes a transmitter, a receiver, and a control circuit. The transmitter transmits a clock signal, and the receiver receives a response signal. The control circuit is coupled to the transmitter and the receiver. The control circuit causes the transmitter to transmit a first clock signal having a first clock period, and to transmit a second clock signal having a second clock period greater than the first clock period. The control circuit determines whether a first pattern of a signal responsive to the first clock signal is the same as a second pattern of a signal responsive to the second clock period. If the patterns are the same, the control circuit delays the clock signal with a delay responsive to the first clock period to generate a delayed clock signal. The receiver samples the response signal using the delayed clock signal during normal operation of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A is a functional block diagram of a first example SPI system in an automotive or industrial environment, the SPI system including a SPI master node and a SPI slave node.

[0005] Figure 1B is a functional block diagram of a second example SPI system.

[0006] Figure 2 is a functional block diagram of a third example SPI system.

[0007] Figure 3 Is Figure 2 Timing diagram of example signals generated by the clock signal delay calibration procedure of an SPI system.

[0008] Figure 4A is used for Figure 2 An example procedure for initial calibration of the clock signal delay of an SPI system.

[0009] Figure 4B It is used to maintain Figure 2An example procedure for calibration of the clock signal delay of an SPI system.

[0010] Figure 5 Yes Figure 2 Functional block diagram of an example delay circuit is shown.

[0011] Figure 6 Yes Figure 5 Circuit and functional block diagram of an example delay cell is shown. DETAILED DESCRIPTION

[0012] The SPI master node transmits the data signal to the SPI daughter node using a chip select (CS) signal and an SPI clock (SCLK) signal, wherein the CS signal selects the SPI daughter node intended to receive the data signal, and the SCLK signal has a frequency corresponding to the data rate of the data signal. The receiver circuit of the SPI master node samples the response signal received from the SPI daughter node using the SCLK signal. The response signal is received by the SPI master node, and there is a certain amount of round trip delay (RTD) from the leading edge of the transmitted SCLK signal to the reception of the response signal. In some instances, the RTD responds to the time from the assertion of the CS signal to the reception of the response signal.

[0013] The example SPI master node reduces the error that may occur due to the incorrect timing of the reception of the SCLK signal that may have occurred. If the SPI master node receiver circuit receives the SCLK signal too quickly, the receiver may sample the line noise or pattern that does not correspond to the response signal. If the SPI master node receiver receives the SCLK signal too late, the receiver may not be able to sample the part of the response signal. Too fast corresponds to a time significantly less than RTD, and too late corresponds to a time significantly more than RTD. Therefore, the example SPI master node includes a delay circuit, which is configured to add a delay equal to RTD to the SCLK signal before the SCLK signal is passed to the SPI master node receiver to sample the response signal. This added delay can enable the SCLK signal to arrive at the SPI master node receiver at the right time (neither too fast nor too late) to sample the response signal.

[0014] The SPI delay circuit may include both coarse delay calibration and fine delay calibration. A coarse initial delay calibration may be performed to determine the initial value of the RTD by varying the frequency of the SCLK signal and comparing the RTD with the period of the SCLK signal. A fine initial delay calibration may be performed using a sequential search or a binary search within the potential range of the RTD determined by the coarse calibration. The resulting determined RTD is applied by the delay circuit to the SCLK signal for sampling the response signal from the corresponding SPI subnode.

[0015] The delay provided by the delay circuit can be calibrated continuously (e.g., continuously) using a delay calibration maintenance process. The delay calibration maintenance process accumulates the measured RTDs of multiple different response signals from the corresponding SPI subnode, averages the measured RTDs, and compares the difference between the average RTD and the currently applied RTD with a threshold to determine whether to replace the currently applied delay. If the difference exceeds the threshold, the delay calibration maintenance process includes applying a new RTD to the SCLK signal for sampling the response signal from the corresponding SPI subnode in response to or based on the average RTD, replacing (updating) the currently applied delay.

[0016] In this document, some different but related structures or signals have reference numerals using the format of [number][letter], such as SPI sub-nodes 104a, 104b, and 104c. In some examples, these structures or signals are generally referred to in singular form or as a group, using [number] instead of [letter], such as SPI sub-node 104. In addition, the same reference numerals or other reference designators are used in the figures to indicate structurally and / or functionally related features.

[0017] Figure 1A 1 is a functional block diagram of an example SPI system 100 in an automotive or industrial environment, the SPI system including an SPI master node 102 and an SPI daughter node 104. The SPI master node 102 and the SPI daughter node 104 are separate ICs. The SPI master node 102 includes a CS output that provides a CS signal, an SCLK output that provides an SCLK signal having an SCLK frequency, a MOSI output that provides a master node out daughter node in (MOSI) data signal to the SPI daughter node 104, and a MISO output that receives a master node in daughter node out (MISO) data signal from the SPI daughter node 104. The SPI daughter node 104 includes a CS input that receives a CS signal, an SCLK input that receives an SCLK signal, a MOSI input that receives a MOSI data signal, and a MISO output that provides a MISO data signal.

[0018] The SPI master node 102 generates a MOSI data signal so that it is synchronized with the SCLK signal. Therefore, the SPI child node 104 uses the SCLK signal to read the MOSI data signal (e.g., sample it). In some instances, the MOSI data signal corresponds to instructions for the SPI child node 104. The SPI child node 104 provides a MISO data signal in response to these instructions. In some instances, the MISO data signal includes data read from a memory of the SPI child node 104 or data generated by a sensor manufactured as part of the SPI child node 104. In some instances, the sensor as part of the SPI child node 104 includes, for example, an armature current on a motor or a temperature, pressure, voltage, or current sensor for motor drive control, or a signal decoder for a device start signal or other input / output signal, or a wireless fidelity (WiFi) or radio frequency receiver signal chain connected to an on-board or on-chip receiver antenna.

[0019] In some examples, the SPI sub-node 104 can provide a MISO signal responsive to the SCLK signal without the need for a MOSI data signal. For example, the SPI sub-node 104 includes a first-in-first-out (FIFO) memory (not shown) that serially reads out one bit of the data captured by the sensor in response to each successive rising (or falling) edge of the SCLK signal. Therefore, because the MISO data signal is responsive to the MOSI data signal or the SCLK signal, and the MOSI data signal is synchronized with the SCLK signal, the MISO data signal is referred to herein as being responsive to the SCLK signal.

[0020] Figure 1B 1 is a functional block diagram of a second example SPI system 106. The second SPI system 106 includes an SPI master node 102, a first SPI child node (SPI child node 0) 104a, a second SPI child node (SPI child node 1) 104b, and a third SPI child node (SPI child node 2) 104c. The first CS output (CS0) of the SPI master node 102 is connected to the CS input of the SPI child node 0 104a. The second CS output (CS1) of the SPI master node 102 is connected to the CS input of the SPI child node 1 104b. The third CS output (CS2) of the SPI master node 102 is connected to the CS input of the SPI child node 2 104c.

[0021] The SCLK output of the SPI master node 102 is connected to the corresponding SCLK inputs of the SPI child nodes 0, 1 and 2 (104a, 104b and 104c). The MOSI output of the SPI master node 102 is connected to the corresponding MOSI inputs of the SPI child nodes 0, 1 and 2 (104a, 104b and 104c) through the bus. The MISO input of the SPI master node 102 is also connected to the corresponding MISO outputs of the SPI child nodes 0, 1 and 2 (104a, 104b and 104c) through the bus. While data is being transmitted between the MISO ports, data can be transmitted between the MOSI ports. Therefore, SPI is a full-duplex interface.

[0022] To start SPI communication, the SPI master node 102 transmits the SCLK signal and selects the SPI subnode 104 by enabling the corresponding CS signal (e.g., the CS signal provided by the CS0 output, the CS1 output, or the CS2 output). In some instances, the CS signal is active low, while in other instances, the CS signal is active high. Selecting the SPI subnode 104 by enabling the corresponding CS signal will determine which SPI subnode 104 is activated to provide a signal in response to the SCLK signal. In some instances, the MOSI data signal represents an instruction to be executed by the selected SPI subnode 104, a control signal for the selected SPI subnode, or a configuration parameter for the selected SPI subnode.

[0023] In some examples, the SPI operating mode can be selected so that the rising edge or the falling edge of the SCLK signal is used to sample the MOSI data signal and shift the data from the memory (e.g., FIFO memory) to the MISO output of the corresponding SPI slave node 104. Therefore, depending on the mode, the rising edge or the falling edge of the MOSI data signal can represent data. The SPI master node 102 similarly samples the received MISO data signal in response to the mode-dependent edge of the SCLK signal.

[0024] Figure 2 is a functional block diagram of a third SPI system 200 . Figure 2 The SPI system 200 can be manufactured on a printed circuit board (PCB) and includes a SPI master node 102, a SPI slave node 104, and other board components 214. The SPI master node 102 includes a processor 202 such as a microcontroller, a memory 204, a clock 206 that provides a clock signal with a reference frequency, a transmitter 208, a calibration control circuit 209, a delay circuit 210, and a receiver 212. Figure 5 An example delay circuit 210 is depicted. SPI sub-node 104 includes various sub-node circuits 240 .

[0025] The child node circuit 240 includes, for example, a CS circuit for activating the SPI child node 104 in response to a CS signal having an ENABLE value, a sampling circuit for sampling the MOSI data signal, a sensor circuit, and a transmitter circuit for transmitting a response signal to the SPI master node 102. The board assembly 214 includes, for example, a galvanic isolator, such as an optical, inductive, or capacitive galvanic isolator.

[0026] Clock 206 is connected to processor 202, memory 204, transmitter 208, and receiver 212, and provides clock signals to them. Processor 202 is bidirectionally connected to request and receive data from memory 204, control transmitter 208, and provide data or prompts to transmitter 208 to initiate transmission to SPI subnode 104. Calibration control circuit 209 is connected to control transmitter 208, and is connected to control delay circuit 210. Receiver 212 is connected to provide data extracted from the received MISO data signal to processor 202. Receiver 212 is also connected to provide timing of the received data signal to calibration control circuit 209.

[0027] Transmitter 208 includes circuitry for generating a MOSI data signal in response to a clock signal and data provided by processor 202 and a CS signal in response to SPI sub-node 104 selection information provided by processor 202. Transmitter 208 also includes circuitry for receiving a clock signal provided by clock 206 and adjusting the clock signal to generate an SCLK signal. In some examples, this includes level shifting the clock signal, multiplying or dividing the frequency of the clock signal, or phase shifting the clock signal so that the level, frequency, and phase of the clock signal correspond to the level, frequency, and phase of the MOSI data signal or a clock signal configured to clock the target SPI sub-node 104 or in response to control of calibration control circuit 209. In some examples, transmitter 208 synchronizes the edge of the SCLK signal used to sample and shift the MOSI data signal with the edge of the MOSI data signal representing the data (or synchronizes the edge of the MOSI data signal with the edge of the SCLK signal).

[0028] The MOSI output of the transmitter 208 is connected to the MOSI pin 216 of the SPI master node 102. The MOSI pin 216 corresponds to the MOSI output of the SPI master node 102. The CS output of the transmitter 208 is connected to the CS input of the calibration control circuit 209 and the CS pin 220 of the SPI master node 102, which corresponds to the CS output of the SPI master node 102. The SCLK output of the transmitter 208 is connected to the SCLK input of the calibration control circuit 209, the clock input of the delay circuit 210, and the SCLK pin 224 of the SPI master node 102. The SCLK pin 224 corresponds to the SCLK output of the SPI master node 102. The output of the delay circuit 210 is connected to the clock input of the receiver 212.

[0029] The MOSI pin 216 of the SPI master node 102 is connected to the MOSI pin 218 of the SPI slave node 104 via the board assembly 214. The CS pin 220 of the SPI master node 102 is connected to the CS pin 222 of the SPI slave node 104 via the board assembly 214. The SCLK pin 224 of the SPI master node 102 is connected to the SCLK pin 226 of the SPI slave node 104 via the board assembly 214. In some instances, the board assembly 214 (and / or off-board components in the circuit path) introduces a significant delay to the MOSI data signal transmitted from the MOSI output of the transmitter 208 to the MOSI pin of the SPI slave node 104. For example, galvanic isolation between different voltage domains with mutually isolated grounds may introduce significant signal delays. In some instances, the delay may be between 2 nanoseconds and 20 nanoseconds. This transmission delay from the SPI master node 102 to the SPI slave node 104 is referred to as Ta. Ta may also be referred to as the time it takes for the leading edge of the SCLK signal to be transmitted from the SPI master node 102 to the SPI slave node 104 .

[0030] The MOSI pin 218, CS pin 222, and SCLK pin 226 of the SPI subnode 104 are connected to respective inputs of the subnode circuit 240. The output of the subnode circuit 240 is connected to the MISO pin 230 of the SPI subnode 104. If the CS signal is selected and activated corresponding to the SPI subnode 104, the subnode circuit 240 processes the SCLK signal received at the SCLK pin 226, and in some examples, processes the MOSI signal received via the MOSI pin 218 in response to the SCLK signal. In response to the received signal, the SPI subnode 104 provides the resulting output signal to its MISO pin 230. This output signal is provided to the MISO pin 230 with a delay (total processing time) Tb relative to the leading edge of the SCLK signal received at the SCLK pin 226.

[0031] The MISO pin 230 of the SPI slave node 104 is connected to the MISO pin 228 of the SPI master node 102 via the board assembly 214. The MISO pin 228 is connected to the data input of the calibration control circuit 209 and the data input of the receiver 212. The receiver 212 processes the received MISO data signal in response to the delayed SCLK signal provided to the clock input of the receiver 212 by the delay circuit 210.

[0032] The delay of the MISO data signal to the delay circuit 210 (or the receiver 212) is Tc. Therefore, the RTD of the transmission of the SCLK signal from the SPI master node 102 to the SPI slave node 104 to the reception of the response data signal from the SPI slave node 104 by the SPI master node 102 is given by RTD=Ta+Tb+Tc. The RTD is measured from the assertion of the CS signal (enabling the corresponding SPI slave node 104) to the first output data switch (rising edge or falling edge, depending on the SPI mode) detected by the receiver 212.

[0033] Receiver 212 samples the received MISO data signal using the SCLK signal to extract the data transmitted by SPI slave node 104. The SCLK signal corresponds to a specific MISO data signal in response to the SCLK signal transmitted by SPI master node 102. As described above, if the SCLK signal arrives at receiver 212 before the MISO data signal, receiver 212 may sample line noise. In some instances, ignoring the noise consumes processor time and power.

[0034] Therefore, calibration control circuit 209 controls delay circuit 210 to add a delay to the SCLK signal provided to receiver 212. Calibration control circuit 209 calibrates the delay to be equal to RTD. Figure 3 , 4A and 4B describe the calibration of the delay.

[0035] Figure 3 Is Figure 2 300 is a timing diagram of example signals generated by the clock signal delay calibration process of the SPI system. In the timing diagram 300, CLK can represent the frequency of the clock signal generated by the clock 206, or a different clock rate, such as the highest frequency clock rate available to the corresponding SPI child node 104.

[0036] The timing diagram 300 includes a CS signal 302, a plurality of SCLK signals 304, 308, 312, and 316, and a plurality of MISO data signals 306, 310, 314, and 318. The SCLK signals 304, 308, 312, and 316 are provided by the SPI master node 102. The MISO data signals 306, 310, 314, and 318 are MISO data signals provided by the SPI slave node 104 and are responsive to corresponding SCLK signals 304, 308, 312, and 316 provided by the SPI master node 102 to the SPI slave node 104. The MISO data signals 306, 310, 314, and 318 are received by the receiver 212 of the SPI master node 102.

[0037] The illustrated SCLK signals and corresponding MISO data signals include a first SCLK signal 304 having a frequency equal to CLK (SCLK=CLK), a first MISO data signal 306 having a data rate equal to CLK (Data is CLK), a second SCLK signal 308 having a frequency equal to CLK divided by 2 (SCLK=CLK / 2), a second MISO data signal 310 having a data rate equal to CLK divided by 2 (Data is CLK / 2), a third SCLK signal 312 having a frequency equal to CLK divided by 4 (SCLK=CLK / 4), a third MISO data signal 314 having a data rate equal to CLK divided by 4 (Data is CLK / 4), a fourth SCLK signal 316 having a frequency equal to CLK divided by 8 (SCLK=CLK / 8), and a fourth MISO data signal 318 having a data rate equal to CLK divided by 8 (Data is CLK / 8).

[0038] CS signal 302 begins to assert at T0 with an ENABLE value (e.g., a high level). After CS signal 302 is asserted, SCLK signal 304, 308, 312, or 316 begins to be provided at T1. The time from T0 to T1 is the clock shift assertion delay. In some examples, this delay is equal to one-half of one cycle of the signal generated by the highest frequency oscillator of SPI master node 102. In some examples, the highest frequency oscillator of SPI master node 102 is clock 206, which provides a clock signal for generating SCLK signal.

[0039] SPI master 102 receives line noise at its receiver 212 until T2, after which valid data is received by receiver 212. Line noise or patterns that do not correspond to the MISO data signal in response to the SCLK signal are indicated as X0, X1, X2, etc. in the corresponding MISO data signal 306, 310, 314, or 318. Valid data is indicated as D0, D1, D2, etc. in the corresponding MISO data signal 306, 310, 314, or 318.

[0040] Figure 4A is used for Figure 2 An example process 400 for initial calibration of the clock signal delay of the SPI system 200 of the embodiment of the present invention. The process 400 is controlled by the calibration control circuit 209 (in some instances, the processor 202), which controls the CS signal timing and the SCLK signal frequency and the timing for the calibration test, and controls the delay added by the delay circuit 210 (for both the normal operation of the process 400 and the SPI master node 102). The calibration is performed for the RTD of the response signal corresponding to the transmission to a specific SPI subnode in one or more SPI subnodes 104 and the specific SPI subnode in the one or more SPI subnodes. Therefore, there are different RTDs determined by the SPI master node 102 for different connected SPI subnodes in one or more connected SPI subnodes 104. In some instances, the SPI master node 102 uses the worst case (longest) RTD determined by the process 400 to compensate for the RTD of each connected SPI subnode 104. In some instances, the RTD determined by the process 400 for the connected SPI subnode 104 is used to compensate for the RTD of the corresponding SPI subnode 104. In parallel with the description of the steps of the initial calibration process 400, Figure 3 .

[0041] refer to Figure 3 and 4A , an initial delay calibration is performed by measuring the RTD. This is done by determining the SCLK signal frequency so that the response signal is received by the receiver 212 within one cycle of the SCLK signal 304, 308, 312, or 316. During this test, it is assumed that repeated reads of the same target SPI subnode 104 will result in the same response MISO signal (thus, the same data is read out of the same memory of the same SPI subnode 104). In step 402, a clock with an interface clock period (T IFPRD =1 / CLK) of the SCLK signal 304, wherein the interface clock period is the clock period T of the oscillator (eg, the clock 206). PRD A known multiple a of T IFPRD =a×T PRD In this example, T PRD is the period of the clock signal provided by clock 206 .

[0042] In step 404, the processor 202 causes the transmitter 208 to transmit the SCLK signal to the corresponding SPI sub-node 104, and the receiver 212 receives the SCLK signal and the MISO data signal provided by the SPI sub-node 104 in response to the SCLK signal. In some examples, the SCLK signal is provided to the receiver 212 with a delay corresponding to the period of the SCLK signal. The response MISO data signal includes at least one data switch, such as from logic 0 to logic 1 or from logic 1 to logic 0. In some examples, the data switch detection is responsive to the output from the receiver 212 to the calibration control circuit 209.

[0043] In step 406, the period of the SCLK signal is multiplied by 2 (the frequency is divided by 2), the modified SCLK signal is transmitted to the SPI subnode 104, and the receiver 212 receives the SCLK signal and the resulting MISO data signal. Let p be the iteration count of step 406, where p is equal to 0 for the SCLK signal transmitted in step 404. The SCLK and MISO signals corresponding to the p-th iteration of step 406 are referred to herein as the p-th iteration signals. Steps 408 to 416 test whether one period of the (p-1)-th iteration SCLK signal is greater than the RTD of the target SPI subnode 104. Therefore, steps 408 to 416 perform a relatively coarse search for the RTD corresponding to the target subnode 104. Step 418 performs a relatively fine search for the RTD corresponding to the target subnode 104, thereby refining the results of steps 408 to 418.

[0044] An initial iteration of step 406 corresponds to second SCLK signal 308 and second MISO data signal 310. Subsequent iterations of step 406 correspond to third SCLK signal 312 and fourth SCLK signal 316 (etc.) and third MISO data signal 314 and fourth MISO data signal 318 (etc.).

[0045] Thus, in a first iteration of step 406, second SCLK signal 308 and second MISO data signal 310 have a frequency that is one-half the frequency of first SCLK signal 304 and first data signal 306 (CLK / 2 instead of CLK). Similarly, in a second iteration of step 406, third SCLK signal 312 and third data signal 314 have a frequency that is one-half the frequency of second SCLK signal 308 and second MISO data signal 310 (CLK / 4 instead of CLK / 2). And the signals in the third iteration of step 406 have a frequency that is one-half the frequency of the signals of the second iteration (CLK / 8 instead of CLK / 4). In some examples, the iteration of step 406 modifies the SCLK signal frequency by a factor (or addend, multiplicand, or other modifier) ​​other than division by 2.

[0046] In step 408, processor 202 determines whether a (p-1)th iteration response (MISO) signal is received from SPI slave node 104 within a single cycle of the (p-1)th iteration SCLK signal. This determination is made by comparing the pattern detected in the (p-1)th iteration MISO data signal with the pattern detected in the pth iteration MISO data signal. The pattern corresponds to a data value detected in the MISO data signal at a rising edge of the SCLK signal after the first rising edge, and thus a logical 1 or a logical 0. (If the SCLK signal is provided to receiver 212 with a delay corresponding to the cycle of the SCLK signal, the detection may occur at the first rising edge.)

[0047] Herein, pattern comparison is performed by comparing a plurality of leading bits before the first data switch (transition from logic 1 to logic 0 or from logic 0 to logic 1) in each MISO data signal and / or comparing the bits after the first data switch in each MISO data signal. The SCLK signal reads a number of bits corresponding to a number of clock cycles in the transmitted SCLK signal from the target SPI subnode 104. If the period of the SCLK signal is less than RTD, one or more leading bits corresponding to line noise will be read. In addition, SCLK signals corresponding to different iterations p will read different numbers of leading bits corresponding to line noise. The same indication that iteration p-1 and iteration p patterns do not contain false data corresponding to line noise. In some instances, the bits corresponding to line noise may be read as random logic values. If it is determined that the two patterns are the same, the results are verified by steps 410 and 412. Otherwise, the process returns to step 406.

[0048] In step 410, the SCLK signals corresponding to iterations p-1 and p are retransmitted. In step 412, the resulting MISO data signals are compared. If the pattern is again determined to be the same, then process 400 proceeds to step 414, otherwise process 400 returns to step 406.

[0049] Steps 414 and 416 determine the edge independence of the pattern matching result. In step 414, the (p-1)th and pth iteration SCLK signals are retransmitted by the SPI master node 102, wherein the SCLK signals are delayed by one-half of the corresponding SCLK signal period. Therefore, the (p-1)th iteration SCLK signal is transmitted to the SPI slave node 104, wherein the clock shift assertion delay (delay after the assertion of the CS signal 302) is 2 p-2 ×T IFPRD , and the pth iteration SCLK signal is transmitted to the SPI sub-node 104, where the clock shift assertion delay is 2 p-1 ×T IFPRD .

[0050] In step 416, the response signal patterns are compared. If the MISO signal patterns of the (p-1)th and pth iteration SCLK signals transmitted in step 414 match, then process 400 proceeds to step 418. Otherwise, process 400 returns to step 406.

[0051] If step 416 determines a match, then the SCLK cycle 2 of the (p-1)th iteration p-1 ×T IFPRD is the upper limit on the RTD of the corresponding SPI child node 104. Therefore, 2 p-2 ×T IFPRD ≤RTD≤2 p-1 ×T IFPRD In some examples, if (p-1) is equal to 0 for a successful iteration, process 400 stops here and the SCLK signal frequency used for step 404 is used as the RTD.

[0052] In the illustrated example, the first output signal data toggle (leading edge of the response data) is received within one cycle of the SCLK signal after step 404 and after two iterations of step 406, where the SCLK frequency is equal to CLK / 4. This is determined in step 408 and verified in steps 410 and 412, and edge independence is confirmed by steps 414 and 416. An iteration that provides a determined and verified RTD upper limit is also referred to herein as a successful iteration or a successful comparison.

[0053] In step 418, a search is performed to determine whether p-2 ×T IFPRD ≤RTD<2 p-1 ×T IFPRD In some instances, this search is performed as a binary search or a sequential search (or using a different search strategy). To perform the search, the SCLK signal is transmitted at a frequency corresponding to the (p-2)th iteration. Therefore, if p is equal to two for a successful (p-1)th iteration, such that T IFPRD ≤RTD<2×T IFPRD , then the SCLK signal is transmitted at a frequency CLK corresponding to the SCLK signal 304. Similarly, if p is equal to 4 for a successful iteration, then the SCLK signal is transmitted at a frequency CLK / 4 corresponding to the SCLK signal 312.

[0054] For sequential search, the SCLK signal is provided to the receiver 212 with a delay corresponding to 2 p-2 ×T IFPRD + k × granularity delay. Here, granularity delay is the selected delay increment used to search the possible RTD delay space described above, and k is a variable with a value ranging from 1 to 2.p-2 ×T IFPRD / granularity delay range. The detected pattern of the response MISO data signal for each value of k is compared to the detected pattern of the response MISO data signal for the corresponding k+1 value. The test ends when the value of k is determined such that one additional bit is read from the MISO data signal in response to k rather than in response to k+1 (thus, the pattern does not match), and values ​​of k greater than k+1 cause the MISO data signal pattern to match the MISO data signal pattern in response to k+1 (thus, the pattern matches). When the test ends, RTD is responsive to the determined k+1 value such that RTD=2 p-2 ×T IFPRD +(k+1)×granularity delay.

[0055] For a binary search, the SCLK signal is provided to the receiver 212 with a delay corresponding to (2 p-2 +2 p-3 )×T IFPRD , therefore, at the midpoint of the determined RTD range. The resulting MISO data signal pattern is compared with the MISO data signal pattern to obtain the value corresponding to 2 p-1 ×T IFPRD If one extra bit is read in response to the midpoint delay of the determined range rather than in response to the upper limit delay of the determined range, then the RTD is in the upper half of the determined range, between the midpoint delay and the upper limit delay. Therefore, in the previous midpoint delay (2 p-2 +2 p-3 )×T IFPRD A new midpoint delay is selected between the current upper delay and the previous midpoint delay becomes the new lower delay. In this example, the new midpoint delay is (2 p-2 +2 p-3 +2 p-4 )×T IFPRD .

[0056] Otherwise, the RTD is in the lower half of the determined range, between the previous midpoint delay and the current lower limit delay (2 p-2 ×T IFPRD ) and the previous midpoint delay becomes the new upper delay. In this example, the new midpoint delay is (2 p-2 +2 p-3 -2 p-4 )×T IFPRD .

[0057] This process of binary search is repeated until a selected granularity level between the midpoint delay and the corresponding upper limit delay is reached. The test ends when it is determined that the midpoint delay causes one of the following two situations to be true. (1) An additional bit is read from the MISO data signal in response to the lower limit delay rather than in response to the corresponding midpoint delay (thus, the pattern does not match), and a delay longer than the midpoint delay causes the MISO data signal pattern to match the MISO data signal pattern in response to the midpoint delay (thus, the pattern matches). For situation (1), when the test ends, the RTD responds to the determined midpoint delay. (2) Alternatively, an additional bit is read from the MISO data signal in response to the midpoint delay rather than in response to the corresponding upper limit delay (thus, the pattern does not match), and a delay longer than the upper limit delay causes the MISO data signal pattern to match the MISO data signal pattern in response to the upper limit delay (thus, the pattern matches). For situation (2), when the test ends, the RTD responds to the determined upper limit delay.

[0058] In step 420 , delay circuit 210 applies the determined RTD to the SCLK signal provided to receiver 212 for capturing (sampling) response signals received from corresponding SPI sub-nodes 104 , including during normal operation of SPI system 200 .

[0059] Figure 4B It is used to maintain Figure 2 An example process 422 of calibrating the clock signal delay of the SPI system 200 is shown. The calibration control circuit 209 (in some examples, the processor 202) controls the maintenance delay calibration process 422, including by controlling the delay added by the delay circuit 210. After step 420, the maintenance delay calibration is performed to compensate for changes in the RTD, such as changes caused by changes in temperature and voltage. In some examples, the process 422 is continuously performed during the operation of the SPI master node 102 to achieve continuous delay calibration of the RTD of the signal between the SPI master node 102 and the corresponding SPI slave node 104.

[0060] In step 424, for each data frame received by the receiver 212, the duration from the assertion of the CS signal to the first data toggle (the first edge of the pattern after RTD) is counted, and for 2 MThe count is accumulated for each data frame, where M is an integer. Here, a data frame is a MISO data signal that provides a complete response to the SCLK signal transmitted from the SPI master node 102 to a specific SPI slave node 104. This count is maintained separately by the SPI master node 102 for each SPI slave node 104. In some examples, this delay can be counted as a multiple of the delay provided by the smallest delay element of the delay circuit 210, or counted as the sum of the delay element control codes of the delay circuit 210. This sum is referred to as RTD SUM Therefore, for 2 M data frames, where RTD (current RTD, RTD CURRENT ) is represented as a delay code with an integer N bits, RTD SUM It may require up to N+M bits to represent.

[0061] In step 426, for each MISO data signal received, the number of leading data bits that did not toggle (from high to low, or from low to high) is counted, and for 2 M This count is accumulated for each frame. This count is called NTGLCNT SUM (No toggle count sum). In step 428, the bit duration (signal duration corresponding to one bit) is multiplied by NTGLCNT SUM With RTD SUM Subtract (multiply the product by RTD SUM The duration of each bit is equal to the period of the SCLK signal, which will be referred to as SCLK PRD Therefore, the refined sum of RTD is RTD SUMRefined Given by Equation 1:

[0062] RTD SUMRefined =RTD SUM -SCLK PRD ×NTGLCNT SUM Equation 1

[0063] In some examples, a delay corresponding to 0, 1, or -1 minimum delay element (one least significant bit (LSB) of the delay code) is included in each data frame RTD SUM Therefore, RTD SUMRefined Can accumulate up to +2 M or -2 M Multiply the error by the LSB of the delay code. In step 430, convert the RTD SUMRefined To express relative to the precise clock reference CLK REF The delay to determine the RTD CLKREFIn some examples, delay circuit 210 is sensitive to temperature and pressure, and the clock reference is independent of temperature and pressure.

[0064] In step 432, the RTD CLKREF Convert back to the delayed element term and discard the M LSBs from the result to determine the RTD FINAL . Execute step 430 to convert, then RTD CLKREF Converting back to delay element terms reduces or eliminates the temperature and pressure dependence of the resulting delay code. Discarding the M LSBs gives 2 M The average RTD between data frames and also average the error to be less than or equal to one LSB, as described, RTD SUMRefined The error in the RTD SUMRefined The M LSBs (in 2 M RTD FINAL The resulting sum error in is less than or equal to one LSB.

[0065] In step 434, the RTD is determined FINAL With RTD CURRENT Is the magnitude of the difference between the two greater than a threshold? If so, then in step 436, RTD FINAL Replace RTD CURRENT , in order to sample the MISO data signal from the corresponding SPI child node 104. Otherwise, in step 438, RTD CURRENT continues to sample the MISO data signal from the corresponding SPI child node 104. In some examples, the new RTD FINAL Code Replacement RTD CURRENT , or in conjunction with the RTD CURRENT The weighted sum of is used to derive the next delay code. In some instances, the weighted sum can be used to limit the amount of delay change for each iteration of the maintenance delay calibration process 422. In some instances, an upper limit on the delay change for each iteration of the process 422 can be used for this (limiting) purpose.

[0066] Figure 5 Yes Figure 22. The functional block diagram of the example delay circuit 210 shown in FIG. The delay circuit includes three delay cells A 502, three delay cells B 504, three delay cells C 506, and three delay cells D 508, a first decoder 510, a second decoder 512, a third decoder 514, and a fourth decoder 516. The three delay cells A 502 include a first delay cell A 502a, a second delay cell A 502b, and a third delay cell A 502c. The three delay cells B 504 include a first delay cell B 504a, a second delay cell B 504b, and a third delay cell B 504c. The three delay cells C 506 include a first delay cell C 506a, a second delay cell C 506b, and a third delay cell C 506c. The three delay cells D 508 include a first delay cell D 508a, a second delay cell D 508b, and a third delay cell D 508c.

[0067] The SCLK input line is connected to the clock input of the delay circuit 210. As described above, the clock input of the delay circuit 210 is connected to the SCLK output of the transmitter 208 and receives the SCLK signal. The SCLK input line is also connected to the first input of the first delay unit A502a.

[0068] The first output of the first delay unit A 502a is connected to the first input of the second delay unit A 502b, and the second output of the second delay unit A 502b is connected to the second input of the first delay unit A 502a. The first output of the second delay unit A 502b is connected to the first input of the third delay unit A 502c, and the second output of the third delay unit A 502c is connected to the second input of the second delay unit A 502b. The first output of the third delay unit A 502c is connected to the second input of the third delay unit A 502c. The second output of the first delay unit A 502a is connected to the first input of the first delay unit B 504a.

[0069] The first output of the first delay unit B 504a is connected to the first input of the second delay unit B 504b, and the second output of the second delay unit B 504b is connected to the second input of the first delay unit B 504a. The first output of the second delay unit B 504b is connected to the first input of the third delay unit B 504c, and the second output of the third delay unit B 504c is connected to the second input of the second delay unit B 504b. The first output of the third delay unit B 504c is connected to the second input of the third delay unit B 504c. The second output of the first delay unit B 504a is connected to the first input of the first delay unit C 506a.

[0070] The first output of the first delay unit C 506a is connected to the first input of the second delay unit C 506b, and the second output of the second delay unit C 506b is connected to the second input of the first delay unit C 506a. The first output of the second delay unit C 506b is connected to the first input of the third delay unit C 506c, and the second output of the third delay unit C 506c is connected to the second input of the second delay unit C 506b. The first output of the third delay unit C 506c is connected to the second input of the third delay unit C 506c. The second output of the first delay unit C 506a is connected to the first input of the first delay unit D 508a.

[0071] The first output of the first delay unit D 508a is connected to the first input of the second delay unit D 508b, and the second output of the second delay unit D 508b is connected to the second input of the first delay unit D 508a. The first output of the second delay unit D 508b is connected to the first input of the third delay unit D 508c, and the second output of the third delay unit D 508c is connected to the second input of the second delay unit D 508b. The first output of the third delay unit D 508c is connected to the second input of the third delay unit D 508c. The second output of the first delay unit D 508a is connected to the delayed SCLK output line. The delayed SCLK output line is connected to the output of the delay circuit 210. As described above, the output of the delay circuit 210 is connected to the clock input of the receiver 212.

[0072] The first decoder 510 receives a first input Bit7 and a second input Bit6. A first output of the first decoder 510 is connected to a control input of a first delay unit A 502a, a second output of the first decoder 510 is connected to a control input of a second delay unit A 502b, and a third output of the first decoder 510 is connected to a control input of a third delay unit A 502c.

[0073] The second decoder 512 receives a first input Bit5 and a second input Bit4. A first output of the second decoder 512 is connected to a control input of the first delay unit B 504a, a second output of the second decoder 512 is connected to a control input of the second delay unit B 504b, and a third output of the second decoder 512 is connected to a control input of the third delay unit B 504c.

[0074] The third decoder 514 receives a first input Bit3 and a second input Bit2. A first output of the third decoder 514 is connected to a control input of the first delay unit C 506a, a second output of the third decoder 514 is connected to a control input of the second delay unit C 506b, and a third output of the third decoder 514 is connected to a control input of the third delay unit C 506c.

[0075] The fourth decoder 516 receives a first input Bit1 and a second input Bit0. A first output of the fourth decoder 516 is connected to a control input of the first delay unit D 508a, a second output of the fourth decoder 516 is connected to a control input of the second delay unit D 508b, and a third output of the fourth decoder 516 is connected to a control input of the third delay unit D 508c.

[0076] Processor 202 provides delay code, for example, 8-bit delay code, i.e., bit B0, ..., B7, to delay circuit 210 in response to the RTD determined by process 400 and / or process 422. The delay code specifies the determined RTD. The delay code selects several delay units 502, 504, 506, and / or 508 to activate. The fourth decoder 516 decodes Bit0 and Bit1 as control signals for delay unit D 508, the third decoder 514 decodes Bit2 and Bit3 as control signals for delay unit C 506, the second decoder 512 decodes Bit4 and Bit5 as control signals for delay unit B 504, and the first decoder 510 decodes Bit6 and Bit7 as control signals for delay unit A 502. The control signal determines which delay units 502, 504, 506, and / or 508 are activated to apply corresponding delays to the SCLK signal.

[0077] For example, if Bit0 and Bit1 are equal to 0, no delay unit D 508 is activated. If Bit0 is equal to 1 and Bit1 is equal to 0, the first delay unit D 508a is activated, and the second delay unit D 508b and the third delay unit D 508c are deactivated. If Bit0 is equal to 0 and Bit1 is equal to 1, the first delay unit D 508a and the second delay unit D 508b are activated, and the third delay unit D 508c is deactivated. If Bit0 is equal to 1 and Bit1 is equal to 1, the first delay unit D 508a, the second delay unit D 508b and the third delay unit D 508c are activated. Other decoders 510, 512 and 514 and delay units 502, 504 and 506 function similarly. Thus, the pairs of delay code bits received by the corresponding decoders 510, 512, 514, and 516 correspond to a count from left to right (as illustrated) of the delay units 502, 504, 506, and / or 508 to be activated. Thus, the delay code specifies which of the delay units 502, 504, 506, and / or 508 are to be activated, and which are to be deactivated. In some examples, the lower numbered bits (e.g., Bit 0) correspond to the LSB of the delay code or RTD in binary, and the higher numbered bits (e.g., Bit 7) correspond to the most significant bit (MSB) of the delay code or RTD in binary.

[0078] The activated delay unit 502, 504, 506 or 508 applies a certain amount of delay to the SCLK signal received at its first input (left side) and outputs the delayed SCLK signal at its first output (right side). The activated delay unit 502, 504, 506 or 508 also applies a certain amount of delay to the SCLK signal received at its second input (right side) and outputs the delayed SCLK signal at its second output (left side). Therefore, whenever the SCLK signal passes through the delay unit 502, 504, 506 and 508, the activated delay unit 502, 504, 506 or 508 applies a delay to the SCLK signal. The deactivated delay unit 502, 504, 506 and 508 receives the SCLK signal at its first input (left side) and outputs the unmodified SCLK signal at its second output (left side).

[0079] In some examples, each delay cell A 502 provides the same first amount of delay, each delay cell B 504 provides the same second amount of delay, each delay cell C 506 provides the same third amount of delay, and each delay cell D 508 provides the same fourth amount of delay. The first amount of delay, the second amount of delay, the third amount of delay, and the fourth amount of delay are different from each other.

[0080] In an example, the first amount of delay is 12800 picoseconds (ps), the second amount of delay is 3200ps, the third amount of delay is 800ps, and the fourth amount of delay is 200ps. Therefore, delay unit A 502 together provides a delay of at most 38400ps, delay unit B 504 together provides a delay of at most 9600ps, delay unit C 506 together provides a delay of at most 2400ps, and delay unit D 508 together provides a delay of at most 600ps. In an example, delay circuit 210 provides a delay with a granularity of 200ps, and can provide a delay of at most 51 nanoseconds, wherein the delay unit provides a delay ranging from very coarse to very fine. Therefore, delay circuit 210 implements a wide, asynchronously programmable delay range with fine granularity.

[0081] Figure 6 Yes Figure 5 1 is a circuit and functional block diagram of an example delay cell 600. Thus, delay cell 600 represents an example of delay cell A 502, delay cell B 504, delay cell C 506, or delay cell D 508. Delay cell 600 includes a buffer 602, an XOR logic gate 604, a first n-channel metal oxide semiconductor field effect transistor (MOSFET) (first NMOS) 606, a first p-channel MOSFET (first PMOS) 608, a second n-channel MOSFET (second NMOS) 610, a second p-channel MOSFET (second PMOS) 612, and an inverter 614 (inverting buffer).

[0082] The external input and output of the delay unit 600 correspond to the Figure 5 The external inputs and outputs of the described delay cells 502, 504, 506, and 508. In some examples, the decoders 510, 512, 514, and 516 also provide an inverted select signal to the respective delay cell 600, and include corresponding connections to the respective delay cells 600 for this purpose. The forward input 616 is connected to a first input of the delay cell 600, the forward output 618 is connected to a first output of the delay cell 600, the return input 620 is connected to a second input of the delay cell 600, and the return output 622 is connected to a second output of the delay cell 600.

[0083] The forward input 616 is connected to the input of the buffer 602, the first terminal of the first NMOS 606, and the first terminal of the first PMOS 608. The second terminal of the first NMOS 606 is connected to the second terminal of the first PMOS 608, the return output 622, the first terminal of the second NMOS 610, and the first terminal of the second PMOS 612. The second terminal of the second NMOS 610 is connected to the second terminal of the second PMOS 612 and the output of the inverter 614.

[0084] The control terminal of the first NMOS 606 and the control terminal of the second PMOS 612 are connected to the control input of the delay unit 600 via an inverter (not shown), so that the control terminal receives an inverted signal ( / control input) from the control input of the delay unit 600. The control terminal of the first PMOS 608 and the control terminal of the second NMOS 610 are connected to the control input of the delay unit 600, so that the control terminal receives a non-inverted signal (control input) from the control input of the delay unit 600. The control terminal of the first PMOS 608 is connected to the control terminal of the second NMOS 610. Therefore, the first transistor 606 and the second transistor 608 together are a first pass gate 624, and the third transistor 610 and the fourth transistor 612 together are a second pass gate 626.

[0085] The input of inverter 614 is connected to return input 620. The output of buffer 602 is connected to a first input of XOR logic gate 604. A second input of XOR logic gate 604 receives the inverted select signal. The output of XOR logic gate 604 is connected to forward output 618.

[0086] When the control input receives a low voltage signal, such as a logic 0, the first pass gate 624 is turned on (conducting) and the second pass gate 626 is turned off (non-conducting). When the control input receives a high voltage signal, such as a logic 1, the first pass gate 624 is turned off and the second pass gate 626 is turned on. Therefore, when the control input receives a logic 0, thereby deactivating the delay cell 600, the second pass gate 626 is turned off and the first pass gate 624 is turned on, thereby shorting the forward input 616 to the return output 622. When the control input receives a logic 1, thereby deactivating the delay cell 600, the first pass gate 624 is turned off and the second pass gate 626 is turned on, thereby connecting the inverted state of the return input 620 to the return output 622.

[0087] When the delay cell 600 is turned on, the SCLK signal is transmitted through the delay circuit 600 in two directions: from the forward input 616 to the forward output 618 (first input to first output) in the first transmission direction, and from the return input 620 to the return output 622 (second input to second output) in the second transmission direction. This enables the SCLK signal to pass through the buffer 602 and the XOR logic gate 604 in the first transmission direction, and through the inverter 614 in the second transmission direction to receive the delayed application from each of these components.

[0088] The invert select signal is set to a logic 1 during normal operation, causing the SCLK signal to be inverted in the first transmission direction by the XOR logic gate 604, and inverted again in the second transmission direction by the inverter 614. Thus, the SCLK signal is not inverted during bidirectional transmission from the forward input 616 to the return output 622. In some examples, the invert select signal can be set to a logic 0, causing the SCLK signal to be inverted through bidirectional transmission. In some examples, the XOR logic gate 604 is used to implement additional fine control of the delay provided by the delay unit 600.

[0089] Modifications to the described examples are possible and other examples are possible within the scope of the claims.

[0090] In some examples, a different number of delay cells and a corresponding number of control bits than in the described example are used.

[0091] In some examples, processor 202 provides programming code to the delay cells and / or adjusts delay cell weights.

[0092] In some examples, the SPI master node 102 or the SPI slave node 104 includes a processor, such as a central processing unit (CPU), a digital signal processor (DSP), or a microcontroller.

[0093] In some examples, the processes described herein are controlled using hardware, software, or a combination thereof.

[0094] In some examples, processor 202 is used to control delay calibration.

[0095] In some examples, in addition to the midpoint delay, intermediate delays (or durations) between the upper and lower limits are used for the binary search.

[0096] In some examples, the amount of delay provided by an individual delay cell may be programmed or otherwise determined using hardware, software, or a combination.

[0097] In some examples, a daisy-chain topology may also be used to connect a SPI master node 102 with multiple SPI slave nodes 104. In some examples, the systems and processes described above may be used to calibrate the RTD of a daisy-chain SPI topology.

[0098] In some examples, the hardware or software of the SPI daughter node 104 enables providing a minimum code (all 0s), a maximum code (all 1s), or an intermediate code (0 followed by 1s, or 1s followed by 0s) MISO response signal. The p-1 iteration MISO data signal is compared to this predetermined response code (rather than the p iteration MISO data signal) to determine the RTD. In some examples, the MOSI data signal is provided to trigger this response code.

[0099] In some examples, the described methods and systems are used to calibrate a delay compensation host (controller / master node) of an RTD-based interface, rather than the SPI master node 102 .

[0100] In some examples, calibration control circuit 209 is part of processor 202 .

[0101] In some examples, delay circuit 210 is part of calibration control circuit 209 .

[0102] The term "coupled" is used throughout this specification. The term may encompass connections, communications, or signal paths that achieve a functional relationship consistent with this specification. For example, if device A provides a signal to control device B to perform an action, then: in a first instance, device A is coupled to device B; or in a second instance, if the intermediate component C does not substantially change the functional relationship between device A and device B, then device A is coupled to device B through the intermediate component C, so that device B is controlled by device A via the control signal provided by device A.

[0103] In this specification, the term "and / or" (when used in the form of, for example, A, B, and / or C) refers to any combination or subset of A, B, C, such as: (a) A alone; (b) B alone; (c) C alone; (d) A and B; (e) A and C; (f) B and C; and (g) A and B and C. In addition, as used herein, the phrase "at least one of A or B" (or "at least one of A and B") refers to an embodiment that includes any of the following: (a) at least one A; (b) at least one B; and (c) at least one A and at least one B.

[0104] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0105] As used herein, the terms "terminal", "node", "interconnect", "pin", "solder ball" and "lead" are used interchangeably. Unless otherwise specified, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices or other electronic devices or semiconductor components or their ends.

[0106] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, for example, by an end user and / or a third party.

[0107] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may actually be used with little change to the rest of the circuitry. For example, metal oxide silicon FETs ("MOSFETs") (e.g., n-channel MOSFETs (nMOSFETs), or p-channel MOSFETs (pMOSFETs)), bipolar junction transistors (BJTs, such as NPN or PNP), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used in place of or in conjunction with the devices disclosed herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, native transistors, or other types of device structure transistors. Furthermore, the devices may be implemented in / on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0108] The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to functionality available before component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the impedance amount represented by the resistors shown. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described as a single component herein may alternatively be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0109] Although certain elements of the described examples may be included in the integrated circuit and other elements are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. In addition, some or all features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

Claims

1. A device comprising: a transmitter configured to transmit a clock signal; a receiver configured to receive the response signal; as well as a control circuit coupled to the receiver and to the transmitter, wherein the control circuit is configured to: enabling the transmitter to transmit a first clock signal having a first clock cycle; causing the transmitter to transmit a second clock signal having a second clock cycle greater than the first clock cycle; determining whether a first pattern of a signal responsive to the first clock signal is the same as a second pattern of a signal responsive to the second clock cycle; in response to the act of determining that the first mode and the second mode are the same, delaying the clock signal with a delay responsive to the first clock cycle to generate a delayed clock signal; as well as The receiver is caused to sample the response signal using the delayed clock signal.

2. The device according to claim 1, wherein the control circuit has a clock input and an output and includes a plurality of decoders and a plurality of groups of delay cells, the clock input being coupled to the transmitter and the output being coupled to the receiver; wherein some of the delay units have corresponding control inputs and are sequentially connected between the clock input of the control circuit and the output of the control circuit; and Some of the decoders have multiple outputs, and different ones of the outputs of some of the decoders are connected to the control inputs of different delay cells of a corresponding group of the multiple groups of delay cells.

3. The apparatus of claim 1 , wherein the control circuit comprises a plurality of delay cells, some of the delay cells comprising: a first pass gate having an input, an output, a first control terminal, and a second control terminal; a second pass gate having an input, an output, a first control terminal coupled to the first control terminal of the first pass gate, and a second control terminal coupled to the second control terminal of the first pass gate; a first buffer having an input coupled to the input of the first pass gate; as well as A second buffer has an output coupled to the input of the second pass gate.

4. The device of claim 1 , wherein the transmitter has a chip select output, and the control circuit is configured to control the transmitter to provide a chip select signal at the chip select output such that the chip select signal uniquely corresponds to an integrated circuit different from the device.

5. The device according to claim 1, wherein the transmitter has a control input and a clock output; Wherein the control circuit comprises a calibration circuit and a delay circuit; wherein the calibration circuit has a clock input, a data input, a first control output, and a second control output, the clock input of the calibration circuit being coupled to the clock output of the transmitter, and the first control output of the calibration circuit being coupled to the control input of the transmitter; wherein the delay circuit has a control input, a clock input, and an output, the control input of the delay circuit being coupled to the second control output of the calibration circuit, the clock input of the delay circuit being coupled to the clock output of the transmitter, and the output of the delay circuit being coupled to the clock input of the receiver; and Wherein the receiver has a data input and a clock input, the data input of the receiver is coupled to the data input of the calibration circuit, and the clock input of the receiver is coupled to the output of the delay circuit.

6. The apparatus of claim 5, further comprising a data pin and a clock pin; wherein the clock output of the transmitter is coupled to the clock pin; and Wherein the data input of the receiver is coupled to the data pin.

7. The device of claim 1 , wherein the control circuit is configured to, in response to the first pattern not matching the second pattern, repeat an action of causing the transmitter to transmit a first clock signal and an action of causing the transmitter to transmit a second clock signal, wherein the first clock signal is replaced by the second clock signal, and the second clock signal is replaced by a third clock signal having a third clock period greater than the second clock period.

8. The device of claim 7, wherein the control circuit is configured to search for a round trip delay between the first clock cycle and the second clock cycle in response to a pattern in response to the second clock signal being the same as a pattern in response to the third clock signal.

9. The apparatus of claim 8, wherein the search is a sequential search or a binary search.

10. The apparatus of claim 1, wherein a duration of the second clock cycle is twice a duration of the first clock cycle.

11. The device of claim 1, wherein the device is a serial peripheral interface master node.

12. A method of operating an integrated circuit IC, the method comprising: transmitting a first clock signal having a first clock period; receiving a first response signal in response to the first clock signal; transmitting a second clock signal having a second clock period greater than the first clock period; receiving a second response signal in response to the second clock signal; determining whether a first pattern of the first response signal is the same as a second pattern of the second response signal; Transmits normal operating clock signal; responsive to the determining, delaying the normally operating clock signal with a delay responsive to the first clock cycle to generate a delayed clock signal; receiving a normal operation response signal in response to the normal operation clock signal; as well as The normal operation response signal is sampled using the delayed clock signal.

13. The method according to claim 12, further comprising: prior to transmitting the first clock signal, asserting a chip select signal corresponding to a selected IC among a plurality of different integrated circuits IC so that the first response signal and the second response signal correspond to the selected IC; Wherein the delay corresponds to a round trip delay between transmitting a leading edge of the first clock signal to the selected IC and receiving the first response signal.

14. The method according to claim 12, further comprising: Transmitting M clock signals corresponding to the M data frames, wherein the clock signal has a clock period; asserting a chip select signal corresponding to a selected IC of a plurality of different integrated circuits IC prior to transmitting each of the clock signals; receiving M response signals, different ones of the response signals corresponding to different instances of the assertion; counting a duration from each instance of assertion of the chip select signal to receipt of a first data toggle of each corresponding response signal and summing the durations to generate a sum; subtracting from the sum a product of the clock period and a sum of the number of leading bits of the response signal without data toggling to generate a refined sum; In response to a magnitude of a difference between the delay and a value responsive to the refined sum being greater than a threshold, a subsequent response signal responsive to the refined sum is sampled.

15. The method according to claim 12, further comprising: In response to the first pattern not matching the second pattern, repeatedly transmitting the first clock signal, receiving the first response signal, transmitting the second clock signal, receiving the second response signal, and determining, wherein the first clock signal is replaced by the second clock signal, and the second clock signal is replaced by a third clock signal having a third clock period greater than the second clock period. 16 . The method of claim 15 , further comprising searching for a round trip delay between the first clock cycle and the second clock cycle in response to a pattern in response to the second clock signal being the same as a pattern in response to the third clock signal. The method of claim 16 , wherein the search is a sequential search or a binary search.

18. The method of claim 15, wherein the first clock cycle is CLK1 and the second clock cycle is CLK2, and wherein the delayed clock signal is a first delayed clock signal, the method further comprising: transmitting a clock signal having a clock period CLK1; delaying the clock signal by CLK1+k×delay granularity to generate a second delayed clock signal, wherein k is an integer, the delay granularity is a delay increment, k ranges between 1 and (CLK2-CLK1) / delay granularity, and k is initially at its minimum or maximum value; receiving a response signal and sampling the response signal in response to the second delayed clock signal; Repeating the transmitting, the receiving and the delaying while iterating k upward by 1 from its minimum value or downward by 1 from its maximum value; determining whether the pattern of the response signal for each value of k is one bit more than the pattern of the response signal for each corresponding value of k+1 before the first data switch, and if so, determining whether the pattern of the response signal for k+1 matches the pattern of the response signal for k+2; In response to the k value (number M) being determined to be positive, a response signal is sampled in response to a delay corresponding to CLK1+(M+1)×delay granularity.

19. The method of claim 15, wherein the first clock cycle is a lower limit and the second clock cycle is an upper limit, and wherein the delayed clock signal is a first delayed clock signal, the method further comprising: transmitting a clock signal having the first clock period; delaying the clock signal for an intermediate duration between the lower limit and the upper limit to generate a second delayed clock signal; receiving an intermediate response signal and sampling the response signal in response to the second delayed clock signal; determining whether it is a first case or a second case, the first case corresponding to a pattern of the intermediate response signal having one more bit than a pattern of the response signal corresponding to the upper limit before the first data switches, and the second case corresponding to a pattern of the response signal corresponding to the lower limit having one more bit than the pattern of the intermediate response signal before the first data switches; In response to the first condition, sampling a response signal in response to a delay between the lower limit and the intermediate duration; In response to the second condition, a response signal responsive to a delay between the intermediate duration and the upper limit is sampled.

20. The method of claim 12, wherein a duration of the second clock cycle is twice a duration of the first clock cycle.

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