Reconfigurable I2C bus read-write control circuit, device and method based on component

Abstract

The invention discloses a reconfigurable I2C bus read-write control circuit, device and method based on components, and belongs to the field of integrated circuits, and the circuit comprises an I2C main equipment control circuit and an I2C interface control component; the I2C master device control circuit is used for utilizing a finite-state machine to jump, responding to an I2C read-write start control signal, actively generating and sending an I2C read-write control signal and instruction, and receiving a read-write completion response and data generated and sent by the I2C interface control component; and the I2C interface control component is used for generating and sending read-write completion response and data. The I2C bus read-write control circuit is simple, reliable, high in universality and easy to reconstruct, the I2C bus data read-write rate can be configured at will according to the Baud rate requirement, and the I2C bus read-write data bit width can be reconstructed in a component configuration mode according to the actual data bit width requirement.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and more specifically, to a component-based reconfigurable I 2 C bus read and write control circuit, device and method. Background Art

[0002] As modern electronic systems continue to develop in the direction of miniaturization and complexity, the design scale is also increasing exponentially. Faced with the ever-increasing demand, current application-specific chips (ASICs) and field-programmable gate arrays (FPGAs) have also exposed problems such as poor portability, strong platform dependence, high dependence of program codes on developers, weak program scalability, low flexibility, and poor system integration and integration. How to enhance the reusability and scalability of the design has become one of the hot topics in current design methodology research.

[0003] At present, modular development is usually adopted in software engineering architecture design, following the principle of "high cohesion and low coupling". "Cohesion" means the closeness between modules. "High cohesion" means that the functions of a module are clear and independent, and the functions of the elements within the module are closely connected. The advantages of "high cohesion" design are that the functions are clear, one module is only responsible for one function, maintainability is strong, the functions within the module are highly correlated, and the modification of functions will not affect other functions. "Coupling" means the correlation and dependence between functional modules. "Low coupling" means minimizing the dependence between functional modules. The advantages of "low coupling" design are that due to the reduced dependence between modules, the reusability and scalability of the system are correspondingly improved, and at the same time, when the module function changes, it will not affect the functions of other modules. The design principle of "high cohesion and low coupling" greatly reduces the impact of functional modification and improves the reusability of the system.

[0004] This idea in software engineering architecture design is also borrowed in current integrated circuit design. In the design of application-specific chips (ASICs), the system-on-chip (SoC) integration method is usually used to enhance the reusability of the development process, that is, modules with specific functions are customized in the form of IP cores, and finally the IP cores of various functions are integrated on a common bus according to requirements; in the design of field programmable gate arrays (FPGAs), device manufacturers or IP core developers also provide a large number of IP soft / hard cores for system integration development.

[0005] I 2 The I C bus protocol is a serial transmission bus protocol used for communication between chips. It uses the serial clock SCL and the serial data line SDA to complete full-duplex data transmission. 2 The advantages of the I C bus are that it has fewer connections and allows multi-machine control and synchronization. It has become a worldwide industrial standard. Many integrated circuit suppliers provide I2 C interface application chip.

[0006] Each integrated circuit supplier has its own needs and is based on the standard I 2 C bus protocol is an extended design.

[0007] First, the baud rates supported by chips from different manufacturers are different. With the advancement of technology and the continuous development of I 2 C bus protocol version is constantly evolving. Due to historical reasons, the baud rates supported by various chips vary greatly. For example, Linear Technology's LTC2991 only supports two modes: standard mode and fast mode. In addition, even different chips from the same manufacturer support different baud rate modes. For example, ADI's ADT75 chip supports two modes: standard mode and fast mode, but AD7994 supports three baud rate modes: standard mode, fast mode and high-speed mode.

[0008] Secondly, due to the differences in application scenarios and functions of various chips, the bit widths of registers supported inside the chips also vary greatly. Some chip internal registers support single-byte read and write operations, some support multi-byte read and write operations, some support single-byte write and multi-byte read operations, etc. There are also differences in single-byte and multi-byte read and write operation methods. When the chip manufacturer changes, the design needs to be customized again, and the degree of commonality is low. Summary of the invention

[0009] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a component-based reconfigurable I 2 C bus read and write control circuit, device and method provide a simple, reliable, versatile and easily reconfigurable I 2 C bus read and write control circuit, which can be arbitrarily configured according to the baud rate requirements 2 C bus data read and write speed, and can reconstruct the I 2 C bus read and write data bit width.

[0010] The object of the present invention is achieved through the following solutions:

[0011] A component-based reconfigurable 2 C bus read and write control circuit, including: I 2 C master device control circuit and I 2 C interface control components;

[0012] I 2 C master device control circuit, used to jump using a finite state machine in response to I 2 C read and write start control signal, actively generates and sends I2 C reads and writes control signals and instructions, and receives I 2 The read and write completion responses and data generated and sent by the C interface control component;

[0013] I 2 C interface control component, used to generate and send read and write completion responses and data.

[0014] Further, the finite state machine specifically includes: a write data state WR, a write data completion confirmation state WR_ACK, a read data state RD, a read data completion confirmation state RD_ACK and a read and write data completion state DONE;

[0015] If I 2 C register, the finite state machine will jump to the write data state WR. After the write data is completed, the finite state machine will jump to the write data completion confirmation state WR_ACK. 2 After C clock cycles, the finite state machine jumps to the read and write data completion state DONE;

[0016] If I 2 C register, the finite state machine will jump to the read data state RD. After the data is read, the finite state machine will jump to the read data completion confirmation state RD_ACK. 2 After C clock cycles, the finite state machine jumps to the read and write data completion state DONE.

[0017] Furthermore, the finite state machine specifically includes: an initial idle state IDLE; when the system is just powered on or an external reset occurs, I 2 C master device control circuit is in idle state IDLE; when the finite state machine jumps back to the initial idle state IDLE from the read and write data completion state, it waits for the next I 2 C read and write operations.

[0018] Furthermore, the I 2 The C interface control component includes a baud rate generating component, and the baud rate generating component is used to generate different baud rates.

[0019] Furthermore, the I 2 The C interface control component includes a single-byte write control component; the single-byte write control component specifically includes a write enable control circuit and a single-byte write control circuit, the write enable control circuit is used to respond to the I 2 C master device control circuit write data state WR, I 2 C master device starts the data write operation;

[0020] The single-byte write control circuit is used to execute the process: in response to I2 C master device starts the write data operation, I 2 C master device sends a start signal;

[0021] I 2 C master sends I 2 C slave device address pointer and write command control word;

[0022] I 2 C is the first response from the device;

[0023] I 2 C master device transmits I 2 C is the internal register address of the slave device;

[0024] I 2 C slave device responds for the second time;

[0025] I 2 C master device transmits single byte data;

[0026] I 2 C The slave device responds for the third time; I 2 C sends a stop signal from the device.

[0027] Furthermore, the I 2 The C interface control component includes a single-byte read control component; the single-byte read control component specifically includes a read start control circuit and a single-byte read control circuit, the read start control circuit is used to respond to the I 2 C master device control circuit read data state RD, I 2 C master device starts the data read operation;

[0028] The single-byte read control component is used to execute the process:

[0029] In response to I 2 C master device starts the data read operation, I 2 C master device sends a start signal;

[0030] I 2 C master sends I 2 C slave device address pointer and read command control word;

[0031] I 2 C is the first response from the device;

[0032] I 2 C master sends I 2 C is the internal register address of the slave device;

[0033] I 2 C slave device responds for the second time;

[0034] I 2 C master sends I 2 C slave device address pointer and read command control word; I 2 C slave device answers for the third time;

[0035] I 2 C master device receives single byte data;

[0036] I 2 C The slave device responds for the fourth time; I 2 C sends a stop signal from the device.

[0037] Furthermore, the I 2 The C interface control component includes a two-byte write control component; the two-byte write control component specifically includes a write enable control circuit and a two-byte write control circuit; the write enable control circuit is used to respond to the I 2 C master device control circuit write data state WR, I 2 C master device starts the data write operation;

[0038] The two-byte write control circuit is used to execute the following process:

[0039] I 2 C master sends I 2 C slave device address and write command control word;

[0040] I 2 C is the first response from the device;

[0041] I 2 C master device transmits I 2 C is the internal register address of the slave device;

[0042] I 2 C slave device responds for the second time;

[0043] I 2 C master device transmits the first single byte of data;

[0044] I 2 C slave device answers for the third time;

[0045] I 2 C master device transmits the second byte of data;

[0046] I 2 C slave device responds for the fourth time;

[0047] I 2 C sends a stop signal from the device.

[0048] Furthermore, the I 2The C interface control component includes a two-byte read control component; the two-byte read control component specifically includes a read start control circuit and a two-byte read control circuit; the read start control circuit is used to respond to the I 2 C master device control circuit read data state RD, I 2 C master device starts the data read operation;

[0049] The two-byte read control circuit is used to execute the following process:

[0050] In response to I 2 C master device starts the write data operation, I 2 C master device sends a start signal;

[0051] I 2 C master sends I 2 C slave device address and write command control word;

[0052] I 2 C is the first response from the device;

[0053] I 2 C master device transmits I 2 C is the internal register address of the slave device;

[0054] I 2 C slave device responds for the second time;

[0055] I 2 C master sends I 2 C slave device address pointer and read command control word;

[0056] I 2 C slave device answers for the third time;

[0057] I 2 C master device receives the first single byte of data;

[0058] I 2 C slave device responds for the fourth time;

[0059] I 2 C master device receives the second byte of data;

[0060] I 2 C slave device responds for the fifth time;

[0061] I 2 C sends a stop signal from the device.

[0062] A component-based reconfigurable 2 C bus read and write control device, comprising a component-based reconfigurable I 2 C bus read and write control circuit; wherein,

[0063] I 2 The single-byte read data / single-byte write data of C bus is reconstructed by combining the single-byte write control component and the single-byte read control component;

[0064] I 2 The two-byte read data / two-byte write data of the C bus is reconstructed by combining the two-byte write control component and the two-byte read control component;

[0065] I 2 The single-byte write data / two-byte read data of C bus is reconstructed by combining the single-byte write control component and the two-byte read control component;

[0066] I 2 The single-byte read data / two-byte write data of the C bus is reconstructed by combining the single-byte read control component and the two-byte write control component.

[0067] A component-based reconfigurable 2 C bus read and write control method, applied to I 2 C master device control circuit and I 2 C interface control component, and includes the following steps:

[0068] S100, through the I 2 C master device control circuit, using finite state machine jump, responding to I 2 C read and write start control signal, generate and send I 2 C reads and writes control signals and instructions, and receives I 2 The read and write completion response and data generated and sent by the C interface control circuit;

[0069] S200, generating a baud rate, based on the above-mentioned device executing I 2 C bus single-byte / two-byte read and write control.

[0070] The beneficial effects of the present invention include:

[0071] The present invention provides a component-based reconfigurable I 2 C bus read and write control scheme, which can realize I 2 C master device in different baud rate modes 2 C reads and writes registers of different bit widths from the device, the read and write methods are configurable, the generalization is high, and the resource usage is low.

[0072] The circuit of the present invention provides a control component with configurable baud rate and read and write data bit widths of single byte and two bytes, providing a simple, reliable, versatile and easily reconfigurable I 2C bus read and write control circuit. This circuit can be arbitrarily configured according to the baud rate requirements. 2 C bus data read and write speed, and can reconstruct the I 2 C bus read and write data bit width. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0074] Figure 1 It is a flowchart of the implementation process of the present invention;

[0075] Figure 2 Embodiment 1 of the present invention 2 C bus single byte write control flow chart;

[0076] Figure 3 Embodiment 1 of the present invention 2 C bus single byte read control flow chart;

[0077] Figure 4 I provided in the embodiment of the present invention 2 C bus single-byte read and write control flow diagram. DETAILED DESCRIPTION

[0078] All features disclosed in all embodiments in this specification, or steps in all methods or processes implicitly disclosed, except for mutually exclusive features and / or steps, can be combined and / or expanded or replaced in any manner.

[0079] In view of the current situation in the background, the inventor of the present application further considered that:

[0080] As modern electronic systems continue to develop in the direction of miniaturization and complexity, the design scale is also increasing exponentially. Faced with the ever-increasing demand, current application-specific chips (ASICs) and field-programmable gate arrays (FPGAs) have also exposed problems such as poor portability, strong platform dependence, high dependence of program codes on developers, weak program scalability, low flexibility, and poor system integration and integration. How to enhance the reusability and scalability of the design has become one of the hot topics in current design methodology research.

[0081] The current software engineering architecture design usually adopts a modular development method, following the principle of "high cohesion and low coupling". "Cohesion" refers to the closeness between modules. "High cohesion" means that the functions of a module are clear and independent, and the functions of the elements within the module are closely related. The advantages of "high cohesion" design are clear functions, one module is only responsible for one functional area, strong maintainability, high correlation between functions within the module, and modification of functions will not affect other functions; "coupling" refers to the correlation and dependency between functional modules, and "low coupling" refers to minimizing the dependency between functional modules. The advantage of "low coupling" design is that due to the reduced dependency between modules, the reusability and scalability of the system are correspondingly improved. At the same time, when the module function changes, it will not affect the functions of other modules, greatly reducing the impact of function modification and improving the reusability of the system.

[0082] This idea in software engineering architecture design is also borrowed in current integrated circuit design. In the design of application-specific chips (ASICs), the system-on-chip (SoC) integration method is usually used to enhance the reusability of the development process, that is, modules with specific functions are customized in the form of IP cores, and finally the IP cores of various functions are integrated on a common bus according to requirements; in the design of field programmable gate arrays (FPGAs), device manufacturers or IP core developers also provide a large number of IP soft / hard cores for system integration development.

[0083] I 2 The I C bus protocol is a serial transmission bus protocol proposed by Philips for inter-chip communication. It uses the serial clock SCL and the serial data line SDA to complete full-duplex data transmission. 2 The I C bus has the characteristics of few connections and allows multi-machine control and synchronization. It has become a global industrial standard. Many integrated circuit suppliers provide I 2 In terms of interface, each integrated circuit supplier has developed a standard IC based on I 2 C bus protocol is an extended design. Specifically, due to the I 2 With the forward evolution of different versions of the C-bus protocol, different application chips support different baud rates. At the same time, due to the differences in application scenarios and functions of each chip, the register bit widths supported by the chip are also quite different. When the chip manufacturer is replaced, it needs to be re-customized and the degree of universalization is low.

[0084] Therefore, in order to solve the above technical problems, a component-based reconfigurable I 2 C bus read and write control circuit.

[0085] In a first preferred embodiment, if Figure 1As shown, a component-based reconfigurable I 2 C bus read and write control circuit, specifically including: I 2 C master device control circuit and I 2 C interface control component; wherein the I 2 C master device control circuit, used to jump using a finite state machine in response to I 2 C read and write start control signal, actively generates and sends I 2 C reads and writes control signals and instructions, and receives I 2 The read and write completion response and data generated and sent by the I C interface control component; 2 C interface control component, used to generate and send read and write completion responses and data.

[0086] In a further embodiment, I 2 The finite state machine of the C master device control circuit includes 5 states: initial idle state (IDLE), write data state (WR), write data completion confirmation state (WR_ACK), read data state (RD), read data completion confirmation state (RD_ACK), read and write data completion state (DONE);

[0087] In a further embodiment, when the system is just powered on or an external reset occurs, I 2 C The master device control circuit is in idle state (IDLE);

[0088] In a further embodiment, I 2 C master device control circuit every clock cycle I 2 C read-write start control signal is sampled. When the rising edge of the signal is sampled, I 2 C master device control circuit starts to start I 2 C read and write operations;

[0089] In a further embodiment, if 2 C register is written, the finite state machine will jump to the write data state (WR), after the write data is completed, the finite state machine jumps to the write data completion confirmation state (WR_ACK), an I 2 After C clock cycles, the finite state machine jumps to the read and write data completion state (DONE);

[0090] In a further embodiment, if 2 C register is read, the finite state machine will jump to the read data state (RD), after the data is read, the finite state machine jumps to the read data completion confirmation state (RD_ACK), an I 2After C clock cycles, the finite state machine jumps to the read and write data completion state (DONE);

[0091] In a further implementation manner, the finite state machine jumps back to the initial idle state (IDLE) from the read and write data completion state, waiting for the next I 2 C read and write operations.

[0092] In a further embodiment, the I 2 C interface control component, including a baud rate generation component, a single-byte write control component, a single-byte read control component, a two-byte write control component and a two-byte read control component;

[0093] In a further implementation manner, the baud rate generating component can generate baud rate modes including: standard mode (100 Kbits / s), fast mode (400 Kbits / s), and high-speed mode (3.4 Mbits / s).

[0094] In other embodiments, there is provided an I 2 C bus single byte read and write control method. Figure 2 and Figure 3 and Figure 4 As shown, Figure 2 The example provided in this embodiment is shown in FIG. 2 C bus single byte read and write control flow diagram, such as Figure 3 This is the embodiment I 2 C bus single-byte read and write control FPGA implementation structure diagram.

[0095] clk_in represents the external input clock, rst_n represents the external input asynchronous reset signal, and start represents I 2 C read-write control start signal, scl represents I 2 C clock signal, sda represents I 2 C data signal, i2c_mst_ctrl represents I 2 C master device control circuit module, which mainly responds to I 2 C read and write start control signal, generate and send I 2 C reads and writes control signals and instructions, and receives I 2 The read and write completion response and data generated and sent by the C interface control circuit; i2c_op_ctrl represents the I 2 C interface control circuit module, which is mainly used to generate baud rate and single-byte read and write control. The method specifically includes the following steps:

[0096] Step S100: In response to I 2 C read and write start control signal, generate and send I 2C reads and writes control signals and instructions, and receives I 2 The read and write completion responses and data generated and sent by the C interface control circuit.

[0097] Specifically, I 2 The finite state machine of the C master device control circuit includes 5 states: initial idle state IDLE, write data state WR, write data completion confirmation state WR_ACK, read data state RD, read data completion confirmation state RD_ACK, read and write data completion state DONE;

[0098] When the system is just powered on or an external reset occurs, I 2 C The master device control circuit will be in idle state;

[0099] I 2 C master device control circuit every clock cycle I 2 C read-write start control signal is sampled. When the rising edge of the signal is sampled, I 2 C master device control circuit starts to start I 2 C read and write operations;

[0100] If I 2 C register is written, the finite state machine will jump to the write data state, after the write data is completed, the finite state machine will jump to the write data completion confirmation state, an I 2 After C clock cycles, the finite state machine jumps to the read and write data completion state;

[0101] If I 2 C register is read, the finite state machine will jump to the data read state, after the data read is completed, the finite state machine will jump to the data read completion confirmation state, an I 2 After C clock cycles, the finite state machine jumps to the read and write data completion state;

[0102] Further, the finite state machine jumps back to the initial idle state from the read and write data completion state, waiting for the next I 2 C read and write operations.

[0103] Step S200: Generate baud rate and single-byte read and write control.

[0104] The baud rate generation component can generate the following baud rates: standard rate 100Kbits / s, fast rate 400Kbits / s, high speed rate 3.4Mbits / s.

[0105] A single-byte write control component, including a write start control circuit and a single-byte write control circuit;

[0106] The write enable control circuit responds to I 2C master device control circuit write data state WR, I 2 C master device starts the data write operation;

[0107] The single-byte write control circuit responds to I 2 C master device starts the write data operation, I 2 C master device sends a start signal;

[0108] I 2 C master sends I 2 C slave device address pointer and write command control word;

[0109] I 2 C is the first response from the device;

[0110] I 2 C master device transmits I 2 C is the internal register address of the slave device;

[0111] I 2 C slave device responds for the second time;

[0112] I 2 C master device transmits single byte data;

[0113] I 2 C slave device answers for the third time;

[0114] I 2 C sends a stop signal from the device.

[0115] A single-byte read control component, including a read start control circuit and a single-byte read control circuit;

[0116] The read enable control circuit responds to I 2 C master device starts the data read operation, I 2 C master device sends a start signal;

[0117] I 2 C master sends I 2 C slave device address pointer and read command control word;

[0118] I 2 C is the first response from the device;

[0119] I 2 C master sends I 2 C is the internal register address of the slave device;

[0120] I 2 C slave device responds for the second time;

[0121] I 2 C master sends I 2 C slave device address pointer and read command control word;

[0122] I 2 C slave device answers for the third time;

[0123] I 2 C master device receives single byte data;

[0124] I 2 C slave device responds for the fourth time;

[0125] I 2 C sends a stop signal from the device.

[0126] The units involved in the embodiments of the present invention may be implemented by software or hardware, and the units described may also be arranged in a processor. The names of these units do not, in some cases, limit the units themselves.

[0127] According to one aspect of an embodiment of the present invention, a computer program product or a computer program is provided, the computer program product or the computer program includes a computer instruction, and the computer instruction is stored in a computer-readable storage medium. A processor of a computer device reads the computer instruction from the computer-readable storage medium, and the processor executes the computer instruction, so that the computer device executes the method provided in the above various optional implementations.

[0128] As another aspect, an embodiment of the present invention further provides a computer-readable medium, which may be included in the electronic device described in the above embodiment; or may exist independently without being assembled into the electronic device. The above computer-readable medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device implements the method described in the above embodiment.

Claims

1. A component-based reconfigurable 2 C bus read and write control circuit, characterized in that: include: I 2 C master device control circuit and I 2 C interface control components; I 2 C master device control circuit, used to jump using a finite state machine in response to I 2 C read and write start control signal, actively generates and sends I 2 C reads and writes control signals and instructions, and receives I 2 The read and write completion responses and data generated and sent by the C interface control component; I 2 C interface control component, used to generate and send read and write completion responses and data.

2. The component-based reconfigurable I according to claim 1 2 C bus read and write control circuit, characterized in that: The finite state machine specifically includes: a write data state WR, a write data completion confirmation state WR_ACK, a read data state RD, a read data completion confirmation state RD_ACK and a read and write data completion state DONE; If I 2 C register, the finite state machine will jump to the write data state WR. After the write data is completed, the finite state machine will jump to the write data completion confirmation state WR_ACK. 2 After C clock cycles, the finite state machine jumps to the read and write data completion state DONE; If I 2 C register, the finite state machine will jump to the read data state RD. After the data is read, the finite state machine will jump to the read data completion confirmation state RD_ACK. 2 After C clock cycles, the finite state machine jumps to the read and write data completion state DONE.

3. The component-based reconfigurable I according to claim 2 2 C bus read and write control circuit, characterized in that: The finite state machine specifically includes: an initial idle state IDLE; when the system is just powered on or an external reset occurs, I 2 C master device control circuit is in idle state IDLE; when the finite state machine jumps back to the initial idle state IDLE from the read and write data completion state, it waits for the next I 2 C read and write operations.

4. The component-based reconfigurable I according to claim 1 2 C bus read and write control circuit, characterized in that: I 2 The C interface control component includes a baud rate generating component, and the baud rate generating component is used to generate baud rates of different rates.

5. The component-based reconfigurable I according to claim 1 2 C bus read and write control circuit, characterized in that: I 2 The C interface control component includes a single-byte write control component; the single-byte write control component specifically includes a write enable control circuit and a single-byte write control circuit, the write enable control circuit is used to respond to the I 2 C master device control circuit write data state WR, I 2 C master device starts the data write operation; The single-byte write control circuit is used to execute the process: in response to I 2 C master device starts the write data operation, I 2 C master device sends a start signal; I 2 C master sends I 2 C slave device address pointer and write command control word; I 2 C is the first response from the device; I 2 C master device transmits I 2 C is the internal register address of the slave device; I 2 C slave device responds for the second time; I 2 C master device transmits single byte data; I 2 C The slave device responds for the third time; I 2 C sends a stop signal from the device.

6. The component-based reconfigurable I according to claim 1 2 C bus read and write control circuit, characterized in that: I 2 The C interface control component includes a single-byte read control component; the single-byte read control component specifically includes a read start control circuit and a single-byte read control circuit, the read start control circuit is used to respond to the I 2 C master device control circuit read data state RD, I 2 C master device starts the data read operation; The single-byte read control component is used to execute the process: In response to I 2 C master device starts the data read operation, I 2 C master device sends a start signal; I 2 C master sends I 2 C slave device address pointer and read command control word; I 2 C is the first response from the device; I 2 C master sends I 2 C is the internal register address of the slave device; I 2 C slave device responds for the second time; I 2 C master sends I 2 C slave device address pointer and read command control word; I 2 C slave device answers for the third time; I 2 C master device receives single byte data; I 2 C The slave device responds for the fourth time; I 2 C sends a stop signal from the device.

7. The component-based reconfigurable I according to claim 1 2 C bus read and write control circuit, characterized in that: I 2 The C interface control component includes a two-byte write control component; the two-byte write control component specifically includes a write enable control circuit and a two-byte write control circuit; the write enable control circuit is used to respond to the I 2 C master device control circuit write data state WR, I 2 C master device starts the data write operation; The two-byte write control circuit is used to execute the following process: I 2 C master sends I 2 C slave device address and write command control word; I 2 C is the first response from the device; I 2 C master device transmits I 2 C is the internal register address of the slave device; I 2 C slave device responds for the second time; I 2 C master device transmits the first single byte of data; I 2 C slave device answers for the third time; I 2 C master device transmits the second byte of data; I 2 C slave device responds for the fourth time; I 2 C sends a stop signal from the device.

8. The component-based reconfigurable I according to claim 1 2 C bus read and write control circuit, characterized in that: I 2 The C interface control component includes a two-byte read control component; the two-byte read control component specifically includes a read start control circuit and a two-byte read control circuit; the read start control circuit is used to respond to the I 2 C master device control circuit read data state RD, I 2 C master device starts the data read operation; The two-byte read control circuit is used to execute the following process: In response to I 2 C master device starts the write data operation, I 2 C master device sends a start signal; I 2 C master sends I 2 C slave device address and write command control word; I 2 C is the first response from the device; I 2 C master device transmits I 2 C is the internal register address of the slave device; I 2 C slave device responds for the second time; I 2 C master sends I 2 C slave device address pointer and read command control word; I 2 C slave device answers for the third time; I 2 C master device receives the first single byte of data; I 2 C slave device responds for the fourth time; I 2 C master device receives the second byte of data; I 2 C slave device responds for the fifth time; I 2 C sends a stop signal from the device.

9. A component-based reconfigurable 2 C bus read-write control device, characterized in that: A component-based reconfigurable I comprising any one of claims 5 to 8 2 C bus read and write control circuit; wherein, I 2 The single-byte read data / single-byte write data of C bus is reconstructed by combining the single-byte write control component and the single-byte read control component; I 2 The two-byte read data / two-byte write data of the C bus is reconstructed by combining the two-byte write control component and the two-byte read control component; I 2 The single-byte write data / two-byte read data of C bus is reconstructed by combining the single-byte write control component and the two-byte read control component; I 2 The single-byte read data / two-byte write data of the C bus is reconstructed by combining the single-byte read control component and the two-byte write control component.

10. A component-based reconfigurable 2 C bus read and write control method, characterized in that: Application 2 C master device control circuit and I 2 C interface control component, and includes the following steps: S100, through the I 2 C master device control circuit, using finite state machine jump, responding to I 2 C read and write start control signal, generate and send I 2 C reads and writes control signals and instructions, and receives I 2 The read and write completion response and data generated and sent by the C interface control circuit; S200, generating a baud rate, based on the device according to claim 9 executing I 2 C bus single-byte / two-byte read and write control.

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