Macro-cell layout method and device, equipment and medium

Abstract

The invention relates to the technical field of chips, in particular to a macro-cell layout method, device, equipment and medium, and the method comprises the following steps: determining layout planning boundary information through netlist information and layout planning shape requirements, which ensures that the layout process meets design requirements; hierarchical division is performed on the design unit through the design hierarchical information to obtain a plurality of virtual macro blocks, so that the complexity of layout is reduced; performing time sequence analysis on the virtual macro block to obtain data interaction information; and then, based on the data interaction information as a basis for virtual module layout, performing virtual macro block layout, and after layout is completed, performing layout on a plurality of macro units corresponding to each virtual macro block. The layout of the virtual macro blocks is carried out according to hierarchy, and then the macro units in the virtual macro blocks after layout are finely arranged, so that the hierarchical layout method not only improves the layout efficiency, but also ensures the quality of the final layout result.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a macro unit layout method, device, equipment and medium. Background Art

[0002] In digital backend physical design, the basic process is mainly divided into six major steps: data preparation, floorplanning, layout, clock tree synthesis, routing, timing and physical verification sign-off. Among them, floorplanning occupies a very important position in digital backend physical design. It is in the early stage of backend physical design. The rationality of floorplanning results directly determines the timing convergence, routing smoothness and power supply stability of the entire design, and directly affects the performance and yield of the entire chip. Its importance is self-evident.

[0003] Layout planning mainly completes the determination of chip or module size, macro cell placement, input and output unit placement and power supply planning. In today's digital back-end physical design, most engineers still use manual placement of macro cells to complete layout planning, and then use automatic placement and routing tools to complete the placement and layout of standard cells, and then adjust the macro cell position according to the layout results of the standard cells, and repeat this process until the best effect is achieved. This method of manually placing macro cells not only consumes the energy of engineers, but also requires multiple iterations to obtain a layout plan with better results. At the same time, it has very high requirements for the personal layout experience and ability of engineers. At the same time, as the design scale of digital integrated circuits becomes larger and larger, an important content reflected in the digital back-end physical design is the increase in the number of macro cells. Now the number of macro cells in a design can reach hundreds or thousands, which makes the manual placement of macro cells more complicated and difficult.

[0004] Therefore, how to improve the efficiency of macro cell layout is a problem that those skilled in the art need to solve. Summary of the invention

[0005] The object of the present invention is to provide a macro cell layout method, device, equipment and medium, which can improve the efficiency of macro cell layout.

[0006] In a first aspect, a macro cell layout method is provided, comprising:

[0007] Determine layout planning boundary information according to netlist information and layout planning shape requirements, wherein the netlist information is used to represent information of design units to be laid out, and the design units include standard units and macro units;

[0008] hierarchically divide the design unit according to the design hierarchical information to obtain a plurality of virtual macro blocks, wherein the area of ​​each of the virtual macro blocks is determined based on the areas of the plurality of design units corresponding to each of the virtual macro blocks;

[0009] Performing timing analysis on the virtual macroblock to obtain data interaction information of the virtual macroblock, wherein the data interaction information of the virtual macroblock includes: the number of first data grid lines of the virtual macroblock and each other block, wherein the other block includes a first input-output unit and other virtual macroblocks;

[0010] Performing virtual macro block layout based on the data interaction information of the virtual macro block and the layout planning boundary information;

[0011] After the virtual macro blocks are laid out, multiple macro units corresponding to each of the virtual macro blocks are laid out to obtain a layout result.

[0012] In a preferred example, the present invention can be further configured as follows: the netlist information includes: quantity information and area information of standard cells, quantity information and area information of macro cells;

[0013] Determine the layout planning boundary information based on the netlist information and layout planning shape requirements, including:

[0014] Determining the total area of ​​the standard units according to the quantity information and area information of the standard units;

[0015] Determining the total area of ​​the macro units according to the quantity information and area information of the macro units;

[0016] Determine the total area of ​​the layout plan according to the total area of ​​the standard cells, the first value corresponding to the standard cells, the total area of ​​the macro cells, and the second value corresponding to the macro cells;

[0017] Layout planning boundary information is determined according to the total area of ​​the layout planning and the layout planning shape requirement.

[0018] In a preferred example, the present invention can be further configured as follows: the design hierarchical information is tree diagram information, each hierarchical level of the tree diagram information corresponds to a plurality of modules, and each module corresponds to a plurality of design units;

[0019] The design unit is hierarchically divided according to the design hierarchical information to obtain multiple virtual macro blocks, including:

[0020] Determine the number of multiple modules corresponding to each hierarchical level according to the design hierarchical information;

[0021] Determine a target hierarchical level according to the number of multiple modules corresponding to each hierarchical level and a preset number threshold;

[0022] The multiple modules corresponding to the target hierarchical level are used as multiple virtual macro blocks.

[0023] In a preferred example, the present invention can be further configured as follows: performing a timing analysis on the virtual macroblock to obtain data interaction information of the virtual macroblock, including:

[0024] Performing timing analysis on the virtual macroblocks to determine data flows between the virtual macroblocks;

[0025] According to the data flow between the virtual macro blocks, a data interaction relationship between the virtual macro blocks and the first input-output unit and a data interaction relationship between the virtual macro blocks are established to form a data line network;

[0026] According to the data line network, data interaction information of the virtual macro block is determined.

[0027] In a preferred example, the present invention may be further configured as follows: before performing virtual macro block layout based on the data interaction information of the virtual macro block and the layout planning boundary information, the method further includes:

[0028] laying out the first input-output unit according to the layout planning boundary information;

[0029] and / or,

[0030] The third-party macro cells are laid out according to the layout planning boundary information and the third-party macro cell placement information.

[0031] In a preferred example, the present invention may be further configured as follows: the data interaction information further includes: the number of first registers between the virtual macroblock and each other block;

[0032] Performing virtual macro block layout based on the data interaction information of the virtual macro block and the layout planning boundary information includes:

[0033] Determine the center position of the first unit in the layout planning boundary information; when there is a third-party macro unit, the third-party macro unit is the first unit, otherwise the first input and output unit is the first unit;

[0034] Determine a target virtual macroblock having the largest number of first number of grid lines with the first unit; and layout the target virtual macroblock according to the center position of the first unit and the number of first registers of the first unit and the target virtual macroblock;

[0035] The target virtual macroblock is used as a new first unit, and the virtual macroblock layout is iteratively performed to complete the virtual macroblock layout.

[0036] In a preferred example, the present invention can be further configured as follows: according to the center position of the first unit, the first unit and the number of first registers of the target virtual macro block, the target virtual macro block is laid out, including:

[0037] Determine a first planning area according to the center position of the first unit as the center of the circle and the target length as the radius; the target length is determined by the number of first registers of the first unit and the target virtual macroblock and a preset driving distance;

[0038] Boundary constraints are performed according to the first planning area, and the target virtual macroblock is laid out at the position with the most layout boundaries.

[0039] In a preferred example, the present invention can be further configured as follows: after performing virtual macro block layout based on the data interaction information and layout planning boundary information of the virtual macro block, the present invention further includes:

[0040] The virtual macroblocks are adjusted to obtain an adjusted virtual macroblock layout, wherein the total bus length of the virtual macroblocks in the adjusted virtual macroblock layout is the shortest.

[0041] In a preferred example, the present invention can be further configured as follows: the data interaction information also includes: the number of second data grids of each macro unit and other macro units in the virtual macro block, and the number of second registers between each macro unit and other macro units;

[0042] Laying out multiple macro units corresponding to each of the virtual macro blocks to obtain a layout result includes:

[0043] Determine the category of each virtual macroblock, wherein if the virtual macroblock includes only standard cells, the category of the virtual macroblock is a standard cell type virtual macroblock; otherwise, the category of the virtual macroblock is a macro cell type virtual macroblock;

[0044] Determine the center position of the second unit in each of the macro-unit-type virtual macro blocks, the second unit in the macro-unit-type virtual macro block being the second input-output unit in the virtual macro block;

[0045] Determine a target macro cell having a maximum second number of network stripes with the second cell;

[0046] Arrange the target macrocell according to the center position of the second cell in the macrocell class virtual macroblock, the second cell in the macrocell class virtual macroblock and the number of second registers of the target macrocell;

[0047] The target macro cell is used as a new second cell, and macro cell layout is iteratively performed to complete the layout of multiple macro cells.

[0048] In a second aspect, a macro cell layout device is provided, comprising:

[0049] A determination module, used to determine layout planning boundary information according to netlist information and layout planning shape requirements, wherein the netlist information is used to characterize information of design units to be laid out, and the design units include standard units and macro units;

[0050] A hierarchical division module, used for hierarchically dividing the design unit according to the design hierarchical information to obtain a plurality of virtual macro blocks, wherein the area of ​​each of the virtual macro blocks is determined based on the areas of the plurality of design units corresponding to each of the virtual macro blocks;

[0051] A timing analysis module, used for performing timing analysis on the virtual macroblock to obtain data interaction information of the virtual macroblock, wherein the data interaction information of the virtual macroblock includes: the number of first data grids of the virtual macroblock and each other block, wherein the other block includes a first input-output unit and other virtual macroblocks;

[0052] A virtual macroblock layout module, configured to perform virtual macroblock layout based on the data interaction information of the virtual macroblock and the layout planning boundary information;

[0053] The macro unit layout module is used to layout multiple macro units corresponding to each virtual macro block after the virtual macro block is laid out to obtain a layout result.

[0054] In a third aspect, an electronic device is provided, including:

[0055] A memory for storing a computer program; a processor for executing the computer program to implement the method as described in any one of the first aspects.

[0056] In a fourth aspect, a computer-readable storage medium is provided, wherein at least one program code is stored in the computer-readable storage medium, and the program code is loaded and executed by a processor to implement any method as described in the first aspect.

[0057] In a fifth aspect, a computer program product is provided, comprising a computer program or instructions, wherein when the computer program or instructions are executed by a processor, the method described in any one of the first aspects is implemented.

[0058] In summary, the method provided by the present invention includes the following beneficial technical effects:

[0059] The layout planning boundary information is determined by the netlist information and the layout planning shape requirements, which ensures that the layout process meets the design requirements; the design unit is hierarchically divided by design hierarchical information to obtain multiple virtual macro blocks, reducing the complexity of the layout; the virtual macro blocks are analyzed for timing to obtain data interaction information; then, based on the data interaction information as the basis for the virtual module layout, the virtual macro blocks are laid out, and after the layout is completed, the multiple macro units corresponding to each virtual macro block are laid out. By first laying out the virtual macro blocks hierarchically, and then carefully laying out the macro units in the virtual macro blocks after the layout is completed, the hierarchical layout method not only improves the layout efficiency, but also ensures the quality of the final layout results.

[0060] In addition, the present invention also provides a macro unit layout device, equipment and medium, all of which have the above-mentioned beneficial technical effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] In order to more clearly illustrate the embodiments of the present invention or the technical solutions of the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0062] Figure 1 It is a schematic diagram of the digital back-end physical design and layout planning process;

[0063] Figure 2 It is a schematic diagram of the result of macro unit placement in the related art;

[0064] Figure 3 is a flow chart of a macro cell layout method provided by an embodiment of the present invention;

[0065] Figure 4 It is a schematic diagram of the structure of hierarchical information of a design provided by an embodiment of the present invention;

[0066] Figure 5 is a process schematic diagram of a layout algorithm provided by an embodiment of the present invention;

[0067] Figure 6 is a schematic diagram of a half-perimeter model provided by an embodiment of the present invention;

[0068] Figure 7 is a structural schematic diagram of a macro cell layout device provided by an embodiment of the present invention;

[0069] Figure 8 It is a structural schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0070] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0071] The terms "including" and "having" in the specification of the present invention and the above-mentioned drawings, as well as any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device including a series of steps or units is not limited to the listed steps or units, but may include steps or units that are not listed.

[0072] It should be noted that in the optional embodiments of the present invention, the object information and other related data involved, when the embodiments of the present invention are applied to specific products or technologies, need to obtain the permission or consent of the object, and the collection, use and processing of the relevant data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. In other words, if the embodiments of the present invention involve data related to the object, it needs to be obtained with the authorization and consent of the object, the authorization and consent of the relevant department, and in compliance with the relevant laws, regulations and standards of the country and region. If personal information is involved in the embodiments, the acquisition of all personal information needs to obtain the consent of the individual. If sensitive information is involved, the separate consent of the information subject needs to be obtained. The embodiments also need to be implemented with the authorization and consent of the object.

[0073] In addition, the term "and / or" in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article, unless otherwise specified, generally means that the associated objects before and after are in an "or" relationship.

[0074] Layout planning mainly completes the determination of chip or module size, macro unit placement, input and output unit (IO) placement and power supply planning, such as Figure 1 Among them, the planning and placement of the macro unit position is the most complex and important content in the entire back-end physical design, which generally takes up 1 / 3 of the entire back-end physical design time and is a very time-consuming and labor-intensive task.

[0075] In the related art, macro cells are automatically placed by automatic layout and routing tools. However, in practice, the automatically placed macro cells are chaotically distributed, the channels between macro cells are too large or too small, and the local standard cell density of the macro cell channel is high. Figure 2This chaotic macrocell distribution will cause difficulties in power planning, unreasonable insertion positions of subsequent testability design logic, serious design congestion, and difficulty in design timing convergence.

[0076] Based on this, the present invention mainly aims at the problem that large-scale (hundreds or thousands) macro cells are difficult to layout, and proposes an automatic macro cell placement algorithm. The algorithm first calculates the total layout planning area by reading the netlist, then divides the entire design into multiple virtual macro blocks, constructs the data line network between the virtual macro blocks, and layouts the virtual macro blocks based on the input and output units or specific macro cells. After completing the layout of the virtual macro blocks, each virtual macro block is regarded as an independent layout planning space, and the layout of the macro cells in each virtual macro block is completed, and finally a macro cell layout with good timing convergence and strong routability is obtained. In order to solve the problem that it is time-consuming and laborious to manually place macro cells, the present invention improves the shortcomings of automatic layout and wiring tools in automatically placing macro cells, and proposes a method for automatically placing macro cells, which greatly improves the layout of macro cells, greatly reduces the iteration time, shortens the design cycle, saves more time for the optimization of subsequent steps, and reduces the strong dependence of back-end physical design engineers on experience.

[0077] In order to enable those skilled in the art to better understand the solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0078] The embodiment of the present invention provides a macro cell layout method, such as Figure 3 As shown, the method provided in the embodiment of the present invention can be executed by an electronic device, and the electronic device is a server. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services. The terminal device can be a smart phone, a tablet computer, a laptop computer, a desktop computer, etc., but is not limited to this. The terminal device and the electronic device can be directly or indirectly connected through wired or wireless communication, and the embodiment of the present invention is not limited here. The method includes:

[0079] S101, determining layout planning boundary information according to netlist information and layout planning shape requirements;

[0080] Netlist information is used to represent information of design units to be laid out, and design units include standard cells and macro cells;

[0081] When performing layout and routing of each design unit, i.e., component in integrated circuit design, netlist information can be obtained. The obtained netlist information includes: the number and area of ​​standard cells and macro cells in the netlist. Of course, the netlist information can also include: all logic elements (such as standard cells, triggers, gates, etc.) and their connection relationships. Macro cells are generally larger modules such as memory and analog modules. Standard cells are smaller logic elements such as gates.

[0082] Layout planning shape requirements (such as square, rectangle with certain aspect ratio, irregular shape, etc.); according to the netlist information and layout planning shape requirements, the coordinates of the layout planning boundary, i.e., the layout planning boundary information, can be obtained. It is understandable that if the layout planning shape requirements are not specifically specified, the module layout planning shape is square by default.

[0083] S102, hierarchically dividing the design unit according to the design hierarchical information to obtain a plurality of virtual macro blocks;

[0084] The area of ​​each virtual macroblock is determined based on the areas of a plurality of design units corresponding to each virtual macroblock;

[0085] The design hierarchical information is given by the chip front-end design engineers when designing the RTL (Register Transfer Level) code. The front-end engineers design according to the module division method, from top to bottom, there are top-level modules, sub-modules, and then sub-modules also have sub-modules, forming a top-down hierarchical information. Figure 4 As shown, the design hierarchical information is represented in a tree diagram, where each node represents a module, each module has submodules, and each module is composed of several design units. According to a certain hierarchical level (according to the actual project situation), the entire netlist can be divided into a design composed of modules. By calculating the sum of the areas of macro cells and standard cells in each module, the area of ​​each module can be obtained. Therefore, the entire design can be physically divided into blocks of different sizes. Select one of the hierarchical levels and define the area block of this hierarchical level as a virtual macro block.

[0086] In the embodiment of the present invention, the entire design is divided into a plurality of virtual macro blocks, each of which includes a plurality of design units.

[0087] S103, performing timing analysis on the virtual macroblock to obtain data interaction information of the virtual macroblock;

[0088] The data interaction information of the virtual macroblock includes: the first number of network stripes of the virtual macroblock and each other block, the other blocks including the first input and output unit and other virtual macroblocks;

[0089] According to the divided virtual macro blocks, use the timing analysis tool to perform time analysis and evaluation on the signal paths between the blocks, and calculate the data flow between the virtual macro blocks. According to the data flow, the data interaction relationship between the virtual macro blocks and the first input and output units and between the virtual macro blocks can be established to form a data line network, and further obtain the number of line networks between them.

[0090] S104, performing virtual macro block layout based on data interaction information and layout planning boundary information of the virtual macro blocks;

[0091] The virtual macro blocks are laid out in sequence based on the first number of mesh strips of the virtual macro block and each other block, and the boundary information of the layout plan.

[0092] S105 . After the virtual macro blocks are laid out, multiple macro units corresponding to each virtual macro block are laid out to obtain a layout result.

[0093] After completing the layout of the virtual macro blocks, each virtual macro block is treated as an independent layout planning space to complete the layout of the macro cells and standard cells in each virtual macro block.

[0094] In an embodiment of the present invention, the layout planning boundary information is determined by the netlist information and the layout planning shape requirements, which ensures that the layout process meets the design requirements; the design unit is hierarchically divided by design hierarchical information to obtain multiple virtual macro blocks, reducing the complexity of the layout; the virtual macro blocks are time-series analyzed to obtain data interaction information; then, based on the data interaction information as the basis for the virtual module layout, the virtual macro block layout is performed, and after the layout is completed, the multiple macro units corresponding to each virtual macro block are laid out. By first laying out the virtual macro blocks according to the hierarchy, and then carefully laying out the macro units in the virtual macro blocks after the layout is completed, the hierarchical layout method not only improves the layout efficiency, but also ensures the quality of the final layout result.

[0095] Furthermore, in a possible implementation of the embodiment of the present invention, the netlist information includes: quantity information and area information of standard cells, quantity information and area information of macro cells; S101 determines the layout planning boundary information according to the netlist information and the layout planning shape requirements, including: determining the total area of ​​the standard cells according to the quantity information and area information of the standard cells; determining the total area of ​​the macro cells according to the quantity information and area information of the macro cells; determining the total area of ​​the layout planning according to the total area of ​​the standard cells, the first value corresponding to the standard cells, the total area of ​​the macro cells, and the second value corresponding to the macro cells; determining the layout planning boundary information according to the total area of ​​the layout planning and the layout planning shape requirements.

[0096] The obtained netlist information includes: the number and area of ​​standard cells and macro cells in the netlist.

[0097] In one possible case, the design unit includes only standard cells and macro cells. According to the number and area of ​​standard cells and macro cells, the total area required for layout planning can be calculated using the formula o , get the total area of ​​the layout plan, is the total area of ​​the layout plan; is the total area of ​​standard units in the design; It is the total area of ​​the macro unit in the design; α and β are engineering experience values, which can be adjusted according to the chip process technology and module utilization requirements; illustratively, α ranges from 1.5-2.5; β ranges from about 1.1.

[0098] In another possible case, the design unit also includes third-party macro units, and the formula , get the total area of ​​the layout plan, is the total area of ​​the third-party IP in the design; γ needs to be determined based on the requirements of the IP document.

[0099] Furthermore, according to the total area of ​​the layout plan and layout planning shape requirements to obtain layout planning boundary information.

[0100] In an embodiment of the present invention, by respectively calculating the total area of ​​the standard cells and the total area of ​​the macro cells, and combining the first value and the second value corresponding to each other, the total area of ​​the layout plan can be determined more accurately; and then based on this total area and the layout plan shape requirements, the layout plan boundary information can be accurately determined.

[0101] In a possible implementation manner of an embodiment of the present invention, the design hierarchical information is tree diagram information, each hierarchical level of the tree diagram information corresponds to multiple modules, and each module corresponds to multiple design units; S102 hierarchically divides the design units according to the design hierarchical information to obtain multiple virtual macro blocks, including: determining the number of multiple modules corresponding to each hierarchical level according to the design hierarchical information; determining the target hierarchical level according to the number of multiple modules corresponding to each hierarchical level and a preset number threshold; and using the multiple modules corresponding to the target hierarchical level as multiple virtual macro blocks.

[0102] The preset number threshold can be set by the user and can be 50, 70, 80, 100, 120, 150, etc., which is not limited in the embodiment of the present invention. According to the number of multiple modules corresponding to each hierarchical level and the preset number threshold, the hierarchical level closest to the preset number threshold is selected as the target hierarchical level. In the embodiment of the present invention, the target hierarchical level is screened by the preset number threshold, so that the virtual macroblock can be accurately determined.

[0103] A possible implementation of the embodiment of the present invention is that S103 performs timing analysis on virtual macroblocks to obtain data interaction information of virtual macroblocks, including: performing timing analysis on virtual macroblocks to determine the data flow between each virtual macroblock; establishing the data interaction relationship between each virtual macroblock and the first input-output unit and the data interaction relationship between each virtual macroblock according to the data flow between each virtual macroblock to form a data line network; determining the data interaction information of virtual macroblocks according to the data line network. Among them, the data flow between virtual macroblocks is calculated to form a data line network. According to the divided virtual macroblocks, a timing analysis tool is used to calculate the data flow between each virtual macroblock, and the data interaction relationship between the virtual macroblock and the first input-output unit and between each virtual macroblock can be established according to the data flow to form a data line network, and the number of lines between them can be further obtained.

[0104] A possible implementation method of an embodiment of the present invention, before S103 performs virtual macroblock layout based on data interaction information of the virtual macroblock and layout planning boundary information, it also includes: laying out the first input and output unit according to the layout planning boundary information; and / or laying out the third-party macro unit according to the layout planning boundary information and the third-party macro unit placement information.

[0105] Among them, the first input and output unit and the specific macro unit (third-party macro unit) are laid out to form a layout base point. According to the project requirements, the first input and output unit is laid out and placed on the specific edge of the layout shape. Today's large-scale designs often use third-party IP, that is, there will be third-party macro units (such as PCIE / DDR PHY). The positions of these third-party macro units and the minimum distances between them and other units have reference values ​​provided by the supplier, which can be specifically recorded in the IP document. These third-party macro units are placed and fixed (set to a fixed state) to ensure that their physical positions are not changed in the subsequent layout process. The laid-out first input and output unit or specific macro unit is used as the base point for the subsequent layout. If there is a specific macro unit, the specific macro unit is used as the base point, otherwise the first input and output unit is selected as the base point.

[0106] In a possible implementation of an embodiment of the present invention, the data interaction information also includes: the number of first registers between the virtual macroblock and each other block; S104 performs virtual macroblock layout based on the data interaction information of the virtual macroblock and the layout planning boundary information, including: determining the center position of the first unit in the layout planning boundary information; when there is a third-party macro unit, the third-party macro unit is the first unit, otherwise the first input and output unit is the first unit; determining the target virtual macro block that has the largest number of first number of network lines with the first unit; laying out the target virtual macro block according to the center position of the first unit and the number of first registers of the first unit and the target virtual macro block; taking the target virtual macro block as the new first unit, iteratively executing the virtual macro block layout to complete the virtual macro block layout.

[0107] The embodiment of the present invention provides a specific process for laying out virtual macro blocks.

[0108] It is understandable that, according to static timing analysis, a design can be seen as consisting of a large number of timing paths, and the timing paths are divided by register Flip-Flop nodes. For simplicity, the IO unit is converted into Flip-Flop according to a certain weight. The specific conversion weight is no longer limited in the embodiment of the present invention, and the user can customize it. In an actual project, the distance driven by a Flip-Flop is limited, which is set to a preset driving distance L. For the convergence of timing, the distance between two Flip-Flops should be less than L.

[0109] In some possible embodiments, the target virtual macroblock is laid out according to the center position of the first unit and the number of first registers of the first unit and the target virtual macroblock, including: determining a first planning area according to the center position of the first unit as the center of a circle and the target length as the radius; the target length is determined by the number of first registers of the first unit and the target virtual macroblock and a preset driving distance; and boundary constraints are performed according to the first planning area to lay out the target virtual macroblock at the position with the most layout boundaries.

[0110] The embodiment of the present invention proposes a layout algorithm, which first determines a base point and then lays out one virtual macroblock at a time. Figure 5 As shown, first determine the base point. If the design has a third-party macro cell, the first cell is the third-party macro cell, and the center position of the third-party macro cell is the base point; otherwise, the first cell is the first input-output cell, and the center position of the first input-output cell is the base point.

[0111] Taking the first input and output unit as the base point, we will find the target virtual macroblock with the largest number of data line nets (i.e., the largest number of first data nets) with the first input and output unit for layout. Calculate the number of register Flip-Flops M (i.e., the first number of registers) between the first input and output unit and the target virtual macroblock. Draw an arc with a radius of . Theoretically, the target virtual macroblock can be laid out in the area included in the arc, so that the virtual macroblock meets the timing requirements.

[0112] Furthermore, a boundary constraint can be added to make the target virtual macroblock layout with the most layout boundaries. In this case, the target virtual macroblock can only be laid out at the lower left corner or the upper left corner, and either of these two positions can be selected.

[0113] Next, take the target virtual macroblock as the base point and find the second virtual macroblock with the largest number of data lines between it and the target virtual macroblock for layout. Calculate the number of flip-flops N between the target virtual macroblock and the second virtual macroblock, and take the center of the first virtual macroblock (target virtual macroblock) as the center of the circle. Draw an arc with radius , and the layout of the second virtual macroblock can be completed. Repeat this cycle to complete the layout of all virtual macroblocks. It should be noted that the layout boundary at this time includes the boundary of the target virtual macroblock.

[0114] It should be noted that if there are multiple identical third-party macro cells, the center position of one third-party macro cell can be arbitrarily selected as the base point, or the center position of the third-party macro cell with the largest total number of digital nets can be selected as the base point, or the center position of the third-party macro cell with the most layout boundaries can be selected as the base point;

[0115] If there are multiple third-party macro units, and the shapes and sizes are not exactly the same, weights are assigned to the shapes and the number of boundaries, with the shape weight being w1 and the boundary weight being w2, and ; For each third-party macro unit, the comprehensive score is calculated based on the shape and the number of boundaries; assuming that the shape of the third-party macro unit i is Si and the number of boundaries is Bi, the comprehensive score is . All third-party macro units are sorted according to the comprehensive scores, and the third-party macro unit with the highest comprehensive score is selected as the final third-party macro unit, and the center position of the third-party macro unit is used as the base point. Of course, the total number of network variables can also be introduced, which is not limited in the embodiment of the present invention, and the user can set it according to actual needs.

[0116] In an embodiment of the present invention, the virtual macroblocks for the next layout are screened out by determining the base point and combining the base point with the number of grid lines of each virtual macroblock, and then the appropriate layout position is selected based on the base point and the number of registers of the virtual macroblock, and the layout of all virtual macroblocks is implemented in turn, making the layout more accurate.

[0117] A possible implementation method of an embodiment of the present invention, after performing virtual macroblock layout based on data interaction information of virtual macroblocks and layout planning boundary information, further includes: S104 adjusting the virtual macroblocks to obtain an adjusted virtual macroblock layout, wherein the total bus length of the virtual macroblocks in the adjusted virtual macroblock layout is the shortest.

[0118] The purpose of this step is to minimize the line length between virtual macro blocks. After completing the layout of all virtual macro blocks, the layout at this time only considers the timing convergence. In order to further consider the smoothness of routing, the total line length between virtual macro blocks is used as the main indicator to consider the quality of the layout. The layout with the smallest total line length also has the smallest average congestion. Reducing the line length can reduce the overall routing requirements of the design.

[0119] Specifically, the half perimeter model is used to calculate the wire length. The half perimeter wire length model uses a minimum bounding rectangle to surround the pins of all virtual macroblocks. The sum of the length and width of this rectangle is approximately the total length of the wire network between virtual macroblocks, which is called the half perimeter wire length (HPWL). The virtual macroblocks are flipped and translated to minimize the wire length, such as Figure 6 As shown, only four virtual macroblocks are shown, and the black dot of each virtual macroblock represents the data port, which is only used as an example. The data port of each virtual macroblock is determined, and the minimum enclosing rectangle that can surround all data ports is found. The sum of the length and width of the rectangle is calculated as the initial semi-perimeter line length; different flipping and translation operations are tried for each virtual macroblock. After each flip or translation, the semi-perimeter line length is recalculated. The layout with the smallest semi-perimeter line length among all attempts is recorded.

[0120] In a possible implementation of an embodiment of the present invention, the data interaction information also includes: the number of second network strips of each macro cell and other macro cells in the virtual macro block, and the number of second registers between each macro cell and other macro cells; multiple macro cells corresponding to each virtual macro block are laid out to obtain a layout result, including: determining the category of each virtual macro block, wherein if the virtual macro block only includes standard cells, the category of the virtual macro block is a standard cell type virtual macro block; otherwise, the category of the virtual macro block is a macro cell type virtual macro block; determining the center position of the second cell in each macro cell type virtual macro block, the second cell in the macro cell type virtual macro block is the second input and output unit in the virtual macro block; determining the target macro cell that has the largest number of second network strips with the second cell; laying out the target macro cell according to the center position of the second cell in the macro cell type virtual macro block, and the number of second registers between the second cell in the macro cell type virtual macro block and the target macro cell; taking the target macro cell as a new second cell, iteratively executing the macro cell layout to complete the layout of multiple macro cells.

[0121] The purpose of this step is to layout the macro cells inside the virtual macro block. After the virtual macro blocks are laid out, the specific location of each virtual macro block is obtained. The virtual macro blocks can be classified into macro cell type virtual macro blocks containing several macro cells (macro cell type virtual macro blocks can include macro cells and standard cells), and standard cell type virtual macro blocks containing only standard cells. If the virtual macro block is a standard cell type virtual macro block, the corresponding data interaction information does not exist.

[0122] For macrocell-type virtual macroblocks, there are macrocells inside these virtual macroblocks, and these macrocells are laid out. At this time, each macrocell-type virtual macroblock is treated as a separate layout planning space, and the macrocells therein are laid out using the same process as the virtual macroblock layout, so that the layout of each macrocell in the entire design can be completed.

[0123] Specifically, each virtual macroblock also has an input and output unit. At this time, the center position of the second input and output unit of the virtual macroblock is used as the base point. According to the number of grid lines, the target macrounit is selected, and then the number of register Flip-Flops P (i.e., the number of second registers) between the second input and output unit and the target macrounit is calculated. With the center of the second input and output unit as the center of the circle, Draw an arc with a radius. Theoretically, the target macrocell can be laid out in the area contained in the arc, so that the target macrocell meets the timing requirements. Add boundary constraints to make the layout boundary with the most target macrocells to be laid out. Until the layout of each macrocell is completed.

[0124] In summary, the current manual placement of large-scale macro cells consumes a lot of time and energy for engineers, and the macro cells automatically placed by the automatic layout and routing tools of the related art are difficult to apply in actual projects. The embodiment of the present invention proposes an automatic layout algorithm for macro cells. The algorithm first reads in the netlist to calculate the total layout planning area, and then divides the entire design into multiple virtual macro blocks, and layouts the virtual macro blocks based on the IO unit or the specific macro cell. After that, each virtual macro block is regarded as an independent layout planning space to complete the layout of the macro cells in each virtual macro block. The present invention takes into account the layout of standard cells (standard cell type virtual macro blocks) while laying out the macro cells, and the final macro cell layout result has good timing convergence and strong routability. The invention can greatly help the layout of large-scale macro cells, while greatly reducing the iteration time and reducing the strong dependence of the back-end staff on personal experience. In the design of large-scale macro cells, it can greatly improve work efficiency and shorten the design cycle, which is a huge breakthrough in the commercial design with increasingly frequent product updates.

[0125] A device provided by an embodiment of the present invention is introduced below. The device described below and the method described above can be referred to each other. The device of this embodiment is set in an electronic device. Figure 7 , Figure 7 : is a structural block diagram of a device according to one embodiment of the present invention, comprising:

[0126] A determination module 210 is used to determine layout planning boundary information according to the netlist information and layout planning shape requirements, wherein the netlist information is used to represent information of the design unit to be laid out, and the design unit includes a standard unit and a macro unit;

[0127] A hierarchical division module 220, configured to hierarchically divide the design unit according to the design hierarchical information to obtain a plurality of virtual macro blocks, wherein the area of ​​each virtual macro block is determined based on the areas of the plurality of design units corresponding to each virtual macro block;

[0128] The timing analysis module 230 is used to perform timing analysis on the virtual macroblock to obtain data interaction information of the virtual macroblock, wherein the data interaction information of the virtual macroblock includes: the number of first data grids of the virtual macroblock and each other block, wherein the other blocks include the first input and output unit and other virtual macroblocks;

[0129] A virtual macroblock layout module 240, configured to perform virtual macroblock layout based on data interaction information and layout planning boundary information of the virtual macroblock;

[0130] The macro unit layout module 250 is used to layout multiple macro units corresponding to each virtual macro block after the layout of the virtual macro block is completed to obtain a layout result.

[0131] In an achievable manner, the netlist information includes: quantity information and area information of standard cells, quantity information and area information of macro cells;

[0132] The determination module 210 is specifically configured to:

[0133] Determine the total area of ​​the standard units according to the quantity information and area information of the standard units;

[0134] Determine the total area of ​​the macro unit according to the quantity information and area information of the macro unit;

[0135] Determine the total area of ​​the layout plan according to the total area of ​​the standard cells, the first value corresponding to the standard cells, the total area of ​​the macro cells, and the second value corresponding to the macro cells;

[0136] Determine the layout plan boundary information based on the total area of ​​the layout plan and the layout plan shape requirements.

[0137] In an achievable manner, the design hierarchical information is tree diagram information, each hierarchical level of the tree diagram information corresponds to a plurality of modules, and each module corresponds to a plurality of design units;

[0138] The hierarchical division module 220 is specifically used for:

[0139] According to the design hierarchical information, determine the number of multiple modules corresponding to each hierarchical level;

[0140] Determine a target hierarchical level according to the number of multiple modules corresponding to each hierarchical level and a preset number threshold;

[0141] A plurality of modules corresponding to the target hierarchical level are taken as a plurality of virtual macro blocks.

[0142] In one achievable manner, the timing analysis module 230 is specifically configured to:

[0143] Performing timing analysis on virtual macroblocks to determine the data flow between each virtual macroblock;

[0144] According to the data flow between each virtual macroblock, a data interaction relationship between each virtual macroblock and the first input-output unit and a data interaction relationship between each virtual macroblock are established to form a data line network;

[0145] According to the data line network, the data interaction information of the virtual macro block is determined.

[0146] In one achievable manner, the present invention further includes:

[0147] A first base point layout module is used to: layout the first input and output unit according to the layout planning boundary information;

[0148] The second base point layout module is used to layout the third-party macro cells according to the layout planning boundary information and the third-party macro cell placement information.

[0149] In an achievable manner, the data interaction information further includes: the number of first registers between the virtual macro block and each other block;

[0150] The virtual macroblock layout module 240 is specifically used for:

[0151] Determine the center position of the first unit in the layout planning boundary information; when there is a third-party macro unit, the third-party macro unit is the first unit, otherwise the first input and output unit is the first unit;

[0152] Determine a target virtual macroblock having the largest number of first number of grid lines with the first unit; layout the target virtual macroblock according to the center position of the first unit and the number of first registers of the first unit and the target virtual macroblock;

[0153] The target virtual macroblock is used as a new first unit, and the virtual macroblock layout is iteratively performed to complete the virtual macroblock layout.

[0154] In one achievable manner, the virtual macroblock layout module 240 is specifically configured to:

[0155] The first planning area is determined according to the center position of the first unit as the center of the circle and the target length as the radius; the target length is determined by the number of first registers of the first unit and the target virtual macroblock and a preset driving distance;

[0156] Boundary constraints are performed according to the first planning area, and the target virtual macroblock is laid out at the position with the most layout boundaries.

[0157] In one achievable manner, the present invention further includes:

[0158] The line length minimization module is used to adjust the virtual macroblock to obtain an adjusted virtual macroblock layout, wherein the total line length of the virtual macroblocks in the adjusted virtual macroblock layout is the shortest.

[0159] In an achievable manner, the data interaction information further includes: the number of second digital grids between each macro unit and other macro units in the virtual macro block, and the number of second registers between each macro unit and other macro units;

[0160] The macro cell layout module 250 is specifically used to determine the category of each virtual macro block, wherein if the virtual macro block only includes standard cells, the category of the virtual macro block is a standard cell type virtual macro block; otherwise, the category of the virtual macro block is a macro cell type virtual macro block;

[0161] Determine the center position of the second unit in each macro unit class virtual macro block, the second unit in the macro unit class virtual macro block is the second input and output unit in the virtual macro block;

[0162] Determine a target macro cell having the largest number of second number of nets with the second cell;

[0163] Arrange the target macrocell according to the center position of the second cell in the macrocell class virtual macroblock, the second cell in the macrocell class virtual macroblock and the number of second registers of the target macrocell;

[0164] The target macro cell is used as a new second cell and macro cell placement is iteratively performed to complete placement of multiple macro cells.

[0165] Figure 8 A structural diagram of an electronic device provided by an embodiment of the present invention, such as Figure 8 As shown, the electronic device includes: a memory 60 for storing a computer program;

[0166] The processor 61 is used to implement the steps of the method in the above embodiment when executing a computer program.

[0167] The electronic device provided in this embodiment may include but is not limited to a smart phone, a tablet computer, a laptop computer or a desktop computer.

[0168] Among them, the processor 61 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 61 can be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), and programmable logic array (PLA). The processor 61 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 61 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 61 may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0169] The memory 60 may include one or more computer-readable storage media, which may be non-transitory. The memory 60 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the memory 60 is at least used to store the following computer program 601, wherein the computer program can implement the relevant steps of the method disclosed in any of the aforementioned embodiments after being loaded and executed by the processor 61. In addition, the resources stored in the memory 60 may also include an operating system 602 and data 603, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 602 may include Windows, Unix, Linux, etc. The data 603 may include but is not limited to netlist information, layout planning shape requirements, layout results, etc.

[0170] In some embodiments, the electronic device may further include a display screen 62 , an input / output interface 63 , a communication interface 64 , a power supply 65 , and a communication bus 66 .

[0171] Those skilled in the art will understand that Figure 8 The structure shown in the figure does not constitute a limitation on the structure of the electronic device, and may include more or fewer components than those shown in the figure.

[0172] It is understandable that if the macro unit layout method in the above embodiment is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention is essentially or the part that contributes to the current technology or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and executes all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), electrically erasable programmable ROM, register, hard disk, removable disk, CD-ROM, magnetic disk or optical disk and other media that can store program code.

[0173] Based on this, an embodiment of the present invention further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned macro cell layout method are implemented.

[0174] Based on this, an embodiment of the present invention further provides a computer program product, including a computer program or instructions, which implement the steps of the above-mentioned macro cell layout method when executed by a processor.

[0175] The above is a detailed introduction to a macrocell layout method, device, equipment and medium provided by an embodiment of the present invention. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0176] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0177] It should be understood that, although the steps in the flowchart of the accompanying drawings are displayed in sequence as indicated by the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the accompanying drawings may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0178] The above is a detailed introduction to a macrocell layout method, device, equipment and medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A macrocell layout method, characterized in that: include: Determine layout planning boundary information according to netlist information and layout planning shape requirements, wherein the netlist information is used to represent information of design units to be laid out, and the design units include standard units and macro units; hierarchically divide the design unit according to the design hierarchical information to obtain a plurality of virtual macro blocks, wherein the area of ​​each of the virtual macro blocks is determined based on the areas of the plurality of design units corresponding to each of the virtual macro blocks; Performing timing analysis on the virtual macroblock to obtain data interaction information of the virtual macroblock, wherein the data interaction information of the virtual macroblock includes: the number of first data grid lines of the virtual macroblock and each other block, wherein the other block includes a first input-output unit and other virtual macroblocks; Performing virtual macro block layout based on the data interaction information of the virtual macro block and the layout planning boundary information; After the virtual macro blocks are laid out, multiple macro units corresponding to each of the virtual macro blocks are laid out to obtain a layout result.

2. The macrocell layout method according to claim 1, characterized in that: The netlist information includes: quantity information and area information of standard cells, quantity information and area information of macro cells; Determine the layout planning boundary information based on the netlist information and layout planning shape requirements, including: Determining the total area of ​​the standard units according to the quantity information and area information of the standard units; Determining the total area of ​​the macro units according to the quantity information and area information of the macro units; Determine the total area of ​​the layout plan according to the total area of ​​the standard cells, the first value corresponding to the standard cells, the total area of ​​the macro cells, and the second value corresponding to the macro cells; Layout planning boundary information is determined according to the total area of ​​the layout planning and the layout planning shape requirement.

3. The macrocell layout method according to claim 1, characterized in that: The design hierarchical information is tree diagram information, each hierarchical level of the tree diagram information corresponds to a plurality of modules, and each module corresponds to a plurality of design units; The design unit is hierarchically divided according to the design hierarchical information to obtain multiple virtual macro blocks, including: Determine the number of multiple modules corresponding to each hierarchical level according to the design hierarchical information; Determine a target hierarchical level according to the number of multiple modules corresponding to each hierarchical level and a preset number threshold; The multiple modules corresponding to the target hierarchical level are used as multiple virtual macro blocks.

4. The macrocell layout method according to claim 1, characterized in that: Performing timing analysis on the virtual macroblock to obtain data interaction information of the virtual macroblock includes: Performing timing analysis on the virtual macroblocks to determine data flows between the virtual macroblocks; According to the data flow between the virtual macro blocks, a data interaction relationship between the virtual macro blocks and the first input-output unit and a data interaction relationship between the virtual macro blocks are established to form a data line network; According to the data line network, data interaction information of the virtual macro block is determined.

5. The macrocell layout method according to claim 1, characterized in that: Before performing virtual macro block layout based on the data interaction information of the virtual macro block and the layout planning boundary information, the method further includes: laying out the first input-output unit according to the layout planning boundary information; and / or, The third-party macro cells are laid out according to the layout planning boundary information and the third-party macro cell placement information.

6. The macrocell layout method according to claim 5, characterized in that: The data interaction information also includes: the number of first registers between the virtual macroblock and each other block; Performing virtual macro block layout based on the data interaction information of the virtual macro block and the layout planning boundary information includes: Determine the center position of the first unit in the layout planning boundary information; when there is a third-party macro unit, the third-party macro unit is the first unit, otherwise the first input and output unit is the first unit; Determine a target virtual macroblock having the largest number of first number of grid lines with the first unit; and layout the target virtual macroblock according to the center position of the first unit and the number of first registers of the first unit and the target virtual macroblock; The target virtual macroblock is used as a new first unit, and the virtual macroblock layout is iteratively performed to complete the virtual macroblock layout.

7. The macrocell layout method according to claim 6, characterized in that: According to the center position of the first unit, the first unit and the number of first registers of the target virtual macro block, the target virtual macro block is laid out, including: Determine a first planning area according to the center position of the first unit as the center of the circle and the target length as the radius; the target length is determined by the number of first registers of the first unit and the target virtual macroblock and a preset driving distance; Boundary constraints are performed according to the first planning area, and the target virtual macroblock is laid out at the position with the most layout boundaries.

8. The macrocell layout method according to claim 6, characterized in that: After performing virtual macro block layout based on the data interaction information and layout planning boundary information of the virtual macro block, the method further includes: The virtual macroblocks are adjusted to obtain an adjusted virtual macroblock layout, wherein the total bus length of the virtual macroblocks in the adjusted virtual macroblock layout is the shortest.

9. The macrocell layout method according to claim 8, characterized in that: The data interaction information also includes: the number of second data grids of each macro unit and other macro units in the virtual macro block, and the number of second registers between each macro unit and other macro units; Laying out multiple macro units corresponding to each of the virtual macro blocks to obtain a layout result includes: Determine the category of each virtual macroblock, wherein if the virtual macroblock includes only standard cells, the category of the virtual macroblock is a standard cell type virtual macroblock; otherwise, the category of the virtual macroblock is a macro cell type virtual macroblock; Determine the center position of the second unit in each of the macro-unit-type virtual macro blocks, the second unit in the macro-unit-type virtual macro block being the second input-output unit in the virtual macro block; Determine a target macro cell having a maximum second number of network stripes with the second cell; Arrange the target macrocell according to the center position of the second cell in the macrocell class virtual macroblock, the second cell in the macrocell class virtual macroblock and the number of second registers of the target macrocell; The target macro cell is used as a new second cell, and macro cell layout is iteratively performed to complete the layout of multiple macro cells.

10. A macrocell layout device, characterized in that: include: A determination module, used to determine layout planning boundary information according to netlist information and layout planning shape requirements, wherein the netlist information is used to characterize information of design units to be laid out, and the design units include standard units and macro units; A hierarchical division module, used for hierarchically dividing the design unit according to the design hierarchical information to obtain a plurality of virtual macro blocks, wherein the area of ​​each of the virtual macro blocks is determined based on the areas of the plurality of design units corresponding to each of the virtual macro blocks; A timing analysis module, used for performing timing analysis on the virtual macroblock to obtain data interaction information of the virtual macroblock, wherein the data interaction information of the virtual macroblock includes: the number of first data grids of the virtual macroblock and each other block, wherein the other block includes a first input-output unit and other virtual macroblocks; A virtual macroblock layout module, configured to perform virtual macroblock layout based on the data interaction information of the virtual macroblock and the layout planning boundary information; The macro unit layout module is used to layout multiple macro units corresponding to each virtual macro block after the virtual macro block is laid out to obtain a layout result.

11. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the macro cell layout method according to any one of claims 1 to 9.

12. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the macro cell layout method according to any one of claims 1 to 9 are implemented.

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