Pixel

Abstract

The invention relates to a pixel. The pixel includes: a first transistor configured to output a driving current corresponding to a magnitude of a data voltage; a second transistor connected to the data line; a third transistor connected between a second terminal of the first transistor and a gate of the first transistor; a fourth transistor connected between a first terminal of the first transistor and the driving voltage line; a fifth transistor connected to a second terminal of the first transistor; a sixth transistor connected between the first terminal of the first transistor and the second transistor; a light emitting diode connected to the fifth transistor; and a storage capacitor connected between the gate of the first transistor and the driving voltage line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0173440 filed in the Korean Intellectual Property Office on December 4, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The present disclosure relates to a pixel designed to block leakage current of a transistor. Background Art

[0004] The display apparatus includes pixels, and each pixel may include a capacitor, a light emitting device, and a transistor driving the light emitting device. Summary of the invention

[0005] One or more embodiments of the present disclosure include a pixel that can improve the image quality of a display device by preventing a data voltage written from a data voltage line from being reduced due to a leakage current of a switching transistor.

[0006] One or more embodiments of the present disclosure include a pixel that can reduce faint light emission in a non-emission period by preventing a driving voltage written from a driving voltage line from flowing into a light emitting diode due to a leakage current of a switching transistor.

[0007] The aspects and features of the embodiments of the present disclosure are not limited to the above-mentioned aspects and features, and other aspects and features not mentioned can be clearly understood by those skilled in the art from the following description.

[0008] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the disclosed embodiments.

[0009] According to one or more embodiments, a pixel includes: a first transistor configured to output a driving current corresponding to the amplitude of a data voltage; a second transistor connected to a data line; a third transistor connected between a second terminal of the first transistor and a gate of the first transistor; a fourth transistor connected between a first terminal of the first transistor and a driving voltage line; a fifth transistor connected to a second terminal of the first transistor; a sixth transistor connected between the first terminal of the first transistor and the second transistor; a light emitting diode connected to the fifth transistor; and a storage capacitor connected between the gate of the first transistor and the driving voltage line.

[0010] The pixel may further include a seventh transistor connected between the third transistor and the initialization voltage line.

[0011] The pixel may further include an eighth transistor connected between the fifth transistor and the initialization voltage line.

[0012] The pixel can operate in a non-emission period and an emission period during a frame period, wherein the non-emission period may include a first period and a second period, in which: in the first period: the seventh transistor is turned on, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the eighth transistor are turned off, and an initialization voltage is applied from an initialization voltage line to the gate of the first transistor; in the second period: the second transistor, the third transistor, the sixth transistor and the eighth transistor are turned on, the fourth transistor, the fifth transistor and the seventh transistor are turned off, a data signal is applied from a data line to the gate of the first transistor, and an initialization voltage is applied from the initialization voltage line to the first terminal of the light-emitting diode.

[0013] In the second period, a data voltage corresponding to the data signal applied to the first transistor and a threshold voltage of the first transistor may be stored in the storage capacitor.

[0014] The fourth transistor and the fifth transistor may be turned on during the emission period.

[0015] The non-emission period may further include a delay period between the second period and the emission period, in which the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are turned off.

[0016] In the second period, the second transistor and the third transistor may be controlled by the first gate signal, the eighth transistor may be controlled by the second gate signal, and the sixth transistor may be controlled by the third gate signal.

[0017] The timing at which the third gate signal transitions from the gate-on voltage to the gate-off voltage and the sixth transistor is turned off may be before the timing at which the first gate signal transitions from the gate-on voltage to the gate-off voltage and the second transistor is turned off.

[0018] During the delay period, a gate-source voltage of the turned-off sixth transistor may be greater than a gate-source voltage of the turned-off second transistor.

[0019] According to one or more embodiments, a pixel includes: a first transistor configured to output a driving current corresponding to the amplitude of a data voltage; a second transistor connected between a first terminal of the first transistor and a data line; a third transistor connected between a second terminal of the first transistor and a gate of the first transistor; a fourth transistor connected between a first terminal of the first transistor and a driving voltage line; a fifth transistor connected to a second terminal of the first transistor; a sixth transistor connected between the fifth transistor and a light emitting diode; a light emitting diode connected to the sixth transistor; and a storage capacitor connected between the gate of the first transistor and the driving voltage line.

[0020] The pixel may further include a seventh transistor connected between the third transistor and the initialization voltage line.

[0021] The pixel may further include an eighth transistor connected between the sixth transistor and the initialization voltage line.

[0022] The pixel can operate in a non-emission period and an emission period during a frame period, wherein the non-emission period may include a first period and a second period, in which: in the first period: the seventh transistor is turned on, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the eighth transistor are turned off, and an initialization voltage is applied from an initialization voltage line to the gate of the first transistor; in the second period: the second transistor, the third transistor and the eighth transistor are turned on, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are turned off, a data signal is applied from a data line to the gate of the first transistor, and an initialization voltage is applied from the initialization voltage line to the first terminal of the light-emitting diode.

[0023] The fourth transistor, the fifth transistor, and the sixth transistor may be turned on in the emission period.

[0024] The non-emission period may further include a delay period between the second period and the emission period, in which the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are turned off.

[0025] In the second period, the second transistor and the third transistor may be controlled by the fourth gate signal, and the eighth transistor may be controlled by the fifth gate signal.

[0026] In the emission period, the fourth transistor and the fifth transistor may be controlled by the sixth gate signal, and the sixth transistor may be controlled by the seventh gate signal.

[0027] The timing at which the seventh gate signal transitions from the gate-on voltage to the gate-off voltage and the sixth transistor is turned off may be before the timing at which the sixth gate signal transitions from the gate-on voltage to the gate-off voltage and the fifth transistor is turned off.

[0028] During the non-emission period, the fifth transistor and the sixth transistor may be turned off, and a gate-source voltage of the turned-off sixth transistor may be greater than a gate-source voltage of the turned-off fifth transistor.

[0029] Furthermore, a computer program stored in a computer-readable recording medium for execution to implement the present disclosure may also be provided.

[0030] Furthermore, a computer-readable recording medium recording a computer program for executing the method for realizing the present disclosure may also be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other aspects and features of the embodiments of the present disclosure will become more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0032] Figure 1 is a diagram schematically showing a display device according to one or more embodiments;

[0033] Figure 2 is an equivalent circuit diagram of a pixel included in a display device according to one or more embodiments;

[0034] Figure 3 is a diagram showing a method according to one or more embodiments Figure 2 A timing diagram of a driving signal of the pixel circuit shown;

[0035] Figure 4 is a timing diagram illustrating a method of preventing current leakage by adjusting a driving timing of an eighth transistor of a pixel circuit according to one or more embodiments;

[0036] Figure 5 is an equivalent circuit diagram of a pixel included in a display device according to one or more embodiments;

[0037] Figure 6 is a diagram showing a method according to one or more embodiments Figure 5 A timing diagram of a driving signal of the pixel circuit shown;

[0038] Figure 7 is a timing diagram illustrating a method of preventing current leakage by adjusting a driving timing of an eighth transistor of a pixel circuit according to one or more embodiments; and

[0039] Fig. 8A is a diagram for explaining turning on and off of a P-type transistor according to a gate voltage of the P-type transistor of a pixel circuit according to one or more embodiments, and Figure 8Bis a diagram for explaining the amount of leakage current according to the threshold voltage of a P-type transistor of a pixel circuit according to one or more embodiments. DETAILED DESCRIPTION

[0040] Reference will now be made in detail to embodiments, examples of which are shown in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this respect, the embodiments presented may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, embodiments are described below only by reference to the accompanying drawings to explain aspects of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. Throughout this disclosure, the expression "at least one of a, b, and c" indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or its variation.

[0041] Since the present disclosure allows for various variations and multiple embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. The effects, aspects, and features of the embodiments of the present disclosure and the manner in which they are achieved will become apparent by reference to the embodiments that will be described in detail later with reference to the drawings. However, the present disclosure is not limited to the following embodiments, but may be implemented in various forms.

[0042] It will be understood that although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms and these terms are only used to distinguish one element from another.

[0043] Unless otherwise limited in the context, a singular expression includes a plural expression.

[0044] In the following embodiments, terms such as “include” or “have” mean that the features or elements described in the specification are present, and do not preclude the possibility of adding one or more other features or elements.

[0045] Herein, “A and / or B” may indicate only A, only B, or both A and B. Also, herein, “at least one of A and B” may indicate only A, only B, or both A and B.

[0046] In the following embodiments, when X and Y are connected to each other, this may include a case where X and Y are electrically connected to each other, a case where X and Y are functionally connected to each other, and a case where X and Y are directly connected to each other. Here, X and Y may be objects (e.g., devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.). Therefore, the connection relationship is not limited to a connection relationship (e.g., a predetermined connection relationship) such as the connection relationship illustrated in the drawings or the detailed description, and the connection relationship may also include a connection relationship other than the connection relationship illustrated in the drawings or the detailed description.

[0047] When X and Y are electrically connected to each other, for example, at least one element capable of electrically connecting between X and Y (eg, a switch, a transistor, a capacitor, an inductor, a resistor, a diode, etc.) may be connected between X and Y.

[0048] In the following embodiments, "ON" used in conjunction with the state of an element can represent the activated state of the element, and "OFF" can represent the disabled state of the element. "ON" used in conjunction with the signal received by the element can represent the signal of the activated element, and "OFF" can represent the signal of the disabled element. The element can be activated by a high level voltage or a low level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low level voltage, and an N-channel transistor (N-type transistor) is activated by a high level voltage. Therefore, it should be understood that the "ON" voltage for a P-type transistor and an N-type transistor is an opposite (low and high) voltage level.

[0049] In the following embodiments, the x-direction, y-direction, and z-direction are not limited to directions along the three axes of a Cartesian coordinate system, and may be interpreted in a broad sense including these. For example, the x-direction, y-direction, and z-direction may be orthogonal to each other, but may also represent different directions that are not orthogonal to each other.

[0050] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings, and in the description with reference to the accompanying drawings, the same reference numerals denote the same elements and redundant descriptions thereof will be omitted.

[0051] Figure 1 is a diagram schematically illustrating a display device according to one or more embodiments.

[0052] refer to Figure 1 The display device 1 may include a pixel unit 11 , a gate driving circuit 12 , a data driving circuit 13 and a controller 14 .

[0053] A plurality of pixels PX and signal lines through which electrical signals may be applied to the plurality of pixels PX may be arranged in the pixel unit 11. The pixel unit 11 may be a display region that displays an image.

[0054] The plurality of pixels PX may be repeatedly arranged along a first direction (x direction, row direction) and a second direction (y direction, column direction). The plurality of pixels PX may be arranged in a stripe arrangement, Arrangement or various forms of mosaic arrangement to achieve an image. is a registered trademark of Samsung Display Co., Ltd. of South Korea. Each of the plurality of pixels PX may include a light emitting diode as a display element, and the light emitting diode may be connected to a pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. Figure 2 A pixel circuit according to one or more embodiments is described.

[0055] The signal lines through which electrical signals can be applied to the plurality of pixels PX may include a plurality of gate lines GL extending in a first direction (e.g., the x direction) and a plurality of data lines DL extending in a second direction (e.g., the y direction). The plurality of gate lines GL may be spaced apart from one another along the second direction (e.g., the y direction) and configured to transmit gate signals GS to the pixels PX. The plurality of data lines DL may be spaced apart from one another in the first direction (e.g., the x direction) and configured to transmit data signals DS to the pixels PX. Each of the plurality of pixels PX may be connected to at least one corresponding gate line among the plurality of gate lines GL and a corresponding data line among the plurality of data lines DL. Figure 1 In the embodiment of the present invention, for convenience of explanation, one gate line connected to the pixel PX is shown. However, each pixel PX may be connected to a plurality of gate lines according to the number of transistors constituting the pixel circuit.

[0056] The gate driving circuit 12 may be connected to a plurality of gate lines GL, generate a gate signal GS in response to a gate control signal GCS from the controller 14, and sequentially provide the gate signal GS to the gate lines GL. The gate lines GL may be connected to the gates of transistors included in the pixels PX. The gate signal GS may be a gate control signal that controls the turning on and off of a transistor having a gate connected to the gate line GL. The gate signal GS may be a square wave signal that includes a turn-on voltage at which the transistor may be turned on and a turn-off voltage at which the transistor may be turned off.

[0057] The data driving circuit 13 may be connected to a plurality of data lines DL and provide data signals DS to the data lines DL in response to control signals DCS from the controller 14. The data driving circuit 13 may receive gamma voltages GV respectively corresponding to grayscales and image data DAT2 from the controller 14 and generate data signals DS corresponding to the grayscales.

[0058] The controller 14 may generate a gate control signal GCS and a data control signal DCS based on a signal input from the outside. The controller 14 may provide the gate control signal GCS to the gate driving circuit 12 and the data control signal DCS to the data driving circuit 13.

[0059] The controller 14 may generate image data DAT2 by converting input image data DAT1 input from an external source (e.g., a graphics processor). For example, the controller 14 may convert input image data DAT1 having an RGB format into image data DAT2 having a format matching the pixel arrangement of the pixel unit 11. The controller 14 may include a storage unit in which a gamma voltage GV corresponding to a grayscale and correction data is written.

[0060] exist Figure 1 , the data driving circuit 13 and the controller 14 are shown as being implemented independently of each other, but the present disclosure is not limited thereto. For example, the data driving circuit 13 and the controller 14 may be implemented as a single integrated circuit (IC) (eg, a driver integrated circuit).

[0061] The display device 1 according to one or more embodiments may be an organic light emitting display device (or organic EL display device), an inorganic light emitting display device (or inorganic EL display device), and / or a quantum dot light emitting display device.

[0062] The display device 1 can be used not only as a display screen for mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs), but can also be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, and / or Internet of Things (IOT) devices. In addition, the display device 1 according to one or more embodiments can be used in wearable devices such as smart watches, watch phones, glasses-type displays, and / or head-mounted displays (HMDs). In addition, the display device 1 according to one or more embodiments can be used as a panel of a vehicle, a central information display (CID) placed on the central instrument panel (fascia) or dashboard of the vehicle, an interior mirror display that replaces the side mirrors of the vehicle, or a display placed on the back of the front seat as a display for entertaining passengers at the rear seat of the vehicle.

[0063] Figure 2 is an equivalent circuit diagram of a pixel included in a display device according to one or more embodiments.

[0064] refer to Figure 2, the pixel PX is a display element (i.e., a light emitting device) and may include a light emitting diode ED and a pixel circuit connected to the light emitting diode ED. In one or more embodiments, the light emitting diode ED may be an organic light emitting diode (OLED). The pixel PX may emit, for example, red light, green light, blue light, and / or white light through the light emitting diode ED. In one or more embodiments, the pixel circuit may include a first transistor T1 to an eighth transistor T8 and a storage capacitor Cst.

[0065] The first transistor T1 may be a driving transistor configured to output a driving current Id corresponding to a data signal, and the second transistor T2 to the eighth transistor T8 may be a switching transistor configured to transmit a signal. The first terminal (e.g., the first electrode) of each of the first transistor T1 to the eighth transistor T8 may be a source or a drain, and the second terminal (e.g., the second electrode) of each of the first transistor T1 to the eighth transistor T8 may be a terminal different from the first terminal. For example, when the first terminal is a source terminal, the second terminal may be a drain terminal.

[0066] In one or more embodiments, the node to which the second transistor T2 and the eighth transistor T8 are connected may be defined as the first node N1, the node to which the first transistor T1 and the fifth transistor T5 are connected may be defined as the second node N2, and the node to which the gate of the first transistor T1 and the third transistor T3 are connected may be defined as the gate node G.

[0067] In one or more embodiments, Figure 2 As shown, the plurality of transistors included in the pixel circuit (i.e., the first transistor T1 to the eighth transistor T8) may be P-type metal oxide semiconductor field effect transistors (MOSFETs). In one or more embodiments, the plurality of transistors included in the pixel circuit may be N-type MOSFETs. In one or more embodiments, some of the plurality of transistors included in the pixel circuit may be N-type MOSFETs, and the other transistors may be P-type MOSFETs.

[0068] In one or more embodiments, the plurality of transistors included in the pixel circuit may be P-type silicon thin film transistors (silicon-TFTs). In one or more embodiments, the plurality of transistors included in the pixel circuit may be N-type oxide thin film transistors (oxide-TFTs). In one or more embodiments, some of the plurality of transistors included in the pixel circuit may be N-type oxide-TFTs, while other transistors may be P-type silicon-TFTs.

[0069] The oxide-TFT may be a low temperature polycrystalline oxide (LTPO) TFT in which the active pattern (e.g., semiconductor layer) includes an oxide. However, this is an example, and the N-type transistor is not limited thereto. For example, the active pattern (e.g., semiconductor layer) included in the N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon) or an organic semiconductor. The silicon-TFT may be a low temperature polycrystalline silicon (LTPS) TFT in which the active pattern (semiconductor layer) includes amorphous silicon, polycrystalline silicon, etc.

[0070] The pixel PX may be connected to a first gate line configured to transmit a first gate signal GW, a second gate line configured to transmit a second gate signal GI, a third gate line configured to transmit a third gate signal GWB, and a fourth gate line configured to transmit a fourth gate signal EM. In one or more embodiments, the fourth gate signal EM may be referred to as an emission control signal, and the fourth gate line may be referred to as an emission control line. In addition, the pixel PX may be connected to a driving voltage line configured to transmit a first driving voltage VDD, an initialization voltage line configured to transmit an initialization voltage Vint, and a data line configured to transmit a data voltage Vdata. The first gate signal GW, the second gate signal GI, the third gate signal GWB, and the fourth gate signal EM may be connected to a first gate line configured to transmit a first gate signal GW, a second gate signal GI, a third gate signal GWB, and a fourth gate signal EM. Figure 1 The gate drive circuit 12 is provided to Figure 1 Pixel unit 11.

[0071] A voltage level of the first driving voltage VDD provided through the driving voltage line may be higher than a voltage level of the second driving voltage VSS. A voltage level of the initialization voltage Vint may be lower than a voltage level of the first driving voltage VDD.

[0072] The first transistor T1 may be connected between the fifth transistor T5 and the sixth transistor T6. In addition, the first transistor T1 may be connected between the third transistor T3 and the eighth transistor T8. The first transistor T1 may include a gate, a first terminal connected to the second node N2, and a second terminal. The first terminal of the first transistor T1 may be connected to a driving voltage line through which a first driving voltage VDD is provided via the fifth transistor T5, and the second terminal of the first transistor T1 may be connected to a pixel electrode (e.g., an anode) of the light emitting diode ED via the sixth transistor T6. The first transistor T1 may be configured to receive a data voltage Vdata through a data line according to a switching operation of the second transistor T2 and the eighth transistor T8, and control the amount of a driving current Id flowing to the light emitting diode ED.

[0073] The second transistor T2 may be connected between the eighth transistor T8 and the data line providing the data voltage Vdata. The second transistor T2 may include a gate connected to the first gate line, a first terminal connected to the data line, and a second terminal connected to the first node N1. The second transistor T2 may be configured to be turned on in response to a first gate signal GW transmitted through the first gate line, and electrically connect the data line to the first node N1, and transmit the data voltage Vdata corresponding to the data signal transmitted through the data line to the first node N1 connected to the eighth transistor T8.

[0074] The third transistor T3 may be connected between the second terminal of the first transistor T1 and the gate of the first transistor T1. In addition, the third transistor T3 may be connected between the fourth transistor T4 and the sixth transistor T6. The third transistor T3 may include a gate connected to the first gate line, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the gate node G and the storage capacitor Cst. In one or more embodiments, the third transistor T3 may be configured to be turned on in response to a first gate signal GW transmitted through the first gate line to connect the second terminal of the first transistor T1 to the gate of the first transistor T1.

[0075] The fourth transistor T4 may be connected between the gate of the first transistor T1 and the initialization voltage line. The fourth transistor T4 may include a gate connected to the second gate line, a first terminal connected to the gate node G, and a second terminal connected to the initialization voltage line. The fourth transistor T4 may be configured to be turned on in response to a second gate signal GI transmitted through the second gate line, and to provide an initialization voltage Vint transmitted through the initialization voltage line to the gate node G.

[0076] The fifth transistor T5 may be connected between the first terminal of the first transistor T1 and a driving voltage line through which the first driving voltage VDD is provided. The fifth transistor T5 may include a gate connected to the fourth gate line, a first terminal connected to the driving voltage line, and a second terminal connected to the second node N2. The fifth transistor T5 may be configured to be turned on in response to a fourth gate signal EM transmitted through the fourth gate line, and transmit the first driving voltage VDD to the first terminal of the first transistor T1.

[0077] The sixth transistor T6 may be connected between the second terminal of the first transistor T1 and the light emitting diode ED. In addition, the sixth transistor T6 may be connected between the third transistor T3 and the seventh transistor T7. The sixth transistor T6 may include a gate connected to a fourth gate line, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to a pixel electrode (anode) of the light emitting diode ED. The sixth transistor T6 may be configured to be turned on in response to a fourth gate signal EM transmitted through a fourth gate line, and provide a driving current Id output by the first transistor T1 to the light emitting diode ED.

[0078] The seventh transistor T7 may be connected between the light emitting diode ED and the initialization voltage line. The seventh transistor T7 may include a gate connected to the first gate line, a first terminal connected to the pixel electrode (anode) of the light emitting diode ED, and a second terminal connected to the initialization voltage line. The seventh transistor T7 may be configured to be turned on in response to the first gate signal GW transmitted through the first gate line, and provide the initialization voltage Vint to the pixel electrode (anode) of the light emitting diode ED. In one or more embodiments, the gate of the seventh transistor T7 may be connected to the second gate line transmitting the second gate signal GI, but may have a different driving timing from the driving timing of the second gate line connected to the gate of the fourth transistor T4. For example, for the pixel PX in the nth row, the gate of the fourth transistor T4 may be connected to the nth second gate line, the nth second gate signal may be received from the nth second gate line, the gate of the seventh transistor T7 may be connected to the n+1th second gate line, and the n+1th second gate signal may be received from the n+1th second gate line.

[0079] The eighth transistor T8 may be connected between the second transistor T2 and the first terminal of the first transistor T1. The eighth transistor T8 may include a gate connected to the third gate line, a first terminal connected to the first node N1, and a second terminal connected to the second node N2. The eighth transistor T8 may be configured to be turned on in response to a third gate signal GWB transmitted through the third gate line, and to provide the data voltage Vdata provided by the second transistor T2 to the first transistor T1. In one or more embodiments, the gate of the eighth transistor T8 may be connected to the first gate line and receive the first gate signal GW from the first gate line.

[0080] In one or more embodiments, when the second transistor T2 is turned on in response to the first gate signal GW, the data voltage Vdata transmitted through the data line may be provided to the first node N1. In this case, when the second transistor T2 is turned off, the voltage level of the first node N1 may be lower than the voltage level of the data voltage Vdata due to leakage current. When the eighth transistor T8 is connected between the second terminal of the second transistor T2 and the first terminal of the first transistor T1, the gate-source voltage (V GS (T8)) can be V GH -Vdata' (where V GH is the gate high voltage of the eighth transistor T8, and Vdata' is the voltage of the first node N1). When the eighth transistor T8 is not connected to the second transistor T2 and the second transistor T2 is directly connected to the first transistor T1, the gate-source voltage (V GS (T2)) can be V GH -Vdata (where V GH is the gate high voltage of the second transistor T2, and Vdata is the data voltage). Since Vdata>Vdata', the gate-source voltage (V GS (T8)) is greater than the gate-source voltage (V GS (T2)), and therefore, when the eighth transistor T8 is connected to the second transistor T2, the cut-off efficiency can be higher than the cut-off efficiency when the eighth transistor T8 is not connected to the second transistor T2. When the cut-off efficiency of the switching transistor is high, the leakage current blocking efficiency can be high.

[0081] The storage capacitor Cst may be connected between the driving voltage line and the gate of the first transistor T1. A first electrode of the storage capacitor Cst may be connected to the driving voltage line, and a second electrode of the storage capacitor Cst may be connected to the gate node G. The storage capacitor Cst may store a threshold voltage of the first transistor T1 and a voltage corresponding to a data signal.

[0082] The light emitting diode ED may be connected to the sixth transistor T6. The light emitting diode ED may include a pixel electrode (e.g., an anode) connected to the second terminal of the sixth transistor T6 and an opposing electrode (e.g., a cathode) facing the pixel electrode, and the second driving voltage VSS may be provided to the opposing electrode. The opposing electrode may be a common electrode shared by a plurality of pixels PX.

[0083] Figure 3 is a diagram showing a method according to one or more embodiments Figure 22 is a timing diagram of the driving signals of the pixel circuit shown.

[0084] The pixel PX may display an image for each frame period. One frame period may include a non-emission period NEP in which the pixel PX does not emit light and an emission period EP in which the pixel PX emits light. The non-emission period NEP may include a first period P11, a second period P12, and a delay period DP1.

[0085] The first gate signal GW, the second gate signal GI, the third gate signal GWB, and the fourth gate signal EM may each have a high level voltage in some cycles and a low level voltage in some other cycles. In one or more embodiments, the high level voltage of each of the first gate signal GW, the second gate signal GI, the third gate signal GWB, and the fourth gate signal EM may be a gate-off voltage that turns off the transistor, and the low level voltage of each of the first gate signal GW, the second gate signal GI, the third gate signal GWB, and the fourth gate signal EM may be a gate-on voltage that turns on the transistor.

[0086] The first period P11 may be an initialization period for initializing the gate of the first transistor T1. The first period P11 may be approximately one horizontal period 1H.

[0087] In the first period P11, a first gate signal GW having a gate-off voltage may be provided to the first gate line, a second gate signal GI having a gate-on voltage may be provided to the second gate line, a third gate signal GWB having a gate-off voltage may be provided to the third gate line, and a fourth gate signal EM having a gate-off voltage may be provided to the fourth gate line. An initialization voltage Vint may be provided through the initialization voltage line. When the initialization voltage Vint is provided, the gate of the first transistor T1 may be initialized.

[0088] The fourth transistor T4 may be turned on in response to the second gate signal GI. The initialization voltage Vint may be transmitted to the gate node G (ie, the gate of the first transistor T1) through the turned-on fourth transistor T4. In the first period P11, the voltage of the gate node G may be initialized to the initialization voltage Vint.

[0089] The second period P12 may be a writing and compensation period, in which the data voltage Vdata is transferred to the gate of the first transistor T1 (e.g., because the first transistor T1 is diode-connected during the second period P12) and the threshold voltage of the first transistor T1 is compensated. The second period P12 may be approximately one horizontal period 1H.

[0090] In the second period P12, a first gate signal GW having a gate-on voltage may be provided to the first gate line, a second gate signal GI having a gate-off voltage may be provided to the second gate line, a third gate signal GWB having a gate-on voltage may be provided to the third gate line, and a fourth gate signal EM having a gate-off voltage may be provided to the fourth gate line. A data voltage Vdata corresponding to the data signal may be provided to the data line.

[0091] The second transistor T2, the third transistor T3, the seventh transistor T7 and the eighth transistor T8 may be turned on by the first gate signal GW and the third gate signal GWB. In this case, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 may be turned off by the second gate signal GI and the fourth gate signal EM having the gate-off voltage.

[0092] When the second transistor T2 is turned on by the first gate signal GW, the data voltage Vdata corresponding to the data signal transmitted through the data line may be transmitted to the first node N1. When the eighth transistor T8 is turned on by the third gate signal GWB, the data voltage Vdata transmitted to the first node N1 connected to the first terminal of the eighth transistor T8 may be provided to the first terminal of the first transistor T1.

[0093] During the second period P12, when the second transistor T2 and the eighth transistor T8 are turned on simultaneously (e.g., synchronously), the voltage levels of the first node N1 and the second node N2 may have the same voltage level as the data voltage Vdata. After the second period P12, when the second transistor T2 and the eighth transistor T8 are turned off by the gate-off voltage of the first gate signal GW and the third gate signal GWB, the voltage level of the first node N1 may ideally be the same voltage level as the voltage in the second period P12, but due to the leakage current of the second transistor T2, may be a voltage level lower than the voltage level of the data voltage Vdata (e.g., Vdata' mentioned above). This will be described later.

[0094] When the third transistor T3 is turned on by the first gate signal GW, the drain of the first transistor T1 and the gate of the first transistor T1 may be coupled, and thus, the first transistor T1 may be in a diode connection state, and the voltage of the second terminal of the first transistor T1 (i.e., the drain voltage (Vd)) may be the gate voltage of the first transistor T1. A voltage obtained by compensating the data voltage Vdata (which is a voltage applied to the first terminal (i.e., the source) of the first transistor T1) by the threshold voltage (Vth) of the first transistor T1 (i.e., Vdata+Vth (where Vdata is the voltage of the second node N2, and Vth is the threshold voltage of the first transistor T1)) may be applied to the gate of the first transistor T1, and a voltage corresponding to Vdata+Vth may be stored in the storage capacitor Cst.

[0095] When the seventh transistor T7 is turned on by the first gate signal GW, the initialization voltage Vint supplied to the initialization voltage line connected to the second terminal of the seventh transistor T7 can be supplied to the pixel electrode of the light emitting diode ED connected to the first terminal of the seventh transistor T7, and the light emitting diode ED can be initialized by the initialization voltage Vint.

[0096] The delay period DP1 may be a period in which the first gate signal GW, the second gate signal GI, the third gate signal GWB, and the fourth gate signal EM all have a gate-off voltage. By increasing the delay period DP1 (in which all of the first gate signal GW, the second gate signal GI, the third gate signal GWB, and the fourth gate signal EM have a gate-off voltage), after the data write period (which is the second period P12), all transistors in the pixel circuit may be turned off, and by reducing interference from adjacent pixels PX, the data voltage Vdata corresponding to the data signal may be stabilized at a specific level. By increasing the delay period DP1, the data voltage Vdata may be more accurately written to the first transistor T1, and therefore, the pixel PX may emit light with less loss by the data voltage Vdata according to the RGB colors in the emission period EP.

[0097] When the first gate signal GW has a gate-off voltage in the delay period DP1 and thus the second transistor T2 is turned off, when a leakage current is generated by the degraded second transistor T2, the voltage level of the first node N1 may be a voltage level (Vdata') lower than the voltage level of the data voltage Vdata. In this case, the source voltage of the eighth transistor T8 may be Vdata', which is the voltage of the first node N1. Therefore, the gate-source voltage (V GS (T8)) is V when the eighth transistor T8 is turned off GH-Vdata' (where V GH is the gate high voltage of the eighth transistor T8, and Vdata′ is the source voltage of the eighth transistor T8), and is greater than the gate-source voltage (V GS (T2)), and thus the eighth transistor T8 can be reliably turned off, and the leakage current of the eighth transistor T8 can be reduced (blocked). The pixel PX according to one or more embodiments includes the second transistor T2 and the eighth transistor T8 connected in series to the second transistor T2 between the data line and the first terminal of the first transistor T1, and thus the turn-off efficiency can be higher than the turn-off efficiency when the second transistor T2 is directly connected to the first transistor T1.

[0098] The emission period EP may be a period during which the light emitting diode ED emits light. During the emission period EP, a fourth gate signal EM having a gate-on voltage may be provided to a fourth gate line. A first gate signal GW having a gate-off voltage may be provided to a first gate line, a second gate signal GI having a gate-off voltage may be provided to a second gate line, and a third gate signal GWB having a gate-off voltage may be provided to a third gate line. In this case, the fourth gate signal EM may be an emission control signal.

[0099] The second transistor T2, the third transistor T3 and the seventh transistor T7 can be turned off by the first gate signal GW, the fourth transistor T4 can be turned off by the second gate signal GI, and the eighth transistor T8 can be turned off by the third gate signal GWB. The fifth transistor T5 and the sixth transistor T6 can be turned on by the fourth gate signal EM.

[0100] When the fifth transistor T5 and the sixth transistor T6 are turned on, a current path for the driving current Id to flow from the driving voltage line to the light emitting diode ED can be formed. The first driving voltage VDD can be provided to the first terminal of the first transistor T1 by the turned-on fifth transistor T5, and the turned-on first transistor T1 can output the driving current (Id∝(V GS (T1)-Vth) 2 ), the magnitude of the driving current corresponds to the gate-source voltage (V GS The voltage (V) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the threshold voltage (Vth) of the first transistor T1 GS (T1)-Vth), and the light emitting diode ED can emit light with brightness corresponding to the amount of the driving current Id, and the amount of the driving current Id is independent of the threshold voltage (Vth) of the first transistor T1.

[0101] Figure 4is a timing diagram illustrating a method of preventing current leakage by adjusting a driving timing of an eighth transistor of a pixel circuit according to one or more embodiments.

[0102] refer to Figure 4 , the second transistor T2, the third transistor T3 and the seventh transistor T7 can be turned on by the gate-on voltage of the first gate signal GW in the second period P12 of the non-emission period NEP. In addition, the eighth transistor T8 can be turned on by the gate-on voltage of the third gate signal GWB. The second period P12 can be approximately one horizontal period 1H.

[0103] In one or more embodiments, the first gate signal GW and the third gate signal GWB may be gate signals transmitted along different gate lines. For example, the first gate signal GW may be a gate signal transmitted by the first gate line, and the third gate signal GWB may be a gate signal transmitted by the third gate line. The first gate signal GW transmitted by the first gate line and the third gate signal GWB transmitted by the third gate line may be provided as a gate-on voltage and a gate-off voltage at different timings.

[0104] refer to Figure 4 , the timing of the third gate signal GWB changing from the gate-on voltage to the gate-off voltage may be earlier than the timing of the first gate signal GW changing from the gate-on voltage to the gate-off voltage by Δt. For example, when the first gate signal GW maintains the gate-on voltage within a horizontal period of 1H, the third gate signal GWB may maintain the gate-on voltage within a horizontal period of (1-Δt)H shorter than the horizontal period of 1H by Δt, and transition to the gate-off voltage. When the third gate signal GWB transitions to the gate-off voltage before the first gate signal GW, the eighth transistor T8 may be turned off before the second transistor T2. When the eighth transistor T8 is turned off, the leakage current of the second transistor T2 may not flow to the first transistor T1 immediately, and the eighth transistor T8 may prevent the leakage current generated in the second transistor T2 from flowing into the first transistor T1. The pixel PX according to one or more embodiments includes a second transistor T2, and an eighth transistor T8 connected in series to the second transistor T2 between the data line and the first terminal of the first transistor T1, and therefore, the cut-off efficiency may be higher than the cut-off efficiency when the second transistor T2 is directly connected to the first transistor T1.

[0105] Figure 5 is an equivalent circuit diagram of a pixel included in a display device according to one or more embodiments.

[0106] refer to Figure 5, the pixel PX is a display element (i.e., a light emitting device) and may include a light emitting diode ED and a pixel circuit connected to the light emitting diode ED. In one or more embodiments, the light emitting diode ED may be an OLED. The pixel PX may emit, for example, red light, green light, blue light, and / or white light through the light emitting diode ED. In one or more embodiments, the pixel circuit may include a first transistor T1 to an eighth transistor T8 and a storage capacitor Cst.

[0107] The first transistor T1 may be a driving transistor configured to output a driving current Id corresponding to a data signal, and the second transistor T2 to the eighth transistor T8 may be a switching transistor configured to transmit a signal. The first terminal (e.g., the first electrode) of each of the first transistor T1 to the eighth transistor T8 may be a source or a drain, and the second terminal (e.g., the second electrode) of each of the first transistor T1 to the eighth transistor T8 may be a terminal different from the first terminal. For example, when the first terminal is a source, the second terminal may be a drain.

[0108] In one or more embodiments, the node to which the first transistor T1 and the sixth transistor T6 are connected may be defined as a third node N3, the node to which the sixth transistor T6 and the eighth transistor T8 are connected may be defined as a fourth node N4, the node to which the eighth transistor T8 and the light emitting diode ED are connected may be defined as a fifth node N5, and the node to which the gate of the first transistor T1 and the third transistor T3 are connected may be defined as a gate node G.

[0109] Figure 5 The position of the eighth transistor T8 in the pixel PX shown is different from Figure 2 The position of the eighth transistor T8 in the pixel PX is shown in FIG. Figure 2 The pixel PX has the same configuration as described in detail, and this description will focus on the differences.

[0110] exist Figure 5In the embodiment, the pixel PX can be connected to a first gate line configured to transmit a first gate signal GW, a second gate line configured to transmit a second gate signal GI, a fourth gate line configured to transmit a fourth gate signal EM, and a fifth gate line configured to transmit a fifth gate signal EMB. In one or more embodiments, the fourth gate signal EM and the fifth gate signal EMB can be referred to as emission control signals, and the fourth gate line and the fifth gate line can be referred to as emission control lines. In addition, the pixel PX can be connected to a driving voltage line configured to transmit a first driving voltage VDD, an initialization voltage line configured to transmit an initialization voltage Vint, and a data line configured to transmit a data voltage Vdata. The first gate signal GW, the second gate signal GI, the third gate signal GWB, the fourth gate signal EM, and the fifth gate signal EMB can be transmitted from Figure 1 The gate drive circuit 12 is provided to Figure 1 The pixel unit 11 in FIG.

[0111] The first transistor T1 may be connected between the fifth transistor T5 and the sixth transistor T6. In addition, the first transistor T1 may be connected between the second transistor T2 and the third transistor T3. The first transistor T1 may include a gate, a first terminal, and a second terminal connected to the third node N3. The first terminal of the first transistor T1 may be connected to a driving voltage line through which a first driving voltage VDD is provided via the fifth transistor T5, and the second terminal of the first transistor T1 may be connected to a pixel electrode (e.g., an anode) of the light emitting diode ED via the sixth transistor T6 and the eighth transistor T8. The first transistor T1 may be configured to receive a data voltage Vdata through a data line according to a switching operation of the second transistor T2, and control the amount of a driving current Id flowing to the light emitting diode ED.

[0112] The second transistor T2 may be connected between the first transistor T1 and a data line providing a data voltage Vdata. The second transistor T2 may include a gate connected to the first gate line, a first terminal connected to the data line, and a second terminal connected to the first transistor T1. The second transistor T2 may be configured to be turned on in response to a first gate signal GW transmitted through the first gate line, and electrically connect the data line to the first terminal of the first transistor T1, and transmit a data voltage Vdata corresponding to a data signal transmitted through the data line to the first transistor T1.

[0113] The third transistor T3 may be connected between the second terminal of the first transistor T1 and the gate of the first transistor T1. In addition, the third transistor T3 may be connected between the fourth transistor T4 and the sixth transistor T6. The third transistor T3 may include a gate connected to the first gate line, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the gate node G and the storage capacitor Cst. In one or more embodiments, the third transistor T3 may be configured to be turned on in response to a first gate signal GW transmitted via the first gate line to connect the second terminal of the first transistor T1 to the gate of the first transistor T1 (e.g., causing the first transistor T1 to be diode-connected).

[0114] The fourth transistor T4 may be connected between the gate of the first transistor T1 and the initialization voltage line. The fourth transistor T4 may include a gate connected to the second gate line, a first terminal connected to the gate node G, and a second terminal connected to the initialization voltage line. The fourth transistor T4 may be configured to be turned on in response to a second gate signal GI transmitted through the second gate line, and to provide an initialization voltage Vint transmitted through the initialization voltage line to the gate node G.

[0115] The fifth transistor T5 may be connected between the first terminal of the first transistor T1 and a driving voltage line through which the first driving voltage VDD is provided. The fifth transistor T5 may include a gate connected to the fourth gate line, a first terminal connected to the driving voltage line, and a second terminal connected to the first transistor T1. The fifth transistor T5 may be configured to be turned on in response to a fourth gate signal EM transmitted through the fourth gate line, and transmit the first driving voltage VDD to the first terminal of the first transistor T1.

[0116] The sixth transistor T6 may be connected between the second terminal of the first transistor T1 and the eighth transistor T8. In addition, the sixth transistor T6 may be connected between the third transistor T3 and the eighth transistor T8. The sixth transistor T6 may include a gate connected to the fourth gate line, a first terminal connected to the second terminal of the first transistor T1, and a second terminal connected to the fourth node N4. The sixth transistor T6 may be configured to be turned on in response to a fourth gate signal EM transmitted through the fourth gate line, and provide the driving current Id output by the first transistor T1 to the light emitting diode ED via the eighth transistor T8.

[0117] The seventh transistor T7 may be connected between the light emitting diode ED and the initialization voltage line. The seventh transistor T7 may include a gate connected to the first gate line, a first terminal connected to the fifth node N5, and a second terminal connected to the initialization voltage line. The seventh transistor T7 may be configured to be turned on in response to the first gate signal GW transmitted through the first gate line, and provide the initialization voltage Vint to the pixel electrode (anode) of the light emitting diode ED. In another embodiment, the gate of the seventh transistor T7 may be connected to the second gate line transmitting the second gate signal GI, but may have a different driving timing from the driving timing of the second gate line connected to the gate of the fourth transistor T4. For example, for the pixel PX in the nth row, the gate of the fourth transistor T4 may be connected to the nth second gate line, the nth second gate signal may be received from the nth second gate line, the gate of the seventh transistor T7 may be connected to the n+1th second gate line, and the n+1th second gate signal may be received from the n+1th second gate line.

[0118] The eighth transistor T8 may be connected between the sixth transistor T6 and the light emitting diode ED. The eighth transistor T8 may include a gate connected to the fifth gate line, a first terminal connected to the fourth node N4, and a second terminal connected to the fifth node N5 and the pixel electrode of the light emitting diode ED. The eighth transistor T8 may be configured to be turned on in response to a fifth gate signal EMB transmitted through the fifth gate line, and to provide the driving current Id provided by the sixth transistor T6 to the light emitting diode ED. In one or more embodiments, the gate of the eighth transistor T8 may be connected to the fourth gate line and receive the fourth gate signal EM from the fourth gate line.

[0119] In one or more embodiments, when the fifth transistor T5 and the sixth transistor T6 are turned off by the fourth gate signal EM, the voltage (V 4 ) can be lower than the voltage of the second node N2 (V 2 ) and / or the voltage of the third node N3 (V 3 When the eighth transistor T8 is connected to the second terminal of the sixth transistor T6, the gate-source voltage (V GS (T8)) can be V GH -V 4 (Wherein, V GH is the gate high voltage of the eighth transistor T8, and V 4 When the eighth transistor T8 is not connected to the sixth transistor T6 and the sixth transistor T6 is directly connected to the light emitting diode ED, the gate-source voltage (V GS (T6)) can be VGH -V 3 (Wherein, V GH is the gate high voltage of the sixth transistor T6, and V 3 is the source voltage of the sixth transistor T6). Because V 3 >V 4 , so the gate-source voltage (V GS (T8)) is greater than the gate-source voltage (V GS (T6)), and therefore, when the eighth transistor T8 is connected to the sixth transistor T6, the cut-off efficiency can be higher than the cut-off efficiency when the eighth transistor T8 is not connected to the sixth transistor T6. When the cut-off efficiency of the switching transistor is high, the leakage current blocking efficiency is high.

[0120] The storage capacitor Cst may be connected between the driving voltage line and the gate of the first transistor T1. A first electrode of the storage capacitor Cst may be connected to the driving voltage line, and a second electrode of the storage capacitor Cst may be connected to the gate node G. The storage capacitor Cst may store a threshold voltage of the first transistor T1 and a voltage corresponding to a data signal.

[0121] The light emitting diode ED may be connected to the eighth transistor T8. The light emitting diode ED may include a pixel electrode (e.g., an anode) connected to the second terminal of the eighth transistor T8 and an opposing electrode (e.g., a cathode) facing the pixel electrode, and the second driving voltage VSS may be provided to the opposing electrode. The opposing electrode may be a common electrode shared by a plurality of pixels PX.

[0122] Figure 6 is a diagram showing a method according to one or more embodiments Figure 5 2 is a timing diagram of the driving signals of the pixel circuit shown.

[0123] The pixel PX may display an image for each frame period. One frame period may include a non-emission period NEP in which the pixel PX does not emit light and an emission period EP in which the pixel PX emits light. The non-emission period NEP may include a first period P21, a second period P22, and a delay period DP2.

[0124] The first gate signal GW, the second gate signal GI, the fourth gate signal EM, and the fifth gate signal EMB may have a high level voltage in some cycles and a low level voltage in some other cycles, respectively. In one or more embodiments, the high level voltage of each of the first gate signal GW, the second gate signal GI, the fourth gate signal EM, and the fifth gate signal EMB may be a gate-off voltage that turns off the transistor, and the low level voltage of each of the first gate signal GW, the second gate signal GI, the fourth gate signal EM, and the fifth gate signal EMB may be a gate-on voltage that turns on the transistor.

[0125] The first period P21 may be an initialization period for initializing the gate of the first transistor T1. The first period P21 may be approximately one horizontal period 1H.

[0126] In the first period P21, a first gate signal GW having a gate-off voltage may be provided to the first gate line, a second gate signal GI having a gate-on voltage may be provided to the second gate line, a fourth gate signal EM having a gate-off voltage may be provided to the fourth gate line, and a fifth gate signal EMB having a gate-off voltage may be provided to the fifth gate line. An initialization voltage Vint may be provided through the initialization voltage line. When the initialization voltage Vint is provided, the gate of the first transistor T1 may be initialized.

[0127] The fourth transistor T4 may be turned on in response to the second gate signal GI. The initialization voltage Vint may be transmitted to the gate node G, ie, the gate of the first transistor T1, through the turned-on fourth transistor T4. In the first period P21, the voltage of the gate node G may be initialized to the initialization voltage Vint.

[0128] The second period P22 may be a writing and compensation period, in which the data voltage Vdata is transferred to the gate of the first transistor T1 (e.g., because the first transistor T1 is diode-connected during the second period P22) and the threshold voltage of the first transistor T1 is compensated. The second period P22 may be approximately one horizontal period 1H.

[0129] In the second period P22, a first gate signal GW having a gate-on voltage may be provided to the first gate line, a second gate signal GI having a gate-off voltage may be provided to the second gate line, a fourth gate signal EM having a gate-off voltage may be provided to the fourth gate line, and a fifth gate signal EMB having a gate-off voltage may be provided to the fifth gate line. A data voltage Vdata corresponding to the data signal may be provided to the data line.

[0130] The second transistor T2, the third transistor T3 and the seventh transistor T7 may be turned on by the first gate signal GW. In this case, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 may be turned off by the second gate signal GI having a gate-off voltage, the fourth gate signal EM and the fifth gate signal EMB.

[0131] When the second transistor T2 is turned on by the first gate signal GW, a data voltage Vdata corresponding to a data signal transmitted through the data line may be provided to the first terminal of the first transistor T1 .

[0132] When the third transistor T3 is turned on by the first gate signal GW, the drain of the first transistor T1 and the gate of the first transistor T1 may be coupled, and thus, the first transistor T1 may be in a diode connection state, and the voltage of the second terminal of the first transistor T1 (i.e., the drain voltage (Vd)) may be the gate voltage of the first transistor T1. A voltage obtained by compensating the data voltage Vdata (which is a voltage applied to the first terminal (i.e., the source) of the first transistor T1) with the threshold voltage (Vth) of the first transistor T1 (i.e., Vdata+Vth (where Vdata is the voltage of the second node N2, and Vth is the threshold voltage of the first transistor T1)) may be applied to the gate of the first transistor T1, and a voltage corresponding to Vdata+Vth may be stored in the storage capacitor Cst.

[0133] When the seventh transistor T7 is turned on by the first gate signal GW, the initialization voltage Vint supplied to the initialization voltage line connected to the second terminal of the seventh transistor T7 can be supplied to the pixel electrode of the light emitting diode ED connected to the first terminal of the seventh transistor T7, and the light emitting diode ED can be initialized by the initialization voltage Vint.

[0134] The delay period DP2 may be a period in which the first gate signal GW, the second gate signal GI, the fourth gate signal EM, and the fifth gate signal EMB all have a gate cut-off voltage. By increasing the delay period DP2 (wherein all of the first gate signal GW, the second gate signal GI, the fourth gate signal EM, and the fifth gate signal EMB have a gate cut-off voltage), after the data write period (which is the second period P22), all transistors in the pixel circuit may be turned off, and by reducing interference from adjacent pixels PX, the data voltage Vdata corresponding to the data signal may be stabilized at a specific level. By increasing the delay period DP2, the data voltage Vdata may be more accurately written to the first transistor T1, and therefore, the pixel PX may emit light with less loss by the data voltage Vdata according to the RGB color in the emission period EP.

[0135] In one or more embodiments, during the non-emission period NEP, the fifth transistor T5 and the sixth transistor T6 may be turned off by the fourth gate signal EM, and the eighth transistor T8 may be turned off by the fifth gate signal EMB. When the leakage current is generated by the degraded sixth transistor T6, the voltage (V 4 ) can be lower than the voltage (V 3 ). When the voltage of the fourth node N4 (V 4 ) is lower than the voltage (V 3 ), the source voltage of the eighth transistor T8 can be lower than the source voltage when no leakage current occurs in the sixth transistor T6. Therefore, the gate-source voltage (V GS (T8)) is V when the eighth transistor T8 is turned off GH -V 4 (Wherein, V GH is the gate high voltage of the eighth transistor T8, and V 4 is the source voltage of the eighth transistor T8), and is greater than the gate-source voltage (V GS (T6)), where the gate-source voltage (V GS (T6)) is V GH -V 3 (Wherein, V GH is the gate high voltage of the sixth transistor T6, and V 3 is the source voltage of the sixth transistor T6). Therefore, the eighth transistor T8 can be reliably turned off, and the leakage current of the sixth transistor T6 can be prevented from flowing into the light emitting diode ED. The pixel PX according to one or more embodiments includes the sixth transistor T6, and the eighth transistor T8 connected in series to the sixth transistor T6 between the light emitting diode ED and the second terminal of the first transistor T1, and therefore, the turn-off efficiency can be higher than the turn-off efficiency when the sixth transistor T6 is directly connected to the light emitting diode ED.

[0136] The emission period EP may be a period during which the light emitting diode ED emits light. During the emission period EP, a fourth gate signal EM having a gate-on voltage may be provided to a fourth gate line. A first gate signal GW having a gate-off voltage may be provided to a first gate line, and a second gate signal GI having a gate-off voltage may be provided to a second gate line. A fourth gate signal EM having a gate-on voltage may be provided to a fourth gate line, and a fifth gate signal EMB having a gate-on voltage may be provided to a fifth gate line.

[0137] In the emission period EP, the second transistor T2, the third transistor T3 and the seventh transistor T7 can be turned off by the first gate signal GW, the fourth transistor T4 can be turned off by the second gate signal GI, the fifth transistor T5 and the sixth transistor T6 can be turned on by the fourth gate signal EM, and the eighth transistor T8 can be turned on by the fifth gate signal EMB.

[0138] When the fifth transistor T5, the sixth transistor T6 and the eighth transistor T8 are turned on, a current path for the driving current Id to flow from the driving voltage line to the light emitting diode ED can be formed. The first driving voltage VDD can be provided to the first terminal of the first transistor T1 through the turned-on fifth transistor T5, and the turned-on first transistor T1 can output the first driving current (Id 1 ∝(V GS (T1)-Vth) 2 ), the magnitude of the first driving current corresponds to the gate-source voltage (V GS The voltage (V) obtained by subtracting the threshold voltage (Vth) of the first transistor T1 from the threshold voltage (Vth) of the first transistor T1 GS (T1)-Vth), and the light emitting diode ED can emit a first driving current Id 1 The magnitude of the first driving current Id corresponds to the brightness of the light. 1 The size of is independent of the threshold voltage (Vth) of the first transistor T1.

[0139] Figure 7 is a diagram illustrating a method of preventing current leakage by adjusting a driving timing of an eighth transistor of a pixel circuit according to one or more embodiments.

[0140] refer to Figure 7 In the non-emission period NEP, the fifth transistor T5 and the sixth transistor T6 may be turned off by the gate-off voltage of the fourth gate signal EM. In addition, the eighth transistor T8 may be turned off by the gate-off voltage of the fifth gate signal EMB.

[0141] In one or more embodiments, the fourth gate signal EM and the fifth gate signal EMB may be gate signals transmitted along different gate lines. For example, the fourth gate signal EM may be a gate signal transmitted by the fourth gate line, and the fifth gate signal EMB may be a gate signal transmitted by the fifth gate line. The fourth gate signal EM transmitted by the fourth gate line and the fifth gate signal EMB transmitted by the fifth gate line may be provided as a gate-on voltage and a gate-off voltage at different timings.

[0142] refer to Figure 7, the timing of the fifth gate signal EMB changing from the gate-on voltage to the gate-off voltage may be earlier than the timing of the fourth gate signal EM changing from the gate-on voltage to the gate-off voltage by Δt. For example, when the fifth gate signal EMB changes to the gate-off voltage earlier than the fourth gate signal EM by Δt, while the fourth gate signal EM maintains the gate-off voltage within four horizontal periods 4H, the fifth gate signal EMB may maintain the gate-off voltage within a horizontal period (4+Δt)H longer than the four horizontal periods 4H by Δt, and may change to the gate-on voltage. When the fifth gate signal EMB changes to the gate-off voltage before the fourth gate signal EM, the eighth transistor T8 may be turned off before the sixth transistor T6. When the eighth transistor T8 is turned off first, the leakage current of the sixth transistor T6 may not immediately flow to the light emitting diode ED, and the eighth transistor T8 may block the leakage current generated in the sixth transistor T6.

[0143] Fig. 8A is a diagram for explaining turning on and off of a P-type transistor according to a gate voltage of the P-type transistor according to one or more embodiments, and Figure 8B is a graph for explaining an amount of leakage current according to a threshold voltage of a P-type transistor according to one or more embodiments.

[0144] refer to Fig. 8A , the threshold voltage V of the P-type transistor th can be a negative voltage value. Therefore, when the gate-source voltage V GS The magnitude (e.g., absolute value) of is greater than or equal to the threshold voltage V th , the P-type transistor can be turned on, and a channel can be formed between the source and drain of the P-type transistor, and thus a current I can flow. On the other hand, when the gate-source voltage V GS The magnitude (e.g., absolute value) of is less than the threshold voltage V th When the threshold voltage V of the P-type transistor is 100V, the current I may not flow into the P-type transistor when the P-type transistor is turned off. However, even when the P-type transistor is turned off, the leakage current may flow through the P-type transistor. th When the magnitude of is reduced due to degradation (ie, it may mean that the threshold voltage V th Increase but the threshold voltage V th The amount of leakage current can increase as the absolute value of Figure 8B , the threshold voltage V of the transistor shown by curve 82 th2 is greater than the threshold voltage V of the transistor shown by curve 81 th1 , and because the threshold voltage V th has a negative value, so the threshold voltage V of the transistor shown in curve 81th1 The absolute value of |V th1 | is greater than the threshold voltage V of the transistor shown by curve 82 th2 The absolute value of |V th2 |, that is, |V th1 |>|V th2 |. Therefore, because the threshold voltage V of the transistor shown in curve 82 th2 is greater than the threshold voltage V of the transistor shown by curve 81 th1 , so the amount of leakage current of the transistor shown by curve 82 is I 2 The amount of leakage current I of the transistor shown by curve 81 may be greater than 1 Therefore, the gate-source voltage V of a P-type transistor with a negative voltage value GS The higher the gate-source voltage V GS The lower the magnitude (e.g., absolute value) of the threshold voltage, and therefore, substantially the same effect as increasing the magnitude (e.g., absolute value) of the threshold voltage can be achieved, and the cutoff efficiency can be increased and the amount of leakage current can be reduced.

[0145] In one or more embodiments, in order to prevent the loss of the data voltage Vdata transmitted to the first transistor T1 (which is a driving transistor), which is caused by the leakage current of the transistor, the pixel PX may include a transistor (e.g., a transistor connected in series with the second transistor T2) between the data line and the first terminal of the first transistor T1. Figure 2 When the second transistor T2 is turned off, the voltage of the second terminal of the second transistor T2 decreases due to the leakage current, and therefore, the gate-source voltage (V GS (T8)) increases. Therefore, the cut-off efficiency of the eighth transistor T8 can be improved, and the cut-off of the eighth transistor T8 can be reliably ensured. Therefore, the reduction of the first terminal voltage of the first transistor T1 due to the leakage current of the second transistor T2 can be prevented.

[0146] In one or more embodiments, in order to prevent micro-emission of light from the light emitting diode ED due to leakage current transmitted to the light emitting diode ED in the non-emission period NEP, the pixel PX may include a transistor ( 100 ) connected in series with the sixth transistor T6 between the second terminal of the first transistor T1 and the light emitting diode ED. Figure 5 When the sixth transistor T6 is turned off, the voltage of the second terminal of the sixth transistor T6 decreases due to the leakage current, and therefore, the gate-source voltage (V GS(T8)) increases. Therefore, the cut-off efficiency of the eighth transistor T8 can be improved, and the cut-off of the eighth transistor T8 can be reliably guaranteed. Therefore, the leakage current of the sixth transistor T6 can be prevented from flowing into the pixel electrode of the light emitting diode ED.

[0147] The operation of the method or algorithm described in conjunction with the embodiments of the present disclosure may be implemented directly as hardware, as a software module executed by hardware, or a combination thereof. The software module may be a random access memory (RAM), a read-only memory (ROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a hard disk, a removable disk, a CD-ROM, or may reside on any type of computer-readable recording medium known in the technical field to which the present disclosure belongs.

[0148] The display device according to some embodiments of the present disclosure can be a device for displaying a video or a static image, and can provide information to the user visually. The display device is used as a display screen of various electronic devices such as televisions, notebook computers, monitors, broadcast panels, and Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). In addition, the display device according to the embodiment can be used for wearable electronic devices such as smart watches, watch phones, glasses-type displays, and head-mounted displays (HMDs). In addition, the display device according to the embodiment can be used as an electronic device such as a central information display (CID) on the dashboard of a vehicle or a central instrument panel or dashboard of a vehicle, an interior mirror display instead of a side mirror of a vehicle, or a display arranged on the rear surface of a front seat as an entertainment device for the rear seat of a vehicle. In addition, the display device can be a flexible device.

[0149] According to means for solving the above-mentioned object of the present disclosure, a display device with improved image quality can be provided by preventing a data voltage written from a data voltage line from being lowered due to a leakage current of a switching transistor.

[0150] The effects, aspects, and features of the embodiments of the present disclosure are not limited to the above-described effects, aspects, and features, and other effects, aspects, and features not mentioned herein can be clearly understood by those skilled in the art from the above description.

[0151] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should generally be considered to be applicable to other similar features or aspects in other embodiments. Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope defined by the appended claims.

Claims

1. Pixels, including: a first transistor configured to output a driving current corresponding to the amplitude of the data voltage; a second transistor connected to the data line; a third transistor connected between the second terminal of the first transistor and the gate of the first transistor; a fourth transistor connected between the first terminal of the first transistor and a driving voltage line; a fifth transistor connected to the second terminal of the first transistor; a sixth transistor connected between the first terminal of the first transistor and the second transistor; a light emitting diode connected to the fifth transistor; as well as A storage capacitor is connected between the gate of the first transistor and the driving voltage line. 2 . The pixel of claim 1 , further comprising a seventh transistor connected between the third transistor and an initialization voltage line. 3 . The pixel of claim 2 , further comprising an eighth transistor connected between the fifth transistor and the initialization voltage line.

4. The pixel according to claim 3, wherein: The pixels operate in non-emitting periods and emitting periods during a frame period, Wherein, the non-transmission period includes: a first period, in which the seventh transistor is turned on, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the eighth transistor are turned off, and an initialization voltage is applied from the initialization voltage line to the gate of the first transistor; and The second cycle, in which the second transistor, the third transistor, the sixth transistor and the eighth transistor are turned on, the fourth transistor, the fifth transistor and the seventh transistor are turned off, a data signal is applied from the data line to the gate of the first transistor, and the initialization voltage is applied from the initialization voltage line to the first terminal of the light-emitting diode.

5. The pixel according to claim 4, wherein: In the second period, a data voltage corresponding to the data signal applied to the first transistor and a threshold voltage of the first transistor are stored in the storage capacitor.

6. The pixel according to claim 4, wherein: The fourth transistor and the fifth transistor are turned on during the emission period.

7. The pixel according to claim 6, wherein: The non-emission period also includes a delay period between the second period and the emission period, during which the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are turned off.

8. The pixel according to claim 7, wherein: In the second period, the second transistor and the third transistor are controlled by a first gate signal, the eighth transistor is controlled by a second gate signal, and the sixth transistor is controlled by a third gate signal.

9. The pixel according to claim 8, wherein: The timing at which the third gate signal changes from the gate-on voltage to the gate-off voltage and the sixth transistor is turned off is before the timing at which the first gate signal changes from the gate-on voltage to the gate-off voltage and the second transistor is turned off.

10. The pixel according to claim 7, wherein: During the delay period, a gate-source voltage of the turned-off sixth transistor is greater than a gate-source voltage of the turned-off second transistor.

11. Pixels, including: a first transistor configured to output a driving current corresponding to the amplitude of the data voltage; a second transistor connected between the first terminal of the first transistor and the data line; a third transistor connected between the second terminal of the first transistor and the gate of the first transistor; a fourth transistor connected between the first terminal of the first transistor and a driving voltage line; a fifth transistor connected to the second terminal of the first transistor; a sixth transistor connected between the fifth transistor and the light emitting diode; The light emitting diode is connected to the sixth transistor; as well as A storage capacitor is connected between the gate of the first transistor and the driving voltage line. 12 . The pixel of claim 11 , further comprising a seventh transistor connected between the third transistor and an initialization voltage line. 13 . The pixel of claim 12 , further comprising an eighth transistor connected between the sixth transistor and the initialization voltage line.

14. The pixel according to claim 13, wherein: The pixels operate in non-emitting periods and emitting periods during a frame period, Wherein, the non-transmission period includes: a first cycle, in which the seventh transistor is turned on, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor and the eighth transistor are turned off, and applying an initialization voltage from the initialization voltage line to the gate of the first transistor; and a second cycle, in which the second transistor, the third transistor and the eighth transistor are turned on, the fourth transistor, the fifth transistor, the sixth transistor and the seventh transistor are turned off, a data signal is applied from the data line to the gate of the first transistor, and The initialization voltage is applied from the initialization voltage line to the first terminal of the light emitting diode.

15. The pixel according to claim 14, wherein: The fourth transistor, the fifth transistor, and the sixth transistor are turned on in the emission period.

16. The pixel according to claim 15, wherein: The non-emission period also includes a delay period between the second period and the emission period, during which the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are turned off.

17. The pixel according to claim 15, wherein: In the second period, the second transistor and the third transistor are controlled by a fourth gate signal, and the eighth transistor is controlled by a fifth gate signal.

18. The pixel according to claim 15, wherein: In the emission period, the fourth transistor and the fifth transistor are controlled by a sixth gate signal, and the sixth transistor is controlled by a seventh gate signal.

19. The pixel according to claim 18, wherein: The timing at which the seventh gate signal changes from the gate-on voltage to the gate-off voltage and the sixth transistor is turned off is before the timing at which the sixth gate signal changes from the gate-on voltage to the gate-off voltage and the fifth transistor is turned off.

20. The pixel according to claim 14, wherein: During the non-emission period, the fifth transistor and the sixth transistor are turned off, and a gate-source voltage of the turned-off sixth transistor is greater than a gate-source voltage of the turned-off fifth transistor.

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