Memory device, buffer chip, and method of operating memory device

Abstract

Provided is a storage device that simultaneously exchanges signals with at least one storage area, the memory device includes a memory controller configured to generate at least one of a chip enable signal and a command / address signal, a buffer chip configured to receive the chip enable signal, the command / address signal, and a data signal from the memory controller, and a memory device including at least one memory region configured to perform at least one of a write operation and a read operation based on a command / address signal and a data signal received by the buffer chip.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the priority benefit of Korean Patent Application No. 10-2023-0175934 filed in the Korean Intellectual Property Office on December 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a memory device, a buffer chip, a method of operating a memory device, and more particularly, to a memory device capable of simultaneously transmitting a command / address signal and a data signal to a plurality of memory areas included in the memory device. Background Art

[0004] Recently developed memory devices include a buffer chip having a channel for transmitting a data signal. The buffer chip operates as an interface connecting stacked memory areas of the memory device to realize a high-capacity memory.

[0005] In order to increase the integration of memory devices, multiple data channels are used to mediate the communication between data signals and command / address signals. Summary of the invention

[0006] As described above, in order to increase the integration of the storage device, multiple data channels are used to mediate the communication between the data signal and the command / address signal. However, there is no distinction between the channel for sending the command / address signal and the channel for sending the data signal. Therefore, in order to send the command / address signal, the buffer chip must temporarily stop the communication of the data signal, which may slow down the operation speed of the storage device.

[0007] Some example embodiments of the inventive concept provide a memory device including a memory controller configured to generate at least one of a chip enable signal and a command / address signal, a buffer chip configured to receive the chip enable signal, the command / address signal, and a data signal from the memory controller, and a memory device including at least one storage area, the at least one storage area being configured to perform at least one of a write operation and a read operation based on the command / address signal and the data signal received by the buffer chip. The buffer chip includes a first channel configured to receive the chip enable signal or the command / address signal, and a second channel configured to receive the data signal, wherein the first channel and the second channel can be configured to send signals received through separate paths to corresponding storage devices in at least one storage device.

[0008] Some example embodiments of the inventive concept provide a method of operating a storage device, the method including generating at least one of a chip enable signal and a command / address signal, receiving the chip enable signal, the command / address signal, and a data signal, and performing at least one of a write operation and a read operation based on the received command / address signal and the data signal. The receiving of the chip enable signal, the command / address signal, and the data signal includes receiving the chip enable signal or the command / address signal through a first channel, receiving the data signal through a second channel different from the first channel, and sending the received signal to a corresponding storage area in at least one storage area.

[0009] Some example embodiments of the inventive concept provide a buffer chip comprising a first channel configured to receive a chip enable signal or a command / address signal, and a second channel configured to receive a data signal, wherein the first channel and the second channel may also be configured to send signals received through separate paths to corresponding storage areas in at least one storage area. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Some example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a block diagram of a storage device according to an example embodiment;

[0012] Figure 2 is a block diagram of a buffer chip according to an example embodiment;

[0013] FIG. 3A to FIG. 3C is a circuit diagram of a memory device 100 according to an example embodiment;

[0014] Figure 4 is a schematic diagram illustrating signals received by a buffer chip according to an example embodiment;

[0015] Figure 5A is a block diagram of a memory device including a plurality of chips according to an example embodiment;

[0016] Figure 5B It shows that it can be Figure 5A A schematic diagram of a signal received by a buffer chip included in;

[0017] Figure 5C is a schematic diagram in which a plurality of chips of a storage device are activated by a plurality of chip enable signals;

[0018] Figure 5D is a schematic diagram in which a plurality of chips of a storage device are activated by a plurality of chip enable signals;

[0019] Figure 6 and Figure 7is a flowchart of a method of operating a storage device according to an example embodiment;

[0020] Figure 8 is a flowchart of a process for determining a storage area with which a first channel and a second channel communicate in a method of operating a storage device according to an example embodiment;

[0021] Fig. 9 is a flowchart of a process for controlling transmission of a command / address signal and a data signal in a method of operating a storage device according to an example embodiment;

[0022] Figures 10 to 12 is a schematic diagram illustrating a three-dimensional V-NAND structure that may be applied to a memory device according to example embodiments; and

[0023] Fig.13 is a block diagram of a storage system according to an example embodiment. DETAILED DESCRIPTION

[0024] In the following, various example embodiments are described with reference to the accompanying drawings. Details such as detailed configuration and structure are provided to help readers understand the following embodiments. Therefore, the example embodiments described herein can be changed or modified in various ways without departing from the concept of the present invention.

[0025] It should be understood that elements and / or their properties (e.g., structures, surfaces, directions, etc.) that may be referred to as "perpendicular", "parallel", etc., relative to other elements and / or their properties (e.g., structures, surfaces, directions, etc.) may be "perpendicular", "parallel", etc., respectively relative to other elements and / or their properties, or may be "substantially perpendicular", "substantially parallel".

[0026] Elements and / or their attributes (e.g., structures, surfaces, directions, etc.) that are “substantially perpendicular” relative to other elements and / or their attributes will be understood to be “perpendicular” relative to other elements and / or their attributes within manufacturing tolerances and / or material tolerances and / or having a magnitude and / or angular deviation of equal to or less than 10% from “perpendicular” relative to other elements and / or their attributes (e.g., a tolerance of ±10%).

[0027] Elements and / or their properties (e.g., structures, surfaces, directions, etc.) that are “substantially parallel” relative to other elements and / or their properties will be understood to be “parallel” relative to other elements and / or their properties within manufacturing tolerances and / or material tolerances and / or having a magnitude and / or angular deviation equal to or less than 10% from “parallel” relative to other elements and / or their properties (e.g., a tolerance of ±10%).

[0028] It should be understood that elements and / or attributes thereof may be described herein as being "identical" or "equal" to other elements, and it should also be understood that elements and / or attributes described herein as being "identical", "identical" or "equal" to other elements may be "identical", "identical" or "equal" or "substantially identical", "substantially identical" or "substantially equal" to other elements and / or attributes. Elements and / or attributes thereof that are "substantially identical", "substantially identical" or "substantially equal" to other elements and / or attributes thereof will be understood to include elements and / or attributes thereof that are identical, identical or equal to other elements and / or attributes thereof within manufacturing tolerances and / or material tolerances. Elements and / or attributes thereof that are identical or substantially identical and / or identical or substantially identical to other elements and / or attributes thereof may be identical or substantially identical in structure, identical or substantially identical in function, and / or identical or substantially identical in composition.

[0029] Figure 1 is a block diagram of a storage device 100 according to an example embodiment.

[0030] refer to Figure 1 , the storage device 100 according to the example embodiment may include a memory controller 110, a buffer chip 120, and a memory device 130. The storage device 100 according to the example embodiment may exchange signals with at least one storage area at the same time. For example, the storage device 100 may send a chip enable signal CE, a command / address signal CA, or a data signal DQ generated from the memory controller 110 to a storage area of ​​the memory device 130 through the buffer chip 120. In addition, the storage device 100 may send a data signal DQ, a chip enable signal CE, or a command / address signal CA, each read from at least one storage area of ​​the memory device 130, to the memory controller 110 through the buffer chip 120.

[0031] The memory controller 110 according to an example embodiment may generate a plurality of signals. For example, the memory controller 110 may generate at least one of a chip enable signal CE and a command / address signal CA for at least one storage area of ​​the memory device 130. The chip enable signal CE according to an example embodiment may be a signal that controls signal transmission of the buffer chip 120 to activate the command / address signal CA. The command / address signal CA according to an example embodiment may be a signal that specifies a storage area of ​​the memory device 130.

[0032] The memory controller 110 according to example embodiments may transmit the data signal DQ to the buffer chip 120. For example, the memory controller 110 may transmit the command / address signal CA to the buffer chip 120, and the buffer chip 120 may transmit the data signal DQ to a designated storage area based on a result of decoding the command / address signal CA. Figure 2 , Figure 3A , Figure 3B and Figure 3C The process of sending the data signal DQ is described in detail.

[0033] The buffer chip 120 according to an example embodiment may be configured to receive a chip enable signal CE, a command / address signal CA, and a data signal DQ from the memory controller 110. For example, the buffer chip 120 may be configured to include a first channel for receiving a chip enable signal CE or a command / address signal CA and a second channel for receiving a data signal DQ. The first channel according to an example embodiment may be a path for receiving a chip enable signal CE or a command / address signal CA. The second channel according to an example embodiment may be a path for receiving a data signal DQ. The first channel and the second channel according to an example embodiment may receive signals through separate paths, and may send the received signals to at least one storage area of ​​the memory device 130. For example, the first channel and the second channel may be physically separated paths for signal transmission, wherein the first channel may receive a chip enable signal CE or a command / address signal CA, and the second channel may receive a data signal DQ. The buffer chip 120 according to an example embodiment may simultaneously send signals received through the first channel and the second channel to the memory device 130.

[0034] The memory device 130 according to the example embodiment may include at least one storage area configured to perform at least one of a write operation and a read operation based on a command / address signal CA and a data signal DQ, each of which is received by the buffer chip 120. The memory device 130 according to the example embodiment may include a first storage area and a second storage area. For example, the memory device 130 may include a first storage area that receives the command / address signal CA and a second storage area that receives the data signal DQ. The first storage area or the second storage area according to the example embodiment may each be a memory die included in the memory device 130. However, the first storage area and the second storage area are classified according to the type of the received signal.

[0035] Figure 2 is a block diagram of a buffer chip 120 according to an example embodiment.

[0036] refer to Figure 1 and Figure 2 , the buffer chip 120 according to example embodiments may include a first channel 121 , a decoder 122 , and a second channel 123 .

[0037] The first channel 121 according to example embodiments may receive a chip enable signal CE or a command / address signal CA and may transmit the received command / address signal CA to the first storage area 131. The first storage area 131 according to example embodiments may be a storage area of ​​the memory device 130 communicating with the first channel 121. Figure 2 In the embodiment, the first storage area 131 may be a memory die included in the memory device 130, but a unit of the first storage area 131 is not limited thereto.

[0038] The first channel 121 according to example embodiments may be configured to transmit the command / address signal CA to a plurality of die included in the memory device 130. For example, in Figure 2 In the embodiment, the first channel 121 communicates with one storage area, but the disclosed buffer chip 120 is not limited thereto. For example, the buffer chip 120 may communicate with a plurality of storage areas of the memory device 130 through a plurality of paths connected to the first channel 121.

[0039] The buffer chip 120 according to an example embodiment may include at least one decoder 122. For example, since the first channel 121 includes the decoder 122, the buffer chip 120 may include the decoder 122. The decoder 122 according to an example embodiment may decode the command / address signal CA. The buffer chip 120 according to an example embodiment may determine a storage area with which the first channel 121 communicates based on a result of the decoder 122 decoding the command / address signal CA. For example, when the first channel 121 is activated by the chip enable signal CE, the decoder 122 may decode the command / address signal CA and determine the first storage area 131 based on the decoding result. The command / address signal CA according to an example embodiment may include information about a storage area to which the command / address signal CA is to be transmitted.

[0040] The buffer chip 120 according to an example embodiment may be configured to determine a storage area with which the second channel 123 communicates based on a result of decoding the command / address signal CA. The second channel 123 according to an example embodiment may transmit the data signal DQ to the second storage area 132 based on a result of decoding the command / address signal CA. For example, based on a result of decoding the command / address signal CA by the decoder 122, the buffer chip 120 may determine the first storage area 131 and the second storage area 132, and may determine the storage area to which the command / address signal CA is not transmitted as the second storage area 132. The command / address signal CA according to an example embodiment may include path information of the data signal DQ.

[0041] When the command / address signal CA is transmitted to the first storage area 131 through the first channel 121, the buffer chip 120 according to the example embodiment may be configured to transmit the data signal DQ with the second storage area 132 through the second channel 123. For example, the first channel 121 and the second channel 123 may be physically separated and simultaneously transmit a plurality of signals to the memory device 130. When the command / address signal CA is transmitted to the first storage area 131 through the first channel 121, the buffer chip 120 according to the example embodiment may transmit the data signal DQ to the second storage area 132 through the second channel 123, so that a write operation or a read operation is performed. In addition, when the data signal DQ is transmitted to the first storage area 131 through the first channel 121, the buffer chip 120 according to the example embodiment may transmit the command / address signal CA to the second storage area 132 through the second channel 123, so that a write operation or a read operation is performed.

[0042] FIG. 3A to FIG. 3C is a circuit diagram of a memory device 100 according to an example embodiment.

[0043] Figure 3A The memory device 100 is shown in which independent paths of the command / address signal CA of the buffer chip 120 according to example embodiments are connected to the first memory area 131 and the second memory area 132 , respectively.

[0044] refer to Figure 3A , the buffer chip 120 according to example embodiments may include a first channel 121 and a second channel 123, and the first channel 121 may include a first data path 121a, a first latch 121b, a first switch 121c, a second switch 121d, a second latch 121e, a third latch 121f, or a decoder 122.

[0045] The first data path 121 a according to example embodiments may be a path through which a chip enable signal CE and a command / address signal CA are transmitted.

[0046] The first latch 121b according to example embodiments may receive a command / address signal CA. For example, when the received command / address signal CA is activated, the first latch 121b may receive the command / address signal CA and may transmit the received command / address signal CA to the decoder 122.

[0047] The decoder 122 according to an example embodiment may decode the command / address signal CA activated by the chip enable signal CE, and may determine the path of the command / address signal CA and the path of the data signal DQ based on the decoding result. For example, the decoder 122 may decode the command / address signal CA, and may determine the first storage area 131 to which the command / address signal CA is transmitted and the second storage area 132 to which the data signal DQ is transmitted based on the decoding result. According to an example embodiment, the buffer chip 120 may control the operation of the first to fourth switches 121c, 121d, 123c, and 123d based on the decoding result.

[0048] The first switch 121c according to an example embodiment may control the transmission of the command / address signal CA. For example, when the first storage area 131 is determined as the area to which the command / address signal CA is transmitted based on the result of decoding the command / address signal CA by the decoder 122, the buffer chip 120 may transmit the command / address signal CA to the first storage area 131 by closing the first switch 121c. In some example embodiments, when the first switch 121c is closed, the path for transmitting the command / address signal CA to the first storage area 131 may be the selection path Sel.

[0049] The second switch 121d according to the example embodiment may control the transmission of the data signal DQ. For example, when the first storage area 131 is determined as an area to which the data signal DQ is not transmitted based on the decoding result of the decoder 122, the buffer chip 120 may not transmit the data signal DQ to the first storage area 131 by turning off the second switch 121d.

[0050] The second latch 121e according to the example embodiment may receive the command / address signal CA based on the result that the decoder 122 decodes the command / address signal CA, and may stably transmit the command / address signal CA to the first storage area 131. The third latch 121f according to the example embodiment may receive the data signal DQ based on the result that the decoder 122 decodes the command / address signal CA, and may stably transmit (or may transmit) the data signal DQ to the first storage area 131.

[0051] The second channel 123 according to example embodiments may include a second data path 123 a , a fourth latch 123 b , a third switch 123 c , a fourth switch 123 d , a fifth latch 123 e , or a sixth latch 123 f .

[0052] The second data path 123 a according to example embodiments may be a path through which a data signal DQ is transmitted.

[0053] The fourth latch 123b according to example embodiments may receive the data signal DQ. For example, when the region to which the data signal DQ is transmitted is determined to be the second storage region 132 based on the decoding result of the first channel 121, the fourth latch 123b may transmit the received data signal DQ to the second storage region 132.

[0054] The third switch 123c according to the example embodiment may control the transmission of the command / address signal CA. For example, in some example embodiments, when the second storage area 132 is determined as an area to which the command / address signal CA is not transmitted based on the decoding result of the decoder 122, the buffer chip 120 may not transmit the command / address signal CA to the second storage area 132 by turning off the third switch 123c.

[0055] The fourth switch 123d according to an example embodiment may control the transmission of the data signal DQ. For example, when the second storage area 132 is determined as the area to which the data signal DQ is transmitted based on the decoding result of the decoder 122 of the first channel 121, the buffer chip 120 may transmit the data signal DQ to the second storage area 132 by closing the fourth switch 123d. In some example embodiments, when the fourth switch 123d is closed, the path for transmitting the data signal DQ to the second storage area 132 may be the selection path Sel.

[0056] The fifth latch 123e according to the example embodiment may receive the command / address signal CA based on the result that the decoder 122 decodes the command / address signal CA, and may stably transmit (or may transmit) the command / address signal CA to the second storage area 132. The sixth latch 123f according to the example embodiment may receive the data signal DQ based on the result that the decoder 122 decodes the command / address signal CA, and may stably transmit (or may transmit) the data signal DQ to the second storage area 132.

[0057] The first storage region 131 according to example embodiments may include a seventh latch 131a, an eighth latch 131b, a fifth switch 131c, a sixth switch 131d, a first storage region decoder 131e, a first storage region logic 131f, or a third data path 131g.

[0058] The seventh latch 131a according to example embodiments may receive a command / address signal CA from the first channel 121 and may transmit the received command / address signal CA to the first storage area decoder 131e. The eighth latch 131b according to example embodiments may receive a data signal DQ from the first channel 121.

[0059] According to example embodiments, the operations of the fifth switch 131c and the sixth switch 131d may be controlled according to the decoding result of the first storage area decoder 131e. For example, when the operation determined based on the result of decoding the command / address signal CA by the first storage area decoder 131e is a read operation, the fifth switch 131c may be closed and the command / address signal CA may be sent to the first storage area logic 131f. In some example embodiments, when the operation determined based on the result of decoding the command / address signal CA by the first storage area decoder 131e is a write operation, the sixth switch 131d may be closed and the data signal DQ may be connected to the third data path 131g. The third data path 131g according to example embodiments may be a path for writing data to the first storage area 131.

[0060] The second storage region 132 according to example embodiments may include a ninth latch 132a, a tenth latch 132b, a seventh switch 132c, an eighth switch 132d, a second storage region decoder 132e, a second storage region logic 132f, or a fourth data path 132g.

[0061] The ninth latch 132a according to the example embodiment may receive the command / address signal CA from the second channel 123 and may transmit the received command / address signal CA to the second storage area decoder 132e. The tenth latch 132b according to the example embodiment may receive the data signal DQ from the second channel 123.

[0062] According to example embodiments, the operation of the seventh switch 132c and the eighth switch 132d may be controlled according to the decoding result of the second storage area decoder 132e, or the opening and closing of the seventh switch 132c and the eighth switch 132d may be controlled based on the result of decoding the command / address signal CA by the decoder 122 of the buffer chip 120. For example, when the operation determined based on the result of decoding the command / address signal CA by the second storage area decoder 132e is a read operation, the seventh switch 132c may be closed, and the command / address signal CA may be transmitted to the second storage area logic 132f. In some example embodiments, when the operation determined based on the result of decoding the command / address signal CA by the second storage area decoder 132e is a write operation, or when the data signal DQ is received based on the result of decoding the command / address signal CA by the decoder 122 of the buffer chip 120, the eighth switch 132d may be closed, and the data signal DQ may be transmitted to the fourth data path 132g. The fourth data path 132g according to example embodiments may be a path for writing data to the second storage area 132.

[0063] Although only the first storage region 131 and the second storage region pattern 132 are shown in 3A, the number of storage regions is not limited thereto, and there may be more storage regions including a plurality of dies.

[0064] Figure 3B The memory device 100 is shown in which a command / address signal CA of a buffer chip 120 according to an example embodiment is transmitted to a first memory area 131 and a second memory area 132 through one path.

[0065] because Figure 3B The configuration of the memory controller 110, the first storage area 131 and the second storage area 132 in Figure 3A Same, so focus on the differences with 3A to describe Figure 3B .

[0066] refer to Figure 3B , the buffer chip 120 according to the example embodiment may include a first channel 121 and a second channel 123, and the first channel 121 may include a first data path 121a, a first latch 121b, a first switch 121c, a second latch 121e, a third latch 121f, or a decoder 122. The second channel 123 according to the example embodiment may include a second data path 123a, a fourth latch 123b, a fourth switch 123d, or a sixth latch 123f. For example, different from Figure 3A, the command / address signal CA can be connected to multiple storage areas and multiple paths through the third latch 121f, and the path of the command / address signal CA or the data signal DQ can be determined based on the result of decoding the command / address signal CA by the decoder in the storage area.

[0067] The first data path 121 a according to example embodiments may be a path through which a chip enable signal CE and a command / address signal CA are transmitted.

[0068] The first latch 121b according to example embodiments may receive a command / address signal CA. For example, the first latch 121b may receive a command / address signal CA and may transmit the received command / address signal CA to the decoder 122 when the received command / address signal CA is activated.

[0069] The decoder 122 according to an example embodiment may decode the command / address signal CA activated by the chip enable signal CE, and may determine a path of the command / address signal CA and a path of the data signal DQ based on the decoding result. For example, the decoder 122 may decode the command / address signal CA, and may determine a first storage area 131 to which the command / address signal CA is transmitted and a second storage area 132 to which the data signal DQ is transmitted based on the decoding result. Figure 3B The buffer chip 120 may control the operation of the first switch 121c or the fourth switch 123d according to the decoding result.

[0070] The decoder 122 of the first channel 121 according to an example embodiment may decode the command / address signal CA, and based on the decoding result, the buffer chip 120 may determine the storage area to which the data signal DQ is transmitted. For example, the buffer chip 120 may decode the command / address signal CA, and may determine the storage area to which the data signal DQ is transmitted as the second storage area 132 based on the decoding result. In some example embodiments, when the storage area to which the data signal DQ is transmitted is determined to be the second storage area 132, the buffer chip 120 may transmit the data signal DQ to the second storage area 132 by closing the fourth switch 123d. In another example, the buffer chip 120 may decode the command / address signal CA, and may determine the storage area to which the data signal DQ is transmitted as the first storage area 131 based on the decoding result. In some example embodiments, when the storage area to which the data signal DQ is transmitted is determined to be the first storage area 131, the buffer chip 120 may transmit the data signal DQ to the first storage area 131 by closing the first switch 123a. According to example embodiments, a path through which the data signal DQ is transmitted from the buffer chip 120 to the memory area may be a selection path Sel.

[0071] The buffer chip 120 according to the example embodiment can transmit the command / address signal CA to multiple storage areas through corresponding paths. For example, the buffer chip 120 does not have a separate switch to control the transmission of the command / address signal CA, but can transmit the command / address signal CA to multiple storage areas through the third latch 121f.

[0072] In some example embodiments, when the command / address signal CA is sent to a plurality of storage areas, each storage area may decode the command / address signal CA by a decoder included in the storage area. For example, the first storage area 131 may decode the received command / address signal CA by the first storage area decoder 131e, and may perform an operation according to the decoding result. For example, the first storage area 131 may perform a read operation or a write operation on the data signal DQ according to the result of decoding the command / address signal CA. In another example, the second storage area 132 may decode the received command / address signal CA by the second storage area decoder 132e, and may perform an operation according to the decoding result. For example, the second storage area 132 may perform a read operation or a write operation on the data signal DQ according to the result of decoding the command / address signal CA. According to an example embodiment, the path through which the command / address signal CA is sent from the buffer chip 120 to the storage area may be the selection path Sel.

[0073] Despite Figure 3B Only the first storage area 131 and the second storage area pattern domain 132 are shown in FIG. 1 , but the number of storage areas is not limited thereto, and there may be more storage areas including a plurality of bare cores.

[0074] Figure 3C An example embodiment is shown in which a plurality of chip enable signals CE_0 , CE_1 , CE_2 , and CE_3 are received by the buffer chip 120 according to an example embodiment.

[0075] because Figure 3C The configuration of the memory controller 110, the first storage area 131 and the second storage area 132 in Figure 3A Same, so pay attention to Figure 3A to describe the difference Figure 3C .

[0076] refer to Figure 3C, the buffer chip 120 according to example embodiments may include a first channel 121 and a second channel 123, and the first channel 121 may include a first data path 121a, a first latch 121b, a first switch 121c, a second switch 121d, a second latch 121e, a third latch 121f, or a decoder 122. The first data path 121a according to example embodiments may be a path through which a chip enable signal CE and a command / address signal CA are transmitted.

[0077] The second channel 123 according to example embodiments may include a second data path 123a, a fourth latch 123b, a third switch 123c, a fourth switch 123d, a fifth latch 123e, or a sixth latch 123f. The second data path 123a according to example embodiments may be a path through which a data signal DQ is transmitted.

[0078] The buffer chip 120 according to the example embodiment may receive a plurality of chip enable signals CE_0, CE_1, CE_2, and CE_3. The buffer chip 120 according to the example embodiment may receive a plurality of chip enable signals CE_0, CE_1, CE_2, and CE_3, and may determine a path of a command / address signal CA and a path of a data signal DQ. For example, the buffer chip 120 may distinguish types of the plurality of chip enable signals CE_0, CE_1, CE_2, and CE_3, and may activate the received plurality of chip enable signals CE_0, CE_1, CE_2, and CE_3 to activate the first switch 121c of the first channel 121 or the third switch 123c of the second channel 123. The first switch 121c of the first channel 121 or the third switch 123c of the second channel 123 according to the example embodiment may be a switch that controls the connection of the path of the command / address signal CA.

[0079] The buffer chip 120 according to an example embodiment may distinguish between a plurality of chip enable signals CE_0, CE_1, CE_2, and CE_3 by using the first logic circuit 124a or the second logic circuit 124b. For example, each of the first logic circuit 124a and the second logic circuit 124b may be composed of an OR gate and may activate the first switch 121c and the third switch 123c depending on the states of the first chip enable signal CE_0 and the second chip enable signal CE_1. The buffer chip 120 according to an example embodiment may disconnect the first switch 121c when the output of the first logic circuit 124a has a high logic value, and may close the first switch 121c when the output of the first logic circuit 124a has a low logic value. The buffer chip 120 according to an example embodiment may disconnect the third switch 123c when the output of the second logic circuit 124b has a high logic value, and may close the third switch 123c when the output of the second logic circuit 124b has a low logic value.

[0080] The first logic circuit 124 a or the second logic circuit 124 b according to example embodiments may be an OR gate, but example embodiments are not limited thereto.

[0081] For example, the buffer chip 120 according to example embodiments may distinguish types of the plurality of chip enable signals CE_0, CE_1, CE_2, and CE_3, may activate the received plurality of chip enable signals CE_0, CE_1, CE_2, and CE_3 to decode the command / address signal CA, and may activate the second switch 121d of the first channel 121 or the third switch 123c of the second channel 123. The second switch 121d of the first channel 121 or the third switch 123c of the second channel 123 according to example embodiments may be a switch for controlling connection of a path of the data signal DQ.

[0082] According to the example embodiment, a plurality of chip enable signals CE_0, CE_1, CE_2, and CE_3 may be distinguished by the third logic circuit 124c. For example, the buffer chip 120 may determine the storage area to which the command / address signal CA is sent based on the output of the third logic circuit 124c. In some example embodiments, when the output of the third logic circuit 124c is high, the decoder 122 may decode the command / address signal CA and may determine the storage area to which the command / address signal CA is sent. However, when the output of the third logic circuit 124c is low, the decoder 122 may not be activated. According to the example embodiment, the third logic circuit 123a may be an OR gate, but the example embodiments are not limited thereto.

[0083] The first latch 121b according to example embodiments may receive a command / address signal CA. For example, the first latch 121b may receive a command / address signal CA and may transmit the received command / address signal CA to the decoder 122 when the received command / address signal CA is activated.

[0084] The decoder 122 according to an example embodiment may decode the command / address signal CA activated by the chip enable signal CE, and may determine the path of the command / address signal CA and the path of the data signal DQ based on the decoding result. For example, the decoder 122 may decode the command / address signal CA, and may determine the first storage area 131 to which the command / address signal CA is transmitted and the second storage area 132 to which the data signal DQ is transmitted based on the decoding result. According to an example embodiment, the buffer chip 120 may control the operation of the first to fourth switches 121c, 121d, 123c, and 123d based on the decoding result.

[0085] The first switch 121c according to an example embodiment may control the transmission of the command / address signal CA. For example, when the first storage area 131 is determined as the area to which the command / address signal CA is transmitted based on the result of decoding the command / address signal CA by the decoder 122, the buffer chip 120 may transmit the command / address signal CA to the first storage area 131 by closing the first switch 121c. In some example embodiments, when the first switch 121c is closed, the path for transmitting the command / address signal CA to the first storage area 131 may be the selection path Sel.

[0086] The second switch 121d according to the example embodiment may control the transmission of the data signal DQ. For example, when the first storage area 131 is determined as an area to which the data signal DQ is not transmitted based on the decoding result of the decoder 122, the buffer chip 120 may not transmit the data signal DQ to the first storage area 131 by turning off the second switch 121d.

[0087] The second latch 121e according to an example embodiment may receive the command / address signal CA based on a result of decoding the command / address signal CA by the decoder 122, and may stably transmit (or may transmit) the command / address signal CA to the first storage area 131. The third latch 121f according to an example embodiment may receive the data signal DQ based on a result of decoding the command / address signal CA by the decoder 122, and may stably transmit (or may transmit) the data signal DQ to the first storage area 131.

[0088] The fourth latch 123b according to example embodiments may receive the data signal DQ. For example, when the region to which the data signal DQ is transmitted is determined to be the second storage region 132 based on the decoding result of the first channel 121, the fourth latch 123b may transmit the received data signal DQ to the second storage region 132.

[0089] The third switch 123c according to the example embodiment may control the transmission of the command / address signal CA. For example, when the second storage area 132 is determined as an area to which the command / address signal CA is not transmitted based on the decoding result of the decoder 122, the buffer chip 120 may not transmit the command / address signal CA to the second storage area 132 by turning off the third switch 123c.

[0090] The fourth switch 123d according to an example embodiment may control the transmission of the data signal DQ. For example, when the area to which the data signal DQ is transmitted is determined to be the second storage area 132 based on the decoding result of the decoder 122 of the first channel 121, the buffer chip 120 may transmit the data signal DQ to the second storage area 132 by closing the fourth switch 123d. In some example embodiments, when the fourth switch 123d is closed, the path for transmitting the data signal DQ to the second storage area 132 may be the selection path Sel.

[0091] The fifth latch 123e according to the example embodiment may receive the command / address signal CA based on the result that the decoder 122 decodes the command / address signal CA, and may stably transmit (or may transmit) the command / address signal CA to the second storage area 132. The sixth latch 123f according to the example embodiment may receive the data signal DQ based on the result that the decoder 122 decodes the command / address signal CA, and may stably transmit (or may transmit) the data signal DQ to the second storage area 132.

[0092] The first storage region 131 according to example embodiments may include a seventh latch 131a, an eighth latch 131b, a fifth switch 131c, a sixth switch 131d, a first storage region decoder 131e, a first storage region logic 131f, or a third data path 131g.

[0093] The seventh latch 131a according to example embodiments may receive a command / address signal CA from the first channel 121 and may transmit the received command / address signal CA to the first storage area decoder 131e. The eighth latch 131b according to example embodiments may receive a data signal DQ from the first channel 121.

[0094] According to example embodiments, the operations of the fifth switch 131c and the sixth switch 131d may be controlled according to the decoding result of the first storage area decoder 131e. For example, when the operation determined based on the result of decoding the command / address signal CA by the first storage area decoder 131e is a read operation, the fifth switch 131c may be closed and the command / address signal CA may be transmitted to the first storage area logic 131f. In some example embodiments, when the operation determined based on the result of decoding the command / address signal CA by the first storage area decoder 131e is a write operation, the sixth switch 131d may be closed and the data signal DQ may be transmitted to the third data path 131g. The third data path 131g according to example embodiments may be a path for writing data to the first storage area 131.

[0095] The second storage region 132 according to example embodiments may include a ninth latch 132a, a tenth latch 132b, a seventh switch 132c, an eighth switch 132d, a second storage region decoder 132e, a second storage region logic 132f, or a fourth data path 132g.

[0096] The ninth latch 132a according to the example embodiment may receive the command / address signal CA from the second channel 123 and may transmit the received command / address signal CA to the second storage area decoder 132e. The tenth latch 132b according to the example embodiment may receive the data signal DQ from the second channel 123.

[0097] According to example embodiments, the operation of the seventh switch 132c and the eighth switch 132d may be controlled according to the decoding result of the second storage area decoder 132e, or the opening and closing of the seventh switch 132c and the eighth switch 132d may be controlled based on the result of decoding the command / address signal CA by the decoder 122 of the buffer chip 120. For example, when the operation determined based on the result of decoding the command / address signal CA by the second storage area decoder 132e is a read operation, the seventh switch 132c may be closed, and the command / address signal CA may be transmitted to the second storage area logic 132f. In some example embodiments, when the operation determined based on the result of decoding the command / address signal CA by the second storage area decoder 132e is a write operation, or when the data signal DQ is received based on the result of decoding the command / address signal CA by the decoder 122 of the buffer chip 120, the eighth switch 132d may be closed, and the data signal DQ may be transmitted to the fourth data path 132g. The fourth data path 132g according to example embodiments may be a path for writing data to the second storage area 132.

[0098] Despite Figure 3COnly the first storage area 131 and the second storage area 132 are shown in FIG. 1 , but the number of storage areas is not limited thereto, and there may be more storage areas including a plurality of bare cores.

[0099] Figure 4 is a schematic diagram illustrating signals received by the buffer chip 120 according to an example embodiment.

[0100] refer to Figure 2 and Figure 4 , the buffer chip 120 according to the example embodiment may receive the command / address signal CA through the CA channel, and may receive the data signal DQ through the DQ channel. The CA channel according to the example embodiment may be Figure 2 The first channel 121, and the DQ channel can be Figure 2 The second channel 123. Figure 4 In the example embodiment, the memory device may be composed of a plurality of chips. For example, although the memory device may be described as including a first chip to a fourth chip, the memory device may also include a plurality of chips.

[0101] The buffer chip 120 according to example embodiments may receive the command / address signal CA for the first chip in an input mode until a first time point T1 through the first channel 121. The input mode according to example embodiments may be a mode in which the command / address signal CA is input to a storage area.

[0102] For example, the buffer chip 120 may receive a command / address signal CA including read data on the first chip through the first channel 121 until a first time point T1. In some example embodiments, when receiving the command / address signal CA including read data on the first chip, the buffer chip 120 may enable the first chip to receive the data signal DQ in an output mode from the first time point T1 to the second time point T2 and perform a read operation. The output mode according to an example embodiment may be a mode for reading data from a storage area. When the first chip receives the data signal DQ, the first channel 121 may send the command / address signal CA to the second chip. For example, the buffer chip 120 according to an example embodiment may simultaneously send the command / address signal CA and the data signal DQ to a separate storage area.

[0103] The buffer chip 120 according to the example embodiment may receive the command / address signal CA for the second chip in the input mode through the first channel 121 until the second time point T2. For example, the buffer chip 120 may receive the command / address signal CA including the write data on the second chip through the first channel 121 until the second time point T2. In some example embodiments, when the command / address signal CA including the write data on the second chip is received, the buffer chip 120 may enable the second chip to receive the data signal DQ in the input mode from the second time point T2 to the third time point T3 and perform a write operation. When the second chip receives the data signal DQ, the first channel 121 may send the command / address signal CA to the third chip in the output mode and may send the command / address signal CA to the fourth chip in the input mode. For example, the buffer chip 120 according to the example embodiment may simultaneously send the command / address signal CA and the data signal DQ to separate storage areas in the input mode and the output mode.

[0104] In some example embodiments, when receiving the command / address signal CA for the fourth chip in the input mode, the buffer chip 120 may perform a write operation on the fourth chip after the third time point T3 .

[0105] Figure 5A is a block diagram of a memory device including a plurality of chips according to example embodiments. Figure 5B It shows that it can be Figure 5A Schematic diagram of the signals received by the buffer chip included in FIG.

[0106] refer to Figure 5A , a memory device 100a according to an example embodiment may include a memory controller 110a, a buffer chip 120a, and a memory device 130a. Since the configuration of the memory controller 110a and the buffer chip pattern 120a of the memory device 100a in 5A is similar to Figure 1 and Figure 2 The configuration is the same as Figure 1 and Figure 2 to describe the differences Figure 5A The memory device 130a in.

[0107] The memory device 130a according to the example embodiment may include a plurality of chips. For example, the memory device 130a may include first to eighth chips 133a, 133b, 133c, 133d, 133e, 133f, 133g, and 133h. However, the number of memory chips is not limited thereto, and the memory device 130a may also include a plurality of memory chips.

[0108] According to example embodiments, the first to eighth chips 133a, 133b, 133c, 133d, 133e, 133f, 133g, and 133h may be each connected to a chip enable signal CE, and may be each connected to a command / address signal CA channel and a data signal DQ channel through a buffer chip 120a.

[0109] refer to Figure 5A and Figure 5B , the first chip 133a according to the example embodiment may receive the chip enable signal CE (LUNSEL packet), and may receive the write command / address signal CA (PGM CMD / ADD) activated by the chip enable signal CE (LUNSEL packet) for the first chip 133a. Likewise, the second chip 133b according to the example embodiment may receive the chip enable signal CE (LUNSEL packet), and may receive the read command / address signal CA (READ CMD / ADD) activated by the chip enable signal CE (LUNSEL packet) for the second chip 133b. In some example embodiments, when the reception of the signal is completed, an operation execution signal (SCE packet) for the chip may be received. For example, the buffer chip 120a may receive the operation execution signal (SCE packet) for the first chip 133a, and may cause the first chip 133a to perform the operation indicated by the write command / address signal CA (PGM CMD / ADD). The first chip 133 a according to example embodiments may receive write data at a first time point T1 and may perform a data write operation indicated by a write command / address signal CA (PGMCMD / ADD).

[0110] In some example embodiments, when the reception of the write data of the first chip 133a is completed, the buffer chip 120a may receive an operation completion signal (SCT data packet), and may receive an operation execution signal (SCE data packet) for the next chip. For example, when the reception of the write data of the first chip 133a is completed, the buffer chip 120a may receive an operation completion signal (SCT data packet) for the first chip 133a, and may receive an operation execution signal (SCE data packet) for the second chip 133b. In some example embodiments, when the operation execution signal (SCE data packet) for the second chip 133b is received, the second chip 133b may receive read data based on a previously received read command / address signal CA (READ CMD / ADD). In some example embodiments, when the reception of the read data is completed, the buffer chip 120a may receive an operation completion signal (SCT data packet).

[0111] For example, a plurality of chips of the memory device 100a according to example embodiments may each simultaneously receive the chip enable signal CE and the command / address signal CA, and may independently perform a data read operation or a data write operation according to an operation indicated by the command / address signal CA.

[0112] Figure 5C is a schematic diagram in which multiple chips of a storage device are activated by multiple chip enable signals CE_0, CE_1, CE_2 and CE_3.

[0113] refer to Figure 5C , a memory device 100b according to example embodiments may include a memory controller 110b, a buffer chip 120b, and a memory device 130b. Figure 5C The configuration of the memory controller 110b and the buffer chip 120b of the storage device 100b is similar to Figure 1 and Figure 2 The configuration is the same as Figure 1 and Figure 2 to describe the differences Figure 5C Memory device 130b.

[0114] The memory device 130b according to the example embodiment may include a plurality of chips. For example, the memory device 130b may include first to eighth chips 133a, 133b, 133c, 133d, 133e, 133f, 133g, and 133h. However, the number of memory chips is not limited thereto, and the memory device 130b may also include a plurality of memory chips.

[0115] According to example embodiments, the first to eighth chips 133a, 133b, 133c, 133d, 133e, 133f, 133g, and 133h may each be connected to the chip enable signal CE, and may each be connected to the command / address signal CA channel and the data signal DQ channel through the buffer chip 120b. For example, the first to eighth chips 133a, 133b, 133c, 133d, 133e, 133f, 133g, and 133h may each be connected to the pre-classified chip enable signal CE channel, and may each receive the command / address signal CA or the data signal DQ from the buffer chip 120b when receiving the chip enable signal CE.

[0116] The first chip enable signal CE_0 according to an example embodiment may be a signal that activates the first chip 133a or the second chip 133b. The second chip enable signal CE_1 according to an example embodiment may be a signal that activates the fifth chip 133e or the sixth chip 133f. The third chip enable signal CE_2 according to an example embodiment may be a signal that activates the third chip 133c or the fourth chip 133d. The fourth chip enable signal CE_3 according to an example embodiment may be a signal that activates the seventh chip 133g or the eighth chip 133h.

[0117] Figure 5D Signals are shown when a plurality of chips of a memory device according to example embodiments are activated by a plurality of chip enable signals CE_0 , CE_1 , CE_2 , and CE_3 .

[0118] refer to Figure 5C and Figure 5D According to example embodiments, the first chip 133a and the third chip 133c may receive the first chip enable signal CE_0 at the first time point T1, the fourth time point T4, and the seventh time point T7, and may perform an internal program operation at the second time point T2.

[0119] In addition, according to example embodiments, the sixth chip 133f and the eighth chip 133h may receive the fourth chip enable signal CE_3 at the third time point T3, the eighth time point T8, or the eleventh time point T11, and may receive the command / address signal CA including the read command signal (READ CMD) until the fifth time point T5. For example, the buffer chip 120b may receive the operation execution signal (SCE data packet) for the first chip 133a at the sixth time point T6, and may cause the first chip 133a to perform the operation indicated by the write command / address signal CA (PGM CMD / ADD). The first chip 133a according to example embodiments may receive write data at the first time point T1, and may perform the data write operation indicated by the write command / address signal CA (PGM CMD / ADD).

[0120] In some example embodiments, when the reception of the write data of the first chip 133a is completed, the buffer chip 120b may receive an operation completion signal (SCT packet) and may receive an operation execution signal (SCE packet) for the next chip. According to example embodiments, the eighth chip 133h may receive the fourth chip enable signal CE_3 and may receive a read command / address signal CA (READ CMD) for the eighth chip 133h. In some example embodiments, when the reception of the signal is completed, an operation execution signal (SCE packet) for the eighth chip 133h may be received at a ninth time point T9. For example, when the reception of the write data of the first chip 133a is completed, the buffer chip 120b may receive an operation completion signal (SCT packet) for the first chip 133a and may receive an operation execution signal (SCE packet) for the eighth chip 133h at a ninth time point T9. In some example embodiments, when the operation execution signal (SCE packet) for the eighth chip 133h is received, the eighth chip 133h may receive read data based on the previously received read command / address signal CA (READ CMD / ADD) until a twelfth time point T12. In some example embodiments, when reception of the read data is completed, the buffer chip 120 b may receive an operation completion signal (SCT data packet).

[0121] For example, a plurality of chips of the memory device 100b according to example embodiments may each receive a chip enable signal CE and a command / address signal CA, and may independently perform a data read operation or a data write operation according to an operation indicated by the command / address signal CA.

[0122] Figure 6 and Figure 7 is a flowchart of a method of operating a storage device according to example embodiments.

[0123] refer to Figure 1 and Figure 6 , according to example embodiments, the memory device 100 may generate at least one of a chip enable signal CE and a command / address signal CA for at least one memory region ( S610 ).

[0124] For example, the memory device 100 may generate at least one of a chip enable signal CE and a command / address signal CA for at least one memory region of the memory device 130. The chip enable signal CE according to example embodiments may be a signal that controls signal transmission of the buffer chip 120 to activate the command / address signal CA. The command / address signal CA according to example embodiments may be a signal that specifies a memory region of the memory device 130.

[0125] In some example embodiments, when at least one of a chip enable signal CE and a command / address signal CA for at least one memory region is generated, the buffer chip 120 of the memory device 100 may receive the chip enable signal CE, the command / address signal CA, and the data signal DQ ( S620 ).

[0126] For example, the buffer chip 120 of the memory device 100 may be configured to include a first channel for receiving a chip enable signal CE or a command / address signal CA and a second channel for receiving a data signal DQ. The first channel according to an example embodiment may be a path for receiving a chip enable signal CE or a command / address signal CA. The second channel according to an example embodiment may be a path for receiving a data signal DQ. The first channel and the second channel according to an example embodiment may receive signals through separate paths, and may send the received signals to at least one storage area of ​​the memory device 130. For example, the first channel and the second channel may be physically separated paths for signal transmission, and the first channel may receive a chip enable signal CE or a command / address signal CA, while the second channel may receive a data signal DQ. The buffer chip 120 according to an example embodiment may simultaneously send signals received through the first channel and the second channel to the memory device 130.

[0127] In some example embodiments, when the buffer chip 120 receives the chip enable signal CE, the command / address signal CA, and the data signal DQ, the memory device 100 may perform at least one of a write operation and a read operation based on the received command / address signal CA and data signal DQ (S630).

[0128] The storage device 100 according to the example embodiment may include at least one storage area configured to perform at least one of a write operation and a read operation based on a command / address signal CA and a data signal DQ, each of which is received by the buffer chip 120. The memory device 130 of the storage device 100 according to the example embodiment may include a first storage area and a second storage area. For example, the memory device 130 may include a first storage area that receives the command / address signal CA and a second storage area that receives the data signal DQ. The first storage area or the second storage area according to the example embodiment may each be a memory die included in the memory device 130. However, the first storage area and the second storage area are classified according to the type of the received signal.

[0129] refer to Figure 1 , Figure 2 and Figure 7, the buffer chip 120 of the memory device 100 according to example embodiments may receive a chip enable signal CE, a command / address signal CA, and a data signal DQ ( S710 ).

[0130] In some example embodiments, when receiving the chip enable signal CE, the command / address signal CA, and the data signal DQ, the memory device 100 may receive the chip enable signal CE or the command / address signal CA through the first channel 121 ( S720 ).

[0131] The buffer chip 120 according to example embodiments may receive a chip enable signal CE or a command / address signal CA and may transmit the received command / address signal CA to the first storage area 131. The first storage area 131 according to example embodiments may be a storage area of ​​the memory device 130 communicating with the first channel 121.

[0132] In some example embodiments, when the chip enable signal CE or the command / address signal CA is received through the first channel 121, the data signal DQ may be received through the second channel 123 different from the first channel 121 (S730). The buffer chip 120 according to example embodiments may be configured to transmit the data signal DQ to the second storage area 132 through the second channel 123 when the command / address signal CA is transmitted to the first storage area 131 through the first channel 121.

[0133] In some example embodiments, when the command / address signal CA is received through the first channel 121 and the data signal DQ is received through the second channel 123 , the memory device 100 may transmit the received signals to at least one memory region ( S740 ).

[0134] For example, the first channel 121 and the second channel 123 may be physically separated and simultaneously transmit a plurality of signals to the memory device 130. When the command / address signal CA is transmitted to the first storage area 131 through the first channel 121, the buffer chip 120 according to example embodiments may transmit the data signal DQ to the second storage area 132 through the second channel 123 so that a write operation or a read operation is performed.

[0135] Figure 8 is a flowchart of a process for determining a storage area with which a first channel and a second channel communicate in a method of operating a storage device according to example embodiments.

[0136] refer to Figure 2 and Figure 8 , the buffer chip 120 of the memory device 100 according to example embodiments may receive a chip enable signal CE, a command / address signal CA, and a data signal DQ ( S810 ).

[0137] For example, the buffer chip 120 of the memory device 100 may receive the command / address signal CA through the first channel 121 , and may receive the data signal DQ through the second channel 123 .

[0138] In some example embodiments, when the buffer chip 120 receives the chip enable signal CE, the command / address signal CA, and the data signal DQ, the memory device 100 may decode the command / address signal CA ( S820 ).

[0139] The memory device 100 according to example embodiments may include at least one decoder 122. For example, since the first channel 121 includes the decoder 122, the memory device 100 may include the decoder 122. The decoder 122 according to example embodiments may decode the command / address signal CA.

[0140] In some example embodiments, when the command / address signal CA is decoded, the storage device 100 may determine a storage area with which the first channel 121 communicates based on a result of decoding the command / address signal CA ( S830 ).

[0141] The storage device 100 according to example embodiments may determine a storage area with which the first channel 121 communicates based on a result of decoding the command / address signal CA. For example, when the first channel 121 is activated by the chip enable signal CE, the storage device 100 may decode the command / address signal CA, and may determine the first storage area 131 based on the decoding result. The command / address signal CA according to example embodiments may include information about a storage area to which the command / address signal CA is to be transmitted.

[0142] In addition, when the command / address signal CA is decoded, the storage device 100 according to example embodiments may determine a storage area with which the second channel 123 communicates based on a result of decoding the command / address signal CA ( S840 ).

[0143] The storage device 100 according to example embodiments may transmit the data signal DQ to the second storage area 132 based on the result of decoding the command / address signal CA. For example, based on the result of decoding the command / address signal CA, the storage device 100 may determine the first storage area 131 and the second storage area 132, and may determine the storage area to which the command / address signal CA is not transmitted as the second storage area 132. The command / address signal CA according to example embodiments may include path information of the data signal DQ.

[0144] Fig. 9 is a flowchart of a process for controlling transmission of command / address signals and data signals in a method of operating a memory device according to example embodiments.

[0145] refer to Figure 3A and Fig. 9 , the buffer chip 120 of the memory device 100 according to example embodiments may receive a chip enable signal CE, a command / address signal CA, and a data signal DQ ( S910 ).

[0146] For example, the buffer chip 120 of the memory device 100 may receive the command / address signal CA through the first channel 121 , and may receive the data signal DQ through the second channel 123 .

[0147] In some example embodiments, when a chip enable signal CE, a command / address signal CA, and a data signal DQ are received by the buffer chip 120, the memory device 100 may control a first switch 121c that controls transmission of the command / address signal CA and a second switch 121d that controls transmission of the data signal DQ (S920).

[0148] For example, when the region to which the command / address signal CA is transmitted is determined to be the first storage region 131 based on the decoding result, the storage device 100 may transmit the command / address signal CA to the first storage region 131 by closing the first switch 121c. In some example embodiments, when the first switch 121c is closed, the path for transmitting the command / address signal CA to the first storage region 131 may be the selection path Sel. In another example, when the first storage region 131 is determined to be the region to which the data signal DQ is not transmitted based on the decoding result, the storage device 100 may not transmit the data signal DQ to the first storage region 131 by opening the second switch 121d.

[0149] In addition, when the chip enable signal CE, the command / address signal CA, and the data signal DQ are received by the buffer chip 120, the memory device 100 according to example embodiments may control the third switch 123c and the fourth switch 123d, the third switch 123c controlling transmission of the command / address signal CA, and the fourth switch 123d controlling transmission of the data signal DQ (S930).

[0150] For example, when the area to which the command / address signal CA is not transmitted is determined as the second storage area 132 based on the decoding result, the storage device 100 may not transmit the command / address signal CA to the second storage area 132 by opening the third switch 123c. For example, when the area to which the data signal DQ is transmitted is determined as the second storage area 132 based on the decoding result, the storage device 100 may transmit the data signal DQ to the second storage area 132 by closing the fourth switch 123d. In some example embodiments, when the fourth switch 123d is closed, the path for transmitting the data signal DQ to the second storage area 132 may be the selection path Sel.

[0151] Figures 10 to 12 is a schematic diagram illustrating a three-dimensional V-NAND structure that may be applied to a memory device according to example embodiments.

[0152] Applies to Figure 1 The nonvolatile memory 1000 of the memory device 130 may include a plurality of memory blocks. Fig.10 and Fig.11 shows the structure of a memory block BLKi among the plurality of memory blocks, and Fig.12 An implementation example of a non-volatile memory 1000 is shown.

[0153] refer to Fig.10 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and a common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST. For the sake of simplicity of the drawings, Fig.10 It is shown in FIG. 4 that each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1 to MC8 , but example embodiments are not limited thereto.

[0154] The string selection transistor SST may be connected to the corresponding string selection lines SSL1, SSL2, and SSL3. A plurality of memory cells MC1 to MC8 may be connected to gate lines GTL1 to GTL8, respectively. The gate lines GTL1 to GTL8 may correspond to word lines, and some of the gate lines GTL1 to GTL8 may correspond to dummy word lines. The ground selection transistor GST may be connected to the corresponding ground selection lines GSL1, GSL2, and GSL3. The string selection transistor SST may be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground selection transistor GST may be connected to the common source line CSL.

[0155] Gate lines (eg, GTL1) of the same height may be connected in common, and ground selection lines GSL1, GSL2, GSL3 may be separated from string selection lines SSL1, SSL2, and SSL3. Fig.10 , it is illustrated that the memory block BLKi is connected to eight gate lines GTL1 to GTL8 and three bit lines BL1 , BL2 , and BL3 , but example embodiments are not limited thereto.

[0156] refer to Fig.11 , the memory block BLKi is formed in a vertical direction with respect to the substrate SUB. Memory cells constituting the memory NAND strings NS11 to NS33 are stacked on a plurality of semiconductor layers.

[0157] On the substrate SUB, a common source line CSL extending in a first direction (Y direction) is provided. In the region of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating films IL extending in the first direction (Y direction) may be sequentially provided in a third direction (Z direction), and the plurality of insulating films IL may be spaced apart from each other by a specific distance in the third direction (Z direction). In the region of the substrate SUB between two adjacent common source lines CSL, a plurality of pillars P are sequentially arranged in the first direction (Y direction) and pass through the plurality of insulating films IL in the third direction (Z direction). The plurality of pillars P may pass through the plurality of insulating films IL and contact the substrate SUB. The surface layer S of each pillar P may include a silicon material doped to a first conductivity type and may be used as a channel region.

[0158] The inner layer I of each pillar P may include an insulating material, such as silicon oxide or an air gap. In the region between two adjacent common source lines CSL, a charge storage layer CS is provided along the exposed surfaces of the insulating film IL, the pillar P, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as a "tunneling insulating layer"), a charge trapping layer, and a blocking insulating layer. In addition, in the region between two adjacent common source lines CSL, a gate electrode GE, such as selection lines GSL and SSL and word lines WL1 to WL8, is provided on the exposed surface of the charge storage layer CS. Drains or drain contacts DR may be provided on a plurality of pillars P, respectively. Bit lines BL1 to BL3 extending in the second direction (X direction) and spaced apart from each other by a specific distance in the first direction (Y direction) may be provided on the drain contacts DR.

[0159] like Fig.11As shown, each memory NAND string NS11 to NS33 may be implemented in a structure in which a first memory stack ST1 and a second memory stack ST2 are stacked. The first memory stack ST1 is connected to a common source line CSL, the second memory stack ST2 is connected to bit lines BL1 to BL3, and the first memory stack ST1 and the second memory stack ST2 are stacked to share a channel hole with each other.

[0160] Fig.12 is a schematic diagram illustrating a memory device 400 according to an example embodiment.

[0161] refer to Fig.12 , the memory device 400 may have a chip-to-chip (C2C) structure. The C2C structure may refer to a structure formed by manufacturing an upper chip including a cell area CELL on a first wafer, manufacturing a lower chip including a peripheral circuit area PERI on a second wafer separated from the first wafer, and then bonding the upper chip and the lower chip to each other. In some example embodiments, the bonding process may include a method of electrically connecting a bonding metal formed on the uppermost metal layer of the upper chip with a bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal may include copper (Cu) using Cu to Cu bonding, but example embodiments are not limited thereto. For example, the bonding metal may also be formed of aluminum (Al) or tungsten (W).

[0162] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 400 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0163] The peripheral circuit region PERI may include a first substrate 210, an interlayer insulating layer 215, a plurality of circuit elements 220a, 220b, and 220c formed on the first substrate 210, first metal layers 230a, 230b, and 230c connected to the plurality of circuit elements 220a, 220b, and 220c, respectively, and second metal layers 240a, 240b, and 240c formed on the first metal layers 230a, 230b, and 230c. In example embodiments, the first metal layers 230a, 230b, and 230c may be formed of tungsten having a relatively high resistivity (or having a high resistivity), and the second metal layers 240a, 240b, and 240c may be formed of copper having a relatively low resistivity (or having a low resistivity).

[0164] exist Fig.12In the illustrated example embodiment, although only the first metal layers 230a, 230b, and 230c and the second metal layers 240a, 240b, and 240c are illustrated and described, the example embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers 240a, 240b, and 240c. At least a portion of the one or more additional metal layers formed on the second metal layers 240a, 240b, and 240c may be formed of aluminum or the like having a resistivity lower than that of copper forming the second metal layers 240a, 240b, and 240c.

[0165] An interlayer insulating layer 215 may be disposed on the first substrate 210 and cover the plurality of circuit elements 220a, 220b, and 220c, the first metal layers 230a, 230b, and 230c, and the second metal layers 240a, 240b, and 240c. The interlayer insulating layer 215 may include an insulating material such as silicon oxide, silicon nitride, or the like.

[0166] The lower bonding metals 271b and 272b may be formed on the second metal layer 240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b in the peripheral circuit area PERI may be electrically bonded to the upper bonding metals 371b and 372b of the cell area CELL. The lower bonding metals 271b and 272b and the upper bonding metals 371b and 372b may be formed of aluminum, copper, tungsten, etc., but example embodiments are not limited thereto. In addition, the upper bonding metals 371b and 372b in the cell area CELL may be referred to as first metal pads, and the lower bonding metals 271b and 272b in the peripheral circuit area PERI may be referred to as second metal pads.

[0167] The cell area CELL may include at least one memory block. The cell area CELL may include a second substrate 310 and a common source line 320. On the second substrate 310, a plurality of word lines 331 to 338 (e.g., 330) may be stacked in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310. At least one string selection line and at least one ground selection line may be arranged on and below the plurality of word lines 330, respectively, and the plurality of word lines 330 may be disposed between the at least one string selection line and the at least one ground selection line.

[0168] In the bit line bonding area BLBA, the channel structure CH may extend in a direction (Z-axis direction) perpendicular to the upper surface of the second substrate 310 and pass through a plurality of word lines 330, at least one string selection line, and at least one ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In example embodiments, the bit line 360c may extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 310.

[0169] exist Fig.12 In the example embodiment shown, a region in which a channel structure CH, a bit line 360c, etc. are provided may be defined as a bit line bonding region BLBA. In the bit line bonding region BLBA, the bit line 360c may be electrically connected to a circuit element 220c providing a page buffer 393 in the peripheral circuit region PERI. The bit line 360c may be connected to upper bonding metals 371c and 372c in the cell region CELL, and the upper bonding metals 371c and 372c may be connected to lower bonding metals 271c and 272c connected to the circuit element 220c of the page buffer 393.

[0170] In the word line bonding area WLBA, a plurality of word lines 330 may extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 310 and perpendicular to the first direction, and may be connected to a plurality of cell contact plugs 341 to 347 (e.g., 340). The plurality of word lines 330 and the plurality of cell contact plugs 340 may be connected to each other in a pad provided by at least a portion of the plurality of word lines 330 extending in different lengths in the second direction. The first metal layer 350b and the second metal layer 360b may be sequentially connected to the upper portions of the plurality of cell contact plugs 340, and the plurality of cell contact plugs 340 are connected to the plurality of word lines 330. The plurality of cell contact plugs 340 may be connected to the peripheral circuit area PERI through the upper bonding metals 371b and 372b of the cell area CELL in the word line bonding area WLBA and the lower bonding metals 271b and 272b of the peripheral circuit area PERI.

[0171] A plurality of cell contact plugs 340 may be electrically connected to the circuit elements 220 b, thereby forming a row decoder 394 in the peripheral circuit region PERI. In example embodiments, the operation voltage of the circuit elements 220 b of the row decoder 394 may be different from the operation voltage of the circuit elements 220 c forming the page buffer 393. For example, the operation voltage of the circuit elements 220 c forming the page buffer 393 may be greater than the operation voltage of the circuit elements 220 b forming the row decoder 394.

[0172] The common source line contact plug 380 may be disposed in the external pad bonding area PA. The common source line contact plug 380 may be formed of a conductive material such as a metal, a metal compound, polysilicon, etc., and may be electrically connected to the common source line 320. The first metal layer 350a and the second metal layer 360a may be sequentially stacked on an upper portion of the common source line contact plug 380. For example, a region in which the common source line contact plug 380, the first metal layer 350a, and the second metal layer 360a are disposed may be defined as the external pad bonding area PA.

[0173] The input-output pads 205 and 305 may be disposed in the external pad bonding area PA. Fig.12 , a lower insulating film 201 covering the lower surface of the first substrate 210 may be formed under the first substrate 210, and a first input-output pad 205 may be formed on the lower insulating film 201. The first input-output pad 205 may be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI through the first input-output contact plug 203, and may be separated from the first substrate 210 by the lower insulating film 201. In addition, a side insulating film may be disposed between the first input-output contact plug 203 and the first substrate 210 to electrically separate the first input-output contact plug 203 and the first substrate 210.

[0174] refer to Fig.12 , an upper insulating film 301 covering an upper surface of a second substrate 310 may be formed on the second substrate 310, and a second input-output pad 305 may be disposed on the upper insulating film 301. The second input-output pad 305 may be connected to at least one of a plurality of circuit elements 220a, 220b, and 220c disposed in the peripheral circuit region PERI through a second input-output contact plug 303. In some example embodiments, the second input-output pad 305 is electrically connected to the circuit element 220a.

[0175] According to some example embodiments, the second substrate 310 and the common source line 320 may not be disposed in a region in which the second input-output contact plug 303 is disposed. In addition, the second input-output pad 305 may not overlap the word line 330 in the third direction (Z-axis direction). Fig.12 The second input-output contact plug 303 may be separated from the second substrate 310 in a direction parallel to the upper surface of the second substrate 310 , and may pass through the interlayer insulating layer 315 of the cell region CELL to be connected to the second input-output pad 305 .

[0176] According to some example embodiments, the first input-output pad 205 and the second input-output pad 305 may be selectively formed. For example, the memory device 400 may include only the first input-output pad 205 disposed on the first substrate 210 or the second input-output pad 305 disposed on the second substrate 310. Alternatively, the memory device 400 may include both the first input-output pad 205 and the second input-output pad 305.

[0177] The metal pattern provided on the uppermost metal layer may be provided as a dummy pattern, or the uppermost metal layer may not exist in each of the external pad bonding area PA and the bit line bonding area BLBA respectively included in the cell area CELL and the peripheral circuit area PERI.

[0178] In the external pad bonding area PA, the memory device 400 may include a lower metal pattern 273a in the uppermost metal layer of the peripheral circuit area PERI, the lower metal pattern 273a corresponding to the upper metal pattern 372a formed in the uppermost metal layer of the cell area CELL, and having the same cross-sectional shape as the upper metal pattern 372a of the cell area CELL so as to be connected to each other. In the peripheral circuit area PERI, the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI may not be connected to the contact. Similarly, in the external pad bonding area PA, an upper metal pattern 372a corresponding to the lower metal pattern 273a formed in the uppermost metal layer of the peripheral circuit area PERI and having the same shape as the lower metal pattern 273a of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL.

[0179] Lower bonding metals 271b and 272b may be formed on the second metal layer 240b in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 271b and 272b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 371b and 372b of the cell area CELL through Cu-to-Cu bonding.

[0180] Furthermore, in the bit line bonding area BLBA, an upper metal pattern 392 corresponding to the lower metal pattern 252 formed in the uppermost metal layer of the peripheral circuit area PERI and having the same cross-sectional shape as the lower metal pattern 252 of the peripheral circuit area PERI may be formed in the uppermost metal layer of the cell area CELL. A contact may not be formed on the upper metal pattern 392 formed in the uppermost metal layer of the cell area CELL.

[0181] In example embodiments, corresponding to the metal pattern formed in the uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, an enhanced metal pattern having the same cross-sectional shape as the metal pattern may be formed in the uppermost metal layer in the other of the cell region CELL and the peripheral circuit region PERI. A contact may not be formed on the enhanced metal pattern.

[0182] Fig.13 is a block diagram of a storage system according to an example embodiment.

[0183] refer to Fig.13 , the storage system 1000 may include a host device 1100 and a storage device 1200. In an example embodiment, the storage device 1200 may include a reference Figures 1 to 13 The storage device 100 described herein. The storage device 1200 may include a high-capacity storage medium, such as a solid-state drive (SSD). The storage device 1200 may be included in one of information processing devices that are configured to process various information and store the processed information, such as a personal computer, a laptop, a server, a workstation, a smart phone, a tablet computer, a digital camera, a black box, etc. However, example embodiments are not limited thereto. The storage device 1200 may be implemented in various forms and may be included in various devices or various systems.

[0184] In example embodiments, the host device 1100 may include a host controller 1110 and a host memory 1120. The host memory 1120 may function as a buffer memory for temporarily storing data to be transmitted to or from the storage device 1200.

[0185] According to example embodiments, the host controller 1110 and the host memory 1120 may be implemented as separate semiconductor chips. Alternatively, in some example embodiments, the host controller 1110 and the host memory 1120 may be integrated into the same semiconductor chip. For example, the host controller 1110 may be one of a plurality of modules included in an application processor, wherein the application processor may be implemented as a system on chip (SoC). In addition, the host memory 1120 may include an embedded memory provided within the application processor, or may include a non-volatile memory or a memory module arranged outside the application processor.

[0186] The host controller 1110 may store data (eg, write data) in a buffer of the host memory 1120 of the nonvolatile memory device 1230 , or may manage an operation of storing data (eg, read data) of the nonvolatile memory device 1230 in a buffer thereof.

[0187] The host device 1100 may be configured to control the storage device 1200. For example, the host device 1100 may store data in the storage device 1200 or read data stored in the storage device 1200 based on a preset interface. In an example embodiment, the preset interface may include a non-volatile memory express (NVMe) interface. However, the example embodiment is not limited thereto. The preset interface may include at least one of various interfaces, such as an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a small computer mini interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnect (PCI), PCI Express (PCIe), a universal flash memory (UFS), IEEE 1394, a universal serial bus (USB), a secure digital (SD) card, a multimedia card (MMC), an embedded MMC (eMMC), an embedded UFS (eUFS), a compact flash (CF) card interface, and a computing eXpress link (CXL) interface.

[0188] The storage device 1200 may include a storage controller 1210, a buffer chip 1220, and a non-volatile storage device 1230. The storage controller 1210 may include a reference Figures 1 to 12 The memory controller 110. The buffer chip 1220 may include a reference Figures 1 to 12 The buffer chip 120. The non-volatile storage device 1230 may include a reference Figures 1 to 12 The storage device 130.

[0189] The storage controller 1210 may operate under the control of the host device 1100. For example, the storage controller 1210 may store data in the nonvolatile storage device 1230 or provide data stored in the nonvolatile storage device 1230 to the host device 1100 under the control of the host device 1100. In an example embodiment, the storage controller 1210 may perform various management operations under the control of the host device 1100. In an example embodiment, these management operations may include setting various information of the storage device 1200 or providing various information set in the storage device 1200 to the host device 1100.

[0190] The storage controller 1210 may include a processor 1211, a buffer memory 1212, an error correction code (ECC) engine 1213, a host interface circuit 1214, and a memory interface circuit 1215. The processor 1211 may be responsible for controlling the overall operation of the storage controller 1210. For example, the processor 1211 may run an operating system or firmware to drive the storage controller 1210. Based on a request from the host device 1100, the processor 1211 may generate commands and addresses to control the non-volatile storage device 1230.

[0191] The buffer memory 1212 may temporarily store data to be stored in the nonvolatile memory device 1230 or data read from the nonvolatile memory device 1230. The buffer memory 1212 may be configured to store various information required for the operation of the memory controller 1210. For example, the buffer memory 1212 may be configured to store a mapping table for accessing the nonvolatile memory device 1230. In an example embodiment, the buffer memory 1212 may include a random access memory. For example, the buffer memory 1212 may include a static random access memory or a dynamic random access memory.

[0192] The ECC engine 1213 may perform ECC encoding on user data to be stored in the nonvolatile memory device 1230 and generate parity data. The generated parity data may be stored in the nonvolatile memory device 1230 together with the user data. The ECC engine 1213 may be configured to perform ECC decoding based on the parity data and the user data read from the nonvolatile memory device 1230 to correct errors in the user data.

[0193] The host interface circuit 1214 may be configured to communicate with the host device 1100. In example embodiments, the host interface circuit 1214 may be configured to comply with a preset interface, communication protocol, or communication standard between the host device 1100 and the storage device 1200.

[0194] The memory interface circuit 1215 may be configured to access the nonvolatile memory device 1230. For example, the memory interface circuit 1215 may be configured to access the nonvolatile memory device 1230 based on a command and an address generated by the processor 1211 for controlling the nonvolatile memory device 1230. In an example embodiment, the memory interface circuit 1215 may communicate with the nonvolatile memory device 1230 based on an interface or protocol determined based on a standard or determined by a manufacturer. In an example embodiment, the above-mentioned interface or protocol may include a toggle interface or an open NAND flash interface (ONFI).

[0195] The nonvolatile memory device 1230 may operate under the control of the memory controller 1210. The nonvolatile memory device 1230 may include a plurality of nonvolatile memories NVM1 to NVM4. However, example embodiments are not limited thereto. The number of nonvolatile memories may be increased or decreased according to specific implementation circumstances.

[0196] In an example embodiment, the plurality of nonvolatile memories NVM1 to NVM4 included in the nonvolatile memory device 1230 may communicate with the storage controller 1210 through a plurality of channels and form a plurality of channels. For example, each of the plurality of nonvolatile memories NVM1 to NVM4 may include a memory die. In an example embodiment, the nonvolatile memory device 1230 may be configured based on a NAND flash memory. However, the exemplary embodiment is not limited thereto. The nonvolatile memory device 1230 may be configured based on at least one of various nonvolatile memory devices, such as a phase change memory, a ferroelectric memory, a magnetic memory, and a resistive memory. For example, the first storage area may include a first nonvolatile memory NVM1 and a second nonvolatile memory NVM2, and the second storage area may include a third nonvolatile memory NVM3 and a fourth nonvolatile memory NVM4.

[0197] In an example embodiment, the buffer chip 1220 may receive a chip enable signal CE and a command / address signal CA from the memory controller 1210. The buffer chip 1220 may receive a data signal DQ from the memory controller 1210, or send a data signal DQ to the memory controller 1210. In an example embodiment, the buffer chip 1220 may receive a command / address signal CA from the memory controller 1210 through a command / address line. The buffer chip 1220 may send a data signal DQ to the memory controller 1210 through a data line, or receive a data signal DQ from the memory controller 1210. The command / address line and the data line may include separate lines. The command / address line and the data line may include different lines. The command / address line and the data line may include separate lines.

[0198] In an example embodiment, the chip enable signal CE may not control the data signal DQ. The chip enable signal CE may control the command / address signal CA. The command / address signal CA may be activated based on the chip enable signal CE. For example, the chip enable signal CE may include a command / address chip enable signal.

[0199] In example embodiments, the first and second nonvolatile memories NVM1 and NVM2 may be connected to first command / address lines and first data lines. The third and fourth nonvolatile memories NVM3 and NVM4 may be connected to second command / address lines and second data lines.

[0200] The first nonvolatile memory NVM1 and the second nonvolatile memory NVM2 may communicate with the buffer chip 1220 through the first command / address line and the first data line. The third nonvolatile memory NVM3 and the fourth nonvolatile memory NVM4 may communicate with the buffer chip 1220 through the second command / address line and the second data line. However, example embodiments are not limited thereto. According to an embodiment, the number of nonvolatile memories sharing the command / address line and the data line may be reduced or increased.

[0201] In example embodiments, the buffer chip 1220 may transmit a first command / address signal CA_1 to the first nonvolatile memory NVM1. The buffer chip 1220 may transmit a first data signal DQ_1 to and receive a first data signal DQ_1 from the first nonvolatile memory NVM1. The buffer chip 1220 may transmit the first command / address signal CA_1 to the first nonvolatile memory NVM1 through the first command / address line. At the same time, the buffer chip 1220 may also transmit and receive a first data signal DQ_1 to and from the first nonvolatile memory NVM1 through the first data line.

[0202] In example embodiments, the buffer chip 1220 may transmit a first command / address signal CA_1 to the second nonvolatile memory NVM2. The buffer chip 1220 may transmit a first data signal DQ_1 to and receive a first data signal DQ_1 from the second nonvolatile memory NVM2. The buffer chip 1220 may transmit the first command / address signal CA_1 to the second nonvolatile memory NVM2 through a first command / address line. The buffer chip 1220 may transmit the first data signal DQ_1 to and receive a first data signal DQ_1 from the second nonvolatile memory NVM2 through a first data line.

[0203] In example embodiments, the buffer chip 1220 may transmit a second command / address signal CA_2 to the third nonvolatile memory NVM3. The buffer chip 1220 may transmit a second data signal DQ_2 to the third nonvolatile memory NVM3 and receive a first data signal DQ_2 from the third nonvolatile memory NVM3. The buffer chip 1220 may transmit the second command / address signal CA_2 to the third nonvolatile memory NVM3 through a second command / address line. The buffer chip 1220 may transmit a second data signal DQ_2 to the third nonvolatile memory NVM3 and receive a first data signal DQ_2 from the third nonvolatile memory NVM3 through a second data line.

[0204] In example embodiments, the buffer chip 1220 may transmit a second command / address signal CA_2 to the fourth nonvolatile memory NVM4. The buffer chip 1220 may transmit a second data signal DQ_2 to the fourth nonvolatile memory NVM4 and receive a first data signal DQ_2 from the fourth nonvolatile memory NVM4. The buffer chip 1220 may transmit the second command / address signal CA_2 to the fourth nonvolatile memory NVM4 through a second command / address line. The buffer chip 1220 may transmit the second data signal DQ_2 to the fourth nonvolatile memory NVM4 and receive a first data signal DQ_2 from the fourth nonvolatile memory NVM4 through a second data line.

[0205] In example embodiments, the first command / address line and the first data line may include separate lines. The second command / address line and the second data line may include separate lines. The second command / address line and the first command / address line may include separate lines. The second data line and the first data line may include separate lines.

[0206] In an example embodiment, the buffer chip 1220 is capable of bidirectional communication of command / address signals and data signals independently and simultaneously with other non-volatile memories. When the buffer chip 1220 sends data to the first storage area and receives data from the first storage area through the first data line, the buffer chip 1220 can send commands / addresses to the second storage area through the second command / address line. Alternatively, when the buffer chip 1220 sends commands / addresses to the first storage area through the first command / address line, the buffer chip 1220 can send data to the second storage area and receive data from the second storage area through the second data line. For example, when the buffer chip 1220 communicates with the first non-volatile memory NVM1 or the second non-volatile memory NVM2 through the first data line, the buffer chip 1220 can communicate with the third non-volatile memory NVM3 or the fourth non-volatile memory NVM4 through the second command / address line.

[0207] For example, when the buffer chip 1220 sends the first command / address signal CA_1 to the first nonvolatile memory NVM1 through the first command / address line, the buffer chip 1220 may receive the second data signal DQ_2 from the third nonvolatile memory NVM2 through the second data line. For example, when the buffer chip 1220 sends data to the first nonvolatile memory NVM1 through the first data line, the buffer chip 1220 may send a command / address to the third nonvolatile memory NVM3 through the second command / address line.

[0208] One or more of the elements disclosed above may include or be implemented in a processing circuit, such as hardware including logic circuits; a hardware / software combination, such as a processor that executes software; or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0209] While the inventive concepts have been particularly shown and described with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, comprising: a memory controller configured to generate at least one of a chip enable signal and a command / address signal; a buffer chip configured to receive the chip enable signal, the command / address signal, and a data signal from the memory controller; as well as a memory device comprising at least one storage area configured to perform at least one of a write operation and a read operation based on the command / address signal and the data signal received by the buffer chip, The buffer chip includes a first channel configured to receive the chip enable signal or the command / address signal and a second channel configured to receive the data signal. The first channel and the second channel are configured to transmit signals received through separate paths to corresponding storage areas of the at least one storage area.

2. The storage device according to claim 1, wherein: The buffer chip also includes a decoder for decoding the command / address signal, and The buffer chip is configured to determine a first storage area with which the first channel communicates based on a result of decoding the command / address signal.

3. The storage device according to claim 2, wherein: The buffer chip is configured to determine a second storage area with which the second channel communicates based on a result of decoding the command / address signal.

4. The storage device according to claim 1, wherein: The buffer chip is configured to transfer the data signal with the second storage area through the second channel when the command / address signal is sent to the first storage area through the first channel.

5. The storage device according to claim 1, wherein: The memory device includes a plurality of chips, and The buffer chip is configured to independently exchange signals with each of the multiple chips.

6. The storage device according to claim 1, wherein: The first channel includes a first switch configured to control transmission of the command / address signal and a second switch configured to control transmission of the data signal, and The second channel includes a third switch configured to control the transmission of the command / address signal and a fourth switch configured to control the transmission of the data signal.

7. The storage device according to claim 1, wherein: The first channel is configured to transmit the command / address signal to a plurality of die included in the memory device.

8. A method for operating a storage device, the method comprising: generating at least one of a chip enable signal and a command / address signal; receiving the chip enable signal, the command / address signal and the data signal; as well as performing at least one of a write operation and a read operation based on the received command / address signal and the data signal, Wherein, the receiving of the chip enable signal, the command / address signal and the data signal comprises: receiving the chip enable signal or the command / address signal through the first channel, receiving the data signal through a second channel different from the first channel, and The received signal is transmitted to a corresponding storage area of ​​the at least one storage area.

9. The method according to claim 8, wherein: The receiving of the chip enable signal, the command / address signal, and the data signal further includes decoding the command / address signal.

10. The method according to claim 9, wherein: The decoding of the command / address signal includes determining a first storage area with which the first channel communicates based on a result of decoding the command / address signal.

11. The method according to claim 9, wherein: The decoding of the command / address signal further includes determining a second storage area with which the second channel communicates based on a result of decoding the command / address signal.

12. The method according to claim 8, wherein: The receiving of the chip enable signal, the command / address signal, and the data signal further includes transmitting the data signal with a second storage area through the second channel when the command / address signal is sent to a first storage area through the first channel.

13. The method according to claim 8, wherein: The receiving of the chip enable signal, the command / address signal, and the data signal further includes independently exchanging signals with each of a plurality of chips of a memory device.

14. The method according to claim 8, wherein: The receiving of the chip enable signal, the command / address signal, and the data signal further comprises: controlling a first switch configured to control transmission of the command / address signal and a second switch configured to control transmission of the data signal; and A third switch configured to control transmission of the command / address signal and a fourth switch configured to control transmission of the data signal are controlled.

15. The method according to claim 8, wherein: The receiving of the chip enable signal, the command / address signal, and the data signal further includes sending the command / address signal to a plurality of die included in a memory device.

16. A buffer chip, comprising: A first channel is configured to receive a chip enable signal or a command / address signal; as well as The second channel is configured to receive a data signal, The first channel and the second channel are further configured to send signals received through separate paths to corresponding storage areas in at least one storage area.

17. The buffer chip according to claim 16, wherein: The first channel also includes a decoder for decoding the command / address signal, and The buffer chip is configured to determine a first storage area with which the first channel communicates based on a result of decoding the command / address signal.

18. The buffer chip according to claim 17, wherein: The first channel is configured to determine a second storage area with which the second channel communicates based on a result of decoding the command / address signal.

19. The buffer chip according to claim 16, wherein: The buffer chip is configured to transfer the data signal with the second storage area through the second channel when the command / address signal is sent to the first storage area through the first channel.

20. The buffer chip according to claim 16, wherein: The first channel and the second channel are configured to independently exchange signals with each chip of a plurality of chips included in a memory device.

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