Reference unit, initialization method and circuit thereof, and STT-MRAM

Abstract

The invention discloses a reference unit and an initialization method and circuit thereof, and an STT-MRAM, and relates to the technical field of memorizers, the reference unit comprises two branches which are connected in parallel, each branch comprises a first tunnel junction, a heavy metal layer and a second tunnel junction which are stacked and connected in series along a first direction, and the first tunnel junction and the second tunnel junction are arranged in a mirror image manner relative to the heavy metal layer, the free layers of the two tunnel junctions are adjacent to the heavy metal layers, and the heavy metal layers of the two branches are electrically connected, so that a one-way current along a second direction is introduced into the heavy metal layers of the two branches, the second direction is perpendicular to the first direction, heavy metal atoms have a very strong spin-orbit coupling effect, and the heavy metal layers of the two branches are electrically connected with the free layers of the two tunnel junctions. The four tunnel junctions of the two branches can be initialized at the same time at a time, the resistance states of the two tunnel junctions of the same branch are complementary, the reference unit initialization circuit structure is simplified, and on-chip resources of the STT-MRAM are saved to a great extent.

Description

Technical Field

[0001] The present application relates to the field of memory technology, and in particular to a reference unit and an initialization method and circuit thereof, and an STT-MRAM. Background Art

[0002] As a new type of memory, magnetic random access memory (MRAM) is considered by the industry to have great application prospects in the field of embedded memory due to its high reliability, non-volatility, high speed, and sustainable miniaturization. It has become one of the essential technologies for international mainstream semiconductor foundries. Among them, spin transfer torque-magnetic memory (Spin Transfer Torque MRAM, referred to as STT-MRAM) has been mass-produced at the 28nm~12nm process node, and related products have completely replaced eFlash in automotive MCU (Microcontroller Unit) and portable mobile terminal devices.

[0003] STT-MRAM uses a magnetic tunnel junction (MTJ) as a storage unit. The magnetic tunnel junction includes a free layer, a tunnel layer, and a fixed layer. The magnetic field polarization direction of the free layer can be changed, while the magnetic field direction of the fixed layer is fixed. When current passes through the fixed layer, due to the fixed magnetization direction of the fixed layer, electrons will be polarized when passing through the fixed layer, forming a spin-polarized current. The electrons in the spin-polarized current carry spin momentum. When these electrons pass through the insulating tunnel layer to reach the free layer, they will transfer the spin momentum to the magnetic moment of the free layer. The magnetic moment of the free layer rotates according to the direction of the spin-polarized current. When the direction of the spin-polarized current is the same as the magnetization direction of the fixed layer, the magnetic moment of the free layer tends to be parallel to the magnetization direction of the fixed layer, and the storage unit presents a low-resistance state "0"; otherwise, it tends to be anti-parallel, and the storage unit presents a high-resistance state "1".

[0004] The readout circuit of STT-MRAM determines whether the stored data is "0" or "1" by detecting the resistance of the memory cell. However, in the actual chip, the resistance state of the memory cell cannot be directly measured. Instead, a reference cell with a fixed resistance is designed in the readout circuit, and the resistance of the reference cell is between the high resistance state and the low resistance state of the memory cell. The constant current or constant voltage mode is used to compare the output voltage or current of the memory cell and the reference cell to determine the storage state of the data. Therefore, the design of the reference cell is also one of the key factors affecting the reliability of STT-MRAM.

[0005] During long-term use of STT-MRAM, the characteristics of its reference cell will deteriorate. Therefore, the reference cell often needs to be reset (i.e., initialized). However, existing reference cells have the problem of complex initialization operations. Summary of the invention

[0006] In order to solve the above technical problems, the embodiments of the present application provide a reference cell and its initialization method and circuit, and STT-MRAM, so as to realize the initialization operation of each tunnel junction in the reference cell at one time, simplify the reference cell initialization circuit structure, and save the on-chip resources of the STT-MRAM to a great extent.

[0007] To achieve the above objectives, the present application provides the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a reference unit, which is applied to STT-MRAM, wherein the reference unit includes two branches connected in parallel, each of which includes:

[0009] a heavy metal layer having a first surface and a second surface opposite to each other along a first direction;

[0010] A first tunnel junction, located on the first surface of the heavy metal layer, the first tunnel junction comprising a first free layer, a first tunnel layer and a first fixed layer stacked in a direction away from the heavy metal layer;

[0011] a second tunnel junction, located on the second surface of the heavy metal layer, the second tunnel junction comprising a second free layer, a second tunnel layer, and a second fixed layer stacked in a direction away from the heavy metal layer, the first fixed layer and the second fixed layer having the same magnetic moment direction;

[0012] The first tunnel junction and the second tunnel junction of the same branch have complementary resistance states;

[0013] The first fixed layers of the first tunnel junctions of the two branches are electrically connected, the second fixed layers of the second tunnel junctions of the two branches are electrically connected, and the heavy metal layers of the two branches are electrically connected;

[0014] The reference unit implements a readout operation by passing a unidirectional current along the first direction into the two branches, and implements an initialization operation by passing a unidirectional current along a second direction into the heavy metal layers of the two branches, wherein the second direction is perpendicular to the first direction.

[0015] Optionally, the heavy metal layers of the two branches are electrically connected including:

[0016] The heavy metal layers of the two branches are connected at the same layer.

[0017] Optionally, the material of the heavy metal layer includes tantalum (Ta), tungsten (W) or iridium (Ir).

[0018] Optionally, the thickness of the heavy metal layer along the first direction ranges from 3 nm to 5 nm, including endpoint values.

[0019] In a second aspect, an embodiment of the present application provides a reference cell initialization method, wherein the reference cell is applied to STT-MRAM, and the reference cell is any of the above-mentioned reference cells, and the reference cell initialization method includes:

[0020] By passing a unidirectional current along the second direction into the heavy metal layer of the two branches in the reference unit, the first tunnel junction and the second tunnel junction of the two branches in the reference unit are initialized simultaneously, so that the resistance states of the first tunnel junction and the second tunnel junction of the same branch in the reference unit are complementary.

[0021] In a third aspect, an embodiment of the present application provides a reference unit initialization circuit, wherein the reference unit is applied to STT-MRAM, the reference unit is any of the above-mentioned reference units, and the reference unit initialization circuit includes a driving circuit and a first switch tube;

[0022] The first end of the driving circuit receives a first control signal, and the first switch tube is closed or turned off under the control of a second control signal;

[0023] The second end and the third end of the driving circuit form a loop through the first switch tube and the heavy metal layers of the two branches in the reference unit;

[0024] When the first control signal and the second control signal are both enable signals, the first switch tube is closed, and the driving circuit passes a unidirectional current along the second direction to the heavy metal layer of the two branches in the reference unit, and the first tunnel junction and the second tunnel junction of the two branches in the reference unit are initialized simultaneously, so that the resistance states of the first tunnel junction and the second tunnel junction of the same branch in the reference unit are complementary.

[0025] In a fourth aspect, an embodiment of the present application provides an STT-MRAM, comprising any of the above-mentioned reference units.

[0026] Optionally, the STT-MRAM further includes a reference cell initialization circuit, wherein the reference cell initialization circuit includes a driving circuit and a first switch tube;

[0027] The first end of the driving circuit receives a first control signal, and the first switch tube is closed or turned off under the control of a second control signal;

[0028] The second end and the third end of the driving circuit form a loop through the first switch tube and the heavy metal layers of the two branches in the reference unit;

[0029] When the first control signal and the second control signal are both enable signals, the first switch tube is closed, and the driving circuit passes a unidirectional current along the second direction to the heavy metal layer of the two branches in the reference unit, and the first tunnel junction and the second tunnel junction of the two branches in the reference unit are initialized simultaneously, so that the resistance states of the first tunnel junction and the second tunnel junction of the same branch in the reference unit are complementary.

[0030] Optionally, the STT-MRAM further includes:

[0031] A memory cell array, the memory cell array comprising a plurality of memory cells;

[0032] A readout circuit is configured to read out the storage state of the selected storage cell by comparing the discharge speed of the selected storage cell with that of the reference cell under the same power supply potential.

[0033] Optionally, the readout circuit includes a pre-charging circuit and a discharging circuit;

[0034] The storage unit is electrically connected between the pre-charging circuit and the discharging circuit through a one-to-one corresponding first selection tube, the reference unit is electrically connected between the pre-charging circuit and the discharging circuit through a second selection tube, and the storage unit and the reference unit are connected to the power supply potential through the pre-charging circuit, and the storage unit and the reference unit are grounded through the discharging circuit;

[0035] When the readout circuit performs a readout operation on the selected storage cell, in the first period, the discharge circuit is turned off, and the precharge circuit precharges the potential of the selected storage cell and the end of the reference cell connected to the precharge circuit to the power supply potential; and then in the second period, the selected storage cell and the reference cell are discharged through the discharge circuit at the same power supply potential, and the precharge circuit outputs the storage state of the selected storage cell based on the discharge speed of the selected storage cell and the reference cell at the same power supply potential. Compared with the prior art, the above technical solution has the following advantages:

[0036] The reference unit provided in the embodiment of the present application is applied to STT-MRAM, and the reference unit includes two branches connected in parallel, each branch includes a first tunnel junction, a heavy metal layer, and a second tunnel junction connected in series in sequence, the heavy metal layer has a first surface and a second surface opposite to each other along a first direction, the first tunnel junction is located on the first surface of the heavy metal layer, the second tunnel junction is located on the second surface of the heavy metal layer, and the arrangement order of the first free layer, the first tunnel layer, and the first fixed layer of the first tunnel junction is mirrored with respect to the arrangement order of the second free layer, the second tunnel layer, and the second fixed layer of the second tunnel junction along the first direction. The first free layer of the first tunnel junction and the second free layer of the second tunnel junction are both adjacent to the heavy metal layer; and the resistance states of the first tunnel junction and the second tunnel junction of the same branch are complementary, that is, when the first tunnel junction is in a high resistance state, the second tunnel junction is in a low resistance state, or when the first tunnel junction is in a low resistance state, the second tunnel junction is in a high resistance state, so that when the magnetic moment directions of the first fixed layer and the second fixed layer are the same, the magnetic moment directions of the first free layer and the second free layer are opposite; and the first fixed layers of the first tunnel junctions of the two branches are electrically connected, the second fixed layers of the second tunnel junctions of the two branches are electrically connected, and the two branches are In this way, the four tunnel junctions of the two branches are connected in series in their respective branches and then in parallel with each other. The equivalent resistance of the reference unit is between the low resistance state and the high resistance state of the tunnel junction of the storage unit. On the one hand, the read operation can be realized by passing a unidirectional current along a first direction into the two branches of the reference unit. On the other hand, a unidirectional current along a second direction can be passed into the heavy metal layers of the two branches of the reference unit. The second direction is perpendicular to the first direction. Therefore, due to the strong spin-orbit coupling effect of the heavy metal atoms, the first surface and the second surface of the heavy metal layer opposite to each other along the first direction are separated. Polarized electrons with opposite spin directions are accumulated separately, inducing the magnetic moments of the first free layer of the first tunnel junction and the second free layer of the second tunnel junction of the same branch to flip in opposite directions, and the initialization operation of the first tunnel junction and the second tunnel junction of the same branch is simultaneously realized, so that the resistance states of the first tunnel junction and the second tunnel junction of the same branch are complementary. Since the heavy metal layers of the two branches are electrically connected, the initialization operation of the four tunnel junctions of the two branches in the reference unit can be realized at one time, which can simplify the reference unit initialization circuit structure and save the on-chip resources of the STT-MRAM to a great extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0038] Figure 1A schematic diagram of the structure of a reference cell and its initialization circuit in an existing STT-MRAM;

[0039] Figure 2 A schematic diagram of the structure of a reference unit provided in an embodiment of the present application;

[0040] Figure 3 A schematic diagram of the structure of another reference unit provided in an embodiment of the present application;

[0041] Figure 4 A schematic diagram of the structure of a reference unit initialization circuit provided in an embodiment of the present application;

[0042] Figure 5 A schematic diagram of a partial circuit structure of an STT-MRAM provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and need not be used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, which is only to describe the distinction mode adopted by the objects of the same attributes when describing in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0045] In existing STT-MRAM, its reference cell is usually cascaded using the same spin-transfer torque-magnetic tunnel junction (STT-MTJ) as its storage cell. Figure 1 FIG. 4 shows a schematic diagram of a reference cell and its initialization circuit in an existing STT-MRAM. Figure 1 As shown, the reference cell REF cell0 includes four tunnel junctions MTJ, each tunnel junction MTJ includes a stacked fixed layer PL, a tunnel layer I and a free layer FL, and the fixed layer PL, the tunnel layer I and the free layer FL in each tunnel junction MTJ are arranged in the same order. It can be seen that Figure 1The magnetic moment directions of the fixed layer PL and the free layer FL in the two tunnel junctions MTJ above ( Figure 1 The two tunnel junctions MTJ are in the same direction as the arrows, and are in the low resistance state RL. Figure 1 The magnetic moment directions of the fixed layer PL and the free layer FL in the two tunnel junctions MTJ in the middle and lower parts ( Figure 1 The two tunnel junctions MTJ are in the high-resistance state RH. Figure 1 In the reference cell REF cell0 shown, two tunnel junctions MTJ with complementary resistance states are connected in series and then in parallel. This approach can provide the largest readout window. It should be noted that Figure 1 The four tunnel junctions MTJ can be arranged in parallel. Figure 1 The “above” and “below” in the text do not represent actual positional relationships.

[0046] During the use of STT-MRAM, the characteristics of the tunnel junction will decay, causing the electrical parameters of the reference cell to drift, affecting the readout reliability, so the reference cell needs to be initialized from time to time. Figure 1 As shown, the reference cell initialization circuit includes a driving circuit Driver0, a switch tube T0, a switch tube T1 and a switch tube T2, and the initialization operation of the reference cell REF cell0 is as follows: when the control signal ENW0 of the driving circuit Driver0, the control signal WR0 of the switch tube T0 and the control signal WR1 of the switch tube T1 are enable signals, the switch tubes T0 and the switch tube T1 are both closed, and other transistors are disconnected, and the driving circuit Driver0 can initialize the two tunnel junctions MTJ in the reference cell REF cell0 that are in a low resistance state RL through the switch tubes T0 and the switch tube T1; when the control signal ENW0 of the driving circuit Driver0, the control signal WR0 of the switch tube T0 and the control signal WR2 of the switch tube T2 are enable signals, the switch tubes T0 and the switch tube T2 are both closed, and other transistors are disconnected, and the driving circuit Driver0 can initialize the two tunnel junctions MTJ in the reference cell REF cell0 that are in a high resistance state RH through the switch tubes T0 and the switch tube T2.

[0047] From this we can see that we need Figure 1 The four tunnel junctions MTJs in the reference cell REF cell0 shown in the figure need to be initialized at least twice to complete the initialization of the four tunnel junctions MTJs. Some of the prior art even require initialization of each tunnel junction in the reference cell bit by bit, which not only increases the complexity of the initialization operation of the reference cell, but also makes the reference cell initialization circuit structure more complicated, wasting on-chip resources, especially the initialization operation of the reference cell is used less frequently, which is not worth the loss for infrequent use.

[0048] In view of this, an embodiment of the present application provides a reference cell, which is applied to STT-MRAM. Figure 2 A schematic diagram of the structure of a reference unit provided in an embodiment of the present application is shown. Figure 2 As shown, the reference cell REFcell includes two branches 10 connected in parallel, and each branch 10 includes:

[0049] A heavy metal layer M1, the heavy metal layer M1 having a first surface S1 and a second surface S2 opposite to each other along a first direction X1;

[0050] A first tunnel junction MTJ1 is located on a first surface S1 of the heavy metal layer M1, and the first tunnel junction MTJ1 includes a first free layer FL1, a first tunnel layer I1, and a first fixed layer PL1 stacked in a direction away from the heavy metal layer M1;

[0051] The second tunnel junction MTJ2 is located on the second surface S2 of the heavy metal layer M1. The second tunnel junction MTJ2 includes a second free layer FL2, a second tunnel layer I2, and a second fixed layer PL2 which are stacked in a direction away from the heavy metal layer M1.

[0052] That is to say, in each branch 10, the arrangement order of the first free layer FL1, the first tunnel layer I1 and the first fixed layer PL1 of the first tunnel junction MTJ1 and the arrangement order of the second free layer FL2, the second tunnel layer I2 and the second fixed layer PL2 of the second tunnel junction MTJ2 are mirrored relative to the heavy metal layer along the first direction X1, and the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 are both adjacent to the heavy metal layer M1. In other words, in each branch 10, the second fixed layer PL2, the second tunnel layer I2, the second free layer FL2, the heavy metal layer M1, the first free layer FL1, the first tunnel layer I1 and the first fixed layer PL1 are stacked in sequence along the first direction X1, wherein the second fixed layer PL2, the second tunnel layer I2 and the second free layer FL2 constitute the second tunnel junction MTJ2, and the first free layer FL1, the first tunnel layer I1 and the first fixed layer PL1 constitute the second tunnel junction MTJ1. At this time, the first tunnel junction MTJ1 and the second tunnel junction MTJ2 are similar to a spin-orbit torque MTJ (STT-MTJ) configuration.

[0053] Moreover, the resistance states of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 are complementary, that is, when the first tunnel junction MTJ1 is in a high resistance state, the second tunnel junction MTJ2 is in a low resistance state, or when the first tunnel junction MTJ1 is in a low resistance state, the second tunnel junction MTJ2 is in a high resistance state. Thus, when the magnetic moment direction of the first fixed layer PL1 of the first tunnel junction MTJ1 and the second fixed layer PL2 of the second tunnel junction MTJ2 (such as Figure 2 When the first fixed layer PL1 and the second fixed layer PL2 are the same, the magnetic moment directions of the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 are opposite. Figure 2 The arrows on the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 are bidirectional arrows, indicating that the directions of the magnetic moments of the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 can change.

[0054] Moreover, if Figure 2 As shown, the first fixed layer PL1 of the first tunnel junction MTJ1 of the two branches 10 is electrically connected, or in other words, the first fixed layer PL1 of the first tunnel junction MTJ1 of the two branches 10 is electrically connected to the first end of the reference cell REF cell; the second fixed layer PL2 of the second tunnel junction MTJ2 of the two branches 10 is electrically connected, or in other words, the second fixed layer PL2 of the second tunnel junction MTJ2 of the two branches 10 is electrically connected to the second end of the reference cell REF cell; the heavy metal layers M1 of the two branches 10 are electrically connected, or in other words, one end of the heavy metal layer M1 of one branch 10 along the second direction X2 is electrically connected to the third end of the reference cell REF cell, the other end of the heavy metal layer M1 of one branch 10 along the second direction X2 is electrically connected to one end of the heavy metal layer M1 of the other branch 10 along the second direction X2, and the other end of the heavy metal layer M1 of the other branch 10 along the second direction X2 is electrically connected to the fourth end of the reference cell REF cell, and the second direction X2 is perpendicular to the first direction X1.

[0055] In this arrangement, the four tunnel junctions (two first tunnel junctions MTJ1 and two second tunnel junctions MTJ2) of the two branches 10 are connected in series in their respective branches and then in parallel to each other. In other words, in any branch 10, the first tunnel junction MTJ1, the heavy metal layer M1 and the second tunnel junction MTJ2 are connected in series in sequence, and the first free layer FL1 of the first tunnel junction MTJ1 is connected in series with the second free layer FL2 of the second tunnel junction MTJ2 through the heavy metal layer M1. Since the first fixed layer PL1 of the first tunnel junction MTJ1 of the two branches 10 is electrically connected, the second fixed layer PL2 of the second tunnel junction MTJ2 of the two branches 10 is electrically connected, and the heavy metal layer M1 of the two branches 10 is electrically connected, the two first tunnel junctions MTJ1 and the two second tunnel junctions MTJ2 are also connected in parallel to each other, so that the equivalent resistance of the reference cell REF cell is between the low resistance state and the high resistance state of the tunnel junction of the storage cell.

[0056] It can be understood that when the four tunnel junctions of the two branches 10 are the same, the equivalent resistance of the reference cell REF cell is 1 / 2 of the sum of the resistance of the same tunnel junction in the low resistance state and the resistance of the same tunnel junction in the high resistance state.

[0057] With the above settings, refer to Figure 2 As shown, the reference cell REF cell provided in the embodiment of the present application can, on the one hand, realize the readout operation by passing a unidirectional current J1 along the first direction X1 into the two branches 10, that is, by passing a unidirectional current J1 along the first direction X1 between the first end and the second end of the reference cell REF cell to realize the readout operation; on the other hand, by passing a unidirectional current J2 along the second direction X2 into the heavy metal layer M1 of the two branches 10 of the reference cell REF cell, that is, by passing a unidirectional current J2 along the second direction X2 between the first end and the second end of the reference cell REF cell to realize the readout operation; A unidirectional current J2 along the second direction X2 is passed between the third end and the fourth end of the cell, and the second direction X2 is perpendicular to the first direction X1. Therefore, due to the strong spin-orbit coupling effect of the heavy metal atoms, polarized electrons with opposite spin directions are accumulated on the first surface S1 and the second surface S2 of the heavy metal layer M1 opposite to each other along the first direction X1, respectively, inducing the magnetic moments of the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 of the same branch 10 to flip in opposite directions, and simultaneously realizing the initialization operation of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10. Since the heavy metal layers M1 of the two branches 10 are electrically connected, the initialization operation of the four tunnel junctions of the two branches 10 in the reference cell REF cell can be realized at one time, which can simplify the reference cell initialization circuit structure and save the on-chip resources of the STT-MRAM to a great extent.

[0058] It can be understood that since the magnetic moment directions of the first fixed layer PL1 of the first tunnel junction MTJ1 and the second fixed layer PL2 of the second tunnel junction MTJ2 are the same, and after the unidirectional current J2 along the second direction X2 is passed through the heavy metal layer M1, the magnetic moments of the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 of the same branch 10 are opposite in direction, thereby making the resistance states of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 complementary, one presents a high resistance state and the other presents a low resistance state.

[0059] It can also be understood that, in the present application, the first direction X1 is the stacking direction of the first tunnel junction MTJ1, the heavy metal layer M1 and the second tunnel junction MTJ2 in the same branch 10, and the second direction X2 is perpendicular to the first direction X1, or in other words, the second direction X2 is parallel to the first surface S1 and the second surface S2 of the heavy metal layer M1, so that when a unidirectional current along the second direction X2 is passed through the heavy metal layer M1, polarized electrons with opposite spin directions are accumulated on the first surface S1 and the second surface S2 of the heavy metal layer M1 opposite to each other along the first direction X1, respectively, inducing the magnetic moments of the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 of the same branch 10 to flip, and the flipping directions are opposite.

[0060] It can be further understood that, for the first tunnel junction MTJ1, the heavy metal layer M1 and the second tunnel junction MTJ2 stacked in the same branch 10, the second fixed layer PL2, the second tunnel layer I2 and the second free layer FL2 of the second tunnel junction MTJ2 can be prepared in sequence first, and then the heavy metal layer M1 is prepared on the second free layer FL2 of the second tunnel junction MTJ2, and then the first free layer FL1, the first tunnel junction I1 and the second fixed layer PL2 of the first tunnel junction MTJ2 are prepared in sequence on the side of the heavy metal layer M1 facing away from the second tunnel junction MTJ2.

[0061] Based on the above embodiments, optionally, in some embodiments of the present application, such as Figure 3 As shown, Figure 3 FIG. 1 is a schematic diagram showing the structure of another reference cell provided in an embodiment of the present application. It can be seen that the heavy metal layer M1 of the two branches 10 in the reference cell REF cell is electrically connected to include:

[0062] The heavy metal layers M1 of the two branches 10 in the reference cell REF cell are connected in the same layer, that is, the heavy metal layers M1 of the two branches 10 in the reference cell REF cell are the same heavy metal layer and are connected in the same layer.

[0063] With such arrangement, the first tunnel junctions MTJ1 of the two branches 10 are located on the same side of the same heavy metal layer M1 along the first direction X1, which facilitates the electrical connection of the first fixed layer PL1 of the first tunnel junctions MTJ1 of the two branches 10; similarly, the second tunnel junctions MTJ2 of the two branches 10 are located on the same side of the same heavy metal layer M1 along the first direction X1, which facilitates the electrical connection of the second fixed layer PL2 of the second tunnel junctions MTJ2 of the two branches 10; and, the heavy metal layer M1 of the two branches 10 is the same heavy metal layer, which is also conducive to simplifying the preparation process, so that the second tunnel junctions MTJ2 of the two branches 10 can be prepared at the same time, the heavy metal layers M1 of the two branches 10 can be prepared at the same time, and the first tunnel junctions MTJ1 of the two branches 10 can also be prepared at the same time.

[0064] Other options, such as Figure 2 As shown, the heavy metal layers M1 of the two branches 10 in the reference cell REF cell may also be electrically connected in other ways, such as through a connecting line.

[0065] On the basis of any of the above embodiments, optionally, in some embodiments of the present application, the material of the heavy metal layer M1 includes tantalum (Ta), tungsten (W) or iridium (Ir).

[0066] On the basis of any of the above embodiments, optionally, in some embodiments of the present application, the thickness of the heavy metal layer M1 along the first direction X1 ranges from 3nm to 5nm, including endpoint values, so that when a unidirectional current along the second direction X2 is passed through the heavy metal layer M1, polarized electrons with opposite spin directions are accumulated on the first surface S1 and the second surface S2 of the heavy metal layer M1 opposite to each other along the first direction X1, respectively, inducing the magnetic moments of the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 of the same branch 10 to flip, and the flipping directions are opposite.

[0067] Accordingly, an embodiment of the present application further provides a reference cell initialization method, wherein the reference cell is applied to STT-MRAM, and the reference cell is the reference cell provided by any of the above embodiments, Figure 2 and Figure 3 As shown, the reference unit initialization method includes:

[0068] By passing a unidirectional current along the second direction X2 into the heavy metal layer M1 of the two branches 10 in the reference cell REF cell, the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the two branches 10 in the reference cell REF cell are initialized simultaneously, so that the resistance states of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 in the reference cell REF cell are complementary.

[0069] It can be understood that by passing a unidirectional current J2 along the second direction X2 to the heavy metal layer M1 of the two branches 10 of the reference cell REF cell, that is, by passing a unidirectional current J2 along the second direction X2 between the third end and the fourth end of the reference cell REF cell, the heavy metal atoms have a strong spin-orbit coupling effect, so that polarized electrons with opposite spin directions are accumulated on the first surface S1 and the second surface S2 of the heavy metal layer M1 opposite to each other along the first direction X1, respectively, inducing the magnetic moments of the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 of the same branch 10 to flip in opposite directions, and at the same time, the initialization operation of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 is realized. Since the heavy metal layers M1 of the two branches 10 are electrically connected, the initialization operation of the four tunnel junctions of the two branches 10 in the reference cell REF cell can be realized at one time, which can simplify the reference cell initialization circuit structure and save the on-chip resources of the STT-MRAM to a great extent.

[0070] Furthermore, since the magnetic moment directions of the first fixed layer PL1 of the first tunnel junction MTJ1 and the second fixed layer PL2 of the second tunnel junction MTJ2 are the same, and after a unidirectional current J2 along the second direction X2 is passed through the heavy metal layer M1, the magnetic moments of the first free layer FL1 of the first tunnel junction MTJ1 and the second free layer FL2 of the second tunnel junction MTJ2 of the same branch 10 are in opposite directions, thereby making the resistance states of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 complementary, one presents a high resistance state and the other presents a low resistance state.

[0071] The embodiment of the present application further provides a reference unit initialization circuit, the reference unit is applied to STT-MRAM, and the reference unit is the reference unit provided by any of the above embodiments, Figure 4 A schematic diagram of the structure of a reference unit initialization circuit provided in an embodiment of the present application is shown, combined with Figure 2-Figure 4 As shown, the reference unit initialization circuit 100 includes a driving circuit Driver10 and a first switch tube T10;

[0072] The first end of the driving circuit Driver10 receives the first control signal ENW1, and the first switch tube T10 is closed or turned off under the control of the second control signal WR10;

[0073] The second end and the third end of the driving circuit Driver10 form a loop through the first switch tube T10 and the heavy metal layer M1 of the two branches 10 in the reference cell REF cell;

[0074] When the first control signal ENW1 and the second control signal WR10 are both enable signals, the first switch tube T10 is closed, and the driving circuit Driver10 passes a unidirectional current along the second direction X2 to the heavy metal layer M1 of the two branches 10 in the reference cell REF cell, and the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the two branches 10 in the reference cell REF cell are initialized simultaneously, so that the resistance states of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 in the reference cell REF cell are complementary.

[0075] Compared to Figure 1 The initialization circuit structure of the existing reference unit shown in the present application Figure 4 The structure of the reference cell initialization circuit 100 shown is simpler, and the number of transistors is reduced by more than half, thus greatly saving the on-chip resources of the STT-MRAM.

[0076] It is understandable that the initialization circuit that can perform the initialization operation on the reference unit provided in the embodiment of the present application is not limited to Figure 4 The reference cell initialization circuit 100 shown in the figure can realize simultaneous initialization of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the two branches 10 in the reference cell REF cell as long as the reference cell initialization circuit can pass a unidirectional current along the second direction X2 into the heavy metal layer M1 of the two branches 10 in the reference cell REF cell, so that the resistance states of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 in the reference cell REF cell are complementary.

[0077] Accordingly, the embodiment of the present application further provides a STT-MRAM, Figure 5 A schematic diagram of a local circuit structure of an STT-MRAM provided in an embodiment of the present application is shown. Figure 5 As shown, the STT-MRAM includes a reference cell REF cell, and the reference cell REF cell may be a reference cell provided by any of the above embodiments.

[0078] Optional, such as Figure 5 As shown, the STT-MRAM further includes a reference cell initialization circuit 100, and the reference cell initialization circuit 100 includes a driving circuit Driver10 and a first switch tube T10;

[0079] The first end of the driving circuit Driver10 receives the first control signal ENW1, and the first switch tube T10 is closed or turned off under the control of the second control signal WR10;

[0080] The second end and the third end of the driving circuit Driver10 form a loop through the first switch tube T10 and the heavy metal layer M1 of the two branches 10 in the reference cell REF cell;

[0081] When the first control signal ENW1 and the second control signal WR10 are both enable signals, the first switch tube T10 is closed, and the driving circuit Driver10 passes a unidirectional current along the second direction X2 to the heavy metal layer M1 of the two branches 10 in the reference cell REF cell, and the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the two branches 10 in the reference cell REF cell are initialized simultaneously, so that the resistance states of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 in the reference cell REF cell are complementary.

[0082] In this way, not only can the four tunnel junctions of the two branches 10 in the reference cell REF cell be initialized at one time, but the structure of the reference cell initialization circuit 100 can also be simplified, thus greatly saving on-chip resources of the STT-MRAM.

[0083] Optional, such as Figure 5 As shown, STT-MRAM also includes:

[0084] A memory cell array 200, the memory cell array 200 includes a plurality of memory cells Data cells, Figure 5 Only one storage unit Data cell (i.e., one STT-MTJ) is shown;

[0085] The read circuit 300 reads the storage state of the selected memory cell Data cell by comparing the discharge speed of the selected memory cell Data cell with the reference cell REFcell under the same power supply potential Vdd.

[0086] It can be understood that the equivalent resistance of the reference cell REF cell is between the low resistance state and the high resistance state of the tunnel junction of the selected memory cell Data cell. If the selected memory cell Data cell stores data "0", that is, the selected memory cell Data cell is in the low resistance state, under the same power supply potential Vdd, the selected memory cell Data cell is discharged faster than the reference cell REF cell; if the selected memory cell Data cell stores data "1", that is, the selected memory cell Data cell is in the high resistance state, under the same power supply potential Vdd, the selected memory cell Data cell is discharged slower than the reference cell REF cell. Therefore, the read circuit 300 can read the storage state of the selected memory cell Data cell by comparing the discharge speeds of the selected memory cell Data cell and the reference cell REF cell under the same power supply potential Vdd.

[0087] Optional, such as Figure 5 As shown, the readout circuit 300 includes a pre-charging circuit 310 and a discharging circuit 320;

[0088] The storage cell Data cell is electrically connected between the pre-charging circuit 310 and the discharging circuit 320 through the first gate transistor G1 corresponding to each other, and the reference cell REF cell is electrically connected between the pre-charging circuit 310 and the discharging circuit 320 through the second gate transistor G2. The storage cell Data cell and the reference cell REF cell are connected to the power supply potential Vdd through the pre-charging circuit 310, and the storage cell Data cell and the reference cell REF cell are grounded through the discharging circuit 320.

[0089] When the read circuit 300 performs a read operation on the selected memory cell Data cell, in the first period, the discharge circuit 320 is turned off, and the precharge circuit 310 precharges the potential of the selected memory cell Data cell and the end of the reference cell REF cell connected to the precharge circuit 310 to the power supply potential Vdd; then in the second period, the selected memory cell Data cell and the reference cell REF cell are discharged through the discharge circuit 320 at the same power supply potential Vdd, and the precharge circuit 310 outputs the storage state of the selected memory cell Data cell based on the discharge speed of the selected memory cell Data cell and the reference cell REF cell at the same power supply potential Vdd.

[0090] Specifically, Figure 5 As shown, the pre-charging circuit 310 includes six transistors from transistor G3 to transistor G8, and the electrical connection relationship between transistor G3 and transistor G8 is as follows: Figure 5As shown, no further details are given; the discharge circuit 320 includes a transistor G9.

[0091] Understandably, Figure 5 When the STT-MRAM shown performs the reference cell REF cell initialization operation, the first control signal ENW1 of the driving circuit Driver10 and the second control signal WR10 of the first switch tube T10 are both enable signals, the first switch tube T10 is closed, and the driving circuit Driver10 passes a unidirectional current along the second direction X2 to the heavy metal layer M1 of the two branches 10 in the reference cell REF cell, and simultaneously initializes the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the two branches 10 in the reference cell REF cell, so that the resistance states of the first tunnel junction MTJ1 and the second tunnel junction MTJ2 of the same branch 10 in the reference cell REF cell are complementary; at the same time, the control signals WL of the first gate tube G1 and the second gate tube G2 are both non-enable signals, controlling the first gate tube G1 and the second gate tube G2 to be turned off, and the control signal EN also controls the pre-charging circuit 310 of the readout circuit 300 to be turned off, and the readout circuit 300 does not perform a readout operation.

[0092] Figure 5 When the STT-MRAM shown in the figure performs a read operation, the first control signal ENW1 of the driving circuit Driver10 and the second control signal WR10 of the first switch tube T10 are both non-enable signals, the first switch tube T10 is turned off, and the reference cell initialization circuit 100 does not initialize the reference cell REF cell.

[0093] At this time, in the first time period, the control signal WL of the first selection tube G1 and the second selection tube G2 is a non-enable signal, the first selection tube G1 and the second selection tube G2 are turned off, and the control signal EN controls the transistor G9 of the discharge circuit 320 to be turned off, and the control signal EN controls the transistor G3 and the transistor G7 of the pre-charging circuit 310 to be closed, and the pre-charging circuit 310 pre-charges the potential of the selected storage cell Datacell and the reference cell REF cell connected to the pre-charging circuit 310 to the power supply potential Vdd.

[0094] Furthermore, in the second period, the control signal WL of the first gate transistor G1 and the second gate transistor G2 is an enable signal, the first gate transistor G1 and the second gate transistor G2 are closed, and the control signal EN controls the transistor G9 of the discharge circuit 320 to be closed, and the control signal EN controls the transistor G3 and the transistor G7 of the pre-charge circuit 310 to be turned off, and the selected storage cell Data cell and the reference cell REF cell are discharged through the discharge circuit 320 at the same power supply potential Vdd. If the selected storage cell Data cell stores data "0", that is, the selected storage cell Data cell is in a low-impedance state, under the same power supply potential Vdd, the selected storage cell Data cell is discharged faster than the reference cell REF cell, and the output terminal OUT of the readout circuit 300 outputs "0"; if the selected storage cell Data cell stores data "1", that is, the selected storage cell Data cell is in a high-impedance state, under the same power supply potential Vdd, the selected storage cell Data cell is discharged slower than the reference cell REF cell, and the output terminal OUT of the readout circuit 300 outputs "1".

[0095] The various parts in this manual are described in a combination of parallel and progressive ways. Each part focuses on the differences from other parts, and the same or similar parts between the various parts can be referenced to each other.

[0096] With respect to the above description of the disclosed embodiments, the features described in the embodiments in this specification may be replaced or combined with each other, so that professionals in the field can implement or use the present application. Various modifications to these embodiments will be apparent to professionals in the field, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A reference cell, applied to STT-MRAM, characterized in that: The reference unit includes two branches connected in parallel, each of which includes: a heavy metal layer having a first surface and a second surface opposite to each other along a first direction; A first tunnel junction, located on the first surface of the heavy metal layer, the first tunnel junction comprising a first free layer, a first tunnel layer and a first fixed layer stacked in a direction away from the heavy metal layer; a second tunnel junction, located on the second surface of the heavy metal layer, the second tunnel junction comprising a second free layer, a second tunnel layer, and a second fixed layer stacked in a direction away from the heavy metal layer, the first fixed layer and the second fixed layer having the same magnetic moment direction; The first tunnel junction and the second tunnel junction of the same branch have complementary resistance states; The first fixed layers of the first tunnel junctions of the two branches are electrically connected, the second fixed layers of the second tunnel junctions of the two branches are electrically connected, and the heavy metal layers of the two branches are electrically connected; The reference unit implements a readout operation by passing a unidirectional current along the first direction into the two branches, and implements an initialization operation by passing a unidirectional current along a second direction into the heavy metal layers of the two branches, wherein the second direction is perpendicular to the first direction.

2. The reference unit according to claim 1, characterized in that The heavy metal layers of the two branches are electrically connected including: The heavy metal layers of the two branches are connected at the same layer.

3. The reference unit according to claim 1 or 2, characterized in that The material of the heavy metal layer includes tantalum (Ta), tungsten (W) or iridium (Ir).

4. The reference unit according to claim 1 or 2, characterized in that: The thickness of the heavy metal layer along the first direction ranges from 3 nm to 5 nm, including end points.

5. A reference cell initialization method, wherein the reference cell is applied to STT-MRAM, characterized in that: The reference unit is a reference unit according to any one of claims 1 to 4, and the reference unit initialization method comprises: By passing a unidirectional current along the second direction into the heavy metal layer of the two branches in the reference unit, the first tunnel junction and the second tunnel junction of the two branches in the reference unit are initialized simultaneously, so that the resistance states of the first tunnel junction and the second tunnel junction of the same branch in the reference unit are complementary.

6. A reference cell initialization circuit, wherein the reference cell is applied to STT-MRAM, characterized in that: The reference unit is the reference unit according to any one of claims 1 to 4, and the reference unit initialization circuit comprises a driving circuit and a first switch tube; The first end of the driving circuit receives a first control signal, and the first switch tube is closed or turned off under the control of a second control signal; The second end and the third end of the driving circuit form a loop through the first switch tube and the heavy metal layers of the two branches in the reference unit; When the first control signal and the second control signal are both enable signals, the first switch tube is closed, and the driving circuit passes a unidirectional current along the second direction to the heavy metal layer of the two branches in the reference unit, and the first tunnel junction and the second tunnel junction of the two branches in the reference unit are initialized simultaneously, so that the resistance states of the first tunnel junction and the second tunnel junction of the same branch in the reference unit are complementary.

7. A STT-MRAM, characterized in that: Comprising the reference unit according to any one of claims 1 to 4.

8. The STT-MRAM according to claim 7, characterized in that: The STT-MRAM further includes a reference cell initialization circuit, wherein the reference cell initialization circuit includes a driving circuit and a first switch tube; The first end of the driving circuit receives a first control signal, and the first switch tube is closed or turned off under the control of a second control signal; The second end and the third end of the driving circuit form a loop through the first switch tube and the heavy metal layers of the two branches in the reference unit; When the first control signal and the second control signal are both enable signals, the first switch tube is closed, and the driving circuit passes a unidirectional current along the second direction to the heavy metal layer of the two branches in the reference unit, and the first tunnel junction and the second tunnel junction of the two branches in the reference unit are initialized simultaneously, so that the resistance states of the first tunnel junction and the second tunnel junction of the same branch in the reference unit are complementary.

9. The STT-MRAM according to claim 7 or 8, characterized in that: The STT-MRAM further includes: A memory cell array, the memory cell array comprising a plurality of memory cells; A readout circuit is configured to read out the storage state of the selected storage cell by comparing the discharge speed of the selected storage cell with that of the reference cell under the same power supply potential.

10. The STT-MRAM according to claim 9, characterized in that: The readout circuit includes a pre-charging circuit and a discharging circuit; The storage unit is electrically connected between the pre-charging circuit and the discharging circuit through a one-to-one corresponding first selection tube, the reference unit is electrically connected between the pre-charging circuit and the discharging circuit through a second selection tube, and the storage unit and the reference unit are connected to the power supply potential through the pre-charging circuit, and the storage unit and the reference unit are grounded through the discharging circuit; When the read circuit performs a read operation on the selected memory cell, in a first time period, the discharge circuit is turned off, and the precharge circuit precharges the potential of the selected memory cell and one end of the reference cell connected to the precharge circuit to the power supply potential; and then in a second time period, the selected memory cell and the reference cell are discharged through the discharge circuit at the same power supply potential, and the precharge circuit outputs the storage state of the selected memory cell based on the discharge speed of the selected memory cell and the reference cell at the same power supply potential.

Images