Memory device for performing refresh operation and operating method thereof

Abstract

The present disclosure provides a memory device for performing a refresh operation and an operating method thereof. The memory device may include a memory device including a memory block including a plurality of strings, each string including a plurality of memory cells, and the memory device is configured to perform a threshold voltage detection operation of detecting a threshold voltage corresponding to each of the plurality of strings by simultaneously applying a detection voltage to a plurality of word lines coupled with the plurality of memory cells; and a memory controller configured to receive read data read by the threshold voltage detection operation from the memory device, determine a number of strings for which the threshold voltage is lower than the detection voltage based on the read data, and determine whether to perform a refresh operation on the memory block based on the determined number of strings.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0174153 filed in the Korean Intellectual Property Office on December 5, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments generally relate to a semiconductor device, and more particularly, to a memory device that performs a refresh operation and a method of operating the memory device. Background Art

[0004] The storage device stores data in response to the control of a host device (eg, a computer), a mobile terminal (eg, a smartphone or a tablet), or various types of electronic devices. The storage device may include a memory device that stores data and a memory controller that controls the memory device.

[0005] However, due to various reasons, data stored in the memory device may gradually be damaged or degraded. In other words, when a predetermined time has passed after the data is stored, the characteristics of the memory device (e.g., retention characteristics) may be degraded. The memory device may perform a scan operation to check whether the retention characteristics are degraded. When it is determined as a result of the scan operation that the data is damaged, the memory device may perform a refresh operation to store the data in a new location before the data is damaged beyond recovery.

[0006] Scan operations can take time to read data. Methods to reduce the read time can improve operations. Summary of the invention

[0007] Various embodiments of the present disclosure relate to a storage device that improves scanning operation performance and reduces time consumed in performing a scanning operation, and a method of operating the storage device.

[0008] According to an embodiment, a memory device may include: a memory device including a memory block, the memory block including a plurality of strings, each string including a plurality of memory cells, and the memory device being configured to perform a threshold voltage detection operation of detecting a threshold voltage corresponding to each of the plurality of strings by simultaneously applying a detection voltage to a plurality of word lines connected to the plurality of memory cells; and a memory controller configured to receive read data read by the threshold voltage detection operation from the memory device, determine the number of strings having a threshold voltage lower than the detection voltage based on the read data, and determine whether to perform a refresh operation on the memory block based on the determined number of strings.

[0009] According to an embodiment, a method of operating a storage device may include: sequentially applying multiple threshold voltage detection voltages to multiple word lines connected to a storage block; acquiring read data corresponding to each of the multiple threshold voltage detection voltages; detecting a threshold voltage distribution of the storage block based on the read data; and determining a degree of degradation of a retention characteristic of the storage block based on the threshold voltage distribution.

[0010] According to an embodiment, a storage device may include: a memory device, the memory device including a memory block, the memory block including multiple strings, each string including multiple memory cells, the memory device configured to perform a first threshold voltage detection operation of detecting a threshold voltage corresponding to each of the multiple strings by simultaneously applying a first detection voltage to a first word line among multiple word lines connected to the multiple memory cells, and to perform a second threshold voltage detection operation of detecting a threshold voltage corresponding to each of the multiple strings by simultaneously applying a second detection voltage to a second word line among the multiple word lines; and a memory controller configured to receive first read data read by the first threshold voltage detection operation and second read data read by the second threshold voltage detection operation from the memory device, determine the number of first strings having a threshold voltage lower than the first detection voltage based on the first read data, determine the number of second strings having a threshold voltage lower than the second detection voltage based on the second read data, and determine whether to perform a refresh operation on the storage block based on the determined number of first strings and the determined number of second strings. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure;

[0012] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure;

[0013] Figure 3 is a diagram illustrating a storage block according to an embodiment of the present disclosure;

[0014] Figure 4 is a diagram illustrating a plurality of threshold voltage detection voltages according to an embodiment of the present disclosure;

[0015] Figure 5 is a diagram illustrating an example of a threshold voltage detection operation according to an embodiment of the present disclosure;

[0016] Figure 6 is a diagram showing an example of counting strings having a threshold voltage lower than a target threshold voltage detection voltage;

[0017] Figure 7 is a flowchart illustrating an example of a method of determining whether to perform a refresh operation according to an embodiment of the present disclosure;

[0018] Figure 8 is a flowchart illustrating another example of a method of determining whether to perform a refresh operation according to an embodiment of the present disclosure;

[0019] Fig. 9 is a diagram showing another example of a threshold voltage detection operation according to an embodiment of the present disclosure;

[0020] Fig.10 is a diagram illustrating an example of determining a degree of degradation of a retention characteristic of a memory block according to an embodiment of the present disclosure;

[0021] Fig.11 is a flowchart illustrating a method of determining a read voltage for performing a refresh operation according to an embodiment of the present disclosure;

[0022] Fig.12 is a diagram showing another example of a threshold voltage detection operation according to an embodiment of the present disclosure;

[0023] Fig.13 is a flowchart illustrating another example of determining whether to perform a refresh operation according to an embodiment of the present disclosure; and

[0024] Fig.14 is a flowchart illustrating another example of a method of determining whether to perform a refresh operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] The specific structural or functional descriptions showing the example embodiments according to the concepts disclosed in this specification are only used to describe the example embodiments according to these concepts. The example embodiments according to these concepts can be implemented in various forms, but these descriptions are not limited to the example embodiments described in this specification.

[0026] Figure 1 is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0027] Reference Figure 1 The storage device 50 can store data in response to the control of a host device (not shown). Examples of the host device may include a cellular phone, a smart phone, an MP3 player, a laptop computer, a server computer, a desktop computer, a game console, a television, a tablet PC, or an in-vehicle infotainment system.

[0028] The memory device 50 may include a memory device 100 and a memory controller 200 that controls operations of the memory device 100 .

[0029] The storage device 50 may be one of various storage devices such as a multimedia card (SSD, MMC, or eMMC), a universal serial bus (USB) storage device, a universal flash memory (UFS) device, a peripheral component interconnect (PCI) or PCI-Express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, a memory stick, etc.

[0030] The memory device 50 may be manufactured as any of various types of packages. For example, the memory device 50 may be manufactured as any of various package types such as: package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer-level manufacturing package (WFP), and wafer-level stacked package (WSP).

[0031] The memory device 100 may store data. The memory device 100 may include a plurality of memory blocks storing data. Each of the memory blocks may include a plurality of memory cells.

[0032] According to an embodiment, the memory device 100 may be a nonvolatile memory that does not lose data even if power is cut off. According to the present disclosure, for convenience of explanation, it will be described assuming that the memory device 100 is a NAND flash memory.

[0033] According to an embodiment, the memory device 100 may receive a command and an address from the memory controller 200. The memory device 100 may perform an operation indicated by the command on a region selected in response to the address. For example, the memory device 100 may perform a write operation (or a program operation), a read operation, and an erase operation.

[0034] According to an embodiment, the memory device 100 may include a voltage controller 131 and a threshold voltage detection operation controller 132 .

[0035] The voltage controller 131 may control operating voltages of a write operation, a read operation, and an erase operation.

[0036] According to an embodiment, the voltage controller 131 may control the generation of a plurality of threshold voltage detection voltages. The threshold voltage detection voltages may be applied to perform a threshold voltage detection operation. The threshold voltage detection operation may be performed in response to the control of the scan operation controller 240 to detect the threshold voltage distribution of the memory block.

[0037] According to an embodiment, the threshold voltage detection operation controller 132 may control the threshold voltage detection operation. The threshold voltage detection operation controller 132 may simultaneously apply a target threshold voltage detection voltage among a plurality of threshold voltage detection voltages to a plurality of word lines coupled to a memory block. In addition, the threshold voltage detection operation controller 132 may sequentially apply a plurality of threshold voltage detection voltages to a plurality of word lines.

[0038] The memory controller 200 may control general operations of the memory device 50 .

[0039] When power is applied to the memory device 50, the memory controller 200 may run firmware (FW). When the memory device 100 is a flash memory device, the firmware FW may include a host interface layer HIL that controls communication with a host device, a flash translation layer FTL that controls communication between the host device and the memory device 100, and a flash interface layer FIL that controls communication with the memory device 100.

[0040] According to an embodiment, the memory controller 200 may receive data and a logical block address LBA from a host device and convert the logical block address LBA into a physical block address PBA, which indicates an address of a memory cell storing data in the memory device 100. In the present disclosure, the expression "logical block address" may have the same meaning as "logical address" or "logical address". In addition, the expression "physical block address" may have the same meaning as "block address" or "physical address".

[0041] According to an embodiment, the memory controller 200 may provide a command, an address, or data corresponding to a program operation, a read operation, or an erase operation to the memory device 100 in response to a request of a host device so that the memory device 100 may perform a corresponding operation.

[0042] According to an embodiment, the memory controller 200 may generate commands, addresses, and data and transmit them to the memory device 100 regardless of a request from a host device. For example, the memory controller 200 may provide commands, addresses, and data to the memory device 100 to perform programming operations and read operations involved in performing internal operations (e.g., wear leveling operations, read recovery operations, garbage collection operations, scan operations, and refresh operations).

[0043] According to an embodiment, the memory controller 200 may include a processor 210, a memory 220, an interface 230, a scan operation controller 240, and a refresh operation controller 250. The processor 210, the memory 220, the interface 230, the scan operation controller 240, and the refresh operation controller 250 may communicate through a communication bus 260. Figure 1Although not shown in the figure, the memory controller 200 may further include an error detection / correction circuit that performs error detection / correction on data.

[0044] The processor 210 may execute firmware including a code, at least one command, or various types of information necessary for the memory controller 200 to operate.

[0045] The memory 220 may be used as a buffer memory, a cache memory, an operating memory, or the like.

[0046] In addition, the memory 220 may store firmware including a code, at least one command, or various types of information necessary for the memory controller 200 to operate.

[0047] The interface 230 may include a host interface for communicating with a host device and a memory interface for communicating with the memory device 100 .

[0048] The scanning operation controller 240 may perform a scanning operation for determining the retention characteristics of the storage block. The scanning operation may include a threshold voltage detection operation for detecting the threshold voltage distribution of the storage block. During the threshold voltage detection operation, the threshold voltage corresponding to each of the multiple strings included in the storage block may be detected, and the threshold voltage distribution of the storage block may be detected based on the threshold voltage corresponding to each of the multiple strings. The target storage block for performing the scanning operation may be a storage block in which a programming operation has been performed. That is, at least one of the multiple word lines included in the target storage block may be in a programmed state. In addition, at least one of the multiple memory cells included in the target storage block may be a memory cell programmed to any one of a plurality of programming states, and the plurality of programming states are divided from each other based on the threshold voltage.

[0049] According to an embodiment, the scan operation controller 240 may provide the memory device 100 with addresses corresponding to a plurality of word lines and a command for instructing to perform a threshold voltage detection operation.

[0050] According to an embodiment, the scan operation controller 240 may receive read data read by the threshold voltage detection operation from the memory device 100, and may count the strings whose threshold voltage is lower than the target threshold voltage detection voltage among the plurality of strings based on the read data. The scan operation controller 240 may determine whether to perform a refresh operation on the memory block based on the string count. For example, when the string count is greater than a predetermined threshold value, the scan operation controller 240 may send a signal to the refresh operation controller 250 to perform a refresh operation.

[0051] According to an embodiment, the scan operation controller 240 may determine whether to perform a weak word line read operation on a storage block based on a string count. A weak word line read operation may be performed on at least one weak word line pre-set among a plurality of word lines. For example, the scan operation controller 240 may pre-store a list of weak word lines among a plurality of word lines. A weak word line may be determined by a variety of factors, such as the physical location of the word line, a read failure or success during a read operation, and a predetermined strategy. When it is determined that a weak word line read operation is to be performed, the scan operation controller 240 may provide an address corresponding to at least one weak word line and a command to perform a weak word line read operation to the memory device 100. The scan operation controller 240 may receive read data read in a weak word line read operation, and may determine whether to perform a refresh operation. For example, when there are a large number of errors in the read data, the scan operation controller 240 may send a signal to the refresh operation controller 250 to perform a refresh operation.

[0052] The refresh operation controller 250 may control a refresh operation.

[0053] According to an embodiment, when a predetermined time has passed after data is programmed, the retention characteristics of the memory device 100 may be degraded. In order to compensate for the degradation of the retention characteristics, the refresh operation controller 250 may control the memory device 100 to move the data stored in the target memory block for performing the refresh operation to another memory block and perform an erase operation on the target memory block.

[0054] The highest programming state having the highest threshold voltage among the plurality of programming states may move in the direction of lowering the threshold voltage due to weak retention characteristics. However, it may be difficult to distinguish the highest programming state from the other programming states by reading the voltage. Therefore, the page read using the reading voltage corresponding to the highest programming state may have weak retention characteristics.

[0055] Figure 2 is a diagram illustrating a memory device according to an embodiment of the present disclosure.

[0056] Reference Figure 2 , the memory device 100 may include a memory cell array 110 , a peripheral circuit 120 , and a control logic 130 .

[0057] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz.

[0058] The plurality of memory blocks BLK1 to BLKz may be coupled to the row decoder 121 through row lines RL.

[0059] Each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. The plurality of memory cells may be coupled to the page buffer group 123 through first to n-th bit lines BL1 to BLn.

[0060] Each of the plurality of memory cells may correspond to any one of the plurality of states. For example, the plurality of states may include an erased state and a plurality of programmed states, which are divided from each other based on a threshold voltage. Each of the plurality of memory cells may be in an erased state, or may be programmed to any one of the plurality of programmed states.

[0061] The peripheral circuit 120 may be configured to perform a program operation, a read operation, or an erase operation on a selected region in the memory cell array 110 in response to the control of the control logic 130 .

[0062] The peripheral circuit 120 may include a row decoder 121 , a voltage generator 122 , a page buffer group 123 , a column decoder 124 , an input / output circuit 125 , and a sensing circuit 126 .

[0063] The row decoder 121 may be configured to decode the row address RADD received from the control logic 130. The row decoder 121 may select at least one memory block among the memory blocks BLK1 to BLKz according to the decoded address. In addition, the row decoder 121 may select at least one word line of the selected memory block according to the decoded address. The row decoder 121 may apply the operating voltage generated by the voltage generator 122 to the selected word line.

[0064] According to an embodiment, the row decoder 121 may apply a threshold voltage detection voltage VOLT to a plurality of word lines coupled to a target memory block during a threshold voltage detection operation.

[0065] The voltage generator 122 may generate an internal power supply voltage by adjusting an external power supply voltage supplied to the memory device 100. The internal power supply voltage generated by the voltage generator 122 may be used as an operating voltage of the memory device 100. The voltage generator 122 may generate various operating voltages for a program operation, a read operation, and an erase operation in response to the operation signal OPSIG. For example, the voltage generator 122 may generate a program voltage, a verification voltage, a read voltage, an erase voltage, and a threshold voltage detection voltage VOLT.

[0066] The page buffer group 123 may include a plurality of first to nth page buffers PB1 to PBn. In response to a page buffer control signal PBSIGNALS, the first to nth page buffers PB1 to PBn may temporarily store data received through the first to nth bit lines BL1 to BLn, or may sense a voltage or current in the first to nth bit lines BL1 to BLn during a read operation or a verification operation.

[0067] The column decoder 124 may transfer data between the input / output circuit 125 and the page buffer group 123 in response to the column address CADD.

[0068] The input / output circuit 125 may transfer a command CMD and an address ADD received from the memory controller 200 to the control logic 130 , or may exchange data DATA with the column decoder 124 .

[0069] The sensing circuit 126 may determine whether a verification operation of a predetermined program state is passed in response to application of a verification voltage.

[0070] For example, during a verification operation, the sensing circuit 126 may generate a reference current in response to the enable bit signal VRYBIT, and output a pass signal PASS or a fail signal FAIL by comparing the sensing voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current. In another example, during a verification operation, the sensing circuit 126 may generate a reference voltage in response to the enable bit signal VRYBIT, and output a pass signal PASS or a fail signal FAIL by comparing the sensing current IPB received from the page buffer group 123 with a reference current generated by the reference voltage.

[0071] The control logic 130 may control the peripheral circuit 120 by outputting an operation signal OPSIG, a row address RADD, and a page buffer control signal PBSIGNALS in response to a command CMD and an address ADDR.

[0072] According to an embodiment, the control logic 130 may include a voltage controller 131 and a threshold voltage detection operation controller 132 .

[0073] According to an embodiment, during the threshold voltage detection operation, the voltage controller 131 may provide the voltage generator 122 with an operation signal OPSIG for instructing to generate the threshold voltage detection voltage VOLT.

[0074] According to an embodiment, the voltage generator 131 may determine a read voltage for performing a refresh operation based on a degree of degradation of retention characteristics of a target memory block. During the refresh operation, the voltage controller 131 may provide an operation signal OPSIG to the voltage generator 122 for instructing generation of the determined read voltage.

[0075] According to an embodiment, during the threshold voltage detection operation, the threshold voltage detection operation controller 132 may control the row decoder 121 to apply the threshold voltage detection voltage VOLT to the plurality of word lines. For example, the threshold voltage detection operation controller 132 may provide the row decoder 121 with an address indicating the plurality of word lines WL1 to WLn.

[0076] Figure 3 is a diagram illustrating a memory block according to an embodiment of the present disclosure.

[0077] Figure 3 The memory block BLKa shown may refer to Figure 2 One of the memory blocks BLK1 to BLKz shown.

[0078] Reference Figure 3 , the storage block BLKa may include multiple strings SR. The multiple strings SR may be respectively connected to multiple first bit lines BL1 to nth bit lines BLn. Each string SR may include a source selection transistor SST, a memory cell MC, and a drain selection transistor DST. The source selection transistor SST of each string SR may be connected between the memory cell MC and the common source line CSL. The source selection transistor SST may be commonly connected to the common source line CSL. The drain selection transistor DST of each string SR may be connected between the memory cell MC and the bit line BL. The drain selection transistor DST of the multiple strings SR may be respectively connected to multiple first bit lines BL1 to nth bit lines BLn. In each string SR, multiple memory cells MC may be arranged between the source selection transistor SST and the drain selection transistor DST. In each string SR, multiple memory cells MC may be connected in series.

[0079] In the plurality of strings SR, memory cells MC located in the same order from a common source line CSL may be commonly coupled to a single word line.The memory cells MC of the plurality of strings SR may be coupled to a plurality of word lines WL1 to WLn.

[0080] Memory cells connected to the same word line in a plurality of strings SR arranged along a row direction may form a single page PAGE. For example, memory cells connected to a first word line WL1 in a plurality of strings SR may constitute a first page PAGE 1. Memory cells connected to a second word line WL2 may form a second page PAGE 2. Memory cells connected to a third word line WL3 may form a third page PAGE 3. Memory cells connected to an nth word line WLn may form an nth page PAGE n.

[0081] The memory device may perform a program operation on selected memory cells in response to a program command received from a memory controller. The program operation may be performed in units of pages respectively corresponding to word lines WL1 to WLn.

[0082] According to an embodiment, a programming operation corresponding to a programming command of a memory controller may be sequentially performed on a plurality of pages according to the position of a word line corresponding to each page. For example, the memory controller may select the first page PAGE 1 to the nth page PAGE n as programming target pages. The memory controller may control the memory device so that a programming operation may be performed on the first page PAGE 1 to the nth page PAGE n in a sequential manner.

[0083] However, the order of performing programming operations on multiple pages may not be limited to this embodiment. For example, the memory controller may control the memory device so that the programming operation may be performed sequentially on the first page PAGE 1 to the nth page PAGE n in reverse order from the nth page PAGE n to the first page PAGE 1.

[0084] Figure 4 is a diagram illustrating a plurality of threshold voltage detection voltages according to an embodiment of the present disclosure.

[0085] Reference Figure 4 The voltage levels of the plurality of threshold voltage detection voltages may be determined by the number of word lines corresponding to the erased state or the programmed state among the plurality of word lines. The word line corresponding to the programmed state may refer to a word line on which a programming operation has been performed. The word line corresponding to the erased state may refer to a word line on which a programming operation has not been performed.

[0086] For example, when there is one word line corresponding to a programming state among a plurality of word lines, the voltage controller 131 may control the generation of a plurality of threshold voltage detection voltages VOLT11 to VOLT1m during the threshold voltage detection operation. In addition, when there are two word lines corresponding to a programming state among a plurality of word lines, the voltage controller 131 may control the generation of a plurality of threshold voltage detection voltages VOLT21 to VOLT2m during the threshold voltage detection operation. In addition, when there are three word lines corresponding to a programming state among a plurality of word lines, the voltage controller 131 may control the generation of a plurality of threshold voltage detection voltages VOLT31 to VOLT3m during the threshold voltage detection operation. In addition, when there are "n" word lines corresponding to a programming state among a plurality of word lines, the voltage controller 131 may control the generation of a plurality of threshold voltage detection voltages VOLTn1 to VOLTnm during the threshold voltage detection operation.

[0087] According to an embodiment, as the number of word lines corresponding to program states increases, the voltage levels of the plurality of threshold voltage detection voltages may also increase accordingly.

[0088] Figure 5 is a diagram showing an example of a threshold voltage detection operation according to an embodiment of the present disclosure. Figure 5, “i” word lines among the plurality of word lines WL1 to WLn correspond to a program state.

[0089] Reference Figure 5 , the memory device 100 may simultaneously apply the same target threshold voltage detection voltage VOLTi_tg having the same level to the plurality of word lines WL1 to WLn.

[0090] The memory device 100 may provide the read data DATA read according to the target threshold voltage detection voltage VOLTi_tg to the memory controller 200 through the page buffer group 123 , the column decoder 124 , and the input / output circuit 125 .

[0091] According to an embodiment, when a target threshold voltage detection voltage VOLTi_tg having the same level is simultaneously applied to a plurality of word lines WL1 to WLn, the memory device 100 may detect a threshold voltage corresponding to each of a plurality of strings SR1 to SRn.

[0092] According to an embodiment, the threshold voltage of the memory cell MC may correspond to the amount of charge contained in the memory cell MC. For example, the memory cell MC may include a data storage layer that captures the charge. The charge may be a negative voltage. When the charge is captured in the charge storage layer, the memory cell MC may have a predetermined threshold value according to the amount of charge captured in the charge storage layer.

[0093] According to an embodiment, a threshold voltage of a string may correspond to an amount of charges contained in a charge storage layer of each memory cell MC included in a corresponding string.

[0094] Figure 6 is a diagram illustrating an example of counting strings having a threshold voltage lower than a target threshold voltage detection voltage according to an embodiment.

[0095] Reference Figure 6 , the horizontal axis of the curve graph represents the voltage magnitude, and the vertical axis of the curve graph represents the string count. In addition, the threshold voltage distribution represented by the dotted line may represent the initial threshold voltage distribution of the memory block, and the threshold voltage distribution represented by the solid line may represent the current threshold voltage distribution of the memory block. According to the retention characteristics of the memory block, the current threshold voltage distribution may be shifted further to the left than the initial threshold voltage distribution.

[0096] According to an embodiment, the memory controller 200 may count target strings SR_TG having a threshold voltage lower than a target threshold voltage detection voltage VOLTi_tg among a plurality of strings included in a target memory block based on read data read through a threshold voltage detection operation.

[0097] In addition, when the number of target strings SR_TG is greater than a predetermined threshold, the memory controller 200 may control the memory device 100 to perform a refresh operation.

[0098] Figure 7 is a flowchart illustrating an example of a method for determining whether to perform a refresh operation according to an embodiment of the present disclosure. Figure 7 The method shown can be Figure 1 The storage device 50 shown executes.

[0099] More specifically, Figure 7 It can be shown that based on Figure 5 The threshold voltage detection operation shown and Figure 6 The method shown is to determine whether to perform a refresh operation by counting the strings.

[0100] Reference Figure 7 In step S701 , the memory device 50 may apply a target threshold voltage detection voltage to a plurality of word lines at the same time.

[0101] In step S703 , the memory device 50 may acquire read data corresponding to the target threshold voltage detection voltage.

[0102] In step S705 , the memory device 50 may count strings having a threshold voltage lower than a target threshold voltage detection voltage based on the read data.

[0103] In step S707 , the storage device 50 may determine whether the string count is greater than a predetermined threshold.

[0104] As a result of the determination in step S707 , when the string count is greater than the predetermined threshold, in step S709 , the memory device 50 may perform a refresh operation.

[0105] As a result of the determination in step S707 , when the string count is not greater than the predetermined threshold, the processing flow may be terminated.

[0106] Figure 8 is a flowchart showing another example of a method for determining whether to perform a refresh operation according to an embodiment of the present disclosure. Figure 8 The method shown can be Figure 1 The storage device 50 shown executes.

[0107] More specifically, Figure 8 It can be shown that based on Figure 5 The threshold voltage detection operation shown and Figure 6 The method of determining whether to perform a refresh operation by counting the string shown in FIG. Figure 7 Compared with the method Figure 8 A method of further performing a weak word line read operation may be shown.

[0108] because Figure 8 Steps S801, S803, S805 and S807 shown are similar to Figure 7 The steps S701, S703, S705 and S707 shown are the same, so detailed descriptions of these steps will be omitted.

[0109] Reference Figure 8 As a result of the determination in step S807, when the string count is greater than the predetermined threshold, in step S809, the memory device 50 may perform a weak word line read operation. On the other hand, as a result of the determination in step S807, when the string count is not greater than the predetermined threshold, the processing flow may be terminated.

[0110] In step S811 , the memory device 50 may acquire read data corresponding to the weak word line read operation.

[0111] In step S813, the storage device 50 may determine whether the number of error bits in the read data is greater than a predetermined threshold value, which may be different from the threshold value in step S807.

[0112] As a result of the determination in step S813 , when the number of error bits is greater than a predetermined threshold, the memory device 50 may perform a refresh operation.

[0113] As a result of the determination in step S813, when the number of error bits is not greater than a predetermined threshold, the processing flow may be terminated.

[0114] Fig. 9 is a diagram showing another example of a threshold voltage detection operation according to an embodiment of the present disclosure. Fig. 9 , “i” word lines among the plurality of word lines WL1 to WLn correspond to a program state.

[0115] Reference Fig. 9 , the memory device 100 may sequentially apply a plurality of first to nth threshold voltage detection voltages VOLTi1 to VOLTin to a plurality of word lines WL1 to WLn. The same voltage is simultaneously applied to the plurality of word lines.

[0116] According to an embodiment, the memory device 100 may sequentially apply a plurality of first threshold voltage detection voltages VOLTi1 to an nth threshold voltage detection voltage VOLTin to a plurality of word lines WL1 to WLn in order from the highest to the lowest voltage level. For example, the memory device 100 may simultaneously apply an nth threshold voltage detection voltage VOLTin having the highest level to a plurality of word lines WL1 to WLn. Subsequently, the memory device 100 may simultaneously apply an n-1th threshold voltage detection voltage VOLTin-1 having the second highest level to a plurality of word lines WL1 to WLn. This process is repeated until the memory device 100 simultaneously applies a first threshold voltage detection voltage VOLTi1 having the lowest level to a plurality of word lines WL1 to WLn.

[0117] According to an embodiment, the memory device 100 may sequentially apply a plurality of first threshold voltage detection voltages VOLTi1 to an nth threshold voltage detection voltage VOLTin to a plurality of word lines WL1 to WLn in order from the lowest to the highest voltage level. For example, the memory device 100 may simultaneously apply a first threshold voltage detection voltage VOLTi1 having a lowest level to a plurality of word lines WL1 to WLn. Subsequently, the memory device 100 may simultaneously apply a second threshold voltage detection voltage VOLTi2 having a second lowest level to a plurality of word lines WL1 to WLn. This process is repeated until the memory device 100 simultaneously applies an nth threshold voltage detection voltage VOLTin having a highest level to a plurality of word lines WL1 to WLn.

[0118] The memory device 100 may provide read data DATA1 to DATAn read according to a plurality of first to nth threshold voltage detection voltages VOLTi1 to VOLTin to the memory controller 200 through the page buffer group 123 , the column decoder 124 , and the input / output circuit 125 .

[0119] According to an embodiment, the memory device 100 may detect a threshold voltage corresponding to each of the plurality of strings SR1 to SRn when a plurality of first to nth threshold voltage detection voltages VOLTi1 to VOLTin are sequentially applied to the plurality of word lines WL1 to WLn.

[0120] Fig.10 is a diagram illustrating an example of determining a degree of degradation of a retention characteristic of a memory block according to an embodiment of the present disclosure. Fig.10 , it is assumed that a plurality of first to nth threshold voltage detection voltages VOLTi1 to VOLTin are sequentially applied to the plurality of word lines WL1 to WLn in order of voltage levels from the highest to the lowest.

[0121] Reference Fig.10, the horizontal axis of the graph represents the voltage magnitude, and the vertical axis of the graph represents the string count. In addition, the threshold voltage distribution represented by the dotted line may represent the initial threshold voltage distribution of the memory block, and the threshold voltage distribution represented by the solid line may represent the current threshold voltage distribution BLK_DISTB of the memory block. According to the retention characteristics of the memory block, the current threshold voltage distribution BLK_DISTB may be shifted further to the left than the initial threshold voltage distribution.

[0122] According to an embodiment, the memory controller 200 may count strings whose voltage is lower than or higher than each of the plurality of threshold voltages VOLTi1 to VOLTin among the plurality of strings based on read data corresponding to each of the plurality of first to nth threshold voltage detection voltages VOLTi1 to VOLTin. The memory controller 200 may detect the current threshold voltage distribution BLK_DISTB based on the voltage levels of the plurality of threshold voltage detection voltages and the string count.

[0123] According to an embodiment, the memory controller 200 can determine the degree of degradation of the retention characteristics of the storage block based on the detected current threshold voltage distribution BLK_DISTB. For example, the memory controller 200 can determine the degree of degradation of the retention characteristics of the storage block by comparing the current threshold voltage distribution BLK_DISTB with the initial threshold voltage distribution and by comparing the threshold voltage exceeded by most strings with a predetermined reference voltage. The degree of degradation of the retention characteristics may include a time period, an operating speed, etc., during which the retention characteristics are degraded.

[0124] Fig.11 is a flow chart showing a method for determining a read voltage for performing a refresh operation according to an embodiment of the present disclosure. For example, Fig.11 The method shown can be Figure 1 The storage device 50 shown executes.

[0125] More specifically, Fig.11 It can be shown that based on Fig. 9 The threshold voltage detection operation shown and Fig.10 The operation of determining the degree of degradation of the retention characteristic is shown as a method of determining a read voltage for a refresh operation.

[0126] Reference Fig.11 In step S1101, the memory device 50 may sequentially apply a plurality of threshold voltage detection voltages to a plurality of word lines coupled to a memory block.

[0127] In step S1103 , the memory device 50 may acquire read data respectively corresponding to a plurality of threshold voltage detection voltages.

[0128] In step S1105 , the memory device 50 may detect a threshold voltage distribution of the memory block based on the read data.

[0129] In step S1107 , the memory device 50 may determine the degree of degradation of the retention characteristic of the memory block based on the threshold voltage distribution.

[0130] In step S1109, the memory device 50 may determine a read voltage for performing a refresh operation on the memory block based on the degree of degradation of the retention characteristic. For example, the memory device 50 may determine a read voltage for a refresh operation by increasing or decreasing a voltage level of a current read voltage applied during a current read operation based on the degree of degradation of the retention characteristic.

[0131] Subsequently, despite Fig.11 Not shown, but when based on Figure 7 or Figure 8 When it is determined by the method to perform a refresh operation, the memory device 50 may perform the refresh operation by using the determined read voltage.

[0132] Fig.12 is a diagram illustrating another example of a threshold voltage detection operation according to an embodiment of the present disclosure.

[0133] Reference Fig.12 , the plurality of word lines WL1 to WLn may be divided into a plurality of word line groups (WLGR1 and WLGR2). For example, the plurality of word lines WL1 to WLn may be divided into a first word line group WLGR1 including first word lines WL1 to WLi and a second word line group WLGR2 including second word lines WLj to WLn.

[0134] However, with Fig.12 The number of word line groups, the number of word lines included in each word line group, and the classification method of the word line groups may vary depending on the example. For example, the plurality of word lines WL1 to WLn may be classified into three or more word line groups. In addition, the word line groups may include the same number or different numbers of word lines. In addition, the odd-numbered word lines may be classified into one word line group, and the even-numbered word lines may be classified into another word line group.

[0135] According to an embodiment, the memory device 100 may perform a first threshold voltage detection operation by simultaneously applying a first target threshold voltage detection voltage VOLT_tg1 among a plurality of threshold voltage detection voltages to the first word lines WL1 to WLi. In addition, the memory device 100 may perform a second threshold voltage detection operation by simultaneously applying a second target threshold voltage detection voltage VOLT_tg2 among a plurality of threshold voltage detection voltages to the second word lines WLj to WLn.

[0136] As mentioned above Figure 4As described, according to an embodiment, the first target threshold voltage detection voltage VOLT_tg1 can be determined based on the number of word lines corresponding to the erase state or the program state among the first word lines WL1 to WLi. In addition, the second target threshold voltage detection voltage VOLT_tg2 can be determined based on the number of word lines corresponding to the erase state or the program state among the second word lines WLj to WLn.

[0137] For example, the memory device 100 may simultaneously apply a first target threshold voltage detection voltage VOLT_tg1 having the same level to the first word lines WL1 to WLi. The memory device 100 may provide the first read data DATA1 read by the first target threshold voltage detection voltage VOLT_tg1 to the memory controller 200 through the page buffer group 123, the column decoder 124, and the input / output circuit 125. Subsequently, the memory device 100 may simultaneously apply a second target threshold voltage detection voltage VOLT_tg2 having the same level to the second word lines WLj to WLn. The memory device 100 may provide the second read data DATA2 read by the second target threshold voltage detection voltage VOLT_tg2 to the memory controller 200 through the page buffer group 123, the column decoder 124, and the input / output circuit 125.

[0138] According to an embodiment, the memory device 100 may sequentially apply a plurality of first threshold voltage detection voltages VOLT1_1 to VOLTn_1 to the first word lines WL1 to WLi at the same time. In addition, the memory device 100 may sequentially apply a plurality of second threshold voltage detection voltages VOLT1_2 to VOLTn_2 to the second word lines WLj to WLn at the same time.

[0139] As mentioned above Figure 4 As described, according to an embodiment, a plurality of first threshold voltage detection voltages VOLT1_1 to VOLTn_1 may be determined based on the number of word lines corresponding to an erase state or a program state among the first word lines WL1 to WLi. In addition, a plurality of second threshold voltage detection voltages VOLT1_2 to VOLTn_2 may be determined based on the number of word lines corresponding to an erase state or a program state among the second word lines WLj to WLn.

[0140] For example, the memory device 100 may sequentially apply a plurality of first threshold voltage detection voltages VOLT1_1 to VOLTn_1 to the first word lines WL1 to WLi in order from the highest to the lowest voltage level. The memory device 100 may provide read data DATA1_1 to DATAn_1 read according to the plurality of first threshold voltage detection voltages VOLT1_1 to VOLTn_1 to the memory controller 200 through the page buffer group 123, the column decoder 124, and the input / output circuit 125. Subsequently, the memory device 100 may sequentially apply a plurality of second threshold voltage detection voltages VOLT1_2 to VOLTn_2 to the second word lines WLj to WLn in order from the highest to the lowest voltage level. The memory device 100 may provide read data DATA1_2 to DATAn_2 read according to the plurality of second threshold voltage detection voltages VOLT1_2 to VOLTn_2 to the memory controller 200 through the page buffer group 123, the column decoder 124, and the input / output circuit 125.

[0141] In another example, the memory device 100 may sequentially apply a plurality of first threshold voltage detection voltages VOLT1_1 to VOLTn_1 to the first word lines WL1 to WLi in order from the lowest to the highest voltage level. The memory device 100 may provide read data DATA1_1 to DATAn_1 read according to the plurality of first threshold voltage detection voltages VOLT1_1 to VOLTn_1 to the memory controller 200 through the page buffer group 123, the column decoder 124, and the input / output circuit 125. Subsequently, the memory device 100 may sequentially apply a plurality of second threshold voltage detection voltages VOLT1_2 to VOLTn_2 to the second word lines WLj to WLn in order from the lowest to the highest voltage level. The memory device 100 may provide read data DATA1_2 to DATAn_2 read according to the plurality of second threshold voltage detection voltages VOLT1_2 to VOLTn_2 to the memory controller 200 through the page buffer group 123, the column decoder 124, and the input / output circuit 125.

[0142] Fig.13 is a flowchart showing another example of determining whether to perform a refresh operation according to an embodiment of the present disclosure. Fig.13 The method shown can be Figure 1 The storage device 50 shown executes.

[0143] Reference Fig.13 In step S1301, the memory device 50 may simultaneously apply a first target threshold voltage detection voltage to a first word line.

[0144] In step S1303 , the memory device 50 may acquire first read data corresponding to a first target threshold voltage detection voltage.

[0145] In step S1305 , the memory device 50 may simultaneously apply a second target threshold voltage detection voltage to the second word line.

[0146] In step S1307 , the memory device 50 may acquire second read data corresponding to the second target threshold voltage detection voltage.

[0147] In step S1309 , the memory device 50 may count first strings having a threshold voltage lower than a first target threshold voltage detection voltage based on the first read data.

[0148] In step S1311, the memory device 50 may count the second strings whose threshold voltage is lower than the second target threshold voltage detection voltage based on the second read data. Figure 6 The operation of counting strings is shown to count a first string and a second string.

[0149] In addition, although not shown, the storage device 50 may be configured to store Fig.10 The operation of determining the degree of degradation of the retention characteristic is shown to determine a read voltage to be used during a refresh operation.

[0150] In step S1313, the storage device 50 may determine whether at least one of the first string count and the second string count is greater than a predetermined threshold. Fig.13 Different from the example shown in , in other embodiments, the storage device 50 may determine whether the sum of the first string count and the second string count is greater than a predetermined threshold. In addition, the storage device 50 may determine whether the first string count and the second string count are greater than a predetermined threshold.

[0151] As a result of the determination in step S1313 , when at least one of the first string count and the second string count is greater than a predetermined threshold, in step S1315 , the memory device 50 may perform a refresh operation.

[0152] As a result of the determination in step S1313 , when it is determined that both the first string count and the second string count are not greater than the predetermined threshold, the processing flow may be terminated.

[0153] Fig.14 is a flowchart showing another example of a method for determining whether to perform a refresh operation according to an embodiment of the present disclosure. Fig.14 The method shown can be Figure 1 The storage device 50 shown executes.

[0154] More specifically, Fig.13 compared to, Fig.14 A method of further performing a weak word line read operation may be shown.

[0155] like Fig.14 Steps S1401, S1403, S1405, S1407, S1409, S1411 and S1413 shown are Fig.13 The steps S1301, S1303, S1305, S1307, S1309, S1311 and S1313 shown are the same. Therefore, the description of these steps will be omitted.

[0156] Reference Fig.14 As a result of the determination in step S1413, when at least one of the first string count and the second string count is greater than the predetermined threshold, in step S1415, the memory device 50 may perform a weak word line read operation. On the other hand, as a result of the determination in step S1413, when it is determined that both the first string count and the second string count are not greater than the predetermined threshold, the process flow may be terminated.

[0157] In step S1417 , the memory device 50 may acquire read data corresponding to the weak word line read operation.

[0158] In step S1419, the storage device 50 may determine whether the number of error bits in the read data is greater than a predetermined threshold value. The threshold value may be different from the threshold value in step S1413.

[0159] As a result of the determination in step S1419 , when the number of error bits is greater than the predetermined threshold, in step S1421 , the memory device 50 may perform a refresh operation.

[0160] As a result of the determination in step S1419, when the number of error bits is not greater than a predetermined threshold, the processing flow may be terminated.

[0161] The present disclosure provides a storage device that improves the performance of a scanning operation and reduces the time taken to perform the scanning operation.

[0162] In the above-described embodiments, all steps may be selectively performed or skipped. In addition, the steps in each embodiment may not always be performed in a regular order. In addition, the embodiments and drawings disclosed in this specification are intended to help those of ordinary skill in the art to more clearly understand the present disclosure, rather than to limit the scope of the present disclosure. In other words, those of ordinary skill in the art to which the present disclosure belongs will be able to easily understand that, based on the technical scope of the present disclosure, various modifications are possible. It will be apparent to those skilled in the art that, without departing from the spirit or scope of the present invention, various modifications may be made to the above-described exemplary embodiments of the present disclosure. Therefore, the present disclosure is intended to cover all such modifications as long as they fall within the scope of the appended claims and their equivalents.

Claims

1. A storage device, comprising: a memory device including a memory block including a plurality of strings, each string including a plurality of memory cells, the memory device performing a threshold voltage detection operation of detecting a threshold voltage corresponding to each of the plurality of strings by simultaneously applying a detection voltage to a plurality of word lines coupled to the plurality of memory cells; as well as A memory controller receives read data read by the threshold voltage detection operation from the memory device, determines the number of strings having a threshold voltage lower than the detection voltage based on the read data, and determines whether to perform a refresh operation on the memory block based on the determined number of strings. 2 . The memory device according to claim 1 , wherein at least one of the plurality of memory cells is programmed into one of a plurality of program states distinguished from each other based on a threshold voltage. 3 . The memory device of claim 1 , wherein the memory controller provides addresses corresponding to the plurality of word lines and a command to perform the threshold voltage detection operation to the memory device. 4 . The memory device according to claim 1 , wherein the memory device simultaneously applies detection voltages having the same level to the plurality of word lines. 5 . The memory device of claim 1 , wherein a voltage level of the detection voltage is determined by the number of word lines corresponding to an erase state or a program state among the plurality of word lines. 6 . The memory device of claim 1 , wherein when the determined number of strings is greater than a predetermined threshold, the memory controller controls the memory device to perform the refresh operation. 7 . The memory device of claim 1 , wherein the memory device sequentially applies a plurality of threshold voltage detection voltages to the plurality of word lines in order of voltage level from highest to lowest.

8. The storage device according to claim 7, wherein the memory controller detects a threshold voltage distribution of the storage block based on read data corresponding to each of the plurality of threshold voltage detection voltages, and determines a degree of degradation of a retention characteristic of the storage block based on the threshold voltage distribution. 9 . The memory device of claim 8 , wherein the memory controller determines a read voltage for the refresh operation based on a degree of degradation of the retention characteristic. 10 . The memory device of claim 1 , wherein the memory controller determines whether to perform a weak word line read operation on the memory block based on the determined number of strings.

11. The memory device of claim 10, wherein when the determined number of strings is greater than a predetermined threshold, the memory controller provides the memory device with an address corresponding to at least one weak word line among the plurality of word lines and a command for instructing to perform the weak word line read operation. 12 . The memory device of claim 11 , wherein the memory controller determines whether to perform the refresh operation based on read data acquired through the weak word line read operation.

13. A method of operating a storage device, comprising: sequentially applying a plurality of threshold voltage detection voltages to a plurality of word lines connected to a memory block; acquiring read data corresponding to each of the plurality of threshold voltage detection voltages; detecting a threshold voltage distribution of the storage block based on the read data; as well as A degree of degradation of retention characteristics of the memory block is determined based on the threshold voltage distribution.

14. The method of claim 13, wherein detecting the threshold voltage distribution comprises: determining, based on the read data, a number of strings having a threshold voltage lower than or higher than each of the plurality of threshold voltage detection voltages among a plurality of strings, each string including a plurality of memory cells coupled to the plurality of word lines; as well as The threshold voltage distribution is detected based on voltage levels of the plurality of threshold voltage detection voltages and the determined number of strings.

15. The method according to claim 13, further comprising: A read voltage for a refresh operation of the memory block is determined based on a degree of degradation of the retention characteristic.

16. The method according to claim 13, further comprising: determining, based on read data corresponding to the detection voltage, the number of strings having a threshold voltage lower than the detection voltage among a plurality of strings, each string including a plurality of memory cells coupled to the plurality of word lines; and Whether to perform a refresh operation on the memory block is determined based on the determined number of strings.

17. A storage device, comprising: a memory device comprising a memory block, the memory block comprising a plurality of strings, each string comprising a plurality of memory cells, the memory device performing a first threshold voltage detection operation of detecting a threshold voltage corresponding to each of the plurality of strings by simultaneously applying a first detection voltage to a first word line among a plurality of word lines coupled to the plurality of memory cells, and performing a second threshold voltage detection operation of detecting a threshold voltage corresponding to each of the plurality of strings by simultaneously applying a second detection voltage to a second word line among the plurality of word lines; as well as A memory controller receives first read data read by the first threshold voltage detection operation and second read data read by the second threshold voltage detection operation from the memory device, determines the number of first strings having a threshold voltage lower than the first detection voltage based on the first read data, determines the number of second strings having a threshold voltage lower than the second detection voltage based on the second read data, and determines whether to perform a refresh operation on the storage block based on the determined number of first strings and the determined number of second strings.

18. The storage device according to claim 17, wherein: A voltage level of the first detection voltage is determined by the number of word lines corresponding to an erase state or a program state among the first word lines, and A voltage level of the second detection voltage is determined by the number of word lines corresponding to an erase state or a program state among the second word lines.

19. The storage device according to claim 17, wherein the memory controller performs a weak word line read operation on the storage block according to the determined number of first strings and the determined number of second strings, and determines whether to perform the refresh operation based on read data obtained by the weak word line read operation.

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