Multi-layer chip stacking packaging structure, preparation method thereof and electronic equipment

Abstract

The invention provides a multi-layer chip stacking packaging structure, a preparation method thereof and electronic equipment. Relates to the technical field of semiconductor device manufacturing. The multi-layer chip stacking packaging structure comprises a first substrate, a first rewiring layer, a second substrate and a second rewiring layer, a first device is arranged in the first substrate, and the first rewiring layer is arranged on one side of the first substrate; a second device is arranged in the second substrate, and the second rewiring layer is arranged on one side of the second substrate; and one side, deviating from the first rewiring layer, of the first substrate is in bonding connection with one side, deviating from the second rewiring layer, of the second substrate. When the multi-layer chip stacking packaging structure is manufactured, before the first substrate and the second substrate are bonded, the rewiring layers can be manufactured on the two substrates respectively, the technological processes of the two rewiring layers do not affect each other, and the risks of warping and layering of the packaging structure can be weakened.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device manufacturing, and in particular to a multi-layer chip stacking packaging structure, an electronic device including the multi-layer chip stacking packaging structure, and a method for preparing the multi-layer chip stacking packaging structure. Background Art

[0002] Driven by the high speed, high performance and miniaturization of electronic products, modules are developing towards high-density miniaturization to achieve high-density and high-performance packaging. To achieve module miniaturization, higher-density fan-out packaging multi-layer stacking is required. At this time, warping and delamination problems will become more prominent and become its bottleneck problem.

[0003] like Figure 1 As shown, Figure 1 The figure shows a multi-layer chip stacking packaging structure. In the middle layer including device 1, device 2, device 3 and device 4, redistribution layers (RDL) are arranged on both the upper and lower sides. When preparing each redistribution layer RDL, it will experience multiple photoresist curing temperature shocks. For example, when each redistribution layer RDL contains four layers of metal routing, Figure 1 The structure shown will produce at least 8 photoresist curing temperature shocks, which will easily cause warping and delamination, and even damage the device performance of the middle layer. Summary of the invention

[0004] The present application provides a multi-layer chip stacking packaging structure, an electronic device including the multi-layer chip stacking packaging structure, and a method for preparing the multi-layer chip stacking packaging structure, with the purpose of reducing warping and delamination phenomena and improving the performance of the multi-layer stacking packaging structure.

[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0006] On the one hand, the present application provides a multi-layer chip stacking packaging structure.

[0007] The multi-layer chip stacking packaging structure includes: a first substrate, a first redistribution layer, a second substrate and a second redistribution layer; a first device is arranged in the first substrate, and the first redistribution layer is arranged on one side of the first substrate; a second device is arranged in the second substrate, and the second redistribution layer is arranged on one side of the second substrate; a side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer.

[0008] When preparing the multi-layer chip stacking packaging structure provided in the present application, a first redistribution layer can be set on one side of the first substrate, and a second redistribution layer can be set on one side of the second substrate, and then the first substrate including the first redistribution layer can be bonded together with the second substrate including the second redistribution layer. Compared with preparing a redistribution layer on one side of a substrate and then preparing another redistribution layer on the other side, the present application can reduce the impact of multiple high-temperature shocks when preparing the redistribution layer. For example, in the present application, since the redistribution layers can be prepared on the two substrates respectively before the first substrate and the second substrate are bonded, the process steps of the two redistribution layers do not affect each other, thereby reducing the risk of warping and delamination of the packaging structure, reducing the risk of damage to the device, and improving the performance of the entire packaging structure. Furthermore, the first device and the second device of the present application are basically located in the middle of the entire packaging structure. During the preparation process, these devices are at a greater risk of warping. However, the present application arranges the first device and the second device in a substrate. Since the thermal expansion coefficient of the substrate and the thermal expansion coefficient of the device are basically close, compared with packaging devices using plastic packaging materials with a larger thermal expansion coefficient, the present application uses a substrate with a smaller difference in thermal expansion coefficient to package devices, which can suppress the degree of warping of the device and can also suppress the risk of delamination between the substrate and the device.

[0009] In one achievable manner, the first device has a first pattern layer on a side facing the second substrate; the second substrate has a first side surface facing the first substrate, the first side surface and the first device form a cavity; and the first pattern layer is located in the cavity.

[0010] In the example of the present application, the first device can be a cavity type device. Since the second substrate and the cavity type device form a cavity, the pattern layer of the cavity type device is arranged in the cavity. The present application can omit the cover structure of the cavity type device and utilize the second substrate as the cover of the cavity type device, thereby simplifying the packaging structure and eliminating the assembly process of the cover.

[0011] In one achievable manner, the first device and the second device are arranged face to face, and the first device and the second device enclose a cavity; the first device has a first pattern layer on a side facing the second substrate; the second device has a second pattern layer on a side facing the first substrate; and the first pattern layer and the second pattern layer are both located in the cavity.

[0012] In this example, the first device and the second device can both be cavity-type devices. The two devices arranged face to face form a cavity, and the pattern layers of the two devices are arranged in the cavity, that is, the second device is used as a cover of the first device, and the first device is used as a cover of the second device.

[0013] In one achievable manner, the first device includes at least one of a filter and a multiplexer.

[0014] In one achievable manner, the first device and the second device are arranged face to face, with the pattern layer of the first device facing the pattern layer of the second device; the pattern layer of the first device is bonded to the pattern layer of the second device.

[0015] When the pattern layers of two devices disposed face to face are disposed opposite to each other, a bonding structure between two substrates may be used to electrically connect the pattern layers of the two devices.

[0016] In one achievable manner, the first device includes at least one of a filter and a multiplexer, and the second device includes an integrated passive device (IPD). In this way, the filter and the IPD are integrated to realize a multifunctional device.

[0017] In one achievable manner, the pattern layer of the first device faces the second substrate; along the thickness direction of the first device, a conductive via is provided in the first device, and the conductive via electrically connects the first redistribution layer and the pattern layer of the first device.

[0018] The device can be interconnected with the first redistribution layer by using conductive vias.

[0019] In one achievable method, a third device is provided on the side of the first redistribution layer facing away from the first substrate; the pattern layer of the first device faces the first redistribution layer, and the pattern layer of the third device faces the first redistribution layer; the pattern layer of the first device and the pattern layer of the third device are both electrically connected to the first redistribution layer.

[0020] In one achievable method, a fourth device is provided on the side of the second redistribution layer facing away from the second substrate; the pattern layer of the second device faces the second redistribution layer, and the pattern layer of the fourth device faces the second redistribution layer; the pattern layer of the second device and the pattern layer of the fourth device are both electrically connected to the second redistribution layer.

[0021] The first redistribution layer can be used to interconnect the first device and the third device, and the second redistribution layer can be used to interconnect the second device and the fourth device, shortening the interconnection path between the first device and the third device, and shortening the interconnection path between the second device and the fourth device.

[0022] In one achievable manner, a first package is provided on the side of the first redistribution layer facing away from the first substrate, and the third device is located in the first package; a second package is provided on the side of the second redistribution layer facing away from the second substrate, and the fourth device is located in the second package.

[0023] The first package body is used to protect the third device, and the second package body is used to protect the fourth device.

[0024] In an achievable manner, the thermal expansion coefficient of the first substrate or the second substrate is 2 ppm / k-3 ppm / k. The thermal expansion coefficient of the first substrate or the second substrate may be equal to 2 ppm / k, or equal to 3 ppm / k.

[0025] In one achievable manner, the material of the first substrate or the second substrate may be at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate, or a glass substrate.

[0026] On the other hand, the present application also provides a method for preparing a multi-layer chip stacking packaging structure, the preparation method comprising:

[0027] A first redistribution layer is formed on one side of a first substrate, wherein a first device is disposed in the first substrate;

[0028] A second redistribution layer is formed on one side of a second substrate, wherein a second device is disposed in the second substrate;

[0029] A side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer.

[0030] When a double-sided redistribution layer is prepared using the method provided in the present application, a redistribution layer is prepared on one side of a substrate, another redistribution layer is prepared on one side of another substrate, and then the two substrates carrying the redistribution layers are bonded together by bonding to obtain a stacked structure of double-sided redistribution layers. Compared with separately preparing redistribution layers on both sides of a substrate, the method provided in the present application can reduce the number of photoresist curing temperature shocks, reduce the degree of damage to the device, and can also weaken warping and delamination phenomena.

[0031] In one achievable manner, before forming the first redistribution layer on one side of the first substrate, the preparation method further includes:

[0032] A first groove is opened in the first substrate, and a first device is arranged in the first groove, with the pattern layer of the first device facing away from the opening of the first groove. After the first substrate and the second substrate are bonded, the pattern layer of the first device is located in the cavity surrounded by the first device and the second substrate.

[0033] In the method exemplified in the present application, the first device may be a cavity-type device, and the second substrate is used as a cover of the cavity device, which can simplify the entire packaging structure and the process steps.

[0034] In one achievable manner, before the first redistribution layer is formed on one side of the first substrate and before the second redistribution layer is formed on one side of the second substrate, the preparation method further includes:

[0035] A first groove is opened in the first substrate, and a first device is disposed in the first groove, with the pattern layer of the first device facing away from the opening of the first groove;

[0036] A second groove is formed in the second substrate, and a second device is disposed in the second groove, with the pattern layer of the second device facing away from the opening of the second groove;

[0037] The bonding of the first substrate to the second substrate comprises:

[0038] The pattern layer of the first device and the pattern layer of the second device are arranged face to face, the first device and the second device surround a cavity, and the pattern layer of the first device and the pattern layer of the second device are both located in the cavity.

[0039] In this example, the first device and the second device may both be cavity-type devices, the first device disposed face to face serves as a cover of the second device, and the second device serves as a cover of the first device.

[0040] In one achievable manner, after the first substrate and the second substrate are bonded, the preparation method further includes:

[0041] Disposing a third device on a side of the first redistribution layer away from the first substrate;

[0042] A fourth device is arranged on a side of the second redistribution layer facing away from the second substrate.

[0043] In this way, a four-layer stacked packaging structure can be produced, further improving the integration density.

[0044] On the other hand, the present application provides an electronic device, which may include a circuit board, and a multi-layer chip stacking packaging structure of any of the above implementations.

[0045] Since the electronic device includes a multi-layer chip stacking packaging structure in any of the above-mentioned implementations, when a double-sided redistribution layer of the multi-layer chip stacking packaging structure is prepared, the risk of warping and delamination of the packaging structure can be weakened, the risk of damage to the device can be reduced, and the performance of the entire packaging structure can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] Figure 1 A schematic diagram of a multi-layer chip stacking packaging structure in the prior art;

[0047] Figure 2 A schematic diagram of a portion of the structure of an electronic device provided in an embodiment of the present application;

[0048] Figure 3 A schematic diagram of a multi-layer chip stacking packaging structure provided in an embodiment of the present application;

[0049] Figure 4A , Figure 4B and Figure 4C A schematic diagram of a structure of a redistribution layer prepared on a substrate provided in an embodiment of the present application;

[0050] Figure 5A , Figure 5B and Figure 5C A schematic diagram of a structure of manufacturing another redistribution layer on another substrate provided in an embodiment of the present application;

[0051] Figure 6 A schematic diagram of a multi-layer chip stacking packaging structure provided in an embodiment of the present application;

[0052] Figure 7 for Figure 6 A magnified image of point A;

[0053] Figure 8 A schematic diagram of the structure of a cavity type device provided in an embodiment of the present application;

[0054] Fig. 9 A schematic diagram of a local structure of a multi-layer chip stacking packaging structure provided in an embodiment of the present application;

[0055] Fig.10 A schematic diagram of a local structure of a multi-layer chip stacking packaging structure provided in an embodiment of the present application;

[0056] Fig.11 A schematic diagram of a local structure of a multi-layer chip stacking packaging structure provided in an embodiment of the present application;

[0057] Fig.12 A schematic diagram of a multi-layer chip stacking packaging structure provided in an embodiment of the present application;

[0058] Fig.13 A process flow chart of a method for preparing a multi-layer chip stacking packaging structure provided in an embodiment of the present application;

[0059] FIG. 14A to FIG. 14N This is a cross-sectional view of the corresponding process structure after each step in a multi-layer chip stacking packaging structure manufacturing method provided in an embodiment of the present application is completed.

[0060] Reference numerals:

[0061] 100-multi-layer chip stacking packaging structure; 200-control circuit; 300-circuit board;

[0062] 1- substrate;

[0063] 2- pattern layer;

[0064] 3-lid;

[0065] 4- Cavity. DETAILED DESCRIPTION

[0066] The embodiment of the present application provides an electronic device, which may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR), a drone and other terminal devices, or may also be a base station, a television, a router, a car and other devices. The embodiment of the present application does not impose any special restrictions on the specific form of the above electronic devices.

[0067] Figure 2 The electronic device may include a circuit board 300. The circuit board 300 in this example may be a printed circuit board (PCB), and electronic devices may be arranged on the circuit board 300. For example, a chip packaging structure may be arranged on the circuit board 300.

[0068] In order to achieve high-density and high-performance packaging, a multi-layer chip stacking packaging structure 100 may be provided on the circuit board 300 , and more devices may be integrated by utilizing the multi-layer stacking structure.

[0069] like Figure 2 A control circuit 200 may also be provided on the circuit board 300 , and the multi-layer chip stacking package structure 100 is electrically connected to the control circuit 200 to control the circuit in the multi-layer chip stacking package structure 100 .

[0070] like Figure 3 , Figure 3 1 is a structural diagram of a multi-layer chip stacking package structure 100 provided in an embodiment of the present application. The multi-layer chip stacking package structure 100 includes a first substrate, in which at least one device is disposed. For example, the first substrate may be provided with Figure 3 Device 11, device 12 and device 13 are shown.

[0071] In some examples, in order to realize interconnection between devices in the first substrate, a first redistribution layer RDL is disposed on one side of the first substrate. For example, the first redistribution layer RDL can realize interconnection between devices 11 , 12 , and 13 .

[0072] The multi-layer chip stacking package structure 100 further includes a second substrate, in which at least one device is disposed. For example, the second substrate may be provided with Figure 3 The device 21, the device 22 and the device 23 are shown. In order to realize the interconnection between the device 21, the device 22 and the device 23, a second redistribution layer RDL is disposed on one side of the second substrate.

[0073] See Figure 3 In the example of the present application, a side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer through a bonding process.

[0074] Figure 3 It can be understood that: the first substrate has a first side surface and a second side surface back to back, and a first redistribution layer is arranged on the first side surface of the first substrate; the second substrate has a first side surface and a second side surface back to back, and a second redistribution layer is arranged on the first side surface of the second substrate; the second side surface of the first substrate is bonded to the second side surface of the second substrate by bonding.

[0075] In some examples, such as Figure 3 A first conductive via can be provided in the first substrate, the first conductive via passes through the first substrate along the thickness direction of the first substrate, and is electrically connected to the first redistribution layer; a second conductive via is provided in the second substrate, the second conductive via passes through the second substrate along the thickness direction of the second substrate, and is electrically connected to the second redistribution layer.

[0076] The first conductive via and the second conductive via disposed opposite to each other can be electrically connected through the bonding layer between the two substrates. In this way, the first redistribution layer and the second redistribution layer can be interconnected. In some examples, the device in the first substrate can be interconnected with the device in the second substrate.

[0077] like Figure 3 The device disposed in the first substrate or the second substrate may be an active device or a passive device, for example, a passive filter or an integrated passive device IPD. Alternatively, the device may be a plurality of bare chips stacked in three dimensions. The present application does not specifically limit the type and structure of the device.

[0078] The first substrate or the second substrate in the example of the present application may be at least one of a silicon substrate, a silicon carbide substrate, a sapphire substrate or a glass substrate. Alternatively, it may be a multi-layer substrate, such as a silicon-on-insulator (SOI) substrate, a piezoelectric-on-insulator (POI) substrate, etc.

[0079] like Figure 4A , Figure 4B and Figure 4C ,as well as, Figure 5A , Figure 5B and Figure 5C , showing an example Figure 3 A possible preparation process of the structure shown.

[0080] like Figure 4AAt least one device is manufactured in the first substrate, for example, device 11, device 12 and device 13 can be manufactured.

[0081] And, a blind first conductive via is formed in the first substrate, that is, the first conductive via does not penetrate the first substrate.

[0082] like Figure 4B A first redistribution layer is formed on one side of the first substrate. For example, the metal wiring of the first redistribution layer may be at least four layers, or the metal wiring may be less than four layers.

[0083] like Figure 4C , the back side of the first substrate is thinned to expose the end face of the first conductive through hole.

[0084] like Figure 5A At least one device is manufactured in the second substrate. For example, device 21, device 22 and device 23 can be manufactured. A blind second conductive through hole is manufactured in the second substrate, that is, the second conductive through hole does not penetrate the second substrate.

[0085] like Figure 5B A second redistribution layer is formed on one side of the second substrate. For example, the metal wiring of the second redistribution layer can be connected to Figure 4B The number of metal routing layers in the first redistribution layer is the same or different.

[0086] like Figure 5C , the back side of the second substrate is thinned to expose the end face of the second conductive through hole.

[0087] The wafer bonding process Figure 4C The structure shown, and Figure 5C The above structure can be bonded to obtain Figure 3 The bonding process can be understood as a method of combining two wafers or two other material structures through chemical and physical effects.

[0088] Based on the preparation process of the above example, it is known that after the redistribution layers are respectively prepared on two substrates, the wafer bonding process is used to bond the substrates integrated with the redistribution layers to obtain a double-sided redistribution layer structure. The preparation process of the first redistribution layer is independent of the preparation process of the second redistribution layer and will not affect each other. For example, when the first redistribution layer and the second redistribution layer respectively include four layers of metal wiring, compared with the redistribution layers with four layers of metal wiring prepared on both sides of a substrate, the number of temperature shocks of photoresist curing in the present application can be halved, reducing the probability of damage to the device, and can significantly reduce the risk of warping and delamination, thereby improving the performance of the entire multi-layer chip stacking packaging structure.

[0089] In some examples, when the number of metal routing layers in the redistribution layer is greater than or equal to 4 layers, for example, greater than 5 layers of metal routing, the photoresist curing temperature shock is more obvious. FIG. 4A to FIG. 4C ,as well as, FIG. 5A to FIG. 5C The method shown in the figure can significantly reduce the warping and delamination phenomena, thus protecting the performance of the device.

[0090] Back to Figure 3 In some examples, devices may be disposed above the first redistribution layer and devices may be disposed below the second redistribution layer. The devices located in the first substrate and the second substrate are basically located in the middle layer of the entire packaging structure, and the risk of warping in the middle layer is greater.

[0091] However, the present application sets the first device in the first substrate and the second device in the second substrate, that is, the device is encapsulated by the substrate. The coefficient of thermal expansion (CTE) of either the first substrate or the second substrate in the present application example can be 2ppm / k-3ppm / k, so the CTE of the substrate is basically close to the CTE of the device. By encapsulating the device with a substrate having a smaller difference in the coefficient of thermal expansion, the warping degree of the first device and the second device can be suppressed, and the risk of delamination between the substrate and the device can also be suppressed.

[0092] In some technologies, the plastic packaging material can be used to encapsulate Figure 3 The thermal expansion coefficient of the plastic encapsulation material of the first device and the second device located in the middle layer is relatively large, for example, it can be greater than or equal to 10ppm / k, which is far different from the thermal expansion coefficient of the device, and it is easy to cause the device to warp. In addition, during the plastic encapsulation process, the liquid plastic encapsulation material can easily impact the device and cause the device to drift. When the redistribution layer is subsequently prepared, it is difficult to control the accuracy of the redistribution layer, and it may even affect the electrical connection between the redistribution layer and the device.

[0093] In the example of the present application, grooves can be opened in the first substrate and the second substrate, and the devices can be embedded in the grooves. The process is simple and the above-mentioned device drift and the difficulty of the redistribution layer preparation process will basically not occur.

[0094] Figure 6 is a structural diagram of another multi-layer chip stacking packaging structure provided in an embodiment of the present application, Figure 7 yes Figure 6 A magnified view of the A. Figure 6 and Figure 7 Some devices disposed in the first substrate may be cavity type devices. For example, device 13 disposed in the first substrate is a cavity type device.

[0095] The structure of the cavity device can be Figure 8 In the exemplary structure, the cavity type device comprises a substrate 1 , and a pattern layer 2 is disposed on one side of the substrate 1 .

[0096] The cavity-type device further includes a packaging structure, such as a cover 3 , which is buckled with the substrate 1 to accommodate the pattern layer 2 in the formed cavity 4 to protect the pattern layer 2 .

[0097] See Figure 6 and Figure 7 When the device 13 disposed in the first substrate is a cavity type device, the pattern layer in the cavity type device may face the second substrate, and the side of the second substrate facing the first substrate and the cavity type device form a cavity, and the pattern layer is located in the cavity.

[0098] It can be understood that: the present application can use the second substrate as the cover of the cavity type device, so that the cover structure can be omitted, the packaging structure can be simplified, and the process can be simplified.

[0099] Figure 6 and Figure 7 In the example, a cavity type device is provided in the first substrate. In some other examples, a cavity type device may be provided in the first substrate, and a cavity type device may also be provided in the second substrate.

[0100] For example, Fig. 9 As shown, the device 13 located in the first substrate and the device 23 located in the second substrate are both cavity-type devices. The pattern layer of the device 13 faces the device 23, and the pattern layer of the device 23 faces the device 13, that is, the device 13 and the device 23 are arranged opposite to each other, and the devices 13 and 23 arranged face to face form a cavity, and the pattern layer of the device 13 and the pattern layer of the device 23 are located in the cavity formed together. That is, the device 13 and the device 23 serve as covers for each other, the device 23 serves as the cover of the device 13, and the device 13 serves as the cover of the device 23.

[0101] In some examples, a device located in a first substrate may be interconnected with a device located in a second substrate, such as Fig.10 , Fig.10 An example of one electrical connection method is to set a third conductive via in the device 13 located in the first substrate, the third conductive via electrically connects the pattern layer of the device 13 and the first redistribution layer located on one side of the first substrate, and set a fourth conductive via in the device 23 located in the second substrate, the fourth conductive via electrically connects the pattern layer of the device 23 and the second redistribution layer located on one side of the second substrate. In this way, the interconnection between the device 13 and the device 23 can be achieved by using the conductive via and the redistribution layer.

[0102] For example, when the device 13 and the device 23 are both filters, the filter device 13 and the filter device 23 may be connected in parallel or in series to implement a multiplex filter.

[0103] Fig.11 This is another electrical connection method provided in the embodiment of the present application. The pattern layer of the device 13 located in the first substrate faces the second substrate, and the pattern layer of the device 23 located in the second substrate faces the first substrate. The two pattern layers are interconnected using a bonding structure located between the first substrate and the second substrate. In this way, the interconnection path can be shortened and the device performance can be improved.

[0104] For example, the device 13 may be a filter, and the device 23 may be an integrated passive device IPD. The filter is electrically connected to the integrated passive device IPD to achieve integration of multifunctional devices.

[0105] In one implementation, Fig.11 A third conductive via may be provided in the device 13 , and the third conductive via electrically connects the pattern layer of the device 13 and the first redistribution layer.

[0106] Fig.12 is a structural diagram of another multi-layer chip stacking packaging structure provided in an embodiment of the present application. Figure 6 In contrast, in the present exemplary structure, at least one device is disposed on a side of the first redistribution layer facing away from the first substrate. For example, device 31 , device 32 , and device 33 may be disposed on the first redistribution layer.

[0107] In order to protect the devices 31, 32 and 33, a first package body may be provided, and the first package body covers the devices 31, 32 and 33. The first package body may be made of a plastic packaging material.

[0108] See you next time Fig.12 At least one device is arranged on the side of the second redistribution layer away from the second substrate. For example, a device 41 can be arranged on the second redistribution layer. A second package can also be arranged, and the second package covers the device 41 to protect the device 41 or to perform electromagnetic shielding. The second package can be made of a plastic packaging material.

[0109] This application example Fig.12 The multi-layer chip stacking packaging structure includes four device layers, which can achieve high-density integration of devices, so that the packaging structure meets the requirements of high-density miniaturization design.

[0110] In some examples, such as Fig.12, the devices arranged on both sides of the first redistribution layer can be interconnected, for example, device 11 can be interconnected with at least one of device 31, device 32 and device 33. The pattern layer of device 11 can face the first redistribution layer, and the pattern layer of device 11 is electrically connected to the first redistribution layer. The pattern layers of devices 31, device 32 and device 33 face the first redistribution layer, and the pattern layers of devices 31, device 32 and device 33 are electrically connected to the first redistribution layer. Thus, the first redistribution layer can be used to realize the interconnection of devices 11, device 31, device 32 and device 33.

[0111] In other examples, such as Fig.12 , the devices arranged on both sides of the second redistribution layer can be interconnected, for example, at least one of the device 21 and the device 22 can be interconnected with the device 41. The pattern layers of the devices 21 and 22 can face the second redistribution layer, and the pattern layers of the devices 21 and 22 are electrically connected to the second redistribution layer, and the pattern layer of the device 41 faces the second redistribution layer, and the pattern layer of the device 41 is electrically connected to the second redistribution layer, so that the second redistribution layer can be used to realize the interconnection of the devices 21, 22 and 41.

[0112] It can be understood that: the devices located in the middle layer (devices located in the first substrate and the second substrate) can be partially interconnected upwards and partially interconnected downwards. The devices located in the middle layer can be arranged up and down according to their respective functions, shortening the interconnection distance between the middle layer devices and the upper and lower devices.

[0113] like Fig.12 In the illustrated multi-layer chip stacking package structure, the first package body is used to package the device 31 , the device 32 , and the device 33 , and the second package body is used to package the device 41 . In some examples, the first package body and the second package body may be made of plastic packaging materials.

[0114] Before using plastic encapsulation material to encapsulate devices 31, device 32 and device 33, devices 31, device 32 and device 33 can be connected to the first redistribution layer through a welding process. When these devices are then encapsulated using liquid plastic encapsulation material, the liquid plastic encapsulation material will basically not cause drift of these devices and will basically not affect the electrical connection between the devices and the redistribution layer.

[0115] In the multi-layer chip stacking packaging structure, the device heat dissipation problem is also a technical difficulty of the packaging structure. In order to improve the heat dissipation effect, such as Fig.12 , the components with higher power and more heat dissipation can be placed in the upper and lower layers, for example, they can be placed in the first package body or in the second package body. In this way, the heat dissipation path can be shortened and the heat dissipation efficiency of the components can be improved.

[0116] In order to make Fig.12The multi-layer chip stacking package structure shown is connected to the circuit board, and a connection structure can be set, such as Fig.12 , can be set on a connecting pin, one end of the connecting pin is electrically connected to the second redistribution layer, and the other end can be electrically connected to the circuit board, so that the multi-layer chip stacking packaging structure is interconnected with other devices on the circuit board.

[0117] The present application also provides a method for preparing a multi-layer chip stacking packaging structure. Fig.13 The flowchart of preparing a multi-layer chip stacking packaging structure is shown as an example. The method includes:

[0118] S1: a first redistribution layer is fabricated on one side of a first substrate, wherein a first device is disposed in the first substrate.

[0119] S2: a second redistribution layer is fabricated on one side of a second substrate, wherein a second device is disposed in the second substrate.

[0120] S3: bonding a side of the first substrate away from the first redistribution layer to a side of the second substrate away from the second redistribution layer.

[0121] In the above-mentioned example method, before the first substrate and the second substrate are bonded, redistribution layers are first prepared on the first substrate and the second substrate respectively, and the two redistribution layers are arranged on different substrates instead of being integrated on one substrate. This can weaken the effects caused by the preparation of the redistribution layers, such as warping and delamination, or the degree of damage to the device.

[0122] The following is a detailed description of a method for preparing a multi-layer chip stacking packaging structure in conjunction with the accompanying drawings.

[0123] like Fig.14A A groove is formed in the first substrate. The groove may not pass through two opposite surfaces of the first substrate.

[0124] The material of the first substrate in the example of the present application may be a semiconductor substrate, such as a silicon substrate, or a glass substrate.

[0125] See you next time Fig.14A A first conductive via is provided in the first substrate. The first conductive via may not penetrate through two opposite surfaces of the first substrate.

[0126] like Fig. 14B , set the device to Fig.14A Open in the groove. For example, Fig. 14B In the embodiment, device 11, device 12 and device 13 are respectively arranged in corresponding grooves.

[0127] exist Fig. 14BIn the example, the pattern layers of the device 11 and the device 12 are both facing upward, and the pattern layer of the device 13 is facing the bottom of the groove. The device 13 may be a cavity type device.

[0128] In some scenarios, the orientation of the device pattern layer may be set according to the device interconnection method.

[0129] The number of devices disposed in the first substrate may be one or more.

[0130] like Fig. 14C A first redistribution layer is formed on one side of the first substrate, wherein the first redistribution layer can be interconnected with the device 11 and the device 12; and the first redistribution layer can be interconnected with the first conductive via.

[0131] In some examples, the metal routing in the first redistribution layer can be 4 layers, 5 layers, or even more layers.

[0132] like Fig.14D ,Will Fig. 14C The resulting structure is temporarily bonded to a carrier.

[0133] like Fig.14E The back surface of the first substrate is thinned so that the end surface of the first conductive via is exposed.

[0134] When the pattern layer of the device disposed in the first substrate is away from the first redistribution layer, the pattern layer of the device needs to be exposed when the first substrate is thinned. Fig.14E , it is necessary to expose the pattern layer of the cavity type device.

[0135] like Fig.14F A groove is formed in the second substrate. The groove may not pass through two opposite surfaces of the second substrate.

[0136] The material of the second substrate in the example of the present application may be the same as that of the first substrate, for example, it may be a silicon substrate or a glass substrate.

[0137] See you next time Fig.14F A second conductive via is provided in the second substrate. The second conductive via may not penetrate through two opposite surfaces of the second substrate.

[0138] like Figure 14G , set the device to Fig.14F Open in the groove. For example, Fig.14F In the embodiment, the device 21, the device 22 and the device 23 are respectively arranged in the corresponding grooves.

[0139] exist Figure 14G In the example, the pattern layers of device 21, device 22 and device 23 are all facing upward.

[0140] The number of devices disposed in the second substrate may be one or more.

[0141] like Fig.14H A second redistribution layer is formed on one side of the second substrate, wherein the second redistribution layer can be interconnected with the device 21, the device 22 and the device 12; and the second redistribution layer can be interconnected with the second conductive via.

[0142] In some examples, the metal routing in the second redistribution layer may be 4 layers, 5 layers, or even more layers. The metal routing may also be less than four layers.

[0143] like Fig.14I ,Will Fig.14H The resulting structure is temporarily bonded to a carrier.

[0144] like Fig.14J , the back side of the second substrate is thinned so that the end surface of the second conductive through hole is exposed.

[0145] like Figure 14K , using wafer bonding technology Fig.14D and Fig.14J The bonding is shown, so that the first substrate and the second substrate are bonded to each other to obtain Figure 14L The multi-layer chip stacking structure shown.

[0146] In some optional processes, an anodic bonding process or a hybrid bonding process may be used to bond the first substrate and the second substrate.

[0147] In some processes, before the first substrate and the second substrate are bonded by wafer bonding, the carrier bonded to the first substrate and the carrier bonded to the second substrate may be removed.

[0148] As mentioned above Fig. 14C and Fig.14H As shown, when preparing a multi-layer chip stacking packaging structure with a double-sided redistribution layer, the redistribution layer is first made on different substrates, and then the substrates already provided with the redistribution layer are bonded and connected to realize a double-sided redistribution layer structure.

[0149] The preparation of double-sided redistribution layers will not affect each other, which can reduce the number of temperature shocks of photoresist curing, thereby reducing the risk of delamination or warping.

[0150] like Fig.14M ,Will Figure 14L The multi-layer chip stack structure is temporarily bonded to a carrier board, and devices are arranged on a side of the first redistribution layer away from the first substrate. For example, devices 31, 32 and 33 may be arranged.

[0151] The pattern layers of the devices 31 , 32 and 33 may all face the first redistribution layer to achieve interconnection with the first redistribution layer.

[0152] The device disposed on the first redistribution layer can be packaged to obtain Fig.14M The first package is shown.

[0153] In some processes, such as Fig.14M , there is no need for temporary bonding of the carrier.

[0154] like Fig.14N , remove Fig.14M In the carrier board, a device is arranged on a side of the second redistribution layer away from the second substrate, for example, the device 41 can be arranged.

[0155] The device disposed on the second redistribution layer can be packaged to obtain Fig.14N The second package is shown.

[0156] Furthermore, a connecting pin can be manufactured, which passes through the second package body and is interconnected with the second redistribution layer.

[0157] The pattern layers of the device 41 may all face the second redistribution layer to achieve interconnection with the second redistribution layer.

[0158] Prepared as Fig.14N The four-layer stacked package structure shown can be arranged on a circuit board and electrically connected to the circuit board using connecting pins.

[0159] In the description of this specification, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0160] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A multi-layer chip stacking packaging structure, It is characterized in that include: a first substrate, wherein a first device is disposed in the first substrate; A first redistribution layer is disposed on one side of the first substrate; a second substrate, wherein a second device is disposed in the second substrate; A second redistribution layer is disposed on one side of the second substrate; A side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer.

2. The multi-layer chip stacking package structure according to claim 1, It is characterized in that The first device has a first pattern layer on a side facing the second substrate; The second substrate has a first side surface facing the first substrate, and the first side surface and the first device form a cavity; The first pattern layer is located in the cavity.

3. The multi-layer chip stacking package structure according to claim 1, It is characterized in that The first device and the second device are arranged face to face, and the first device and the second device enclose a cavity; The first device has a first pattern layer on a side facing the second substrate; The second device has a second pattern layer on a side facing the first substrate; The first pattern layer and the second pattern layer are both located in the cavity.

4. The multi-layer chip stacking package structure according to claim 2 or 3, It is characterized in that The first device includes at least one of a filter and a multiplexer.

5. The multi-layer chip stacking package structure according to claim 1, It is characterized in that The first device and the second device are arranged face to face, and the pattern layer of the first device faces the pattern layer of the second device; The pattern layer of the first device is bonded to the pattern layer of the second device.

6. The multi-layer chip stacking package structure according to any one of claims 1 to 5, It is characterized in that The pattern layer of the first device faces the second substrate; A conductive through hole is disposed in the first device along a thickness direction of the first device, and the conductive through hole electrically connects the first redistribution layer and the pattern layer of the first device.

7. The multi-layer chip stacking package structure according to claim 1, It is characterized in that A third device is disposed on a side of the first redistribution layer facing away from the first substrate; The pattern layer of the first device faces the first redistribution layer, and the pattern layer of the third device faces the first redistribution layer; The pattern layer of the first device and the pattern layer of the third device are both electrically connected to the first redistribution layer.

8. The multi-layer chip stacking package structure according to claim 7, It is characterized in that A fourth device is disposed on a side of the second redistribution layer facing away from the second substrate; The pattern layer of the second device faces the second redistribution layer, and the pattern layer of the fourth device faces the second redistribution layer; The pattern layer of the second device and the pattern layer of the fourth device are both electrically connected to the second redistribution layer.

9. The multi-layer chip stacking package structure according to claim 8, It is characterized in that A first package is provided on the side of the first redistribution layer facing away from the first substrate, and the third device is located in the first package; a second package is provided on the side of the second redistribution layer facing away from the second substrate, and the fourth device is located in the second package.

10. A method for preparing a multi-layer chip stacking packaging structure, It is characterized in that The preparation method comprises: A first redistribution layer is formed on one side of a first substrate, wherein a first device is disposed in the first substrate; Producing a second redistribution layer on one side of a second substrate, wherein a second device is disposed in the second substrate; A side of the first substrate facing away from the first redistribution layer is bonded to a side of the second substrate facing away from the second redistribution layer.

11. The method for preparing a multi-layer chip stacking packaging structure according to claim 10, It is characterized in that Before forming the first redistribution layer on one side of the first substrate, the preparation method further includes: A first groove is opened in the first substrate, and the first device is set in the first groove, with the pattern layer of the first device facing away from the opening of the first groove. After the first substrate and the second substrate are bonded, the pattern layer of the first device is located in a cavity surrounded by the first device and the second substrate.

12. The method for preparing a multi-layer chip stacking packaging structure according to claim 10, It is characterized in that Before forming the first redistribution layer on one side of the first substrate and before forming the second redistribution layer on one side of the second substrate, the preparation method further includes: Opening a first groove in the first substrate, disposing the first device in the first groove, with the pattern layer of the first device facing away from the opening of the first groove; Opening a second groove in the second substrate, disposing the second device in the second groove, with the pattern layer of the second device facing away from the opening of the second groove; The bonding of the first substrate and the second substrate comprises: The pattern layer of the first device and the pattern layer of the second device are arranged face to face, the first device and the second device surround a cavity, and the pattern layer of the first device and the pattern layer of the second device are both located in the cavity.

13. The method for preparing a multi-layer chip stacking packaging structure according to any one of claims 10 to 12, It is characterized in that After the first substrate and the second substrate are bonded, the preparation method further includes: Disposing a third device on a side of the first redistribution layer away from the first substrate; A fourth device is disposed on a side of the second redistribution layer facing away from the second substrate.

14. An electronic device, It is characterized in that include: Circuit boards; The multi-layer chip stacking packaging structure as described in any one of claims 1-9, wherein the multi-layer chip stacking packaging structure is arranged on the circuit board.

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