Chip packaging structure, chip inverted packaging method and electronic equipment

Abstract

The invention provides a chip packaging structure, a chip inverted packaging method and electronic equipment, relates to the field of semiconductors, does not occupy resources of bare chips and electronic devices, and also can filter high-frequency noise. The chip packaging structure comprises a bare chip, an electronic device, a plurality of conductive bumps and a first capacitor. The bare chip comprises a first wire, and the electronic device comprises a second wire and a third wire. The plurality of conductive salient points are arranged between the bare chip and the electronic device, and the plurality of conductive salient points comprise first conductive salient points and second conductive salient points. The first capacitor is arranged between the bare chip and the first conductive bump; the first wire is electrically connected with the second wire through the first capacitor and the first conductive bump; and the first wire is also electrically connected with the third wire through the second conductive bump. Wherein the first wire and the third wire are grounding wires, and the second wire is a power supply wire; or, the first wire and the third wire are power wires, and the second wire is a grounding wire.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a chip packaging structure, a chip flip packaging method, and an electronic device. Background Art

[0002] As the speed, power consumption and complexity of chips increase, the chip power integrity (PI) problem has gradually become a key bottleneck for the overall function and performance of the chip. Therefore, the demand for decoupling capacitors (decap) has increased. According to the placement of decoupling capacitors, decoupling capacitors are generally divided into: on-die decoupling capacitors (on die decap), package built-in decoupling capacitors (package decap), and board-level decoupling capacitors (board decap).

[0003] However, on-chip decoupling capacitors occupy resources on the bare chip and are costly. The built-in decoupling capacitors in the package affect the routing of the package substrate, increase the assembly cost of the package substrate, and the density of the decoupling capacitors is low. In addition, the decoupling capacitors are far away from the load in the bare chip, which is not conducive to filtering high-frequency noise. The filtering range of board-level decoupling capacitors is limited, and they mainly filter low-frequency noise.

[0004] Therefore, using decoupling capacitors to filter out high-frequency noise without occupying the active area resources of the bare chip and the packaging substrate is an urgent problem to be solved. Summary of the invention

[0005] In order to solve the above technical problems, the present application provides a chip packaging structure, a chip flip packaging method, and an electronic device. By setting a first capacitor between a bare chip and a first conductive bump, the resources of the bare chip and the electronic device are not occupied, and high-frequency noise can be filtered out.

[0006] In a first aspect, the present application provides a chip packaging structure, which includes a bare chip, an electronic device, a plurality of conductive bumps, and a first capacitor. The bare chip includes a first routing line, and the electronic device includes a second routing line and a third routing line. The plurality of conductive bumps are arranged between the bare chip and the electronic device, and the plurality of conductive bumps include a first conductive bump and a second conductive bump. The first capacitor is arranged between the bare chip and the first conductive bump; the first routing line is electrically connected to the second routing line through the first capacitor and the first conductive bump; the first routing line is also electrically connected to the third routing line through the second conductive bump. Among them, the first routing line and the third routing line are ground routing lines, and the second routing line is a power routing line; or, the first routing line and the third routing line are power routing lines, and the second routing line is a ground routing line.

[0007] The first capacitor in the present application is used as a decoupling capacitor. By making the first capacitor occupy part of the original first conductive bump, the first capacitor is set between the bare chip and the first conductive bump. In addition, the first capacitor is also electrically connected to the second routing line through the first conductive bump, so that the first capacitor is electrically connected between the power routing line and the ground routing line. Compared with the on-chip decoupling capacitor, the first capacitor of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the package built-in decoupling capacitor, the first capacitor of the present application does not affect the routing of the electronic device, saving costs, and the first capacitor can be set at a high density; and the distance between the first capacitor of the present application and the active area in the bare chip is closer than the distance between the package built-in decoupling capacitor and the active area in the bare chip, so the first capacitor of the present application is more conducive to filtering high-frequency noise. The distance between the first capacitor of the present application and the active area in the bare chip is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip, so the first capacitor of the present application is more conducive to filtering high-frequency noise.

[0008] In some possible implementations, the bare chip further includes a fourth routing line, the plurality of conductive bumps further includes a third conductive bump, and the fourth routing line is electrically connected to the second routing line through the third conductive bump. The second routing line and the fourth routing line are both ground routing lines; or the second routing line and the fourth routing line are both power routing lines. In this way, taking a transistor electrically connected between the power routing line and the ground routing line as an example, the first capacitor is electrically connected between the power routing line and the ground routing line, the drain of the transistor is electrically connected to the ground routing line, and the source of the transistor is electrically connected to the power routing line.

[0009] In some possible implementations, there are multiple first capacitors and multiple first conductive bumps, and multiple first capacitors are connected in parallel between the first trace and the second trace. In this way, different capacitance requirements can be achieved by designing the capacitance values ​​of the two first capacitors according to the parallel relationship of the two first capacitors.

[0010] In some possible implementations, the chip packaging structure further includes a second capacitor disposed between the first conductive bump and the electronic device, and the first wiring is electrically connected to the second wiring through the first capacitor, the first conductive bump, and the second capacitor.

[0011] Compared with the on-chip decoupling capacitor, the second capacitor of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the built-in decoupling capacitor of the package, the second capacitor of the present application does not affect the routing of the electronic device, saving costs, and the second capacitor can be set at a high density; and the distance between the second capacitor of the present application and the active area in the bare chip is closer than the distance between the built-in decoupling capacitor of the package and the active area in the bare chip, so the second capacitor of the present application is more conducive to filtering high-frequency noise. The distance between the second capacitor of the present application and the active area in the bare chip is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip, so the second capacitor of the present application is more conducive to filtering high-frequency noise.

[0012] On this basis, different capacitance requirements can be achieved by designing the capacitance value of the first capacitor and the capacitance value of the second capacitor according to the series relationship between the first capacitor and the second capacitor.

[0013] In some possible implementations, the chip packaging structure further includes a first seed layer disposed between the bare chip and the plurality of conductive bumps, and a second seed layer disposed between the electronic device and the plurality of conductive bumps; the first capacitor is disposed between the first conductive bump and the first seed layer. In this way, the first seed layer and the second seed layer can also be used to prevent the material of the plurality of conductive bumps from reacting with the first connection pad of the bare chip and the second connection pad of the electronic device.

[0014] In some possible implementations, along the direction from the bare chip to the electronic device, the first capacitor includes a first electrode, a first dielectric layer, and a second electrode, and the first conductive bump is reused as the second electrode. Along the direction from the electronic device to the bare chip, the second capacitor includes a third electrode, a second dielectric layer, and a fourth electrode, and the first conductive bump is also reused as the fourth electrode.

[0015] In some possible implementations, the electronic device is a packaging substrate, and the bare chip is flip-packaged on the packaging substrate.

[0016] In a second aspect, the present application provides a chip flip packaging method, comprising: forming a first capacitor and a plurality of first bumps on a bare chip in sequence to obtain a first substrate; the bare chip comprises a first routing line, and the plurality of first bumps comprise a first sub-bump and a second sub-bump; the first capacitor is located between the bare chip and the first sub-bump. Forming a plurality of second bumps on an electronic device to obtain a second substrate; the electronic device comprises a second routing line and a third routing line, and the plurality of second bumps comprise a third sub-bump and a fourth sub-bump. The first substrate and the second substrate are matched; the first sub-bump and the third sub-bump are arranged one by one opposite to each other, and the second sub-bump and the fourth sub-bump are arranged one by one opposite to each other; the first routing line is electrically connected to the second routing line through the first capacitor, the first sub-bump, and the third sub-bump; the first routing line is also electrically connected to the third routing line through the second sub-bump and the fourth sub-bump; wherein the first routing line and the third routing line are ground routing lines, and the second routing line is a power routing line; or the first routing line and the third routing line are power routing lines, and the second routing line is a ground routing line.

[0017] In some possible implementations, before forming multiple second bumps on the electronic device, the chip flip packaging method also includes: forming a second capacitor on the electronic device; the second capacitor is located between the third sub-bump and the electronic device, and the first routing is electrically connected to the second routing through the first capacitor, the first sub-bump, the third sub-bump, and the second capacitor.

[0018] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can refer to the technical effects corresponding to the above-mentioned first aspect and any implementation of the first aspect, which will not be repeated here.

[0019] The foregoing describes the situation where the first conductive bump and the second conductive bump are electrically connected to the same first trace in the bare chip. In other possible implementations, the first conductive bump and the second conductive bump may also be electrically connected to the same trace in the package substrate, as specifically described in the third and fourth aspects of the specification.

[0020] In a third aspect, the present application provides a chip packaging structure, which includes a bare chip, an electronic device, a plurality of conductive protrusions, and a first capacitor. The bare chip includes a first routing line and a second routing line, and the electronic device includes a third routing line. A plurality of conductive bumps are arranged between the bare chip and the electronic device, and the plurality of conductive bumps include a first conductive bump and a second conductive bump. The first capacitor is arranged between the bare chip and the first conductive bump; the first routing line is electrically connected to the third routing line through the first capacitor and the first conductive bump, and the second routing line is electrically connected to the third routing line through the second conductive bump. The first routing line is a ground routing line, and the second routing line and the third routing line are power routing lines; or, the first routing line is a power routing line, and the second routing line and the third routing line are ground routing lines.

[0021] The first capacitor in the present application is used as a decoupling capacitor. By making the first capacitor occupy part of the original first conductive bump, the first capacitor is set between the bare chip and the first conductive bump. In addition, the first capacitor is also electrically connected to the third routing line through the first conductive bump, so that the first capacitor is electrically connected between the power routing line and the ground routing line. Compared with the on-chip decoupling capacitor, the first capacitor of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the package built-in decoupling capacitor, the first capacitor of the present application does not affect the routing of the electronic device, saving costs, and the first capacitor can be set at a high density; and the distance between the first capacitor of the present application and the active area in the bare chip is closer than the distance between the package built-in decoupling capacitor and the active area in the bare chip, so the first capacitor of the present application is more conducive to filtering high-frequency noise. The distance between the first capacitor of the present application and the active area in the bare chip is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip, so the first capacitor of the present application is more conducive to filtering high-frequency noise.

[0022] In some possible implementations, the electronic device further includes a fourth routing line, the plurality of conductive bumps further include a third conductive bump, and the fourth routing line is electrically connected to the first routing line through the third conductive bump. The first routing line and the fourth routing line are both ground routing lines; or the first routing line and the fourth routing line are both power routing lines. In this way, taking a transistor electrically connected between the power routing line and the ground routing line as an example, the first capacitor is electrically connected between the power routing line and the ground routing line, the drain of the transistor is electrically connected to the ground routing line, and the source of the transistor is electrically connected to the power routing line.

[0023] In some possible implementations, there are multiple first capacitors and multiple first conductive bumps, and multiple first capacitors are connected in parallel between the first wiring and the third wiring. In this way, different capacitance requirements can be achieved by designing the capacitance values ​​of the two first capacitors according to the parallel relationship of the two first capacitors.

[0024] In some possible implementations, the chip packaging structure further includes a second capacitor disposed between the first conductive bump and the electronic device, and the first wiring is electrically connected to the third wiring through the first capacitor, the first conductive bump, and the second capacitor.

[0025] Compared with the on-chip decoupling capacitor, the second capacitor of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the built-in decoupling capacitor of the package, the second capacitor of the present application does not affect the routing of the electronic device, saving costs, and the second capacitor can be set at a high density; and the distance between the second capacitor of the present application and the active area in the bare chip is closer than the distance between the built-in decoupling capacitor of the package and the active area in the bare chip, so the second capacitor of the present application is more conducive to filtering high-frequency noise. The distance between the second capacitor of the present application and the active area in the bare chip is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip, so the second capacitor of the present application is more conducive to filtering high-frequency noise.

[0026] On this basis, different capacitance requirements can be achieved by designing the capacitance value of the first capacitor and the capacitance value of the second capacitor according to the series relationship between the first capacitor and the second capacitor.

[0027] In some possible implementations, the chip packaging structure further includes a first seed layer disposed between the bare chip and the plurality of conductive bumps, and a second seed layer disposed between the electronic device and the plurality of conductive bumps, and the first capacitor is disposed between the first conductive bump and the seed layer. In this way, the first seed layer and the second seed layer can also be used to prevent the material of the plurality of conductive bumps from reacting with the first connection pad of the bare chip and the second connection pad of the electronic device.

[0028] In some possible implementations, the electronic device is a packaging substrate, and the bare chip is flip-packaged on the packaging substrate.

[0029] In a fourth aspect, the present application provides a chip flip packaging method, comprising: forming a first capacitor and a plurality of first bumps on a bare chip in sequence to obtain a first substrate; the bare chip comprises a first routing line and a second routing line, and the plurality of first bumps comprise a first sub-bump and a second sub-bump; the first capacitor is located between the bare chip and the first sub-bump. Forming a plurality of second bumps on an electronic device to obtain a second substrate; the electronic device comprises a third routing line, and the plurality of second bumps comprise a third sub-bump and a fourth sub-bump. The first substrate and the second substrate are matched; the first sub-bump and the third sub-bump are arranged one by one in a positive direction, and the second sub-bump and the fourth sub-bump are arranged one by one in a positive direction; the first routing line is electrically connected to the third routing line through the first capacitor, the first sub-bump, and the third sub-bump; the second routing line is electrically connected to the third routing line through the second sub-bump and the fourth sub-bump; wherein the first routing line is a ground routing line, and the second routing line and the third routing line are power routing lines; or, the first routing line is a power routing line, and the second routing line and the third routing line are ground routing lines.

[0030] In some possible implementations, before forming multiple second bumps on the electronic device, the chip flip packaging method also includes: forming a second capacitor on the electronic device; the second capacitor is located between the third sub-bump and the electronic device, and the first routing is electrically connected to the third routing through the first capacitor, the first sub-bump, the third sub-bump, the second capacitor, and the third routing.

[0031] The fourth aspect and any implementation of the fourth aspect correspond to the third aspect and any implementation of the third aspect, respectively. The technical effects corresponding to the fourth aspect and any implementation of the fourth aspect can refer to the technical effects corresponding to the third aspect and any implementation of the third aspect, which will not be repeated here.

[0032] In a fifth aspect, the present application provides an electronic device, which includes a circuit board, solder balls, and the chip packaging structure described in the first aspect or the third aspect, wherein the electronic devices of the chip packaging structure are soldered to the circuit board through solder balls.

[0033] The fifth aspect and any implementation of the fifth aspect correspond to the first aspect, the third aspect, and any implementation of the first aspect and the third aspect, respectively. The technical effects corresponding to the fifth aspect and any implementation of the fifth aspect can refer to the technical effects corresponding to the first aspect, the third aspect, and any implementation of the first aspect and the third aspect, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1a A top view of a bare chip provided in an embodiment of the present application;

[0035] Figure 1b A diagram of the connection between the chip packaging structure and the circuit board provided for the related technology;

[0036] Figure 2 A diagram of the location of the decoupling capacitor provided for the related art;

[0037] Figure 3a A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0038] Figure 3b for Figure 3a The circuit diagram corresponding to the chip packaging structure shown;

[0039] Figure 3c A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0040] Figure 3d for Figure 3c The circuit diagram corresponding to the chip packaging structure shown;

[0041] Figure 4aA schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0042] Figure 4b for Figure 4a The circuit diagram corresponding to the chip packaging structure shown;

[0043] Figure 4c A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0044] Figure 4d for Figure 4c The circuit diagram corresponding to the chip packaging structure shown;

[0045] Figure 5a A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0046] Figure 5b A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0047] Figure 6a A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0048] Figure 6b A schematic diagram of a first capacitor and a second capacitor provided in an embodiment of the present application;

[0049] Figure 6c A schematic diagram of a first capacitor and a second capacitor provided in an embodiment of the present application;

[0050] Figure 6d for Figure 6c A1-A2 sectional view;

[0051] Figure 7 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0052] Figure 8 A schematic diagram of a chip packaging structure provided in an embodiment of the present application;

[0053] Fig. 9 A flowchart of the chip packaging structure provided in the embodiment of the present application;

[0054] Figure 10a-10h A process diagram of forming a first capacitor and a first bump on a bare chip provided in an embodiment of the present application;

[0055] Figure 11a-Figure 11c A process diagram of forming a second bump on a packaging substrate provided in an embodiment of the present application;

[0056] Figure 12a-12e A process diagram of forming a second capacitor and a second bump on a packaging substrate provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0058] The term "and / or" in this article is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0059] The terms "first" and "second" in the description and claims of the embodiments of the present application are used to distinguish different objects rather than to describe a specific order of objects. For example, a first target object and a second target object are used to distinguish different target objects rather than to describe a specific order of target objects.

[0060] In the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0061] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "multiple" refers to two or more than two. For example, multiple processing units refer to two or more processing units; multiple systems refer to two or more systems.

[0062] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a household electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a chip.

[0063] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, storage devices, radars, base stations, and other communication equipment that contain chips.

[0064] For the convenience of explanation, the following description takes a mobile phone as an example of an electronic device. The mobile phone may include a circuit board, and a processor, a memory, etc. may be integrated on the circuit board. For example, the processor may be implemented by connecting circuits on one or more chips. Of course, the mobile phone may also include other components, and other circuit structures may be integrated on the circuit board, which is not limited in the embodiments of the present application.

[0065] With the increase of chip interconnection density and the continuous reduction of interconnection size, chip packaging technology has become more and more diversified. Since the chip flip-chip technology can shorten the interconnection length within the package and better adapt to the development needs of high integration, it has been widely used in the field of chip packaging. The chip flip-chip technology is to directly make conductive bumps on the bare chip as connection terminals, and solder them on the packaging substrate in a flip-chip manner, so as to achieve electrical connection between the bare chip and the packaging substrate.

[0066] Specifically, Figure 1a FIG. 1 shows a top view of a bare chip 10, wherein the bare chip 10 includes a first connection pad 11, which may also be referred to as a solder pad or other names. Figure 1b As shown, the bare chip 10 is flipped on the packaging substrate 20, and the conductive bumps 30 are respectively in contact with the first connection pad 11 of the bare chip 10 and the second connection pad 21 of the packaging substrate 20, so that the first connection pad 11 is electrically connected to the second connection pad 21 through the conductive bumps 30, thereby leading the first connection pad 11 in the bare chip 10 to the second connection pad 21 of the packaging substrate 20 through the conductive bumps 30.

[0067] like Figure 1bAs shown, the packaging substrate 20 also includes a third connection pad 22 opposite to the second connection pad 21. The second connection pad 21 and the third connection pad 22 are electrically connected through the wiring layer in the packaging substrate 20. The bare chip 10 is soldered to the circuit board 40 through the third connection pad 22 and the solder balls in the packaging substrate 20.

[0068] As mentioned in the background technology, as the speed, power consumption and complexity of chips increase, the chip power integrity (PI) problem has gradually become a key bottleneck for the overall function and performance of the chip. Therefore, the demand for decoupling capacitors (decap) in chips has increased. According to the placement of decoupling capacitors, decoupling capacitors are generally divided into: on-chip decoupling capacitors, package built-in decoupling capacitors, and board-level decoupling capacitors.

[0069] On-chip decoupling capacitors are formed in the back end of line (BEOL) process of the bare chip. Figure 2 As shown, the package built-in decoupling capacitor generally refers to a surface capacitor or a back-mounted capacitor disposed on the package substrate 20. Figure 2 As shown, the board-level decoupling capacitor is arranged on the circuit board 40 .

[0070] However, on-chip decoupling capacitors occupy resources on the bare chip 10 and are costly. The built-in decoupling capacitors in the package affect the routing of the package substrate 20, increase the assembly cost of the package substrate 20, and the density of the decoupling capacitors is low. In addition, the decoupling capacitors are far away from the active area in the bare chip 10, which is not conducive to filtering out high-frequency noise. The filtering range of the board-level decoupling capacitors is limited, and they mainly filter out low-frequency noise. Among them, the active area refers to: the area in the bare chip 10 where the transistors made using the previous process are located.

[0071] As chip speed, power consumption and complexity increase, high-frequency noise in chip power network circuits becomes more and more serious. How to solve high-frequency noise with low-cost decoupling capacitor solutions has become a research hotspot.

[0072] Based on this, an embodiment of the present application provides a chip packaging structure, which can be applied to circuits that need to filter out high-frequency noise, such as chip power network circuits, signal isolation circuits, etc.

[0073] like Figure 3a and Figure 4a As shown, the chip packaging structure includes a bare chip 10, an electronic device, a plurality of conductive bumps 30, and a first capacitor 51. The electronic device may be a packaging substrate 20, an integrated passive device (IPD), etc. For the convenience of description, the electronic device is taken as the packaging substrate 20 as an example for description.

[0074] The bare chip 10 includes a first trace 11, and the package substrate 20 includes a second trace 21 and a third trace 22. A plurality of conductive bumps 30 are disposed between the bare chip 10 and the package substrate 20, and the plurality of conductive bumps 30 include a first conductive bump 31 and a second conductive bump 32. The first capacitor 51 is disposed between the bare chip 10 and the first conductive bump 31. It can also be said that the first capacitor 51 is a part of the first conductive bump 31, and in the first conductive bump 31, the first capacitor 51 is closer to the bare chip 10.

[0075] The first wiring 11 is electrically connected to the second wiring 21 through the first capacitor 51 and the first conductive bump 31, and the first wiring 11 is also electrically connected to the third wiring 22 through the second conductive bump 32. Figure 3a As shown, the first line 11 and the third line 22 are ground lines, and the second line 21 is a power line. Figure 4a As shown, the first wiring 11 and the third wiring 22 are power wirings, and the second wiring 21 is a ground wiring.

[0076] The first capacitor 51 in the present application is used as a decoupling capacitor. By making the first capacitor 51 occupy part of the original first conductive bump 31, the first capacitor 51 is set between the bare chip 10 and the first conductive bump 31. In addition, the first capacitor 51 is also electrically connected to the second wiring 21 through the first conductive bump 31, so that the first capacitor 51 is electrically connected between the power wiring and the ground wiring. Compared with the on-chip decoupling capacitor, the first capacitor 51 of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the package built-in decoupling capacitor, the first capacitor 51 of the present application does not affect the wiring of the package substrate 20, saving costs, and the first capacitor can be set at a high density; and the distance between the first capacitor 51 of the present application and the active area in the bare chip 10 is closer than the distance between the package built-in decoupling capacitor and the active area in the bare chip 10. Therefore, the first capacitor 51 of the present application is more conducive to filtering out high-frequency noise. The distance between the first capacitor 51 of the present application and the active area in the bare chip 10 is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip 10 . Therefore, the first capacitor 51 of the present application is more conducive to filtering out high-frequency noise.

[0077] In addition, the bare chip 10 may further include a plurality of transistors and conductive wires 70. The transistor includes a channel layer 61, a source 62, and a drain 63.

[0078] For example, a transistor is electrically connected between a power line and a ground line. Figure 3a and Figure 3bAs shown, if the first routing line 11 and the third routing line 22 are ground routing lines, and the second routing line 21 is a power routing line, the drain electrode 63 of the transistor is electrically connected to different conductive bumps through the same ground routing line in the bare chip 10. Specifically, the ground routing line in the bare chip 10 is electrically connected to the ground routing line in the package substrate 20 through the conductive lead 70 and the second conductive bump 32, and the ground routing line in the bare chip 10 is also electrically connected to the power routing line in the package substrate 20 through the conductive lead 70, the first capacitor 51, and the first conductive bump 31. In this way, the first capacitor 51 is electrically connected between the power routing line and the ground routing line, and the drain electrode 63 of the transistor is electrically connected to the ground routing line. In the embodiment of the present application, the power supply in the circuit diagram represents the power routing line.

[0079] On this basis, if Figure 3a and Figure 3b As shown, the bare chip 10 also includes a fourth routing line 22, which is a power routing line. The plurality of conductive bumps also include a third conductive bump 33, and the source 62 of the transistor is electrically connected to the power routing line in the package substrate 20 through the power routing line and the conductive lead 70 in the bare chip 10 and the third conductive bump 33. In this way, the source 62 of the transistor is electrically connected to the power routing line. Among them, the power routing line electrically connected to the first conductive bump 31 in the package substrate 20 and the routing line electrically connected to the third conductive bump 31 in the package substrate 20 are the same second routing line 21.

[0080] Among some possible implementations, Figure 3a and Figure 3b As shown, the number of the first conductive bump 31 and the number of the first capacitor 51 are both one; or Figure 3c and Figure 3d As shown, the number of the first conductive bumps 31 and the number of the first capacitors 51 are both multiple. For example, the number of the first conductive bumps 31 and the number of the first capacitors 51 are both two, and the two first capacitors 51 are connected in parallel between the grounding line and the power supply line. In this way, different capacitance requirements can be achieved by designing the capacitance values ​​of the two first capacitors 51 according to the parallel relationship of the two first capacitors 51.

[0081] Still taking a transistor electrically connected between a power supply line and a ground line as an example, Figure 4a and Figure 4bAs shown, if the first line 11 and the third line 22 are power lines, and the second line 21 is a ground line, the source 62 of the transistor is electrically connected to different conductive bumps through the same power line in the bare chip 10. Specifically, the power line in the bare chip 10 is electrically connected to the power line in the package substrate 20 through the conductive lead 70 and the second conductive bump 32, and the power line in the bare chip 10 is also electrically connected to the ground line in the package substrate 20 through the conductive lead 70, the first capacitor 51, and the first conductive bump 31. In this way, the first capacitor 51 is electrically connected between the power line and the ground line, and the source 62 of the transistor is electrically connected to the power line.

[0082] On this basis, if Figure 4a and Figure 4b As shown, the bare chip 10 also includes a fourth routing line 22, which is a ground routing line. The plurality of conductive bumps also include a third conductive bump 33, and the drain of the transistor is electrically connected to the ground routing line in the package substrate 20 through the ground routing line and the conductive lead 70 in the bare chip 10, and the third conductive bump 33. In this way, the drain 63 of the transistor is electrically connected to the ground routing line. Among them, the ground routing line electrically connected to the first conductive bump 31 in the package substrate 20 and the ground routing line electrically connected to the third conductive bump 31 in the package substrate 20 are the same second routing line 21.

[0083] Among some possible implementations, Figure 4a and Figure 4b As shown, the number of the first conductive bump 31 and the number of the first capacitor 51 are both one; or Figure 4c and Figure 4d As shown, the number of the first conductive bumps 31 and the number of the first capacitors 51 are both multiple. For example, the number of the first conductive bumps 31 and the number of the first capacitors 51 are both two, and the two first capacitors 51 are connected in parallel between the grounding line and the power supply line. In this way, different capacitance requirements can be achieved by designing the capacitance values ​​of the two first capacitors 51 according to the parallel relationship of the two first capacitors 51.

[0084] The above exemplarily describes a transistor electrically connected between a power line and a ground line. Of course, other circuits may also be electrically connected between the power line and the ground line, and the embodiments of the present application are not limited to this.

[0085] In some embodiments, Figure 4aAs shown, the first capacitor 51 includes a first electrode 511, a first dielectric layer 512, and a second electrode 513. The first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence along the direction from the bare chip 10 to the package substrate 20. Considering that both the second electrode 513 and the first conductive bump 31 include conductive materials, the first conductive bump 31 can be reused as the second electrode 513.

[0086] The above description describes the case where the first capacitor 51 is disposed between the bare chip 10 and the first conductive bump 31. In other embodiments, as shown in FIG. Figure 5a and Figure 5b As shown, the chip packaging structure may further include a second capacitor 52. The second capacitor 52 is disposed between the first conductive bump 31 and the packaging substrate 20. It can also be said that the second capacitor 52 is a part of the first conductive bump 31, and in the first conductive bump 31, the second capacitor 51 is closer to the packaging substrate 20. The first trace 11 is electrically connected to the second trace 21 through the first capacitor 51, the first conductive bump 31, and the second capacitor 52.

[0087] Compared with the on-chip decoupling capacitor, the second capacitor 52 of the present application does not need to occupy resources on the bare chip, saving costs. Compared with the built-in decoupling capacitor of the package, the second capacitor 52 of the present application does not affect the routing of the package substrate 20, saving costs, and the second capacitor 52 can be set at a high density; and the distance between the second capacitor 52 of the present application and the active area in the bare chip 10 is closer than the distance between the built-in decoupling capacitor of the package and the active area in the bare chip 10, so the second capacitor 52 of the present application is more conducive to filtering high-frequency noise. The distance between the second capacitor 52 of the present application and the active area in the bare chip 10 is closer than the distance between the board-level decoupling capacitor and the active area in the bare chip 10, so the second capacitor 52 of the present application is more conducive to filtering high-frequency noise.

[0088] On this basis, different capacitance requirements can be achieved by designing the capacitance value of the first capacitor 51 and the capacitance value of the second capacitor 52 according to the series relationship between the first capacitor 51 and the second capacitor 52 .

[0089] For example, a transistor is electrically connected between a power line and a ground line. Figure 5aAs shown, if the first routing line 11 and the third routing line 22 are ground routing lines, and the second routing line 21 is a power routing line, the drain 63 of the transistor is electrically connected to different conductive bumps through the same ground routing line in the bare chip 10. Specifically, the ground routing line in the bare chip 10 is electrically connected to the ground routing line in the package substrate 20 through the conductive lead 70 and the second conductive bump 32, and the ground routing line in the bare chip 10 is also electrically connected to the power routing line in the package substrate 20 through the conductive lead 70, the first capacitor 51, the first conductive bump 31, and the second capacitor 51. In this way, the first capacitor 51 is electrically connected between the power routing line and the ground routing line, and the drain 63 of the transistor is electrically connected to the ground routing line.

[0090] Still taking a transistor electrically connected between a power supply line and a ground line as an example, Figure 5b As shown, if the first line 11 and the third line 22 are power lines, and the second line 21 is a ground line, the source 62 of the transistor is electrically connected to different conductive bumps through the same power line in the bare chip 10. Specifically, the power line in the bare chip 10 is electrically connected to the power line in the package substrate 20 through the conductive lead 70 and the second conductive bump 32, and the power line in the bare chip 10 is also electrically connected to the ground line in the package substrate 20 through the conductive lead 70, the first capacitor 51, the first conductive bump 31, and the second capacitor 52. In this way, the first capacitor 51 is electrically connected between the power line and the ground line, and the source 62 of the transistor is electrically connected to the power line.

[0091] In some possible implementations, the embodiments of the present application do not limit the specific structures of the first capacitor 51 and the second capacitor 52, as long as the first capacitor 51 includes a first electrode 511, a first dielectric layer 512, and a second electrode 513 stacked in sequence, and the second capacitor 52 includes a third electrode, a second dielectric layer, and a fourth electrode stacked in sequence.

[0092] Optional, such as Figure 5a and Figure 5b As shown, the first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence along the direction from the bare chip 10 to the packaging substrate 20, the first electrode 511 and the first dielectric layer 512 are in a concave shape, and the second electrode 513 is located in the concave groove; the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are stacked in sequence along the direction from the packaging substrate 20 to the bare chip 10, the third electrode 521 and the second dielectric layer 522 are in a concave shape, and the fourth electrode 523 is located in the concave groove.

[0093] Optional, such as Figure 6aAs shown, the first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence along the direction from the bare chip 10 to the packaging substrate 20, and the first electrode 511, the first dielectric layer 512, and the second electrode 513 are all in the shape of a plate; the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are stacked in sequence along the direction from the packaging substrate 20 to the bare chip 10, and the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are all in the shape of a plate.

[0094] Optional, such as Figure 6b As shown, the first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence along the direction from the bare chip 10 to the packaging substrate 20, the first electrode 511 and the first dielectric layer 512 each include a plurality of grooves, and the second electrode 513 is located in the plurality of grooves; the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are stacked in sequence along the direction from the packaging substrate 20 to the bare chip 10, the third electrode 521 and the second dielectric layer 522 each include a plurality of grooves, and the fourth electrode 523 is located in the plurality of grooves.

[0095] like Figure 6c and Figure 6d As shown, along the direction from the second conductive bump 32 to the first conductive bump 31, the first electrode 511, the first dielectric layer 512, and the second electrode 513 are stacked in sequence and are in a ring shape; along the direction from the second conductive bump 32 to the first conductive bump 31, the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 are stacked in sequence and are in a ring shape. Among them, in the first capacitor 51, the number of the first electrode 511, the first dielectric layer 512, and the second electrode 513 can be one or more; in the second capacitor 52, the number of the third electrode 521, the second dielectric layer 522, and the fourth electrode 523 can be one or more. In the case where the number of the first electrode 511 is multiple, the multiple first electrodes 511 are electrically connected. In the case where the number of the second electrode 513 is multiple, the multiple second electrodes 513 are electrically connected. In the case where the number of the third electrode 521 is multiple, the multiple third electrodes 521 are electrically connected. In the case where the number of the fourth electrode 523 is multiple, the multiple fourth electrodes 523 are electrically connected.

[0096] In some embodiments, if the material of the multiple conductive bumps can react with the material of the second connection pad of the redistribution layer 20 and the first connection pad of the bare chip 10 to form an intermetallic compound, it will cause the second connection pad of the redistribution layer 20 and the first connection pad of the bare chip 10 to undergo a phase change, resulting in shrinkage and collapse and other problems, thereby greatly reducing the welding reliability of the multiple conductive bumps.

[0097] For example, the material of the first connection pad and the second connection pad is copper (Cu), and the material of the plurality of conductive bumps includes tin (Sn). Copper and tin react to generate a copper-tin intermetallic compound.

[0098] like Figure 7 As shown, the chip packaging structure also includes a first seed layer 81 disposed between the bare chip 10 and the plurality of conductive protrusions, and a second seed layer 82 disposed between the packaging substrate 20 and the plurality of conductive protrusions. The first capacitor 51 is disposed between the first conductive bump 31 and the first seed layer 81, and the second capacitor 52 is disposed between the first conductive bump 31 and the second seed layer 82. In this way, the first seed layer 81 and the second seed layer 82 can also be used to prevent the materials of the plurality of conductive bumps from reacting with the first connection pad of the bare chip 10 and the second connection pad of the packaging substrate 20.

[0099] Furthermore, in order to ensure that the second connection pad of the package substrate 20 is electrically connected to the first connection pad of the bare chip 10, the materials of the first seed layer 81 and the second seed layer 82 both include conductive materials, so that the second connection pad of the package substrate 20 is electrically connected to the first connection pad of the bare chip 10 through the first seed layer 81, the plurality of conductive bumps, and the second seed layer 82. Optionally, the first seed layer 81 and the second seed layer 82 can be a stack of titanium (Ti) and Cu.

[0100] In some embodiments, Figure 8 As shown, the plurality of conductive bumps may include a stack of titanium (Ti) / titanium nitride (TiN) and copper (Cu), and the Cu layer is located on the side of the Ti / TiN layer away from the bare chip 10. On this basis, the chip packaging structure may further include a tin (Sn) layer (or SnAg layer) 92, and the Sn layer 92 is disposed on the side of the Cu layer away from the bare chip 10.

[0101] In order to prevent the diffusion of Cu in the Cu layer and to better bond the Sn layer 92 , the chip packaging structure may further include a nickel (Ni) layer 91 , and the Ni layer 91 is located between the Cu layer and the Sn layer 92 .

[0102] In another embodiment, the present application provides a chip-to-package method, such as Fig. 9 As shown, this can be achieved through the following steps:

[0103] S110, forming a first capacitor 51 and a plurality of first bumps in sequence on the bare chip 10 to obtain a first substrate; the bare chip 10 includes a first trace 11, and the plurality of first bumps include a first sub-bump and a second sub-bump; the first capacitor 51 is located between the bare chip 10 and the first sub-bump.

[0104] Specifically, Fig.10aAs shown, before forming the first capacitor 51, a first seed layer 81 may be formed on the bare chip 10, and a first photoresist 101 may be formed on the first seed layer 81. Fig.10b As shown, the first photoresist 101 is exposed and developed to obtain a first photoresist pattern 102, wherein the first photoresist pattern 102 exposes the region where the first sub-bump to be formed is located, and the first photoresist pattern 102 covers the region where the second sub-bump to be formed is located.

[0105] Next, under the protection of the first photoresist pattern 102, the first capacitor 51 is formed on the first seed layer 81. Figure 10c-10f As shown, a first electrode 511, a first dielectric layer 512, and a second electrode 513 are sequentially formed on the first seed layer 81. Fig.10e As shown, a portion of the second electrode 5131 may be deposited by atomic layer deposition (ALD), and then, as shown in FIG. Fig.10f As shown, chemical vapor deposition (CVD) is used to deposit another portion of the second electrode 5132. The second electrode 5131 and the second electrode 5132 together form the second electrode 513.

[0106] In some possible implementations, the second electrode 513 is reused as the first sub-bump 301 , and forming the second electrode 513 is equivalent to forming the first sub-bump 301 .

[0107] Among some possible implementations, Fig.10e and Fig.10f As shown in FIG. 1 , in the case where the second electrode 513 is reused as the first sub-bump 301, after forming the first dielectric layer 512 and before forming the second electrode 513, the first photoresist pattern 102 can be further exposed, and the first photoresist pattern 102 after development also exposes the area where the second sub-bump to be formed is located. In this way, the second sub-bump 302 can also be deposited while depositing the second electrode 5131 and the second electrode 5132. Next, as shown in FIG. Figure 10g and Fig.10h As shown, a Ni layer 91 and a Sn layer (or SnAg layer) 92 may be formed sequentially on the plurality of first bumps.

[0108] S120, forming a plurality of second bumps on the packaging substrate 20 to obtain a second substrate; the packaging substrate 20 includes a second wiring 21 and a third wiring 22, and the plurality of second bumps include a third sub-bump and a fourth sub-bump.

[0109] Specifically, Fig.11aAs shown, a second seed layer 82 may be formed on the bare chip 10, and a second photoresist 103 may be formed on the second seed layer 82. Fig.11b As shown, the second photoresist 103 is exposed and developed to obtain a second photoresist pattern 104, where the second photoresist pattern 104 exposes an area where a second bump is to be formed.

[0110] In some possible implementations, the packaging substrate 20 may be, for example, a silicon-based substrate or an interposer.

[0111] Then, if Fig.11c As shown, a plurality of second bumps are formed under the protection of the first photoresist pattern 102. The plurality of second bumps include a third sub-bump 303 and a fourth sub-bump 304.

[0112] S130, reference Figure 3a As shown, the first substrate and the second substrate are matched; the first sub-bump 301 and the third sub-bump 303 are arranged opposite to each other, and the second sub-bump 302 and the fourth sub-bump 304 are arranged opposite to each other; the first routing line 11 is electrically connected to the second routing line 21 through the first capacitor 51, the first sub-bump 301, and the third sub-bump 303; the first routing line 11 is also electrically connected to the third routing line 22 through the second sub-bump 302 and the fourth sub-bump 304. Among them, the first routing line 11 and the third routing line 22 are ground routing lines, and the second routing line 21 is a power routing line; or, the first routing line 11 and the third routing line 22 are power routing lines, and the second routing line 21 is a ground routing line.

[0113] The third sub-bump 303 is aligned with the first sub-bump 301 to form a first conductive bump 31 ; the fourth sub-bump 304 is aligned with the second sub-bump 302 to form a second conductive bump 32 .

[0114] The above describes the case where the chip packaging structure includes the first capacitor 51. In some embodiments, the chip packaging structure also includes a second capacitor 52. Specifically, Fig.12a As shown, after forming the second seed layer 82 and before step S120, the second photoresist 103 is exposed and developed to obtain a second photoresist pattern 104, which exposes the area where the third sub-bump to be formed is located. In addition, the second photoresist pattern 104 covers the area where the fourth sub-bump to be formed is located.

[0115] Next, under the protection of the second photoresist pattern 104, the first capacitor 51 is formed on the second seed layer 82. Figure 12a-Figure 10e As shown, a third electrode 521, a second dielectric layer 522, and a fourth electrode 523 are sequentially formed on the second seed layer 82. Fig.12dAs shown, a portion of the fourth electrode 5231 may be deposited by ALD first, and then, as shown in FIG. Fig.12e As shown, another portion of the fourth electrode 5232 is deposited by CVD. The fourth electrode 5231 and the fourth electrode 5232 together constitute the fourth electrode 523.

[0116] In some possible implementations, the fourth electrode 523 is reused as the third sub-bump 303 , and forming the fourth electrode 523 is equivalent to forming the third sub-bump 303 .

[0117] Among some possible implementations, Fig.12d and Fig.12e As shown, in the case where the fourth electrode 523 is reused as the third sub-bump 303, after forming the second dielectric layer 522 and before forming the fourth electrode 523, the second photoresist pattern 104 can be further exposed, and the developed second photoresist pattern 104 also exposes the area where the fourth sub-bump to be formed is located. In this way, the fourth sub-bump 304 can be deposited while the fourth electrode 5231 and the fourth electrode 5232 are deposited.

[0118] In addition, other explanations and beneficial effects of the embodiments of the present application are the same as those of the previous embodiments and will not be repeated here.

[0119] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A chip packaging structure, It is characterized in that It includes a bare chip, an electronic device, a plurality of conductive bumps, and a first capacitor; The bare chip includes a first routing line, and the electronic device includes a second routing line and a third routing line; The plurality of conductive bumps are disposed between the bare chip and the electronic device, and the plurality of conductive bumps include a first conductive bump and a second conductive bump; The first capacitor is disposed between the bare chip and the first conductive bump; the first routing line is electrically connected to the second routing line through the first capacitor and the first conductive bump; the first routing line is also electrically connected to the third routing line through the second conductive bump; The first routing line and the third routing line are ground routing lines, and the second routing line is a power routing line; or the first routing line and the third routing line are power routing lines, and the second routing line is a ground routing line.

2. The chip packaging structure according to claim 1, It is characterized in that The bare chip further includes a fourth trace, and the plurality of conductive bumps further includes a third conductive bump; The fourth wiring is electrically connected to the second wiring through the third conductive bump; Wherein, the second routing line and the fourth routing line are both ground routing lines; or, the second routing line and the fourth routing line are both power routing lines.

3. The chip packaging structure according to claim 1 or 2, It is characterized in that There are multiple first capacitors and multiple first conductive bumps, and multiple first capacitors are connected in parallel between the first wiring and the second wiring.

4. The chip packaging structure according to any one of claims 1 to 3, It is characterized in that The chip packaging structure also includes a second capacitor; The second capacitor is disposed between the first conductive bump and the electronic device, and the first wiring is electrically connected to the second wiring through the first capacitor, the first conductive bump, and the second capacitor.

5. The chip packaging structure according to any one of claims 1 to 4, It is characterized in that The chip packaging structure further includes a first seed layer disposed between the bare chip and the plurality of conductive bumps, and a second seed layer disposed between the electronic device and the plurality of conductive bumps; The first capacitor is disposed between the first conductive bump and the first seed layer.

6. The chip packaging structure according to claim 4 or 5, It is characterized in that Along the direction from the bare chip to the electronic device, the first capacitor includes a first electrode, a first dielectric layer, and a second electrode, and the first conductive bump is reused as the second electrode; Along the direction from the electronic device to the bare chip, the second capacitor includes a third electrode, a second dielectric layer, and a fourth electrode, and the first conductive bump is also reused as the fourth electrode.

7. The chip packaging structure according to any one of claims 1 to 6, It is characterized in that The electronic device is a packaging substrate.

8. A chip flip packaging method, It is characterized in that include: A first capacitor and a plurality of first bumps are sequentially formed on a bare chip to obtain a first substrate; the bare chip comprises a first trace, and the plurality of first bumps comprises a first sub-bump and a second sub-bump; the first capacitor is located between the bare chip and the first sub-bump; A plurality of second bumps are formed on the electronic device to obtain a second substrate; the electronic device includes a second routing line and a third routing line, and the plurality of second bumps include a third sub-bump and a fourth sub-bump; The first substrate and the second substrate are aligned; the first sub-bump and the third sub-bump are arranged one by one opposite to each other, and the second sub-bump and the fourth sub-bump are arranged one by one opposite to each other; the first routing is electrically connected to the second routing through the first capacitor, the first sub-bump, and the third sub-bump; the first routing is also electrically connected to the third routing through the second sub-bump and the fourth sub-bump; wherein the first routing and the third routing are ground routing, and the second routing is a power routing; or, the first routing and the third routing are power routing, and the second routing is a ground routing.

9. The chip flip packaging method according to claim 8, It is characterized in that Before forming a plurality of second bumps on the electronic device, the chip flip packaging method further comprises: A second capacitor is formed on the electronic device; the second capacitor is located between the third sub-bump and the electronic device, and the first wiring is electrically connected to the second wiring through the first capacitor, the first sub-bump, the third sub-bump, and the second capacitor.

10. An electronic device, It is characterized in that It comprises a circuit board, solder balls, and the chip packaging structure according to any one of claims 1 to 7, wherein the electronic device of the chip packaging structure is soldered on the circuit board through the solder balls.

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