Chip packaging structure and electronic equipment

Abstract

The invention provides a chip packaging structure and electronic equipment, and belongs to the field of power electronics. The chip packaging structure comprises a packaging chip and a packaging frame, the packaging frame is provided with a first surface and a second surface which are opposite, the packaging chip is bound on the first surface, a plurality of grooves are formed in the packaging frame, and the grooves penetrate from the first surface to the second surface; in the cross section of the packaging frame passing through the plurality of grooves, the adjacent grooves divide the packaging frame into a plurality of frame blocks, and the second surfaces of the frame blocks are located in the orthographic projections of the frame blocks on the second surfaces. And the area of the first surface of the frame block is greater than or equal to that of the second surface of the frame block. According to the embodiment of the invention, the connection reliability of the packaging chip and the packaging frame can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of power electronics, and in particular to a chip packaging structure and an electronic device. Background Art

[0002] High Electron Mobility Transistor (HEMT) is a heterojunction field effect transistor that is widely used in various electronic appliances.

[0003] In the related art, transistors are usually packaged on a packaging frame, and the source, drain and gate of the transistor are bonded to the solder joints on the packaging frame. Then, a packaging layer is formed on the surface of the packaging frame, so that the packaging layer wraps the transistor, thereby forming a packaging structure of the transistor.

[0004] In order to improve the connection reliability between the packaging layer and the packaging frame, a groove is set on the surface of the packaging frame to allow the packaging layer to extend into the groove to increase the contact area between the packaging layer and the packaging frame. However, the density requirements of transistors are getting higher and higher, making the area available for opening holes in the packaging frame smaller and smaller, which leads to a smaller size of the groove, reducing the contact area between the packaging layer and the packaging frame, and thus affecting the connection reliability between the transistor and the packaging frame. Summary of the invention

[0005] The embodiments of the present disclosure provide a chip packaging structure and an electronic device, which can increase the contact area between the packaging layer and the packaging frame to improve the connection reliability between the packaged chip and the packaging frame. The technical solution is as follows:

[0006] On the one hand, an embodiment of the present disclosure provides a chip packaging structure, which includes: a packaging chip and a packaging frame, the packaging frame having a first surface and a second surface in opposite directions, the packaging chip is bound to the first surface, and a plurality of grooves are provided on the packaging frame, the grooves extending from the first surface to the second surface; in a cross-section of the packaging frame passing through the plurality of grooves, adjacent grooves separate the packaging frame into a plurality of frame blocks, the second surface of the frame block is located within the orthographic projection of the frame block on the second surface, and the area of ​​the first surface of the frame block is greater than or equal to the area of ​​the second surface of the frame block.

[0007] In one implementation of the present disclosure, in the direction from the first surface to the second surface, the packaging frame includes a first conductive layer, a second conductive layer and a third conductive layer connected in sequence; the surface of the first conductive layer has a first groove penetrating the first conductive layer, the surface of the second conductive layer has a second groove penetrating the second conductive layer, and the surface of the third conductive layer has a third groove penetrating the third conductive layer, the first groove corresponds to the second groove one-to-one, the second groove corresponds to the third groove one-to-one, the first groove is connected to the corresponding second groove, the second groove is connected to the corresponding third groove, and the width of the first groove and the width of the third groove are both different from the width of the second groove; the chip packaging structure also includes a packaging layer, which is located on the first surface, in the first groove, in the second groove and in the third groove, and covers the packaged chip.

[0008] In one implementation of the present disclosure, the width of the first groove is smaller than the width of the corresponding second groove, and the width of the second groove is smaller than the width of the corresponding third groove; the orthographic projection of the first groove on the second surface is located within the orthographic projection of the corresponding second groove on the second surface, and the orthographic projection of the second groove on the second surface is located within the orthographic projection of the corresponding third groove on the second surface.

[0009] In another implementation of the present disclosure, the width of the first groove is less than or equal to the width of the corresponding second groove, and the width of the second groove is less than the width of the corresponding third groove; the orthographic projection of the first groove on the second surface intersects with the orthographic projection of the corresponding second groove on the second surface, and the orthographic projection of the second groove on the second surface is located within the orthographic projection of the corresponding third groove on the second surface.

[0010] In another implementation of the present disclosure, a ratio of the width of the first groove to the width of the second groove is 0.5 to 1; a ratio of the width of the second groove to the width of the third groove is greater than or equal to 0.5 and less than 1.

[0011] In another implementation of the present disclosure, the width of the first groove is 145 μm to 150 μm; the width of the second groove is 150 μm to 300 μm; and the width of the third groove is 150 μm to 600 μm.

[0012] In another implementation of the present disclosure, the thickness of the first conductive layer is 60 μm to 80 μm; the thickness of the second conductive layer is 60 μm to 80 μm; and the thickness of the third conductive layer is 50 μm to 70 μm.

[0013] In another implementation of the present disclosure, the first conductive layer includes a Cu layer, the second conductive layer includes a Cu layer, and the third conductive layer includes a Cu layer.

[0014] In another implementation of the present disclosure, the first surface has a plurality of solder joints, the solder joints are arranged at intervals with the first grooves, the plurality of solder joints correspond one-to-one with the electrodes of the packaged chip, and the electrodes of the packaged chip are connected to the corresponding solder joints.

[0015] On the other hand, an embodiment of the present disclosure provides an electronic device, comprising: a circuit board and a chip packaging structure as described in the preceding item, wherein the packaging frame is located on a surface of the circuit board.

[0016] The beneficial effects brought by the technical solution provided by the embodiments of the present disclosure include at least:

[0017] In the chip packaging structure provided by the embodiment of the present disclosure, the packaged chip is bound to the first surface of the packaging frame. The packaging frame is provided with a plurality of grooves extending from the first surface to the second surface. In the cross section of the packaging frame passing through the plurality of grooves, the adjacent grooves separate the packaging frame into a plurality of frame blocks. The second surface of the frame block is located within the orthographic projection of the frame block on the second surface, indicating that the size of the second surface of the frame block is smaller than the maximum size of the frame block, that is, the side wall of the frame block is not a plane, which can increase the contact area between the side wall of the frame block and the packaging layer, so as to improve the connection reliability between the packaged chip and the packaging frame.

[0018] At the same time, the area of ​​the first surface of the frame block is greater than or equal to the area of ​​the second surface of the frame block, that is, the size of the groove is gradually narrowed in the direction from the second surface to the first surface, so that when the packaging layer extends into the groove, the size of the packaging layer closest to the second surface is larger than the size of the packaging layer farthest from the second surface, so that the packaging layer forms a film layer structure with a larger bottom and a smaller top, so that the packaging layer is not easy to fall off from the groove, so as to improve the connection reliability between the packaged chip and the packaging frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 It is a schematic diagram of a chip packaging structure provided by the related technology;

[0021] Figure 2It is a schematic diagram of a chip packaging structure provided by an embodiment of the present disclosure.

[0022] The descriptions of the marks in the figure are as follows:

[0023] 10. Package chip; 11. Electrode;

[0024] 20. packaging frame; 201. first surface; 202. second surface; 203. solder joint; 204. frame block;

[0025] 21, first conductive layer; 210, first groove; 22, second conductive layer; 220, second groove; 23, third conductive layer; 230, third groove;

[0026] 30. Encapsulation layer;

[0027] 40. Groove. DETAILED DESCRIPTION

[0028] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0029] Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second", "third" and similar words used in the patent application specification and claims of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one" or "one" do not indicate a quantity limitation, but indicate the existence of at least one. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before "include" or "comprise" include the elements or objects listed after "include" or "comprise" and their equivalents, and do not exclude other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right", "top", "bottom" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0030] Figure 1 It is a schematic diagram of a chip packaging structure provided by the related technology. Figure 1 As shown, the chip packaging structure includes: a packaging chip 10, a packaging frame 20 and a packaging layer 30, the electrode 11 of the packaging chip 10 is bound to the welding point 203 of the packaging frame 20, and the packaging layer 30 is located on the packaging frame 20 and wraps the packaging chip 10.

[0031] Optionally, the packaged chip 10 may be a light emitting diode and / or a transistor.

[0032] Exemplarily, when the packaged chip 10 is a light emitting diode, the electrode 11 of the packaged chip 10 may be a p-electrode or an n-electrode.

[0033] Exemplarily, when the packaged chip 10 is a transistor, the electrode 11 of the packaged chip 10 may be a source, a drain or a gate.

[0034] like Figure 1 As shown, a groove 40 is also provided on the surface of the packaging frame 20, and the packaging layer 30 also extends into the groove 40 to increase the contact area between the packaging layer 30 and the packaging frame 20, so as to make the connection between the packaging layer 30 and the packaging frame 20 more secure. As the distribution density of the packaged chips is required to be higher and higher, the area of ​​the packaging frame 20 available for etching to form the groove 40 is also getting smaller and smaller, which leads to a smaller size of the groove 40, reducing the contact area between the packaging layer 30 and the packaging frame 20, thereby affecting the connection reliability between the transistor and the packaging frame 20.

[0035] like Figure 1 As shown in the dotted box, in the groove 40 formed by etching the packaging frame 20, part of the groove wall is a straight plane. It is difficult for the packaging layer 30 to adhere to the plane and the adhesion is poor, which can easily cause the packaging layer 30 to fall off from the groove 40.

[0036] To this end, an embodiment of the present disclosure provides a chip packaging structure. Figure 2 Schematic diagram of a chip packaging structure provided by an embodiment of the present disclosure. Figure 2 As shown, the chip packaging structure includes: a packaging chip 10 and a packaging frame 20 .

[0037] like Figure 2 As shown, the packaging frame 20 has a first surface 201 and a second surface 202 opposite to each other. The packaged chip 10 is bound to the first surface 201 . A plurality of grooves are formed on the packaging frame 20 , and the grooves extend from the first surface 201 to the second surface 202 .

[0038] like Figure 2 As shown, in a cross section of the packaging frame 20 passing through a plurality of grooves, adjacent grooves separate the packaging frame 20 into a plurality of frame blocks 204, a second surface 202 of the frame block 204 is located within the orthographic projection of the frame block 204 on the second surface 202, and an area of ​​the first surface 201 of the frame block 204 is greater than or equal to an area of ​​the second surface 202 of the frame block 204.

[0039] In the chip packaging structure provided by the embodiment of the present disclosure, the packaged chip is bound to the first surface of the packaging frame. The packaging frame is provided with a plurality of grooves extending from the first surface to the second surface. In the cross section of the packaging frame passing through the plurality of grooves, the adjacent grooves separate the packaging frame into a plurality of frame blocks. The second surface of the frame block is located within the orthographic projection of the frame block on the second surface, indicating that the size of the second surface of the frame block is smaller than the maximum size of the frame block, that is, the side wall of the frame block is not a plane, which can increase the contact area between the side wall of the frame block and the packaging layer, so as to improve the connection reliability between the packaged chip and the packaging frame.

[0040] At the same time, the area of ​​the first surface of the frame block is greater than or equal to the area of ​​the second surface of the frame block, that is, the size of the groove is gradually narrowed in the direction from the second surface to the first surface, so that when the packaging layer extends into the groove, the size of the packaging layer closest to the second surface is larger than the size of the packaging layer farthest from the second surface, so that the packaging layer forms a film layer structure with a larger bottom and a smaller top, so that the packaging layer is not easy to fall off from the groove, so as to improve the connection reliability between the packaged chip and the packaging frame.

[0041] Alternatively, if Figure 2 As shown, in the direction from the first surface 201 to the second surface 202 , the package frame 20 includes a first conductive layer 21 , a second conductive layer 22 and a third conductive layer 23 which are connected in sequence.

[0042] like Figure 2 As shown, the surface of the first conductive layer 21 has a first groove 210 that penetrates the first conductive layer 21, the surface of the second conductive layer 22 has a second groove 220 that penetrates the second conductive layer 22, and the surface of the third conductive layer 23 has a third groove 230 that penetrates the third conductive layer 23. The first groove 210 corresponds to the second groove 220 one by one, and the second groove 220 corresponds to the third groove 230 one by one. The first groove 210 is connected to the corresponding second groove 220, and the second groove 220 is connected to the corresponding third groove 230. The width of the first groove 210 and the width of the third groove 230 are different from the width of the second groove 220.

[0043] like Figure 2 As shown, the chip packaging structure further includes a packaging layer 30 , which is located on the first surface 201 , in the first groove 210 , in the second groove 220 and in the third groove 230 , and covers the packaged chip 10 .

[0044] In the chip packaging structure provided by the embodiment of the present disclosure, the packaged chip 10 is bound to the first surface 201 of the packaging frame 20. The packaging frame 20 includes a stacked first conductive layer 21, a second conductive layer 22, and a third conductive layer 23. The surface of the first conductive layer 21 has a first groove 210, the surface of the second conductive layer 22 has a second groove 220, and the surface of the third conductive layer 23 has a third groove 230. The first groove 210 is connected to the corresponding second groove 220, and the second groove 220 is connected to the corresponding third groove 230, that is, the first groove 210, the second groove 220, and the third groove 230 can form a groove that passes through the packaging frame 20.

[0045] Furthermore, the width of the first groove 210 and the width of the third groove 230 are both different from the width of the second groove 220, that is, the groove wall formed by the combination of the first groove 210 and the second groove 220 is not a smooth plane, and there is a step at the connection between the first groove 210 and the second groove 220. Therefore, when the encapsulation layer 30 extends into the first groove 210 and the second groove 220, in addition to contacting the groove wall of the first groove 210 and the groove wall of the second groove 220, it will also contact the step at the connection between the first groove 210 and the second groove 220, thereby increasing the contact area between the encapsulation layer 30 and the groove; at the same time, the groove wall formed by the combination of the second groove 220 and the third groove 230 is not a smooth plane, and there is a step at the connection between the second groove 220 and the third groove 230. Therefore, when the encapsulation layer 30 extends into the second groove 220 and the third groove 230, in addition to contacting the groove wall of the second groove 220 and the groove wall of the third groove 230, it also contacts the step at the connection between the second groove 220 and the third groove 230, thereby further increasing the contact area between the encapsulation layer 30 and the groove. Therefore, the contact area between the encapsulation layer 30 and the encapsulation frame 20 can be effectively increased to improve the connection reliability between the encapsulation chip 10 and the encapsulation frame 20.

[0046] Alternatively, if Figure 2 As shown in the dotted frame A, in the cross section of the chip packaging structure perpendicular to the first surface 201 , the width of the first groove 210 is smaller than the width of the corresponding second groove 220 , and the width of the second groove 220 is smaller than the width of the corresponding third groove 230 .

[0047] The orthographic projection of the first groove 210 on the second surface 202 is located within the orthographic projection of the corresponding second groove 220 on the second surface 202 , and the orthographic projection of the second groove 220 on the second surface 202 is located within the orthographic projection of the corresponding third groove 230 on the second surface 202 .

[0048] In the above implementation, the width of the first groove 210 is smaller than the width of the second groove 220, and the orthographic projection of the first groove 210 on the second surface 202 falls within the orthographic projection of the second groove 220 on the second surface 202. In this way, a step can be formed between the groove wall of the first groove 210 and the groove wall of the second groove 220, that is, the first groove 210 and the second groove 220 are combined to form a stepped groove, which can effectively increase the contact area between the encapsulation layer 30 and the groove. The width of the second groove 220 is smaller than the width of the third groove 230, and the orthographic projection of the second groove 220 on the second surface 202 falls within the orthographic projection of the third groove 230 on the second surface 202. In this way, a step can be formed between the groove wall of the second groove 220 and the groove wall of the third groove 230, that is, the second groove 220 and the third groove 230 are combined to form a stepped groove, which can effectively increase the contact area between the encapsulation layer 30 and the groove.

[0049] The three-layer stepped groove formed by the combination of the first groove 210, the second groove 220 and the third groove 230 can prevent the packaging layer 30 from falling off from the groove by utilizing the two-layer step surfaces of the groove, thereby improving the connection reliability between the packaging layer 30 and the groove.

[0050] Alternatively, if Figure 2 As shown in the dotted box B, the width of the first groove 210 is less than or equal to the width of the corresponding second groove 220 , and the width of the second groove 220 is less than the width of the corresponding third groove 230 .

[0051] The orthographic projection of the first groove 210 on the second surface 202 intersects with the orthographic projection of the corresponding second groove 220 on the second surface 202 , and the orthographic projection of the second groove 220 on the second surface 202 is located within the orthographic projection of the corresponding third groove 230 on the second surface 202 .

[0052] In the above implementation, the width of the first groove 210 is less than or equal to the width of the second groove 220, and the orthographic projection of the first groove 210 on the second surface 202 intersects with the orthographic projection of the corresponding second groove 220 on the second surface 202. In this way, the first groove 210 and the second groove 220 overlap, rather than the orthographic projection of the first groove 210 falling into the orthographic projection of the second groove 220, so that the position of the first groove 210 on the first surface 201 can be flexibly adjusted to meet the arrangement requirements of the chip electrodes 11.

[0053] Furthermore, since the minimum width of the etched groove is limited by the thickness of the conductive layer, when the thickness of the conductive layer is too thick, it is difficult to make the width of the groove smaller. Therefore, the above implementation method allows the width of the first groove 210 to be the same as the width of the second groove 220. In this way, when the etching capacity of the etching equipment is limited and a groove smaller than the size of the second groove 220 cannot be etched, a step can still be formed between the groove wall of the first groove 210 and the groove wall of the second groove 220, that is, the first groove 210 and the second groove 220 are combined to form a stepped groove, which can effectively increase the contact area between the encapsulation layer 30 and the groove.

[0054] At the same time, the width of the second groove 220 is smaller than the width of the third groove 230, and the orthographic projection of the second groove 220 on the second surface 202 falls within the orthographic projection of the third groove 230 on the second surface 202. In this way, a step can be formed between the groove wall of the second groove 220 and the groove wall of the third groove 230, that is, the second groove 220 and the third groove 230 are combined to form a stepped groove, which can effectively increase the contact area between the encapsulation layer 30 and the groove.

[0055] In this way, the three-layer stepped groove formed by the combination of the first groove 210, the second groove 220 and the third groove 230 can prevent the packaging layer 30 from falling off from the groove by using the two step surfaces of the groove, thereby improving the connection reliability between the packaging layer 30 and the groove.

[0056] Optionally, a ratio of the width of the first groove 210 to the width of the second groove 220 is 0.5 to 1.

[0057] For example, when the orthographic projection of the first groove 210 on the second surface 202 intersects the orthographic projection of the corresponding second groove 220 on the second surface 202, the ratio of the width of the first groove 210 to the width of the second groove 220 may be equal to 1 or less than 1. For example, the ratio of the width of the first groove 210 to the width of the second groove 220 is 0.7.

[0058] Exemplarily, when the orthographic projection of the first groove 210 on the second surface 202 is within the orthographic projection of the corresponding second groove 220 on the second surface 202, the ratio of the width of the first groove 210 to the width of the second groove 220 is less than 1. For example, the ratio of the width of the first groove 210 to the width of the second groove 220 is 0.8.

[0059] Optionally, a ratio of a width of the second groove 220 to a width of the third groove 230 is greater than or equal to 0.5, and a ratio of a width of the third groove 230 to a width of the second groove 220 is less than 1.

[0060] By setting the width ratio of the second groove 220 to the third groove 230 within the above range, it is possible to avoid the width of the second groove 220 being too much smaller than that of the third groove 230, thereby increasing the difficulty of etching the second groove 220. It is also possible to avoid the second groove 220 and the third groove 230 overlapping and failing to form a step between the second groove 220 and the third groove 230, thereby affecting the connection reliability between the encapsulation layer 30 and the second groove 220 and the third groove 230.

[0061] Exemplarily, the ratio of the width of the second groove 220 to the width of the third groove 230 is 0.7.

[0062] Optionally, the width of the first groove 210 is 145 μm to 150 μm.

[0063] Controlling the width of the first groove 210 within the above range can prevent the width of the first groove 210 from being too small, thereby increasing the difficulty of etching the groove, which is beneficial to improving the preparation efficiency of the packaging frame.

[0064] Exemplarily, the width of the first groove 210 is 150 μm.

[0065] Optionally, the width of the second groove 220 is 150 μm to 300 μm.

[0066] By controlling the width of the second groove 220 within the above range, it is possible to ensure that the width of the second groove 220 is large enough, so that when etching the first groove 210, the width of the first groove 210 can be selected in a wide enough range to simplify the etching difficulty of the first groove 210. It is also possible to avoid the width of the second groove 220 being too large, which results in a larger width of the third groove 230, causing more areas of the packaging frame to be etched, affecting the stability of the packaging frame.

[0067] Exemplarily, the width of the second groove 220 is 200 μm.

[0068] Optionally, the width of the third groove 230 is 150 μm to 600 μm.

[0069] Controlling the width of the third groove 230 within the above range can prevent the width of the third groove 230 from being too large, which would cause more areas of the packaging frame to be etched, affecting the stability of the packaging frame; it can also prevent the width of the third groove 230 from being too small, which would reduce the optional range of the width of the first groove 210 and increase the difficulty of etching the first groove 210.

[0070] Exemplarily, the width of the third groove 230 is 300 μm.

[0071] Optionally, the thickness of the first conductive layer 21 is 60 μm to 80 μm.

[0072] Exemplarily, the thickness of the first conductive layer 21 is 70 μm.

[0073] Optionally, the thickness of the second conductive layer 22 is 60 μm to 80 μm.

[0074] Exemplarily, the thickness of the second conductive layer 22 is 70 μm.

[0075] Optionally, the thickness of the third conductive layer 23 is 50 μm to 70 μm.

[0076] Exemplarily, the thickness of the third conductive layer 23 is 60 μm.

[0077] In one implementation, the thicknesses of the first conductive layer 21 , the second conductive layer 22 , and the third conductive layer 23 may be the same.

[0078] In another implementation, the thickness of the first conductive layer 21 is smaller than the thickness of the second conductive layer 22 , and the thickness of the second conductive layer 22 is smaller than the thickness of the third conductive layer 23 .

[0079] Since the first groove 210 is located on the first conductive layer 21 and the width of the first groove 210 is usually small, the thickness of the first conductive layer 21 can be minimized to facilitate etching of the first groove 210 with a small width. The thickness of the second conductive layer 22 can also be smaller than the thickness of the third conductive layer 23, which is conducive to forming a second groove 220 with a smaller size on the second conductive layer 22.

[0080] In the above implementation, the preparation of the packaging wire frame may include: first forming a third conductive layer 23, and then etching the surface of the third conductive layer 23 to form a third groove 230; then, forming a second conductive layer 22 on the surface of the third conductive layer 23; then, etching the surface of the second conductive layer 22 to form a second groove 220 connected to the third groove 230; finally, forming a first conductive layer 21 on the surface of the second conductive layer 22, and etching the surface of the first conductive layer 21 to form a first groove 210 connected to the second groove 220.

[0081] Optionally, the first conductive layer 21 includes a Cu layer, the second conductive layer 22 includes a Cu layer, and the third conductive layer 23 includes a Cu layer.

[0082] Using metal Cu as the preparation material of the packaging frame can meet the electrical connection between the packaging frame and the electrode 11 of the chip, so that the current can be input to the chip through the packaging frame; and metal Cu has good strength, which can improve the stability of the packaging frame.

[0083] Alternatively, if Figure 2As shown, the first surface 201 has a plurality of solder joints 203 , which are arranged alternately with the first grooves 210 , and the plurality of solder joints 203 correspond one-to-one to the electrodes 11 of the packaged chip 10 , and the electrodes 11 of the packaged chip 10 are connected to the corresponding solder joints 203 .

[0084] For example, Figure 2 As shown, the packaged chip 10 may be a transistor. Figure 2 From left to right in the figure, the first electrode 11 of the transistor is the source, the second electrode 11 and the third electrode 11 of the transistor are both drains, the fourth electrode 11 of the transistor is the source, the fifth electrode 11 and the sixth electrode 11 of the transistor are both drains, and the seventh electrode 11 of the transistor is the gate.

[0085] For example, Figure 2 As shown, the first surface 201 of the packaging frame has seven solder joints 203 , and each solder joint 203 is respectively bonded to an electrode 11 of a transistor.

[0086] like Figure 2 As shown, the packaging layer 30 also extends to the gap between the electrode 11 and the solder joint 203. By wrapping the electrode 11 and the solder joint 203 with the packaging layer 30, the connection reliability between the electrode 11 and the solder joint 203 can be improved.

[0087] Optionally, the encapsulation layer 30 includes a resin layer. The resin layer can protect the chip, making the chip less susceptible to moisture or moisture absorption and less susceptible to stress damage, thereby improving reliability.

[0088] Optionally, the packaged chip 10 may be a light emitting diode and / or a transistor.

[0089] Exemplarily, the transistor includes: an epitaxial wafer, a source, a drain and a gate; the epitaxial wafer includes a channel layer and a barrier layer stacked in sequence, the source, the drain and the gate are all located on the barrier layer, the source and the drain penetrate the barrier layer and are connected to the channel layer, the gate is located between the source and the drain, and the gate is connected to the barrier layer.

[0090] Exemplarily, the channel layer is a GaN layer, and the barrier layer is an AlGaN layer. A high-concentration two-dimensional electron gas channel can be formed at the AlGaN / GaN heterojunction interface. The high-concentration and high-electron-mobility two-dimensional electron gas channel is the biggest advantage of GaN high-electron-mobility transistors over traditional field-effect transistors.

[0091] Exemplarily, the drain electrode, the drain electrode, and the gate electrode may each include at least one of a Ti layer, an Al layer, a Pt layer, a Ni layer, and an Au layer.

[0092] The above metal materials have good heat dissipation performance. Therefore, the drain, drain electrode and gate electrode prepared by the above materials also have good heat dissipation performance, which can improve the heat dissipation effect of the transistor.

[0093] Exemplarily, the light emitting diode includes an epitaxial layer and two electrodes 11. The epitaxial layer includes a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer stacked in sequence, and the surface of the second semiconductor layer has a groove exposing the first semiconductor layer.

[0094] Optionally, one electrode 11 is located in the groove and connected to the first semiconductor layer, and the other electrode 11 is located on the surface of the second semiconductor layer.

[0095] In the embodiment of the present disclosure, one of the first semiconductor layer and the second semiconductor layer is an n-type layer, and the other of the first semiconductor layer and the second semiconductor layer is a p-type layer.

[0096] Exemplarily, the first semiconductor layer is an n-type layer, and the second semiconductor layer is a p-type layer.

[0097] The following is an exemplary description of each layer structure by taking the blue light epitaxial structure as an example. In the blue light epitaxial structure, the p-type layer includes a p-type GaN layer.

[0098] The multi-quantum well layer may include alternately grown InGaN quantum well layers and GaN quantum barrier layers. The third light emitting layer may include 3 to 8 periods of alternately stacked InGaN quantum well layers and GaN quantum barrier layers.

[0099] The n-type layer includes an n-type GaN layer.

[0100] Optionally, the epitaxial layer has a thickness of 2 μm to 10 μm.

[0101] Exemplarily, the thickness of the epitaxial layer is 6 μm.

[0102] An embodiment of the present disclosure provides an electronic device, which includes a circuit board and the chip packaging structure as described above, and a packaging frame is located on a surface of the circuit board.

[0103] Exemplarily, the electronic device may be any electronic device including a packaging substrate, such as a server, a mobile phone, a computer, a television, a game console, an electronic watch, or the like.

[0104] The above description is only an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: a packaging chip (10) and a packaging frame (20), the packaging frame (20) having a first surface (201) and a second surface (202) opposite to each other, the packaging chip (10) being bound to the first surface (201), and a plurality of grooves being formed on the packaging frame (20), the grooves penetrating from the first surface (201) to the second surface (202); In a cross section of the packaging frame (20) passing through a plurality of the grooves, adjacent grooves separate the packaging frame (20) into a plurality of frame blocks (204), a second surface (202) of the frame block (204) is located within a positive projection of the frame block (204) on the second surface (202), and an area of ​​the first surface (201) of the frame block (204) is greater than or equal to an area of ​​the second surface (202) of the frame block (204).

2. The chip packaging structure according to claim 1, characterized in that: In a direction from the first surface (201) to the second surface (202), the packaging frame (20) comprises a first conductive layer (21), a second conductive layer (22) and a third conductive layer (23) which are connected in sequence; The surface of the first conductive layer (21) has a first groove (210) penetrating the first conductive layer (21), the surface of the second conductive layer (22) has a second groove (220) penetrating the second conductive layer (22), and the surface of the third conductive layer (23) has a third groove (230) penetrating the third conductive layer (23), the first groove (210) corresponds to the second groove (220) one-to-one, the second groove (220) corresponds to the third groove (230) one-to-one, the first groove (210) is connected to the corresponding second groove (220), the second groove (220) is connected to the corresponding third groove (230), and the width of the first groove (210) and the width of the third groove (230) are both different from the width of the second groove (220); The chip packaging structure further comprises a packaging layer (30), wherein the packaging layer (30) is located on the first surface (201), in the first groove (210), in the second groove (220) and in the third groove (230), and covers the packaged chip (10).

3. The chip packaging structure according to claim 2, characterized in that: The width of the first groove (210) is smaller than the width of the corresponding second groove (220), and the width of the second groove (220) is smaller than the width of the corresponding third groove (230); The orthographic projection of the first groove (210) on the second surface (202) is located within the orthographic projection of the corresponding second groove (220) on the second surface (202), and the orthographic projection of the second groove (220) on the second surface (202) is located within the orthographic projection of the corresponding third groove (230) on the second surface (202).

4. The chip packaging structure according to claim 2, characterized in that: The width of the first groove (210) is smaller than or equal to the width of the corresponding second groove (220), and the width of the second groove (220) is smaller than the width of the corresponding third groove (230); The orthographic projection of the first groove (210) on the second surface (202) intersects with the orthographic projection of the corresponding second groove (220) on the second surface (202), and the orthographic projection of the second groove (220) on the second surface (202) is located within the orthographic projection of the corresponding third groove (230) on the second surface (202).

5. The chip packaging structure according to any one of claims 2 to 4, characterized in that: The ratio of the width of the first groove (210) to the width of the second groove (220) is 0.5 to 1; The ratio of the width of the second groove (220) to the width of the third groove (230) is greater than or equal to 0.5 and less than 1.

6. The chip packaging structure according to claim 5, characterized in that: The width of the first groove (210) is 145 μm to 150 μm; The width of the second groove (220) is 150 μm to 300 μm; The width of the third groove (230) is 150 μm to 600 μm.

7. The chip packaging structure according to any one of claims 2 to 4, characterized in that: The thickness of the first conductive layer (21) is 60 μm to 80 μm; The thickness of the second conductive layer (22) is 60 μm to 80 μm; The thickness of the third conductive layer (23) is 50 μm to 70 μm.

8. The chip packaging structure according to any one of claims 2 to 4, characterized in that: The first conductive layer (21) includes a Cu layer, the second conductive layer (22) includes a Cu layer, and the third conductive layer (23) includes a Cu layer.

9. The chip packaging structure according to any one of claims 2 to 4, characterized in that: The first surface (201) has a plurality of solder joints (203), the solder joints (203) and the first grooves (210) are arranged at intervals, the plurality of solder joints (203) correspond one-to-one with the electrodes (11) of the packaged chip (10), and the electrodes (11) of the packaged chip (10) are connected to the corresponding solder joints (203).

10. An electronic device, characterized in that: The electronic device comprises: a circuit board and a chip packaging structure as claimed in any one of claims 1 to 9, wherein the packaging frame (20) is located on a surface of the circuit board.

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