A broadband low-noise differential amplifier

Abstract

The present application belongs to the field of integrated electronic communication technology and specifically discloses a broadband low-noise differential amplifier, wherein the differential amplifier includes a first-stage amplification circuit and a second-stage amplification circuit, wherein the first-stage amplification circuit is used to receive a positive-phase differential input signal and a negative-phase differential input signal and perform a first-stage amplification to obtain a positive-phase differential input signal and a negative-phase differential input signal after the first-stage amplification; and the second-stage amplification circuit is used to perform a second-stage amplification on the positive-phase differential input signal and the negative-phase differential input signal after the first-stage amplification to obtain a positive-phase differential input signal and a negative-phase differential input signal after the second-stage amplification. The present application can broaden the operating frequency range of traditional amplifiers and simultaneously achieve efficient, low-noise amplification within a wide frequency band of 0.1 GHz to 20 GHz.

Description

Technical Field

[0001] The present application belongs to the field of integrated electronic communication technology, and specifically relates to a broadband low-noise differential amplifier. Background Art

[0002] As modern wireless communication systems evolve toward portability, intelligence, multi-band, multi-mode, and multi-functionality, broadband low-noise amplifiers (LNAs) capable of covering multiple frequency bands have become a research focus. As a crucial component in RF receiver systems, the LNA is the first active amplification link in the signal chain, typically connected directly after the antenna. Because the signal received by the antenna is extremely weak, it must be initially amplified by the LNA for subsequent circuit processing. Furthermore, to prevent the useful signal from being overwhelmed by noise, the noise introduced by the LNA itself must be minimized.

[0003] However, the design of traditional low-noise amplifiers faces several challenges, including the following: Bandwidth limitation: The influence of transistor parasitic parameters causes the gain of the low-noise amplifier to drop significantly as the operating frequency increases, which makes wide-band design difficult. Gain fluctuation: The pole distribution and mismatch problems within the circuit can cause the gain to fluctuate with frequency. Excessive gain fluctuation may cause signal distortion and reduce gain flatness. Nonlinear effects: Under high-frequency operating conditions, transistors exhibit stronger nonlinear characteristics, which reduces the linearity of the low-noise amplifier. Stability issues: Ensuring that the amplifier remains stable throughout the entire operating frequency band is also a key consideration.

[0004] Current low-noise amplifier designs employ a variety of structures and technologies to overcome these challenges, including distributed, balanced, and negative feedback architectures. They also utilize filter-based broadband matching structures and peaking inductor technology to expand bandwidth. Differential circuits, in particular, offer inherent noise immunity advantages due to their ability to effectively suppress common-mode noise, such as power supply noise and electromagnetic interference, enhancing the signal's ability to resist interference.

[0005] Despite this, existing low-noise differential amplifiers still find it difficult to simultaneously resolve all bandwidth limiting factors, and it is difficult to achieve high-gain low-noise amplification while covering a wide frequency band. Summary of the Invention

[0006] In response to the deficiencies in the prior art, the purpose of this application is to provide a broadband low-noise differential amplifier, which can broaden the operating frequency range of traditional amplifiers and achieve efficient, low-noise amplification within a wide frequency band of 0.1 GHz to 20 GHz.

[0007] To achieve the above objectives, this application provides the following technical solutions:

[0008] A broadband low-noise differential amplifier comprises: a first-stage amplification circuit and a second-stage amplification circuit, wherein the first-stage amplification circuit is used to receive a positive-phase differential input signal and a negative-phase differential input signal and perform a first-stage amplification to obtain a positive-phase differential input signal and a negative-phase differential input signal after the first-stage amplification; and the second-stage amplification circuit is used to perform a second-stage amplification on the positive-phase differential input signal and the negative-phase differential input signal after the first-stage amplification to obtain a positive-phase differential input signal and a negative-phase differential input signal after the second-stage amplification.

[0009] Optionally, the first-stage amplifier circuit includes: a first input matching and negative feedback branch, a first bias branch, a first gain branch, a first source degeneration branch, a second input matching and negative feedback branch, a second bias branch, a second gain branch, and a second source degeneration branch; wherein the first input matching and negative feedback branch and the second input matching and negative feedback branch are respectively used to optimize the matching of the inverting differential input signal and the positive differential input signal and provide negative feedback; the first gain branch and the second gain branch are respectively used to perform signal gain on the inverting differential input signal and the positive differential input signal after optimized matching; the first bias branch and the second bias branch are respectively used to provide a stable DC operating point for the first gain branch and the second gain branch; the first source degeneration branch and the second source degeneration branch are respectively used to increase the source impedance for the first gain branch and the second gain branch; The secondary amplifier circuit is used to perform a second-stage amplification on the positive-phase differential input signal and the negative-phase differential input signal after the first-stage amplification to obtain the positive-phase differential input signal and the negative-phase differential input signal after the second-stage amplification; the second-stage amplifier circuit includes: a third input matching and negative feedback branch, a third bias branch, a third gain branch, a fourth input matching and negative feedback branch, a fourth bias branch and a fourth gain branch, wherein the third input matching and negative feedback branch and the fourth input matching and negative feedback branch are respectively used to optimize the matching of the positive-phase differential input signal and the negative-phase differential input signal after the first-stage amplification; the third gain branch and the fourth gain branch are respectively used to perform signal gain on the optimized matching of the positive-phase differential input signal and the negative-phase differential input signal after the first-stage amplification; the third bias branch and the fourth bias branch are respectively used to provide stable DC operating points for the third gain branch and the fourth gain branch.

[0010] Optionally, the first input matching and negative feedback branch includes: a first inductor, a second inductor, a third inductor, a first capacitor and a second resistor, wherein the first end of the first inductor is connected to the inverting end of the differential input signal, and the second end of the first inductor is connected to the first end of the second inductor to form a first node; the second end of the second inductor is connected to the first input end of the first gain branch; the first end of the third inductor is connected to the first node, and the second end of the third inductor is connected to the first end of the second resistor through the first capacitor; the second end of the second resistor is connected to the second input end of the first gain branch to form a second node; the first bias branch includes: a first resistor, wherein the first end of the first resistor is connected to the first node, and the second end of the first resistor is connected to a first DC voltage source.

[0011] Optionally, the first gain branch includes: a first transistor, a fourth inductor, a fifth inductor and a third resistor, wherein the gate of the first transistor is connected to the second end of the second inductor as the first input end of the first gain branch, the drain of the first transistor is connected to the second node, and the source of the first transistor is connected to the input end of the first source degeneration branch; the first end of the fourth inductor is connected to the second node, the second end of the fourth inductor is connected to the first end of the fifth inductor to form a third node; the second end of the fifth inductor is connected to the first power supply via the third resistor; the first source degeneration branch includes: an eighth inductor, wherein the first end of the eighth inductor is connected to the source of the first transistor as the input end of the first source degeneration branch, the second end of the eighth inductor is connected to the input end of the first current source as the output end of the first source degeneration branch to form a sixth node; the output end of the first current source is connected to the first ground end.

[0012] Optionally, the second input matching and negative feedback branch includes: a tenth inductor, an eleventh inductor, a twelfth inductor, a fifth resistor and a second capacitor, wherein the first end of the tenth inductor is connected to the first input end of the second gain branch, and the second end of the tenth inductor is connected to the first end of the twelfth inductor to form a seventh node; the second end of the twelfth inductor is connected to the positive phase end of the differential input signal; the first end of the eleventh inductor is connected to the seventh node, and the second end of the eleventh inductor is connected to the first end of the fifth resistor through the second capacitor; the second end of the fifth resistor is connected to the second input end of the second gain branch to form a fifth node; the second bias branch includes: a sixth resistor, wherein the first end of the sixth resistor is connected to the seventh node, and the second end of the sixth resistor is connected to the second DC voltage source.

[0013] Optionally, the second gain branch includes: a second transistor, a sixth inductor, a seventh inductor and a fourth resistor, wherein the gate of the second transistor is connected to the first end of the tenth inductor as the first input end of the second gain branch, the drain of the second transistor is connected to the fifth node, and the source of the second transistor is connected to the input end of the second source degeneration branch; the first end of the sixth inductor is connected to the fifth node, the second end of the sixth inductor is connected to the first end of the seventh inductor to form a fourth node; the second end of the seventh inductor is connected to the first power supply via the fourth resistor; the second source degeneration branch includes: a ninth inductor, wherein the first end of the ninth inductor is connected to the source of the second transistor as the input end of the second source degeneration branch, and the second end of the ninth inductor is connected to the sixth node as the output end of the second source degeneration branch.

[0014] Optionally, the third input matching and negative feedback branch includes: a thirteenth inductor, a fourteenth inductor, a fifteenth inductor, a third capacitor and an eighth resistor, wherein the first end of the thirteenth inductor is connected to the fourth node, and the second end of the thirteenth inductor is connected to the first end of the fourteenth inductor to form an eighth node; the second end of the fourteenth inductor is connected to the first input end of the third gain branch; the first end of the fifteenth inductor is connected to the eighth node, and the second end of the fifteenth inductor is connected to the first end of the eighth resistor through the third capacitor; the second end of the eighth resistor is connected to the second input end of the third gain branch to form a ninth node; the third bias branch includes: a seventh resistor, wherein the first end of the seventh resistor is connected to the eighth node, and the second end of the seventh resistor is connected to the third DC voltage source.

[0015] Optionally, the third gain branch includes: a third transistor, a sixteenth inductor, a seventeenth inductor and a ninth resistor, wherein the gate of the third transistor is connected to the second end of the fourteenth inductor as the first input end of the third gain branch, the drain of the third transistor is connected to the ninth node, the source of the third transistor is connected to the input end of the second current source to form a thirteenth node; the output end of the second current source is connected to the second ground end; the first end of the sixteenth inductor is connected to the ninth node, the second end of the sixteenth inductor is connected to the first end of the seventeenth inductor to form an eleventh node; and the second end of the seventeenth inductor is connected to the second power supply via the ninth resistor.

[0016] Optionally, the fourth input matching and negative feedback branch includes: a twentieth inductor, a twenty-first inductor, a twenty-second inductor, an eleventh resistor and a fourth capacitor, wherein the first end of the twentieth inductor is connected to the first input end of the fourth gain branch, and the second end of the twentieth inductor is connected to the first end of the twenty-second inductor to form a fourteenth node; the second end of the twenty-second inductor is connected to the third node; the first end of the twenty-first inductor is connected to the fourteenth node, and the second end of the twenty-first inductor is connected to the first end of the eleventh resistor through the fourth capacitor; the second end of the eleventh resistor is connected to the second input end of the fourth gain branch to form a tenth node; the fourth bias branch includes: a twelfth resistor, wherein the first end of the twelfth resistor is connected to the fourteenth node, and the second end of the twelfth resistor is connected to the fourth DC voltage source.

[0017] Optionally, the fourth gain branch includes: a fourth transistor, an eighteenth inductor, a nineteenth inductor and a tenth resistor, wherein the gate of the fourth transistor is connected to the first end of the twentieth inductor as the first input end of the fourth gain branch, the drain of the fourth transistor is connected to the tenth node, and the source of the fourth transistor is connected to the thirteenth node; the first end of the eighteenth inductor is connected to the tenth node, the second end of the eighteenth inductor is connected to the first end of the nineteenth inductor to form a twelfth node; the second end of the nineteenth inductor is connected to the second power supply via the tenth resistor; and the eleventh node and the twelfth node are connected to the output end of the amplifier.

[0018] Compared with the prior art, the present invention has the following beneficial effects:

[0019] The broadband, low-noise differential amplifier described in this application achieves efficient and stable signal amplification across a wide frequency band while maintaining low noise characteristics. By optimizing the first- and second-stage amplifier circuits, the differential amplifier ensures good input-output matching, a flat gain response, and excellent linearity across the entire operating frequency band. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 This is a circuit diagram of a broadband low-noise differential amplifier provided by the present application;

[0021] FIG2(a) is a diagram of the S of a broadband low-noise differential amplifier provided by an embodiment of the present application. 11 Schematic diagram of the simulation results of input return loss;

[0022] FIG2( b ) is a diagram of the S of a broadband low-noise differential amplifier provided by an embodiment of the present application. 12 Schematic diagram of the simulation results of the reverse transmission coefficient;

[0023] FIG2(c) is a diagram of the S of a broadband low-noise differential amplifier provided by an embodiment of the present application. 21 Schematic diagram of the simulation results of forward gain;

[0024] FIG2(d) is a diagram of the S of a broadband low-noise differential amplifier provided by an embodiment of the present application. 22 Schematic diagram of the simulation results of the output reflection coefficient;

[0025] FIG3( a ) is a schematic diagram of a noise figure curve of a broadband low-noise differential amplifier provided in an embodiment of the present application within a frequency range of 0.1 to 20 GHz;

[0026] FIG3( b ) is a Smith chart showing the noise figure of a broadband low-noise differential amplifier provided by one embodiment of the present application within a frequency range of 0.1 to 20 GHz;

[0027] Figure 4 This is a schematic diagram of simulation results of a 1dB compression point output by a broadband low-noise differential amplifier provided in one embodiment of the present application. DETAILED DESCRIPTION

[0028] Specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. Although specific embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0029] It should be noted that certain words are used in the specification and claims to refer to specific components. Those skilled in the art should understand that technicians may use different nouns to refer to the same component. This specification and claims do not use the difference in nouns as a way to distinguish components, but use the difference in the functions of the components as the criterion for distinction. As mentioned throughout the specification and claims, "including" or "comprising" is an open term, so it should be interpreted as "including but not limited to". The subsequent description of the specification is a preferred embodiment of the present application, but the description is based on the general principles of the specification and is not intended to limit the scope of the present application. The scope of protection of this application shall be as defined by the attached claims.

[0030] Figure 1 FIG. 1 is a schematic diagram of a circuit structure of a broadband low-noise differential amplifier provided by an exemplary embodiment of the present application. Figure 1As shown, the amplifier includes: a first-stage amplification circuit and a second-stage amplification circuit, wherein the first-stage amplification circuit is used to receive and perform a first-stage amplification on the radio frequency signal to obtain a radio frequency signal after the first stage amplification; the first-stage amplification circuit includes a first input matching and negative feedback branch, a first bias branch, a first gain branch, a first source degeneration branch, a second input matching and negative feedback branch, a second bias branch, a second gain branch, and a second source degeneration branch; the second-stage amplification circuit is used to perform a second-stage amplification on the radio frequency signal after the first stage amplification to obtain a radio frequency signal after the second stage amplification; the second-stage amplification circuit includes a third input matching and negative feedback branch, a third bias branch, a third gain branch, a fourth input matching and negative feedback branch, a fourth bias branch, and a fourth gain branch.

[0031] By setting up a two-stage amplifier circuit, the present application can reasonably distribute the total gain to each stage, avoiding the stability problems and nonlinear distortion caused by the high gain achieved in single-stage amplification. In addition, the use of two-stage amplification can ensure that the gain of each stage is within a reasonable range, thereby improving the linearity and stability of the differential amplifier. In addition, single-stage amplifiers often find it difficult to simultaneously meet the requirements of wide bandwidth and high gain. The use of a two-stage amplifier structure can improve the bandwidth characteristics of the entire system by carefully designing the impedance matching network between each stage. Each stage can be optimized for a specific frequency range, allowing the entire amplifier to maintain good matching and flat gain response over a wider frequency band. Furthermore, each stage of the amplifier circuit can independently consider stability factors, such as using techniques such as source degeneration to enhance stability and reduce the potential risk of parasitic oscillations. In addition, the two-stage architecture allows the implementation of a negative feedback mechanism between each stage, which helps to reduce the possibility of gain fluctuations with frequency changes, ensuring that signals at different frequencies are consistently amplified, thereby improving linearity.

[0032] In another exemplary embodiment, the first input matching and negative feedback branch 10 includes a first inductor L1, a second inductor L2, a third inductor L3, a first capacitor C1, and a second resistor R2, wherein the first end of the first inductor L1 is connected to the inverting end RFin- of the differential input signal, the second end of the first inductor L1 is connected to the first end of the second inductor L2 to form a first node N1, and the second end of the second inductor L2 is connected to the first input end of the first gain branch 12; the first end of the third inductor L3 is connected to the first node N1, the second end of the third inductor L3 is connected to the first end of the second resistor R2 through the first capacitor C1, and the second end of the second resistor R2 is connected to the second input end of the first gain branch 12 to form a second node N2.

[0033] In this embodiment, the first inductor L1, as a direct connection point to the inverting terminal RFin- of the differential input signal (i.e., the RF signal that has been converted to differential form), is used to provide a high-impedance path for the differential input signal, helping to minimize differential input signal reflections and ensure that the differential input signal can be efficiently transmitted to the first-stage amplifier circuit. The second inductor L2, located between the first node N1 and the first input end of the first gain branch 12, can further optimize the initial input matching provided by the first inductor L1. In conjunction with the first inductor L1, the input impedance characteristics are adjusted to meet broadband requirements, thereby allowing the first-stage amplifier circuit to maintain good matching performance over a wide frequency range, thereby improving the overall amplification efficiency of the first-stage amplifier circuit and the integrity of the amplified signal.

[0034] In addition, the third inductor L3, the first capacitor C1 and the second resistor R2 form a first negative feedback branch, which can provide stable negative feedback over the entire operating frequency band, thereby helping to stabilize the output of the first-stage amplifier circuit and improve linearity.

[0035] In another exemplary embodiment, the first bias branch includes a first resistor R1, a first end of the first resistor R1 is connected to the first node N1, and a second end of the first resistor R1 is connected to a first DC voltage source V G1 .

[0036] In this embodiment, the first resistor R1 is used to provide a stable DC bias condition for the first transistor M1. By selecting an appropriate resistance value, it can be ensured that the first transistor M1 receives a suitable gate voltage, so that it can operate stably under the expected working state and avoid signal distortion. In addition, the first DC voltage source V G1 It is a fixed DC voltage source, used to set the DC operating point of the gate of the first transistor M1, that is, to determine the operating region (such as the saturation region or the linear region) of the first transistor N1.

[0037] In another exemplary embodiment, the first gain branch 12 includes a first transistor M1, a fourth inductor L4, a fifth inductor L5, and a third resistor R3, wherein the gate of the first transistor M1 is connected to the second end of the second inductor L2 as the first input end of the first gain branch 12, the drain of the first transistor M1 is connected to the second node N2, the source of the first transistor M1 is connected to the input end of the first source degeneration branch 13, the first end of the fourth inductor L4 is connected to the second node N2, the second end of the fourth inductor L4 is connected to the first end of the fifth inductor L5 to form a third node N3, and the second end of the fifth inductor L5 is connected to the first power supply VDD1 via the third resistor R3.

[0038] In this embodiment, the fourth inductor L4 and the fifth inductor L5 form a first output matching network, wherein the first end of the fourth inductor L4 is connected to the second node N2, i.e., the drain of the first transistor M1, and the second end is connected to the first end of the fifth inductor L5 at the third node N3. This configuration allows for adjustment of the output impedance to achieve optimal power transfer to the next stage circuit, ensuring that the differential input signal can be effectively transmitted and minimizing reflection loss. The third resistor R3 is used to provide the necessary current path for the first transistor M1 under DC bias conditions and also performs a certain impedance matching function in the AC signal path. In addition, the third resistor R3 can help stabilize the operating point of the first transistor M1 and prevent possible parasitic oscillation.

[0039] In another exemplary embodiment, the first source degeneration branch 13 includes an eighth inductor L8. A first end of the eighth inductor L8 serves as an input end of the first source degeneration branch 13 and is connected to the source of the first transistor M1. A second end of the eighth inductor L8 serves as an output end of the first source degeneration branch 13 and is connected to the input end of the first current source ISS1 to form a sixth node N6. The output end of the first current source ISS1 is connected to the first ground end GND1.

[0040] In this embodiment, source degeneration is a method for adjusting the input impedance of a transistor by introducing additional impedance to its source. This helps improve amplifier stability, reduces gain to reduce nonlinear distortion, and enhances input matching performance. The first source degeneration branch implements the source degeneration effect by using the eighth inductor L8, reducing the gain of the first transistor M1, thereby improving the stability of the first-stage amplifier circuit and reducing the potential risk of parasitic oscillations. Due to the presence of the eighth inductor L8, the input impedance of the first transistor M1 is increased, helping to achieve better high-frequency response and a flatter gain curve.

[0041] The first current source ISS1 provides the necessary DC bias conditions for the first transistor M1, ensuring that the first transistor M1 can operate at the expected operating point. At the same time, the first current source ISS1 can also play a role in AC isolation. That is, the first current source ISS1 can effectively prevent the AC signal from flowing directly into the ground terminal, and instead force the AC signal to form a loop through the eighth inductor L8. In this way, the noise on the ground line can be prevented from affecting the performance of the first-stage amplifier circuit, thereby enabling the first-stage amplifier circuit to maintain a good signal-to-noise ratio.

[0042] In another exemplary embodiment, the second input matching and negative feedback branch 14 includes a tenth inductor L10, an eleventh inductor L11, a twelfth inductor L12, a fifth resistor R5, and a second capacitor C2, wherein a first end of the tenth inductor L10 is connected to the first input end of the second gain branch 16, a second end of the tenth inductor L10 is connected to the first end of the twelfth inductor L12 to form a seventh node N7, a second end of the twelfth inductor L12 is connected to the positive phase terminal RFin+ of the differential input signal, a first end of the eleventh inductor L11 is connected to the seventh node N7, a second end of the eleventh inductor L11 is connected to the first end of the fifth resistor R5 via the second capacitor C2, and a second end of the fifth resistor R5 is connected to the second input end of the second gain branch 16 to form a fifth node N5.

[0043] In this embodiment, the tenth inductor L10 is primarily used to provide a high-impedance path for the differential input signal, thereby helping to reduce reflection loss and ensure efficient transmission of the differential input signal. The twelfth inductor L12 is directly connected to the positive-phase terminal RFin+ of the differential input signal, helping to adjust the input impedance to cover a wide frequency band while providing a path for the differential input signal to efficiently enter the first-stage amplifier circuit. Similarly, the eleventh inductor L11, the second capacitor C2, and the fifth resistor R5 form a second negative feedback branch. Like the first negative feedback branch, this second negative feedback branch is also designed to provide stable negative feedback across the entire operating frequency band to enhance the stability and linearity of the first-stage amplifier circuit.

[0044] In another exemplary embodiment, the second bias branch 15 includes a sixth resistor R6, a first end of the sixth resistor R6 is connected to the seventh node N7, and a second end of the sixth resistor R6 is connected to the second DC voltage source V G2 .

[0045] In this embodiment, the sixth resistor R6 is used to provide a stable DC bias condition for the second transistor M2. By selecting an appropriate value of R6, it can be ensured that the second transistor M2 receives a suitable gate voltage, so that it can operate stably under the expected working state and avoid signal distortion. In addition, the second DC voltage source V G2 It is a fixed DC voltage source, used to set the DC operating point of the gate of the second transistor M2, that is, to determine the operating region of the second transistor N2 (such as the saturation region or the linear region).

[0046] In another exemplary embodiment, the second gain branch 16 includes a second transistor M2, a sixth inductor L6, a seventh inductor L7, and a fourth resistor R4, wherein the gate of the second transistor M2 is connected to the first end of the tenth inductor L10 as the first input end of the second gain branch 16, the drain of the second transistor M2 is connected to the fifth node N5, the source of the second transistor M2 is connected to the input end of the second source degeneration branch 17, the first end of the sixth inductor L6 is connected to the fifth node N5, the second end of the sixth inductor L6 is connected to the first end of the seventh inductor L7 to form a fourth node N4, and the second end of the seventh inductor L7 is connected to the first power supply VDD1 via the fourth resistor R4.

[0047] In this embodiment, the sixth inductor L6 and the seventh inductor L7 form a second output matching network, which can achieve optimal impedance matching from the second transistor M2 to the next-stage circuit, ensuring effective transmission of the differential input signal and minimizing reflection loss. The fourth resistor R4 is used to provide the necessary current path for the second transistor M2 under DC bias conditions, and also plays a certain impedance matching role in the AC signal path. In addition, the fourth resistor R4 can also help stabilize the operating point of the second transistor M2 and prevent possible parasitic oscillation.

[0048] In another exemplary embodiment, the second source degeneration branch 17 includes a ninth inductor L9, a first end of the ninth inductor L9 serving as an input end of the second source degeneration branch 17 connected to the source of the second transistor M2, and a second end of the ninth inductor L9 serving as an output end of the second source degeneration branch 17 connected to the sixth node N6.

[0049] In this embodiment, similar to the function of the eighth inductor L8, the second source degeneration branch 17 utilizes the ninth inductor L9 to achieve a source degeneration effect, thereby reducing the gain of the second transistor M2, thereby further improving the stability of the first-stage amplifier circuit and reducing the potential risk of parasitic oscillation. Due to the presence of the ninth inductor L9, the input impedance of the second transistor M2 is increased, which helps achieve better high-frequency response and a flatter gain curve.

[0050] In another exemplary embodiment, the third input matching and negative feedback branch 20 includes a thirteenth inductor L13, a fourteenth inductor L14, a fifteenth inductor L15, a third capacitor C3, and an eighth resistor R8, wherein a first end of the thirteenth inductor L13 is connected to the fourth node N4, a second end of the thirteenth inductor L13 is connected to the first end of the fourteenth inductor L14 to form an eighth node N8, a second end of the fourteenth inductor L14 is connected to the first input end of the third gain branch 22, a first end of the fifteenth inductor L15 is connected to the eighth node N8, a second end of the fifteenth inductor L15 is connected to the first end of the eighth resistor R8 via the third capacitor C3, and a second end of the eighth resistor R8 is connected to the second input end of the third gain branch 22 to form a ninth node N9.

[0051] In this embodiment, the fifteenth inductor L15, the third capacitor C3, and the eighth resistor R8 form a third negative feedback branch, thereby stabilizing the gain of the third transistor M3 and reducing the possibility of gain fluctuation with frequency. This helps maintain a flat gain response across the entire frequency band, ensuring consistent amplification of signals at different frequencies. Furthermore, the eighth resistor R8 provides the necessary DC bias path for the third transistor M3, ensuring that it operates at the correct operating point, thereby ensuring that the third transistor M3 operates stably under the intended conditions.

[0052] It should be noted that the first end of the thirteenth inductor L13, by being connected to the fourth node N4, can adjust the input impedance of the second amplifier circuit, enabling the second amplifier circuit to better match the output impedance of the first-stage amplifier circuit, ensuring efficient signal transmission from the first-stage amplifier circuit to the second-stage amplifier circuit and reducing reflection losses. Furthermore, the first end of the thirteenth inductor L13, by being connected to the fourth node N4, can form a local negative feedback loop to help stabilize the operating point of the third transistor M3, helping to reduce gain fluctuations of the third transistor M3 caused by temperature changes or component parameter differences, and reducing nonlinear distortion, thereby improving the overall linearity performance of the amplifier.

[0053] In another exemplary embodiment, the third bias branch 21 includes a seventh resistor R7, a first end of the seventh resistor R7 is connected to the eighth node N8, and a second end of the seventh resistor R7 is connected to a third DC voltage source V G3 .

[0054] In this embodiment, the seventh resistor R7 not only provides a stable DC bias voltage for the gate of the third transistor M3, but also serves as an isolation function, separating the DC bias voltage from the AC signal path, thereby preventing the DC voltage from affecting the AC characteristics of the input signal. It also prevents the AC signal from interfering with the DC bias condition, so that the third transistor M3 can maintain a stable DC operating point even when processing high-frequency signals, thereby avoiding bias drift caused by the AC signal.

[0055] The third DC voltage source V G3 It is used to set the DC operating point of the gate of the third transistor M3 to ensure that the third transistor M3 can operate in the saturation region or the linear region.

[0056] In another exemplary embodiment, the third gain branch 22 includes a third transistor M3, a sixteenth inductor L16, a seventeenth inductor L17, and a ninth resistor R9, wherein the gate of the third transistor M3 is connected to the second end of the fourteenth inductor L14 as the first input end of the third gain branch 22, the drain of the third transistor M3 is connected to the ninth node N9, the source of the third transistor M3 is connected to the input end of the second current source ISS2 to form a thirteenth node N13, the output end of the second current source ISS2 is connected to the second ground end GND2, the first end of the sixteenth inductor L16 is connected to the ninth node N9, the second end of the sixteenth inductor L16 is connected to the first end of the seventeenth inductor L17 to form an eleventh node N11, and the second end of the seventeenth inductor L17 is connected to the second power supply VDD2 via the ninth resistor R9.

[0057] In this embodiment, the sixteenth inductor L16 and the seventeenth inductor L17 form a third output matching network, which can achieve optimal impedance matching from the third transistor M3 to the next-stage circuit, ensuring effective signal transmission and minimizing reflection loss. The ninth resistor R9 is used to provide the necessary current path for the third transistor M3 under DC bias conditions, and also plays a certain impedance matching role in the AC signal path. In addition, the ninth resistor R9 can also help stabilize the operating point of the third transistor M3 and prevent possible parasitic oscillation.

[0058] In another exemplary embodiment, the fourth input matching and negative feedback branch 23 includes a twentieth inductor L20, a twenty-first inductor L21, a twenty-second inductor L22, an eleventh resistor R11, and a fourth capacitor C4, wherein a first end of the twentieth inductor L20 is connected to the first input end of the fourth gain branch 25, a second end of the twentieth inductor L20 is connected to the first end of the twenty-second inductor L22 to form a fourteenth node N14, a second end of the twenty-second inductor L22 is connected to the third node N3, a first end of the twenty-first inductor L21 is connected to the fourteenth node N14, a second end of the twenty-first inductor L21 is connected to the first end of the eleventh resistor R11 via the fourth capacitor C4, and a second end of the eleventh resistor R11 is connected to the second input end of the fourth gain branch 25 to form a tenth node N10.

[0059] In this embodiment, the twenty-first inductor L21, the fourth capacitor C4, and the eleventh resistor R11 form a fourth negative feedback branch, thereby stabilizing the gain of the fourth transistor M4 and reducing the possibility of gain fluctuation with frequency. This helps maintain a flat gain response across the entire frequency band, ensuring that signals at different frequencies are consistently amplified. Furthermore, the eleventh resistor R11 provides the necessary DC bias path for the fourth transistor M4, ensuring that it operates at the correct operating point, thereby ensuring that the fourth transistor M4 can operate stably under the expected conditions.

[0060] It should be noted that the second end of the twenty-second inductor L22 can adjust the input impedance of the fourth gain branch 25 by connecting to the third node N3, so that the fourth gain branch 25 can better match the output impedance of the first-stage amplifier circuit, which helps to reduce signal reflection and improve signal transmission efficiency.

[0061] In another exemplary embodiment, the fourth bias branch 24 includes a twelfth resistor R12, a first end of the twelfth resistor R12 is connected to the fourteenth node N14, and a second end of the twelfth resistor R12 is connected to a fourth DC voltage source V G4 .

[0062] In this embodiment, similar to the function of the seventh resistor R7, the twelfth resistor R12 not only provides a stable DC bias voltage for the gate of the fourth transistor M4, but also serves as an isolation function, separating the DC bias voltage from the AC signal path, thereby preventing the DC voltage from affecting the AC characteristics of the input signal. It also prevents the AC signal from interfering with the DC bias condition, so that the fourth transistor M4 can maintain a stable DC operating point even when processing high-frequency signals, thereby avoiding bias drift caused by the AC signal.

[0063] The fourth DC voltage source V G4 It is used to set the DC operating point of the gate of the fourth transistor M4 to ensure that the fourth transistor M4 can operate in the saturation region or the linear region.

[0064] In another exemplary embodiment, the fourth gain branch 25 includes a fourth transistor M4, an eighteenth inductor L18, a nineteenth inductor L19, and a tenth resistor R10, wherein the gate of the fourth transistor M4 is connected to the first end of the twentieth inductor L20 as the first input terminal of the fourth gain branch 25, the drain of the fourth transistor M4 is connected to the tenth node N10, the source of the fourth transistor M4 is connected to the thirteenth node N13, the first end of the eighteenth inductor L18 is connected to the tenth node N10, the second end of the eighteenth inductor L18 is connected to the first end of the nineteenth inductor L19 to form a twelfth node N12, the second end of the nineteenth inductor L19 is connected to the second power supply VDD2 via the tenth resistor R10, and the eleventh node N11 and the twelfth node N12 are connected to the output terminal RF of the amplifier. out .

[0065] In this embodiment, the eighteenth inductor L18 and the nineteenth inductor L19 constitute a fourth output matching network, which can achieve optimal impedance matching from the fourth transistor M4 to the next-stage circuit, ensuring effective signal transmission and minimizing reflection loss. The main function of the tenth resistor R10 is to provide the necessary current path for the fourth transistor M4 under DC bias conditions, and also play a certain impedance matching role in the AC signal path. In addition, the tenth resistor R10 can also help stabilize the operating point of the fourth transistor M4 and prevent possible parasitic oscillation.

[0066] FIG2(a) is a diagram of the S of a broadband low-noise differential amplifier provided by an embodiment of the present application. 11 Schematic diagram of the simulation results of input return loss; FIG2(b) is a schematic diagram of the S of a broadband low-noise differential amplifier provided by an embodiment of the present application. 12 Schematic diagram of the simulation results of the reverse transmission coefficient; FIG2(c) is a schematic diagram of the S of the broadband low-noise differential amplifier provided by an embodiment of the present application 21 2 (d) is a schematic diagram of the simulation results of the forward gain of the broadband low-noise differential amplifier provided by an embodiment of the present application. 22Schematic diagram of the simulation results of the output reflection coefficient. Figures 2(a) and 2(d) show that within the operating frequency band, the input and output matching of this embodiment are both above 10 dB, demonstrating excellent matching. Figure 2(c) shows that the forward gain of this embodiment is in the range of 19.9 to 21.0 dB, achieving high gain and flatness from 0.1 to 20 GHz.

[0067] Figure 3(a) is a schematic diagram of the noise figure curve of a broadband low-noise differential amplifier provided by one embodiment of the present application within the frequency range of 0.1 to 20 GHz; Figure 3(b) is a Smith chart of the noise figure of a broadband low-noise differential amplifier provided by one embodiment of the present application within the frequency range of 0.1 to 20 GHz. As can be seen from Figure 3(a), within the frequency range of 0.1 to 20 GHz, Figure 1 The maximum noise figure of the broadband low-noise differential amplifier shown is 2.13dB. When the frequency is 18.5Hz, the noise figure reaches a minimum of 2.00dB, which shows that the amplifier described in this application maintains a relatively stable low noise level at both lower and higher frequencies. As shown in Figure 3(b), the trajectory of the noise figure does not deviate significantly from the center of the circle over the entire frequency range. In the Smith chart, the position close to the center of the circle represents lower reflection loss or a better matching state, which means that the amplifier not only maintains a low noise figure throughout the operating frequency band, but also exhibits good input matching characteristics, thereby ensuring effective transmission and amplification of the signal.

[0068] In summary, Figure 1 The broadband low-noise differential amplifier shown demonstrates excellent low-noise amplification capabilities within its designed frequency range of 0.1 to 20 GHz. The maximum noise figure does not exceed 2.13 dB and remains at a lower level at most frequencies. Furthermore, the noise figure trajectory on the Smith chart approaches the center of the circle, indicating that the amplifier has good input matching performance, which facilitates efficient, low-noise signal amplification. Therefore, it can be said that this amplifier successfully achieves low-noise amplification requirements over a broadband range, making it suitable for applications requiring high sensitivity and broadband operation.

[0069] Figure 4 The figure is a schematic diagram of the simulation results of the 1dB compression point output of the broadband low-noise differential amplifier. Figure 4 It can be seen that in the frequency range of 0.1 to 20 GHz, Figure 1The output 1dB compression point of the broadband low-noise differential amplifier shown in the figure ranges from 5.84 to 6.34dBm, with a minimum value of 5.84dBm occurring at 1.8GHz. This demonstrates that even at its lowest point (5.84dBm at 1.8GHz), the amplifier described in this application can still provide relatively high output power without significantly entering the nonlinear region. Considering this is a broadband amplifier design, the ability to maintain a relatively stable output 1dB compression point over such a wide frequency range demonstrates its good linearity performance across different frequencies.

[0070] In summary, the broadband low-noise differential amplifier designed in this application has a wide frequency range, flat gain within the frequency band, a low noise figure, and sufficiently high power gain. This broadband low-noise differential amplifier designed in this application overcomes multiple bandwidth limitations that have been difficult to balance in previous amplifiers, achieving high-gain, low-noise amplification across a bandwidth range of 0.1 GHz to 20 GHz, meeting the diverse, wide-bandwidth, and compact requirements of modern wireless communication systems.

[0071] The above description is only a specific implementation method of the present application. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes; all disclosed features, or all steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

Claims

1. A broadband low-noise differential amplifier, characterized in that: The differential amplifier comprises: The first stage amplifier circuit and the second stage amplifier circuit, wherein, The first-stage amplification circuit is used to receive a positive-phase differential input signal and a negative-phase differential input signal and perform a first-stage amplification to obtain a positive-phase differential input signal and a negative-phase differential input signal after the first-stage amplification; The second-stage amplification circuit is used to perform a second-stage amplification on the positive-phase differential input signal and the negative-phase differential input signal after the first-stage amplification, so as to obtain the positive-phase differential input signal and the negative-phase differential input signal after the second-stage amplification; The first-stage amplifier circuit includes: a first input matching and negative feedback branch, a first bias branch, a first gain branch, a first source degeneration branch, a second input matching and negative feedback branch, a second bias branch, a second gain branch, and a second source degeneration branch; wherein, The first input matching and negative feedback branch and the second input matching and negative feedback branch are used to optimize matching of the inverted differential input signal and the positive differential input signal and provide negative feedback respectively; The first gain branch and the second gain branch are used to perform signal gain on the inverse phase differential input signal and the positive phase differential input signal after optimized matching, respectively; The first bias branch and the second bias branch are used to provide stable DC operating points for the first gain branch and the second gain branch respectively; The first source degeneration branch and the second source degeneration branch are used to increase source impedance for the first gain branch and the second gain branch respectively; in, The first input matching and negative feedback branch includes: a first inductor, a second inductor, a third inductor, a first capacitor, and a second resistor, wherein: The first end of the first inductor is connected to the inverting end of the differential input signal, and the second end of the first inductor is connected to the first end of the second inductor to form a first node; The second end of the second inductor is connected to the first input end of the first gain branch; A first end of the third inductor is connected to the first node, and a second end of the third inductor is connected to the first end of the second resistor via the first capacitor; The second end of the second resistor is connected to the second input end of the first gain branch to form a second node; The first bias branch comprises: The first resistor, where A first end of the first resistor is connected to the first node, and a second end of the first resistor is connected to a first DC voltage source.

2. A broadband low-noise differential amplifier according to claim 1, characterized in that: The second-stage amplifier circuit includes: a third input matching and negative feedback branch, a third bias branch, a third gain branch, a fourth input matching and negative feedback branch, a fourth bias branch, and a fourth gain branch, wherein: The third input matching and negative feedback branch and the fourth input matching and negative feedback branch are used to optimize and match the positive phase differential input signal and the negative phase differential input signal after the first stage amplification, respectively; The third gain branch and the fourth gain branch are used to perform signal gain on the positive phase differential input signal and the negative phase differential input signal after the first stage amplification after optimized matching, respectively; The third bias branch and the fourth bias branch are used to provide stable DC operating points for the third gain branch and the fourth gain branch, respectively.

3. The broadband low-noise differential amplifier according to claim 2, wherein: The first gain branch comprises: a first transistor, a fourth inductor, a fifth inductor and a third resistor, wherein: The gate of the first transistor is connected to the second end of the second inductor as the first input end of the first gain branch, the drain of the first transistor is connected to the second node, and the source of the first transistor is connected to the input end of the first source degeneration branch; The first end of the fourth inductor is connected to the second node, and the second end of the fourth inductor is connected to the first end of the fifth inductor to form a third node; The second end of the fifth inductor is connected to the first power supply through the third resistor; The first source degeneration branch comprises: The eighth inductor, where A first end of the eighth inductor serves as an input end of the first source degeneration branch and is connected to the source of the first transistor. A second end of the eighth inductor serves as an output end of the first source degeneration branch and is connected to the input end of the first current source to form a sixth node. An output terminal of the first current source is connected to a first ground terminal.

4. The broadband low-noise differential amplifier according to claim 3, wherein: The second input matching and negative feedback branch includes: a tenth inductor, an eleventh inductor, a twelfth inductor, a fifth resistor, and a second capacitor, wherein: The first end of the tenth inductor is connected to the first input end of the second gain branch, and the second end of the tenth inductor is connected to the first end of the twelfth inductor to form a seventh node; The second end of the twelfth inductor is connected to the positive phase end of the differential input signal; The first end of the eleventh inductor is connected to the seventh node, and the second end of the eleventh inductor is connected to the first end of the fifth resistor via the second capacitor; The second end of the fifth resistor is connected to the second input end of the second gain branch to form a fifth node; The second bias branch comprises: The sixth resistor, wherein A first end of the sixth resistor is connected to the seventh node, and a second end of the sixth resistor is connected to a second DC voltage source.

5. The broadband low-noise differential amplifier according to claim 4, characterized in that: The second gain branch includes: a second transistor, a sixth inductor, a seventh inductor and a fourth resistor, wherein: The gate of the second transistor is connected to the first end of the tenth inductor as the first input end of the second gain branch, the drain of the second transistor is connected to the fifth node, and the source of the second transistor is connected to the input end of the second source degeneration branch; The first end of the sixth inductor is connected to the fifth node, and the second end of the sixth inductor is connected to the first end of the seventh inductor to form a fourth node; The second end of the seventh inductor is connected to the first power supply through the fourth resistor; The second source degeneration branch includes: Ninth inductor, where A first end of the ninth inductor serves as an input end of the second source degeneration branch and is connected to the source of the second transistor. A second end of the ninth inductor serves as an output end of the second source degeneration branch and is connected to the sixth node.

6. The broadband low-noise differential amplifier according to claim 5, characterized in that: The third input matching and negative feedback branch includes: a thirteenth inductor, a fourteenth inductor, a fifteenth inductor, a third capacitor and an eighth resistor, wherein: The first end of the thirteenth inductor is connected to the fourth node, and the second end of the thirteenth inductor is connected to the first end of the fourteenth inductor to form an eighth node; The second end of the fourteenth inductor is connected to the first input end of the third gain branch; A first end of the fifteenth inductor is connected to the eighth node, and a second end of the fifteenth inductor is connected to the first end of the eighth resistor via the third capacitor; The second end of the eighth resistor is connected to the second input end of the third gain branch to form a ninth node; The third bias branch comprises: The seventh resistor, wherein A first end of the seventh resistor is connected to the eighth node, and a second end of the seventh resistor is connected to a third DC voltage source.

7. The broadband low-noise differential amplifier according to claim 6, wherein: The third gain branch comprises: a third transistor, a sixteenth inductor, a seventeenth inductor and a ninth resistor, wherein: The gate of the third transistor is connected to the second end of the fourteenth inductor as the first input end of the third gain branch, the drain of the third transistor is connected to the ninth node, and the source of the third transistor is connected to the input end of the second current source to form a thirteenth node; The output terminal of the second current source is connected to the second ground terminal; The first end of the sixteenth inductor is connected to the ninth node, and the second end of the sixteenth inductor is connected to the first end of the seventeenth inductor to form an eleventh node; The second end of the seventeenth inductor is connected to the second power supply through the ninth resistor.

8. The broadband low-noise differential amplifier according to claim 7, characterized in that: The fourth input matching and negative feedback branch includes: a twentieth inductor, a twenty-first inductor, a twenty-second inductor, an eleventh resistor, and a fourth capacitor, wherein: A first end of the 20th inductor is connected to the first input end of the fourth gain branch, and a second end of the 20th inductor is connected to the first end of the 22nd inductor to form a fourteenth node; The second end of the twenty-second inductor is connected to the third node; A first end of the twenty-first inductor is connected to the fourteenth node, and a second end of the twenty-first inductor is connected to the first end of the eleventh resistor via the fourth capacitor; The second end of the eleventh resistor is connected to the second input end of the fourth gain branch to form a tenth node; The fourth bias branch comprises: The twelfth resistor, A first end of the twelfth resistor is connected to the fourteenth node, and a second end of the twelfth resistor is connected to a fourth DC voltage source.

9. The broadband low-noise differential amplifier according to claim 8, characterized in that: The fourth gain branch comprises: a fourth transistor, an eighteenth inductor, a nineteenth inductor, and a tenth resistor, wherein: The gate of the fourth transistor is connected to the first end of the twentieth inductor as the first input end of the fourth gain branch, the drain of the fourth transistor is connected to the tenth node, and the source of the fourth transistor is connected to the thirteenth node; The first end of the eighteenth inductor is connected to the tenth node, and the second end of the eighteenth inductor is connected to the first end of the nineteenth inductor to form a twelfth node; The second end of the nineteenth inductor is connected to the second power supply via the tenth resistor; The eleventh node and the twelfth node are connected to output terminals of the amplifier.

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