FPGA-based multi-channel amplitude and phase correction method and system for RF receiver

Abstract

A multi-channel amplitude and phase correction method for a radio frequency receiver based on an FPGA includes steps S1, where the radio frequency receiver groups the real-time received signals in a large-scale multi-input multi-output system, with each group including a reference channel signal and a channel signal to be calibrated. Steps S2 and S3 are then executed for each group to perform signal correction. Step S2 preprocesses each group of received signals to obtain a preprocessed sampled signal. Step S3 constructs an amplitude and phase correction model, calculates phase and amplitude correction factors based on the preprocessed sampled signal, performs iterative correction operations on the channel signal to be calibrated, and outputs the corrected signal. Step S4 completes the correction for all groups, obtaining M groups of corrected signals, and completing this round of signal correction. This design reduces FPGA computing resource consumption while ensuring amplitude and phase correction accuracy, and avoids the problem of decreased correction accuracy that occurs when the number of sampling points is not an integer of the signal period.

Description

Technical Field

[0001] The present invention relates to a multi-channel amplitude and phase correction method and system for a radio frequency receiving end based on FPGA, and is particularly suitable for performing real-time signal correction using FPGA. Background Art

[0002] 5G is becoming increasingly integrated into our lives. Its core technologies include massive multiple-input, multiple-output (MIMO) systems and orthogonal frequency division multiplexing (OFDM). Massive MIMO systems improve spectrum utilization, reduce transmit power, and increase system capacity by increasing the number of antennas. Furthermore, the use of a large number of antennas simplifies power control and effectively overcomes frequency-selective channel fading. However, massive MIMO systems also face new challenges, a key one being multi-channel amplitude and phase calibration. In massive MIMO systems, subtle hardware differences between channels, antenna coupling, and environmental interference can lead to amplitude and phase inconsistencies between different channels at the receiver, impacting system operation. To ensure proper system operation, high-precision amplitude and phase calibration is essential; resolving this issue is crucial for improving system performance.

[0003] Most current multi-channel amplitude and phase correction systems utilize analog circuits. These circuits, such as gain-controlled amplifiers and analog phase shifters, can achieve highly accurate amplitude and phase correction for specific RF transceiver systems. However, these circuits are subject to long development cycles and are difficult to modify. Any adjustments to the communication device, such as modifications to the communication protocol, changes to communication parameters, or significant changes in environmental conditions, require recalibration. However, these modifications to analog circuits are costly, time-consuming, and lack guaranteed calibration accuracy. However, the rapid advancement of wireless communication technology has made analog amplitude and phase correction circuits no longer suitable for today's environment.

[0004] Against this backdrop, software-defined radio (SDR) technology emerged. It uses software to configure various parameters in wireless communications, including baseband signal type, sampling rate, signal transmission bandwidth, and RF frequency band. SDR platforms not only process baseband signals but also program and reconfigure intermediate frequency (IF) signals. Among the many SDR development platforms, FPGAs offer unique advantages. Unlike the sequential execution of conventional processors, FPGAs enable efficient parallel data processing, making them particularly well-suited for implementing complex algorithms and processing high-speed signals in wireless communications. Furthermore, FPGA platforms can be dynamically reconfigured to suit different communication tasks. Developers can quickly change algorithms or optimize logic based on application scenarios without redesigning hardware, significantly shortening R&D cycles and improving development efficiency.

[0005] Currently, amplitude and phase correction using FPGAs can generally only be performed on narrowband signals. When correcting wideband signals, the correction time is long and the accuracy is low. At the same time, the current amplitude and phase correction algorithm consumes a lot of FPGA logic resources and cannot be deployed on resource-constrained FPGAs.

[0006] In summary, the development of an FPGA-based multi-channel amplitude and phase calibration system can not only effectively solve the amplitude and phase correction problem in large-scale MIMO systems, but also meet the requirements of future wireless communication systems for high flexibility, low power consumption, and high integration, thus pushing wireless communication technology to a new level and having far-reaching significance for the development of the entire communications field. Summary of the Invention

[0007] The purpose of the present invention is to overcome the problem in the prior art that broadband signals cannot be accurately and quickly corrected, and to provide an FPGA-based RF receiving end multi-channel amplitude and phase correction method and system for accurately and quickly correcting broadband signals.

[0008] To achieve the above objectives, the technical solution of the present invention is:

[0009] In a first aspect, the present invention provides a multi-channel amplitude and phase correction method for a radio frequency receiving end based on FPGA, comprising the following steps:

[0010] In a large-scale MIMO system, the RF receiver receives the signal of each channel in real time, groups the received signals into groups, and each group includes a reference channel signal and a channel signal to be calibrated. Steps S2-S3 are then executed for each group to perform signal correction.

[0011] S2. Sampling each group of received signals, and preprocessing the sampled signals to obtain preprocessed sampled signals;

[0012] S3. Construct an amplitude-phase correction model, calculate the phase correction factor and the amplitude correction factor based on the preprocessed sampled signal, perform iterative correction operation on the channel signal to be calibrated, and output the corrected signal;

[0013] S4. After all groups have been calibrated, M groups of calibrated signals are obtained, and this round of signal calibration is completed.

[0014] In the large-scale multi-input multi-output system, the RF receiving end receives the signal of each channel in real time and sets any one of the channels as the reference channel signal A. a (t), the remaining M channels are the channel signals to be calibrated { B b1 (t), B b2 (t)…B bm (t)…B bM (t)}; Each channel signal to be calibrated Bbm (t) and the reference channel signal A a (t) The phase and amplitude calibration operations are performed by combining the phase and amplitude calibration operations into one group and performing the steps S2 to S3 for each group.

[0015] In S2, each group of received signals is sampled and the sampled signals are preprocessed:

[0016] First, the received signal is smoothed and truncated using the Hanning window function to obtain the smoothed signal {A a (n), B bm (n)};

[0017] If {A a (n), B bm (n)} is less than 10% of its signal center frequency, then let {A a (n), B bm (n)} as the preprocessed sampled signal {A a (n), B b (n)} output;

[0018] If {A a (n), B bm (n)} is greater than or equal to 10% of its signal center frequency, then the frequency domain LMS filter is used to filter B bm (n) Perform filtering iterative operation to obtain the filtered channel signal to be calibrated B b (n), let {A a (n), B b (n)} is output as the preprocessed sampling signal.

[0019] In S2, the frequency domain LMS filter is used to filter B bm (n) Perform filtering iterative operation:

[0020] S21, smoothed reference channel signal A a (n) Perform fast Fourier transform to obtain the reference channel signal M in the frequency domain a (f) For the smoothed channel signal B to be corrected bm (n) Perform fast Fourier transform to obtain the channel signal N to be corrected in the frequency domain b (f) Assume that the coefficient of the frequency domain LMS filter is W(K), let K = 0, and set the initial value of the coefficient of the frequency domain LMS filter to W(0);

[0021] S22, the output signal of the frequency domain LMS filter is L(K):

[0022] L(K)= N b (f)* W(K);

[0023] The reference channel signal M a (f) After delay, get M del (f), M del (f) and L(K) are used to calculate the error, and the error value e(K) between the reference channel signal and the channel signal to be calibrated is obtained:

[0024] e(K)= M del (f)-L(K);

[0025] S23. If the error value e(K) is greater than the set threshold and the maximum number of iterations has not been reached, the coefficients of the frequency domain LMS filter are updated:

[0026] W(K+1)= W(K)+µ(K)* e(K)* N b (f);

[0027] Where µ(K) is the iteration step size, µ(K)=kµ(K-1)+b*e 2 (K-1), k is the coefficient of dynamic adjustment in actual test, b is the adjustment factor, b=αµ(K-2)+(1-α)*e 2 (K-2), α is the fine-tuning factor;

[0028] If the error value e(K) is less than the set threshold or reaches the maximum number of iterations, L(K) is subjected to inverse fast Fourier transform to obtain the filtered channel signal to be calibrated B b (n) .

[0029] The S3 includes:

[0030] S31, build an amplitude phase correction model, receive the pre-processed sampling signal {A a (n), B b (n)}, setting: the signal A of the reference channel after preprocessing a (n) The I-path signal and Q-path signal are I a (n), Q a (n), let the preprocessed signal B of the channel to be corrected be b (n) is the signal B of the channel to be calibrated during the first calibration b (n)1,B b (n)1's I-path signal and Q-path signal are I b (n)1, Q b (n)1;

[0031] S32. Calculate the amplitude correction factor for the sth correction :

[0032] S33. Calculate the phase correction factor for the sth correction: Calculate the phase difference using the cordic algorithm The angle value of , and then calculate the phase correction factor of the sth correction;

[0033] S34, based on the amplitude correction factor and phase correction factor of the sth correction, correct the channel signal to be corrected to obtain the correction result B b (n) s+1 :

[0034] If the amplitude correction factor or phase difference If the set threshold is not met, set s=s+1 and correct the result B b (n) s+1 Return to S32 to continue iterative calculation;

[0035] If the amplitude correction factor Phase difference If all meet the set threshold or reach the maximum number of iterations, the correction result B b (n) s+1 Output as the corrected signal.

[0036] In the step S32, the amplitude correction factor of the sth correction is calculated. :

[0037] ;

[0038] in, is the power ratio between the reference channel signal in the s-th calibration and the channel signal to be corrected in the s-th calibration;

[0039] ;

[0040] Among them, I b (n) s is the I signal of the channel to be corrected for the sth correction, Q b (n) s is the Q-channel signal of the channel to be corrected for the sth correction, N is the length of the Hanning window, and n is the current sampling point.

[0041] against Design a divider with limited bit width, set the bit width of the divisor and dividend of the divider, and the bit width of the dividend is:

[0042] ;

[0043] The divisor width is:

[0044] ;

[0045] The bit width of the quotient is: quotient = integer + decimal;

[0046] Among them, integer is the bit width of the integer part of the quotient, which is the set value, and decimal is the bit width of the decimal part of the quotient, as shown in the following formula:

[0047] ;

[0048] Amp is the set amplitude difference threshold, Amp res is the resolution of the amplitude difference threshold;

[0049] against The square root module sets its input bit width to match the bit width of the decimal and integer parts of the divider quotient, and sets the square root module output bit width to:

[0050] ;

[0051] Where root is the output bit width of the amplitude correction factor square root module.

[0052] In S33, the phase correction factor of the s-th correction is calculated:

[0053] The reference channel signal A is calculated using fast Fourier transform a (n) and the channel signal B to be corrected for the sth correction bm (n) Tangent of the phase difference , use the cordic algorithm to calculate the phase difference The angle value of the sth correction is obtained by:

[0054] ;

[0055] Set the number of iterations of the cordic algorithm and index the cordic tangent table value in an incremental manner. That is, the cordic tangent table address value is no longer recalculated in each iteration, but is incremented according to the table address value of the previous iteration;

[0056] In S34, the channel signal to be corrected is corrected based on the amplitude correction factor and phase correction factor corrected for the sth time, and a correction result is obtained:

[0057] ;

[0058] Among them, I b (n) s+1 The I-channel signal in the correction result is also the I-channel signal of the channel to be corrected in the s+1th correction; Q b (n) s+1The Q-channel signal in the correction result is also the Q-channel signal of the channel to be corrected in the (s+1)th correction.

[0059] In a second aspect, the present invention provides an FPGA-based RF receiving end multi-channel amplitude phase correction system, which is used to execute the aforementioned FPGA-based RF receiving end multi-channel amplitude phase correction method, specifically including: a sampling grouping module, a preprocessing module, an amplitude phase correction module, and a data integration module;

[0060] Sampling and grouping module: used in large-scale multiple-input multiple-output systems. The RF receiver receives the signal of each channel in real time and groups the received signals. Each group includes a reference channel signal and a channel signal to be calibrated. Signal correction is performed on a group-by-group basis.

[0061] Preprocessing module: used to sample each group of received signals, preprocess the sampled signals, and obtain preprocessed sampled signals;

[0062] Amplitude and phase correction module: used to build an amplitude and phase correction model. Based on the preprocessed sampling signal, it calculates the phase correction factor and amplitude correction factor, performs iterative correction operations on the channel signal to be calibrated, and outputs the corrected signal.

[0063] Data integration module: used to obtain M groups of corrected signals after all groups have been corrected, thus completing this round of signal correction.

[0064] In a third aspect, the present invention provides an FPGA-based RF receiving end multi-channel amplitude and phase correction device, comprising a memory and a processor, wherein the memory is used to store computer program code and transmit the computer program code to the processor;

[0065] The processor is configured to execute the aforementioned FPGA-based RF receiving end multi-channel amplitude and phase correction method according to instructions in the computer program code.

[0066] Compared with the prior art, the present invention has the following beneficial effects:

[0067] 1. In the FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiving end of the present invention, a Hanning window is added to smooth the sampled signal after signal sampling, thereby avoiding the problem of decreased correction accuracy when the number of sampling points is not an integer of the signal period.

[0068] 2. In the FPGA-based multi-channel amplitude and phase correction method for the RF receiving end of the present invention, a variable step size frequency domain LMS filter is designed for broadband signals when performing amplitude and phase correction on the signal, and the broadband signal is equalized in the frequency domain to ensure the correction accuracy of the broadband signal.

[0069] 3. In the FPGA-based RF receiving end multi-channel amplitude and phase correction method of the present invention, when performing amplitude correction, a divider and square root module with limited bit width are designed according to the amplitude correction accuracy, which greatly reduces the logic resource consumption of FPGA.

[0070] 4. In the FPGA-based RF receiving end multi-channel amplitude and phase correction method of the present invention, when performing phase correction, the Verilog implementation of the used Cordic algorithm is optimized. According to the calculation principle of Cordic, the calculation relationship between the iteration round and the address value of the Cordic tangent table is established, the algorithm implementation logic is optimized, and the logic resource consumption of the FPGA is reduced.

[0071] 5. The present invention provides an FPGA-based multi-channel amplitude and phase correction system for a radio frequency receiver, comprising: a sampling grouping module, a preprocessing module, an amplitude and phase correction module, and a data integration module. This system is configured to implement the steps of the FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiver as provided in any of the aforementioned technical solutions. Therefore, this system also includes all the beneficial effects of the FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiver as provided in any of the aforementioned technical solutions, and will not be further elaborated here.

[0072] 6. A FPGA-based multi-channel amplitude and phase correction device for a radio frequency receiver according to the present invention includes a processor and a memory. The memory is configured to store computer program code and transmit the computer program code to the processor. The processor is configured to execute the FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiver according to any of the aforementioned technical solutions according to the instructions in the computer program code. Therefore, this device also includes all the beneficial effects of the FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiver according to any of the aforementioned technical solutions, and no further description is given here. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] Figure 1 It is a flow chart of the method of the present invention.

[0074] Figure 2 Schematic diagram of the variable step-size frequency-domain LMS filter in Example 1.

[0075] Figure 3 3 is a waveform comparison diagram before and after multi-channel amplitude and phase correction in Example 1.

[0076] Figure 4 It is a system schematic diagram of the present invention.

[0077] Figure 5 It is an equipment diagram of the present invention.

[0078] Figure 6 Schematic diagram of the vector and rotation mode of the Cordic algorithm in Example 1 of the present invention. DETAILED DESCRIPTION

[0079] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0080] Example 1:

[0081] See also Figures 1 to 3 The present invention provides an FPGA-based multi-channel amplitude and phase correction method and system for a radio frequency receiver. By incorporating a Hanning window function during sampling, this method avoids spectrum leakage and reduced correction accuracy when the number of sampling points is not an integer of the signal period. Furthermore, a frequency-domain equalization filter is designed, enabling the method to correct both narrowband and wideband signals. During amplitude correction, the bit widths of the square root and division modules are designed based on the amplitude difference threshold. During phase correction, a Cordic algorithm is used to establish a computational relationship between iteration rounds and the address values of the Cordic tangent table, reducing logic resource consumption and improving correction accuracy. Finally, correction data is transmitted back over Ethernet to ensure accurate correction.

[0082] The specific process of the FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiving end of the present invention is as follows:

[0083] In a large-scale MIMO system, the RF receiver receives the signal of each channel in real time, groups the received signals into groups, and each group includes a reference channel signal and a channel signal to be calibrated. Steps S2-S3 are then executed for each group to perform signal correction.

[0084] In a large-scale MIMO system, the RF receiver receives the signal of each channel in real time and sets any one of the channels as the reference channel signal A. a (t), the remaining M channels are the channel signals to be calibrated {B b1 (t), B b2 (t)…B bm (t)…B bM (t)}; Each channel signal to be calibrated B bm (t) and the reference channel signal A a (t) The phase and amplitude calibration operations are performed by combining the phase and amplitude calibration operations into one group and performing the steps S2 to S3 for each group.

[0085] In essence, each channel transmits the same signal, but due to losses, interference and errors in the transmission process, the signals received by different channels are different.

[0086] S2. Sampling each group of received signals, and preprocessing the sampled signals to obtain preprocessed sampled signals;

[0087] Collect the signal from the RF front end and process the sampled signal through the Hanning window function to obtain the discrete reference channel sampling signal and the sampling signal of the channel to be calibrated;

[0088] When sampling the signal, a Hanning window function is added to reduce the impact of reduced amplitude and phase correction accuracy caused by spectrum leakage.

[0089] Specifically, the signal of the RF front end is divided into the reference channel signal A a (t) and the channel signal B to be calibrated bm (t), where t represents continuous time.

[0090] For reference channel signal A a (t) is sampled to obtain a discrete reference channel signal , channel signal B to be calibrated bm (t) is sampled to obtain the discrete channel signal to be corrected ;

[0091] Discrete reference channel signal and the discrete channel signal to be corrected After passing through the Hanning window, the smoothed reference channel sampling signal A is obtained a (n) and the smoothed channel sampling signal B to be calibrated bm (n);

[0092] If {A a (n), B bm (n)} is less than 10% of its signal center frequency, then let {A a (n), B bm (n)} as the preprocessed sampled signal {A a (n), B b (n)} output;

[0093] If {A a (n), B bm (n)} is greater than or equal to 10% of its signal center frequency, then the frequency domain LMS filter is used to filter B bm (n) Perform filtering iterative operation to obtain the filtered channel signal to be calibrated B b (n), let {A a (n), B b (n)} is output as the preprocessed sampling signal.

[0094] Signal A a (n), Bbm (n), input into an improved frequency domain LMS filter, and perform frequency domain equalization on the signals of the reference channel and the channel to be corrected. The structural block diagram of the overall variable step size frequency domain LMS filter is as follows Figure 2 shown.

[0095] Using frequency domain LMS filter to filter B bm (n) Perform filtering iterative operation:

[0096] S21, smoothed reference channel signal A a (n) Perform fast Fourier transform (FFT) to obtain the reference channel signal M in the frequency domain a (f) For the smoothed channel signal B to be corrected bm (n) Perform fast Fourier transform to obtain the channel signal N to be corrected in the frequency domain b (f), f refers to the frequency component index obtained after FFT transformation, and its value range is 0 to N-1, where N is the length of the Hanning window in step S1, which is also the length of the discrete signal; let the coefficient of the frequency domain LMS filter be W(K), let K=0, and set the initial value of the coefficient of the frequency domain LMS filter to W(0);

[0097] S22, the output signal of the frequency domain LMS filter is L(K):

[0098] L(K)= N b (f)* W(K);

[0099] The reference channel signal M a (f) After delay, get M del (f), M del (f) and L(K) are used to calculate the error, and the error value e(K) between the reference channel signal and the channel signal to be calibrated is obtained:

[0100] e(K)= M del (f)-L(K);

[0101] S23. If the error value e(K) is greater than the set threshold and the maximum number of iterations has not been reached, the coefficients of the frequency domain LMS filter are updated:

[0102] W(K+1)= W(K)+µ(K)* e(K)* N b (f);

[0103] Where µ(K) is the iteration step size, µ(K)=kµ(K-1)+b*e 2 (K-1), k is the coefficient of dynamic adjustment in actual test, b is the adjustment factor, b=αµ(K-2)+ (1-α)*e 2 (K-2), α is the fine-tuning factor;

[0104] If the error value e(K) is less than the set threshold or reaches the maximum number of iterations, L(K) is subjected to inverse fast Fourier transform to obtain the filtered channel signal to be calibrated B b (n) .

[0105] S3. Construct an amplitude-phase correction model, calculate the phase correction factor and the amplitude correction factor based on the preprocessed sampled signal, perform iterative correction operation on the channel signal to be calibrated, and output the corrected signal;

[0106] S31, build an amplitude phase correction model, receive the pre-processed sampling signal {A a (n), B b (n)}, setting: the signal A of the reference channel after preprocessing a (n) The I-path signal and Q-path signal are I a (n), Q a (n), let the preprocessed signal B of the channel to be corrected be b (n) is the signal B of the channel to be calibrated during the first calibration b (n)1,B b (n)1's I-path signal and Q-path signal are I b (n)1, Q b (n)1;

[0107] S32. Calculate the amplitude correction factor for the sth correction : Using the principle of signal strength (RSSI), the amplitude ratio between the two channels is calculated to obtain the amplitude correction factor.

[0108] Assuming that the received baseband I and Q signals are expressed in complex form I+jQ, the formula for calculating the sample power of the current sample is: , according to the sampling value of S2, the average power of the reference channel during the sampling time is:

[0109] ;

[0110] The average power of the signal of the channel to be corrected within the same sampling time is:

[0111] ;

[0112] Among them, I b (n) s is the I signal of the channel to be corrected for the sth correction, Q b (n) s is the Q-channel signal of the channel to be corrected for the sth correction, N is the length of the Hanning window, and n is the current sampling point.

[0113] The power ratio between the sth calibration reference channel and the channel to be calibrated for:

[0114] ;

[0115] Amplitude correction factor for the sth correction :

[0116] ;

[0117] against Design a divider with limited bit width to reduce FPGA logic resource consumption. Set the bit width of the divisor and dividend of the divider. The bit width is determined by the size of the divisor and dividend. That is, the bit width of the dividend is:

[0118] ;

[0119] The divisor width is:

[0120] ;

[0121] The bit width of the quotient is: quotient = integer + decimal;

[0122] Among them, integer is the bit width of the integer part of the quotient, which is a set value and is generally taken as 8; decimal is the bit width of the decimal part of the quotient, as shown in the following formula:

[0123] ;

[0124] Amp is the set amplitude difference threshold, Amp res is the resolution of the amplitude difference threshold;

[0125] against The square root module sets its input bit width to match the bit width of the decimal and integer parts of the divider quotient, and sets the square root module output bit width to:

[0126] ;

[0127] Where root is the output bit width of the amplitude correction factor square root module.

[0128] S33. Calculate the phase correction factor for the sth correction: Calculate the phase difference using the cordic algorithm The angle value of , and then calculate the phase correction factor of the sth correction;

[0129] The reference channel signal A is calculated using fast Fourier transform a(n) and the channel signal B to be corrected for the sth correction bm (n) Tangent of the phase difference , use the cordic algorithm to calculate the phase difference The angle value of the sth correction is obtained by:

[0130] ;

[0131] Set the number of iterations of the Cordic algorithm to 16, and index the Cordic tangent table values incrementally. That is, the Cordic tangent table address value is no longer recalculated in each iteration, but is incremented based on the table address value of the previous iteration; for example, in the nth iteration, only a fixed address increment is needed based on the previous iteration.

[0132] S34, based on the amplitude correction factor and phase correction factor of the sth correction, correct the channel signal to be corrected to obtain the correction result B b (n) s+1 :

[0133] ;

[0134] Among them, I b (n) s+1 The I-channel signal in the correction result is also the I-channel signal of the channel to be corrected in the s+1th correction; Q b (n) s+1 The Q-channel signal in the correction result is also the Q-channel signal of the channel to be corrected in the (s+1)th correction.

[0135] If the amplitude correction factor or phase difference If the set threshold is not met, set s=s+1 and correct the result B b (n) s+1 Return to S32 to continue iterative calculation;

[0136] If the amplitude correction factor Phase difference If all meet the set threshold or reach the maximum number of iterations, the correction result B b (n) s+1 Output as the corrected signal.

[0137] See also Figure 3 The specific model of the FPGA chip used is XC7K325T, and the RF transceiver chip used is two AD9361s.

[0138] The specific test conditions are as follows: the four receiving channels are K0-K3, with K0 selected as the reference channel. For narrowband signals, the received signal type is QPSK, with a bandwidth of 1MHz, a center frequency of 200MHz, and a sampling rate of 122.88MHz. Before correction, the amplitude errors of K1-K3 relative to K0 are set to -4.32dB, 1.51dB, and 2.61dB; the phase errors are 116°, -57°, and 55°. After correction, the amplitude errors are 0.18dB, -0.19dB, and -0.26dB, respectively; and the phase errors are -0.882°, 0.427°, and -0.621°, respectively. The average amplitude error is 0.21dB, less than 0.5dB; the average phase error is 0.643°, less than 1°.

[0139] For a wideband signal, the bandwidth was set to 20 MHz, with all other parameters unchanged. The corrected amplitude errors were 0.15 dB, 0.36 dB, and -0.25 dB, respectively; the corrected phase errors were 1.652°, 0.927°, and -1.421°, respectively. The average amplitude error was 0.29 dB, less than 0.5 dB; the average phase error was 1.333°, less than 2°.

[0140] The present invention provides an FPGA-based RF receiving end multi-channel amplitude and phase correction method and system. The amplitude correction module is designed with a limited bit width divider and a square root module. Compared with a general amplitude correction module, the LUT (lookup table) resources are reduced by 57.8%.

[0141] The present invention provides an FPGA-based RF receiving end multi-channel amplitude and phase correction method and system. The Cordic algorithm designed for the phase correction module reduces LUT resources by 60.4% compared to the general Cordic algorithm implementation.

[0142] Example 2:

[0143] Based on Example 1:

[0144] See also Figure 6 In S33, the tangent value of the phase difference between the reference channel and the channel to be corrected is calculated.

[0145] Specifically, the reference channel signal A is calculated using the fast Fourier transform (FFT) a (n) and the channel signal to be corrected B b (n) The tangent of the phase difference (I / Q channel), denoted as .Will This angle is mapped into a two-dimensional coordinate space, where the vertex of the angle is the origin of the coordinates, one of the sides extends in the positive direction of the x-axis, and the coordinates of the end point of the other side are (x, y). It can be expressed as x / y.

[0146] Calculate the sine and cosine values corresponding to the tangent value of the phase difference between the two and the corresponding angle value.

[0147] Specifically, the known phase difference The tangent value of x / y is used. First, use the vector mode of cordic to calculate the specific size of the phase difference. Corresponding to the initial vector (x, y) in the two-dimensional coordinate space, let the initial vector (x, y) of the cordic algorithm be Figure 6 x0, y0 in the vector mode. Assume that the initial angle θ0 of the cordic algorithm is 0. The following is the iterative process, the number of iterations I, takes values from 0 to I-1; x i ,y i In the iterative process Corresponding to a vector in two-dimensional coordinate space.

[0148] (1) In each iteration, according to the current y i The sign of the value selects the direction of rotation.

[0149] (2) Calculate the rotation angle θ of this iteration i =arctan(2 -i ).

[0150] (3) Update the calculated angle, θ i+1 =(1-d i )θ i , where d i is the rotation factor of the i-th iteration process, and its value is based on y i The sign of y i <0 then d i =1, if y i >0 then d i =-1;

[0151] (4) Calculate the new coordinate point:

[0152] ;

[0153] The iterative termination condition of the above iterative calculation algorithm is that the calculation reaches the required round I, where I is 16. The final calculation result of θ is the angle of the phase difference. The specific size.

[0154] After obtaining the specific size of the phase difference, the obtained The specific size is input into the rotation mode of the cordic algorithm to calculate The sine and cosine of .

[0155] The x0 coordinate value of the initial point of the initial vector is calculated as follows, and the y0 coordinate value is 0.

[0156] ;

[0157] When the algorithm is initialized, the remaining rotation angle θ is set to the angle calculated by the above rotation mode. The following is the iterative process, j is the number of iterations, ranging from 0 to J-1; x j ,y j In the iterative process The corresponding cosine value and sine .

[0158] (1) In each iteration, according to the current residual angle θ j , select the direction of rotation.

[0159] (2) Calculate the rotation angle θ of this iteration j =arctan(2 -j ).

[0160] (3) Update the calculated angle, θ j+1 =(1-d j )θ j , where d j is the rotation factor of the jth round of iteration, and its value is based on y j The sign of y j <0 then d j =1, if y j >0 then d j =-1.

[0161] (4) Calculate the new coordinate point:

[0162] ;

[0163] The termination condition is the same as that of the vector mode, and the final x J ,y J Corresponding angles The cosine value of and sine , which is the phase correction factor, where j is the iteration round and the size of J is 16.

[0164] Example 3:

[0165] See also Figure 4, a RF receiving end multi-channel amplitude and phase correction system based on FPGA, the system is used to execute the aforementioned RF receiving end multi-channel amplitude and phase correction method based on FPGA, specifically including: a sampling grouping module, a preprocessing module, an amplitude and phase correction module, and a data integration module;

[0166] Sampling and grouping module: used in large-scale multiple-input multiple-output systems. The RF receiver receives the signal of each channel in real time and groups the received signals. Each group includes a reference channel signal and a channel signal to be calibrated. Signal correction is performed on a group-by-group basis.

[0167] Preprocessing module: used to sample each group of received signals, preprocess the sampled signals, and obtain preprocessed sampled signals;

[0168] Amplitude and phase correction module: used to build an amplitude and phase correction model. Based on the preprocessed sampling signal, it calculates the phase correction factor and amplitude correction factor, performs iterative correction operations on the channel signal to be calibrated, and outputs the corrected signal.

[0169] Data integration module: used to obtain M groups of corrected signals after all groups have been corrected, thus completing this round of signal correction.

[0170] Example 4:

[0171] See also Figure 5 A multi-channel amplitude and phase correction device for a radio frequency receiving end based on FPGA includes a memory and a processor, wherein the memory is used to store computer program code and transmit the computer program code to the processor; the processor is used to execute the aforementioned multi-channel amplitude and phase correction method for a radio frequency receiving end based on FPGA according to instructions in the computer program code.

[0172] Example 5:

[0173] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the aforementioned FPGA-based RF receiving end multi-channel amplitude and phase correction method.

Claims

1. A multi-channel amplitude and phase correction method for a radio frequency receiver based on FPGA, characterized by: The steps include: In a large-scale MIMO system, the RF receiver receives the signal of each channel in real time, groups the received signals into groups, and each group includes a reference channel signal and a channel signal to be calibrated. Steps S2-S3 are then executed for each group to perform signal correction. S2. Sampling each group of received signals, and preprocessing the sampled signals to obtain preprocessed sampled signals; Sample each group of received signals and preprocess the sampled signals: First, the Hanning window function is used to smooth and truncate the sampled signal to obtain the smoothed signal {A a (n), B bm (n)}; If {A a (n), B bm (n)} is less than 10% of its signal center frequency, then let {A a (n), B bm (n)} as the preprocessed sample signal {A a (n), B b (n)} output; If {A a (n), B bm (n)} is greater than or equal to 10% of its signal center frequency, then the frequency domain LMS filter is used to filter B bm (n) Perform filtering iterative operation to obtain the filtered channel signal to be calibrated B b (n), let {A a (n), B b (n)} is output as the pre-processed sampling signal; Using frequency domain LMS filter to filter B bm (n) Perform filtering iterative operation: S21, smoothed reference channel signal A a (n) Perform fast Fourier transform to obtain the reference channel signal M in the frequency domain a (f) For the smoothed channel signal B to be corrected bm (n) Perform fast Fourier transform to obtain the channel signal N to be corrected in the frequency domain b (f) Assume that the coefficient of the frequency domain LMS filter is W(K), let K = 0, and set the initial value of the coefficient of the frequency domain LMS filter to W(0); S22, the output signal of the frequency domain LMS filter is L(K): L(K)= N b (f)* W(K); The reference channel signal M a (f) After delay, get M del (f), M del (f) and L(K) are used to calculate the error, and the error value e(K) between the reference channel signal and the channel signal to be calibrated is obtained: e(K)= M del (f)-L(K); S23. If the error value e(K) is greater than the set threshold and the maximum number of iterations has not been reached, the coefficients of the frequency domain LMS filter are updated: W(K+1)= W(K)+µ(K)* e(K)* N b (f); Where µ(K) is the iteration step size, µ(K)=kµ(K-1)+b*e 2 (K-1), k is the coefficient of dynamic adjustment in actual test, b is the adjustment factor, b=αµ(K-2)+ (1-α)*e 2 (K-2), α is the fine-tuning factor; If the error value e(K) is less than the set threshold or reaches the maximum number of iterations, L(K) is subjected to inverse fast Fourier transform to obtain the filtered channel signal to be calibrated B b (n); S3. Construct an amplitude-phase correction model, calculate the phase correction factor and the amplitude correction factor based on the preprocessed sampled signal, perform iterative correction operation on the channel signal to be calibrated, and output the corrected signal; S4. After all groups have been calibrated, M groups of calibrated signals are obtained, and this round of signal calibration is completed.

2. The FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiving end according to claim 1, wherein: In the large-scale multi-input multi-output system, the RF receiving end receives the signal of each channel in real time and sets any one of the channels as the reference channel signal A. a (t), the remaining M channels are the channel signals to be calibrated { B b1 (t), B b2 (t)…B bm (t)…B bM (t)}; Each channel signal to be calibrated B bm (t) and the reference channel signal A a (t) The phase and amplitude calibration operations are performed by combining the phase and amplitude calibration operations into one group and performing the steps S2 to S3 for each group.

3. The FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiving end according to claim 1, wherein: The S3 includes: S31, build an amplitude phase correction model, receive the pre-processed sampling signal {A a (n), B b (n)}, setting: the signal A of the reference channel after preprocessing a (n) The I-path signal and Q-path signal are I a (n), Q a (n), let the preprocessed signal B of the channel to be corrected be b (n) is the signal B of the channel to be calibrated during the first calibration b (n)1,B b (n)1's I-path signal and Q-path signal are I b (n)1, Q b (n)1; S32. Calculate the amplitude correction factor for the sth correction : S33. Calculate the phase correction factor for the sth correction: Calculate the phase difference using the cordic algorithm The angle value of , and then calculate the phase correction factor of the sth correction; S34, based on the amplitude correction factor and phase correction factor of the sth correction, correct the channel signal to be corrected to obtain the correction result B b (n) s+1 : If the amplitude correction factor or phase difference If the set threshold is not met, set s=s+1 and correct the result B b (n) s+1 Return to S32 to continue iterative calculation; If the amplitude correction factor Phase difference If all meet the set threshold or reach the maximum number of iterations, the correction result B b (n) s+1 Output as the corrected signal.

4. The FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiving end according to claim 3, wherein: In the step S32, the amplitude correction factor of the sth correction is calculated. : ； in, is the power ratio between the reference channel signal in the s-th calibration and the channel signal to be corrected in the s-th calibration; ； Among them, I b (n) s is the I signal of the channel to be corrected for the sth correction, Q b (n) s is the Q-channel signal of the channel to be corrected for the sth time, N is the length of the Hanning window, and n is the current sampling point.

5. The FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiving end according to claim 4, characterized in that: against Design a divider with limited bit width, set the bit width of the divisor and dividend of the divider, and the bit width of the dividend is: ； The divisor width is: ； The bit width of the quotient is: quotient = integer + decimal; Among them, integer is the bit width of the integer part of the quotient, which is the set value, and decimal is the bit width of the decimal part of the quotient, as shown in the following formula: ； Amp is the set amplitude difference threshold, Amp res is the resolution of the amplitude difference threshold; against The square root module sets its input bit width to match the bit width of the decimal and integer parts of the divider quotient, and sets the square root module output bit width to: ； Where root is the output bit width of the amplitude correction factor square root module.

6. The FPGA-based multi-channel amplitude and phase correction method for a radio frequency receiving end according to claim 3, characterized in that: In S33, the phase correction factor of the s-th correction is calculated: The reference channel signal A is calculated using fast Fourier transform a (n) and the channel signal B to be corrected for the sth correction bm (n) Tangent of the phase difference , use the cordic algorithm to calculate the phase difference The angle value of the sth correction is obtained by: ； Set the number of iterations of the cordic algorithm and index the cordic tangent table value in an incremental manner. That is, the cordic tangent table address value is no longer recalculated in each iteration, but is incremented according to the table address value of the previous iteration; In S34, the channel signal to be corrected is corrected based on the amplitude correction factor and phase correction factor corrected for the sth time, and a correction result is obtained: ； Among them, I b (n) s+1 The I-channel signal in the correction result is also the I-channel signal of the channel to be corrected in the s+1th correction; Q b (n) s+1 The Q-channel signal in the correction result is also the Q-channel signal of the channel to be corrected in the (s+1)th correction.

7. A multi-channel amplitude and phase correction system for RF receiver based on FPGA, characterized in that: The system is used to execute the FPGA-based RF receiving end multi-channel amplitude and phase correction method according to any one of claims 1 to 6, specifically comprising: a sampling grouping module, a preprocessing module, an amplitude and phase correction module, and a data integration module; Sampling and grouping module: used in large-scale multiple-input multiple-output systems. The RF receiver receives the signal of each channel in real time and groups the received signals. Each group includes a reference channel signal and a channel signal to be calibrated. Signal correction is performed on a group-by-group basis. Preprocessing module: samples each group of received signals, preprocesses the sampled signals, and obtains preprocessed sampled signals; Amplitude and phase correction module: used to build an amplitude and phase correction model. Based on the preprocessed sampling signal, it calculates the phase correction factor and amplitude correction factor, performs iterative correction operations on the channel signal to be calibrated, and outputs the corrected signal. Data integration module: used to obtain M groups of corrected signals after all groups have been corrected, thus completing this round of signal correction.

8. A multi-channel amplitude and phase correction device for a radio frequency receiving end based on FPGA, characterized in that: comprising a memory and a processor, wherein the memory is configured to store computer program code and transmit the computer program code to the processor; The processor is configured to execute the FPGA-based RF receiving end multi-channel amplitude and phase correction method according to any one of claims 1 to 6 according to the instructions in the computer program code.

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