A method and apparatus for implementing an EtherCAT master station system without an operating system

Abstract

This invention relates to a method and apparatus for implementing an EtherCAT master system without an operating system. The method includes: adapting the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master by using byte order processing based on bitmasks and a phased shift strategy, and EtherCAT frame transmission and reception control based on circular buffer index management; adapting the SOEM protocol stack to the operating system abstraction layer of the EtherCAT master by using non-real-time task priority scheduling based on hardware timers, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring; and adapting the EtherCAT master application layer through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and the periodic position mode of slave stations. This invention achieves an operating system-free EtherCAT master system and microsecond-level communication jitter by optimizing and adapting the SOEM protocol stack.

Description

Technical Field

[0001] This invention belongs to the field of industrial internet technology, specifically relating to a method and apparatus for implementing an EtherCAT master station system without an operating system. Background Technology

[0002] With the rapid development of Industry 4.0 and smart manufacturing technologies, industrial automation systems are placing higher demands on real-time communication performance. Industrial Ethernet technology, as a next-generation industrial communication solution, significantly improves communication performance by introducing Ethernet technology into the industrial control field, while maintaining Ethernet's low-cost advantage. Among them, the EtherCAT (Ethernet for Control Automation Technology) protocol, with its unique technological advantages, has become an important solution in the industrial Ethernet field. This protocol adopts a master-slave communication architecture, supports various network topologies such as linear, tree, and star topologies, and its innovative "fly-read / fly-write" data processing mechanism and distributed clock synchronization technology can achieve microsecond-level communication cycles and nanosecond-level synchronization accuracy, fully meeting the needs of high real-time applications such as industrial motion control.

[0003] The main problems with existing EtherCAT master station technology can be summarized as follows: 1. High cost and technical limitations of commercial solutions: Commercial EtherCAT master station systems, represented by TwinCAT, have expensive dedicated controllers and supporting software, and their core technologies are controlled by foreign manufacturers, which is not conducive to their promotion and application in key industrial fields. 2. Insufficient real-time performance of open-source solutions: Open-source EtherCAT master station solutions based on general-purpose operating systems have inherent defects in task scheduling, interrupt response, and memory management due to the non-real-time characteristics of Windows / Linux systems. This results in large communication cycle jitter, making it difficult to meet the real-time requirements of high-precision industrial control scenarios. Summary of the Invention

[0004] To implement an EtherCAT master system without an operating system, the first aspect of this invention provides a method for implementing an EtherCAT master system without an operating system, comprising: adapting the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master by byte order processing based on bitmasking and phased shifting strategies, and EtherCAT frame transmission and reception control based on circular buffer index management; adapting the SOEM protocol stack to the operating system abstraction layer of the EtherCAT master by non-real-time task priority scheduling based on hardware timers, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring; and adapting the application layer of the EtherCAT master by network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and the periodic position mode of the slave station.

[0005] In some embodiments of the present invention, the byte order processing based on bitmasks and a phased shift strategy includes: for 16-bit data conversion: using a combination of bitmasks and shift operations, performing a bitwise AND operation on the original data and 0xFF00, then shifting it right by 8 bits, and merging the results through an OR operation; for 32-bit data conversion: performing a 24 / 16 / 8-bit phased shift combination; for 64-bit data conversion: splitting the 64-bit data into two 32-bit data, performing a 32-bit data conversion on each 32-bit data, and then merging the conversion results.

[0006] In some embodiments of the present invention, the non-real-time task priority scheduling process includes: dividing the master station tasks into high real-time periodic communication tasks and event-driven non-real-time tasks; the periodic communication tasks are used for real-time data exchange and precise motion control, while the non-real-time tasks are used for instruction calculation, status monitoring, and fault handling.

[0007] In some embodiments of the present invention, the blocking communication synchronization mechanism combined with timer timeout monitoring includes: based on the blocking communication mechanism, the master station immediately enters a receiving waiting state after sending a data frame; while continuously detecting the return frame, the waiting time is monitored, and the waiting is terminated when the waiting exceeds a preset threshold.

[0008] In some embodiments of the present invention, the memory management mechanism based on CoE standard mapping includes: dividing a fixed-bit byte space in the slave station memory, the byte space being used to store the slave station's process data; constructing mapping configuration instructions based on the CoE protocol standard; configuring the slave station's PDO mapping table via mailbox communication and establishing a mapping relationship between the master station's memory space and the slave station's memory space; determining whether the slave station device is in a safe operating state and verifying whether the mapping relationship is correct.

[0009] In some embodiments of the present invention, the slave station's periodic position mode includes: setting the interpolation period of the position command; sending a new position command to the servo driver every interpolation period; and ensuring that the period of the automatic reload register is consistent with the interpolation period.

[0010] A second aspect of the present invention provides an implementation device for an EtherCAT master station system without an operating system, comprising: a first implementation module, used to adapt the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station through byte order processing based on bitmasks and phased shift strategies, and EtherCAT frame transmission and reception control based on circular buffer index management; a second implementation module, used to adapt the SOEM protocol stack to the operating system abstraction layer of the EtherCAT master station through non-real-time task priority scheduling processing based on hardware timers, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring; and a third implementation module, used to adapt the EtherCAT master station application layer through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and the periodic position mode of the slave station.

[0011] A third aspect of the present invention provides an electronic device comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the operating system-based EtherCAT master station system implementation method provided in the first aspect of the present invention.

[0012] In a fourth aspect, the present invention provides a computer-readable medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the EtherCAT master station system implementation method based on an operating system-free system provided in the first aspect of the present invention.

[0013] The beneficial effects of this invention are: by adopting an open-source protocol stack to implement complete EtherCAT master station functionality, it breaks through the technical barriers of foreign manufacturers in the field of high-end industrial control, achieving independent control of core technologies. Compared with imported solutions, this solution can reduce system costs and provides an economical and feasible technical path for the domestic substitution of industrial control equipment.

[0014] This innovative approach employs an operating system-free architecture, reducing communication jitter caused by factors such as task scheduling, interrupt response, and memory management in traditional operating systems. This achieves high real-time performance and low jitter in EtherCAT communication. Actual testing shows that the communication cycle jitter is controlled within 1μs, meeting the stringent requirements of high-precision industrial control scenarios.

[0015] A precise periodic control method based on a hardware timer is proposed, which achieves microsecond-level communication cycle accuracy by directly manipulating hardware registers, significantly improving the timing determinism of the system. This method not only ensures the strict timeliness of the communication cycle but also provides a reliable time reference for multi-axis synchronous control.

[0016] A flexible and efficient slave network management and control mechanism is designed to support the application needs of various industrial control scenarios. This solution can be widely used in high-precision control fields such as motion control, industrial robots, and CNC machine tools, and has good market prospects and promotional value.

[0017] The implementation of this invention will not only enhance my country's independent innovation capabilities in the field of industrial communication protocols, but also provide reliable technical support for the localization of industrial control equipment, which will strongly promote technological progress and industrial upgrading in my country's industrial automation field. Attached Figure Description

[0018] Figure 1 This is a basic flowchart illustrating the implementation method of an EtherCAT master station system without an operating system in some embodiments of the present invention.

[0019] Figure 2 This is a system architecture design diagram of an EtherCAT master station based on an operating system without an operating system, according to some embodiments of the present invention;

[0020] Figure 3 This is a schematic diagram of the network driver logic structure in some embodiments of the present invention;

[0021] Figure 4 This is a block diagram of Ethernet driver logic in some embodiments of the present invention;

[0022] Figure 5 This is a design diagram of a periodic task in some embodiments of the present invention;

[0023] Figure 6 This is a schematic diagram of a linear topology in some embodiments of the present invention;

[0024] Figure 7 This is an application flow in some embodiments of the present invention;

[0025] Figure 8 This is a schematic diagram of the memory space mapping between the master station and the slave station in some embodiments of the present invention;

[0026] Figure 9 This is a schematic diagram illustrating the communication cycle and jitter verification in some embodiments of the present invention;

[0027] Figure 10This is a schematic diagram of the structure of an EtherCAT master station system implementation device based on an operating system without an operating system in some embodiments of the present invention;

[0028] Figure 11 This is a schematic diagram of the structure of an electronic device in some embodiments of the present invention. Detailed Implementation

[0029] The principles and features of the present invention are described below with reference to the accompanying drawings. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0030] refer to Figure 1 and Figure 2 In a first aspect, the present invention provides a method for implementing an EtherCAT master system without an operating system, comprising: S100. Adapting the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master by byte order processing based on bitmasking and phased shifting strategies, and EtherCAT frame transmission and reception control based on circular buffer index management; S200. Adapting the SOEM protocol stack to the operating system abstraction layer of the EtherCAT master by non-real-time task priority scheduling based on hardware timers, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring; S300. Adapting the application layer of the EtherCAT master by network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and the periodic position mode of the slave station.

[0031] It should be noted that in this embodiment, the mainstream domestic embedded platform—Rockchip RK3568—is selected as the hardware platform. Its multi-core CPU and Ethernet driver (Media Access Controller, MAC) hardware resources are fully utilized to achieve efficient protocol processing and data transmission, thus realizing the EtherCAT master station. As the core development framework, the system uses the SOEM open-source protocol stack, which has excellent cross-platform compatibility. It is compatible with multiple operating systems such as Windows, Linux, and INtime, and also supports the implementation of complete EtherCAT communication functions on embedded hardware platforms without an operating system.

[0032] Specifically, this invention focuses on the following tasks: First, for the RK3568 hardware platform, it implements hardware abstraction layer (OSHW) adaptation, including the development of core functions such as network driver, byte order conversion, and direct memory access (DMA) transfer, ensuring efficient transmission and reception of EtherCAT frames; Second, it implements operating system abstraction layer (OSAL) in an operating system-less environment, providing high-precision time management and task scheduling functions through precise timer management and interrupt control; Finally, it constructs a complete EtherCAT master station control framework, develops application layer programs, and implements specific control functions such as network scanning, data interaction, real-time monitoring, and Cyclic Synchronous Position Mode (CSP).

[0033] In step S100 of some embodiments of the present invention, the byte order processing based on bitmask and staged shift strategy includes: For 16-bit data conversion: S101. Using a combination of bitmask and shift operation, the original data is ANDed with 0xFF00 and then shifted right by 8 bits, and the result is merged by OR operation; S102. For 32-bit data conversion: Perform a 24 / 16 / 8-bit staged shift combination; For 64-bit data conversion: S103. Split the 64-bit data into two 32-bit data, perform 32-bit data conversion on each 32-bit data, and then merge the conversion results.

[0034] Specifically, the Hardware Abstraction Layer (HAL), serving as the interface between the SOEM protocol stack and the underlying hardware, is primarily responsible for implementing network communication services. During the protocol stack porting on the RK3568 platform, OSHW adaptation is a core task, comprising two core functional modules: a byte order processing module responsible for byte order conversion between the master station and the network; and a network driver module used to manage underlying network communication, including Ethernet DMA transmission control and EtherCAT data frame transmission and reception processing.

[0035] The byte order processing module provides crucial conversion services. Because the RK3568 platform uses little-endian byte order storage (where the least significant byte is stored at a lower memory address), while network transmission uses big-endian byte order (where the least significant byte is stored at a higher memory address), this difference necessitates that the master station perform byte order conversion during data transmission. Therefore, during the porting of the hardware abstraction layer, it is essential to implement the byte order conversion-related API interfaces to ensure correct data conversion between different storage modes.

[0036] For the conversion of 16-bit data, a method combining bit mask and shift operation is used. The original data is ANDed with 0xFF00 and then shifted right by 8 bits. At the same time, the original data is ANDed with 0x00FF and then shifted left by 8 bits. Finally, the results are combined by OR operation.

[0037] For the conversion of 32-bit data, a staged shift strategy is adopted: 24-bit, 16-bit, and 8-bit shift operations are performed sequentially, and the results of each stage are combined by OR operation.

[0038] The conversion of 64-bit data extends this method by using segmented processing, dividing the data into high 32 bits and low 32 bits, converting them separately, and then merging them. Specifically, this includes: little-endian to big-endian conversion, converting local little-endian byte order data to network big-endian byte order, for example, 0x12345678 → 0x78563412; and big-endian to little-endian conversion, converting received network big-endian byte order data to local little-endian byte order, for example, 0x78563412 → 0x12345678.

[0039] refer to Figure 3 and Figure 4 In step S100 of some embodiments of the present invention, the SOEM protocol stack is adapted to the hardware abstraction layer of the EtherCAT master station based on the EtherCAT frame transmission and reception control managed by the ring buffer index.

[0040] Specifically, the network driver module, as a core component of OSHW, focuses on the implementation of physical layer communication services and does not involve the protocol parsing and encapsulation processing of EtherCAT frames. For example... Figure 2 As shown, the network driver module needs to implement a buffer management mechanism to configure the capacity of the send and receive buffers. When performing a frame transmission operation, the system first allocates a free index (idx) in the send buffer, and after loading the frame data, it transmits it through the physical layer via the MAC controller. The receiving end needs to achieve precise mapping of the receive buffer through the same index to ensure the timing consistency between the sent and received frames.

[0041] Furthermore, the network driver module interacts directly with the underlying network data transmission module to build a complete physical layer communication channel, enabling the sending and receiving of EtherCAT frames. It abstracts four interfaces that need to provide functions for: initializing the network port, closing the network port, sending EtherCAT frames, and receiving EtherCAT frames.

[0042] Figure 3The logic block diagram of the Ethernet controller on the RK3568 hardware platform is described. In this embodiment, the network port initialization implementation steps are as follows: Pin initialization: Initialize relevant pins according to standard transmission protocols (MII / RMII / GMII / RGMII), configure the multiplexing function of IO pins, and ensure the correct transmission of physical layer signals; Physical layer (Ethernet Physical Layer, PHY) chip configuration: Configure the transmission mode and rate of the external PHY chip (e.g., 10 / 100 / 1000Mbps), complete the initialization of the address mapping between the control register and status register of the PHY chip, and establish a stable underlying communication link; MAC initialization: Set the MAC clock and interface mode, configure the MAC address, and ensure that the MAC layer can correctly identify and process data frames; First-in-First queue (FIFO) Out (FIFO) initialization: Initialize the MAC's FIFO memory, set the capacity of the send and receive buffers, and clear the buffers to ensure that the memory area is in a known and clean state before use; DMA configuration: Build a receive circular descriptor queue, define the source address, destination address, transmission direction and data length of the data, configure the physical address mapping of the head and tail pointer registers, activate the circular addressing mechanism of the descriptor queue, and establish a zero-copy transmission channel between the MAC and system memory.

[0043] The implementation steps for the network port shutdown function are as follows: Disable MAC: Turn off the MAC clock gating signal, set the transmit enable / disable bit and receive enable / disable bit in the MAC control register, trigger the forced stop mechanism of the transmit and receive engines, and ensure the complete shutdown of the physical layer data frame transmission channel; DMA resource reclamation: Clear the address mapping of the current descriptor pointer register, reset the descriptor head and tail pointer registers to the initial state, and release the memory resources of the ring buffer; Memory reclamation: Reclaim the memory space occupied by the receive ring descriptor queue and transmit ring descriptor queue associated with the MAC, clear the relevant data structures, and release the occupied system resources; Hardware register reset: Write 0x00000001 to the MAC software reset register, start the synchronous reset sequence of the MAC internal state machine, write the hardware reset instruction (Bit15=1) to the basic control register of the PHY chip, and restore the hardware resources to the default state; Pin reset: Reset the multiplexed IO pins, restore the default configuration, and ensure that the hardware resources can be reused by other modules.

[0044] The implementation steps of the EtherCAT frame transmission function are as follows: Data acquisition: Automatically obtain the start address and length field of the EtherCAT frame to be transmitted from the transmit ring descriptor queue in system memory to ensure the integrity of the data frame; DMA copy: Activate the DMA chained transmission engine to write the data frame directly from the zero-copy ring buffer to the MAC transmit FIFO to ensure the efficiency of data transmission; Physical layer transmission: Call the MAC layer frame transmission function in the HAL library of RK3568, set the transmit enable bit of the MAC control register, start the MII / RMII / GMII / RGMII interface clock synchronization, and transmit the data frame from the transmit FIFO to the external PHY to complete the physical layer frame transmission.

[0045] The implementation steps of the EtherCAT frame reception function are as follows: Frame reception: Call the MAC layer frame reception function in the HAL library of RK3568 to receive data frames from the external PHY and store them in the receive FIFO; Data integrity verification: Automatically discard erroneous frames (CRC check failure / oversized frames / fragmented frames) through receive filtering, obtain the start address and data length of the correct data frames in the receive FIFO, and ensure the integrity of the data frames; DMA copy: Trigger the data transfer request of the DMA controller, update the status bits of the receive descriptor to mark the valid data area, and copy the data frame from the receive FIFO to the system memory for further processing by the upper-layer protocol stack. Through the above steps, the hardware abstraction layer implements efficient network communication services, providing stable and reliable underlying support for the EtherCAT master station. This design not only ensures efficient transmission of data frames, but also significantly reduces the CPU load and improves the overall system performance through the optimized use of DMA and FIFO.

[0046] refer to Figure 5 and Figure 6 In step S200 of some embodiments of the present invention, the SOEM protocol stack is adapted to the EtherCAT master station operating system abstraction layer by using non-real-time task priority scheduling based on hardware timers, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring. Specifically, the operating system abstraction layer defines a unified interface specification, including basic data types, time management structures, and core functional interfaces such as time / timer operation APIs and thread control APIs. The main task of the operating system abstraction layer is to provide an operating system-independent abstract interface for the upper-layer protocol stack, ensuring the portability and real-time performance of the system on different platforms.

[0047] Time and timer-related interfaces are core components for implementing EtherCAT communication. Because SOEM uses a blocking communication mechanism, the master station immediately enters a receive waiting state after sending a data frame, typically completing frame reception within microseconds. To ensure communication reliability, the system implements a timeout control mechanism, which monitors the waiting time while continuously detecting returned frames, and immediately terminates the waiting when a preset threshold is exceeded. This mechanism relies on a precise time management API. Furthermore, EtherCAT's distributed clock synchronization function also requires accurate system time support.

[0048] Therefore, this embodiment uses the 32-bit general-purpose timer / counter TIMER4 of the RK3568 to implement the system time management function. The timer frequency is set to 1MHz, that is, the timing period is 1 microsecond, and the maximum count value of the timer / counter is 4294967295, which means that the timer will return to zero every 4295 seconds (approximately 71.6 minutes). This configuration fully meets the high-precision time management requirements of EtherCAT communication.

[0049] Unlike time management APIs, thread-related APIs are optional implementation components. This invention, based on the RK3568 platform, divides the main station task into high real-time periodic communication tasks and event-driven non-real-time tasks, employing a task management mechanism without an operating system architecture. Periodic communication tasks are primarily responsible for real-time data exchange and precise motion control, while non-real-time tasks focus on instruction calculation, status monitoring, and fault handling. To address this task division characteristic, this embodiment integrates non-real-time tasks into the main event loop for unified management, avoiding the system overhead of multi-task scheduling. This design ensures that there is no task scheduling or context switching other than periodic communication during EtherCAT communication, achieving exclusive access to hardware resources and thus achieving the performance goals of high real-time performance and low jitter.

[0050] It should be noted that, to adapt to operating environments without an operating system, this study has made targeted optimizations to the protocol stack: Streamlined thread management mechanism: Given the system's non-multithreaded architecture, thread management components related to the POSIX Thread specification, including core functions such as thread creation, destruction, and synchronization, have been removed. Concurrency control mechanisms such as mutexes and semaphores have also been simplified, achieving a lightweight design for the protocol stack. Optimized task communication architecture: The original thread calling mechanism has been restructured at the architectural level, using atomic event flag groups to replace the traditional message queue communication mode, ensuring that the system can still maintain efficient inter-task communication and task scheduling even after removing thread management functions. High-precision periodic task control: A 32-bit programmable timer / counter TIMER5 is used to manage periodic communication tasks. The timer frequency is set to 24MHz, i.e., the timing period is 41.67 nanoseconds. An automatic reload register is configured to support dynamic adjustment of the load value, achieving a programmable period of 50μs-10ms. Furthermore, in high real-time periodic communication tasks, this disclosure designs an interrupt-masking-based exclusive access mechanism to shield unnecessary interrupts during the execution of critical communication tasks, ensuring the atomicity and real-time response capability of core operations and effectively avoiding timing jitter caused by task switching.

[0051] Understandably, after completing the hardware abstraction of the SOEM protocol stack and the operating system abstraction on the RK3568 hardware platform, the next step is to develop the EtherCAT master application layer program to implement specific control functions. The application layer is the core part of the EtherCAT master system, responsible for data interaction with slave devices and executing corresponding control logic.

[0052] In step S300 of some embodiments of the present invention, network scanning and communication parameter configuration includes: using an RK3568 development board as the EtherCAT master station, and selecting two sets of TSVB-EtherCAT servo drives and their matching Huada servo motors manufactured by Wuhan Jiutong Intelligent Technology Co., Ltd. as slave devices. Figure 5 As shown, the system adopts a linear topology, with two EtherCAT servo drives connected in series via a network cable. The first drive, directly connected to the master station, is slave 1, and the second drive is slave 2. All drives operate in Cyclic Synchronous Position Mode (CSP) to verify the master station's EtherCAT communication functionality and performance. The EtherCAT master station application layer program needs to implement network scanning and configuration, data interaction management, and execution control logic. The application layer program flowchart is shown below. Figure 7 As shown, the specific implementation steps are as follows:

[0053] After the master station starts up, it first scans the EtherCAT network to identify connected slave devices and initializes their configuration parameters. This process includes: network topology discovery and device identification: the master station sends an ETG.1000 standard topology discovery broadcast frame, captures all slave response frames, resolves the device physical addresses, and assigns a logical address to each slave; parameter initialization: based on the type of slave device, the master station initializes the slave configuration registers via the mailbox communication protocol, initializing its operating parameters (such as communication cycle, operating mode, etc.); status check: ensuring that all slave devices are in a pre-operational state, preparing for subsequent data interaction.

[0054] refer to Figure 7 and Figure 8 In step S300 of some embodiments of the present invention, the memory management mechanism based on CoE standard mapping includes: S301. Dividing a fixed-bit byte space in the slave station memory, the byte space being used to store the slave station's process data; S302. Constructing mapping configuration instructions based on the CoE protocol standard; configuring the slave station's PDO mapping table through mailbox communication, and establishing a mapping relationship between the master station memory space and the slave station memory space; S303. Determining whether the slave station device is in a safe operating state, and verifying whether the mapping relationship is correct.

[0055] Specifically, after completing the network scan, it is necessary to perform process data object (PDO) mapping on the slave station to establish a mapping relationship between the master station's memory space and the slave station's memory space. For example... Figure 7 As shown, a 64-byte memory space is allocated in the master station, and the slave station process data structure is partitioned within it. The specific steps, using CoE (CANopen over EtherCAT) standard mapping configuration instructions, include: Memory allocation: Allocating 64 bytes of space in the master station's memory to store the slave station's process data; PDO mapping: Constructing mapping configuration instructions conforming to the CoE protocol standard, configuring the slave station's PDO mapping table via mailbox communication, and establishing the mapping relationship between the master station's memory space and the slave station's memory space.

[0056] Mapping verification: Ensure all slave devices are in a safe-operational state and verify that the mapping relationship is correct. If an abnormality is found, the program will exit abnormally; otherwise, continue to execute subsequent operations.

[0057] In step S300 of some embodiments of the present invention, the periodic position mode of the slave station includes: setting the interpolation period of the position command; sending a new position command to the servo driver every interpolation period; and setting the operating mode of the slave device to periodic synchronous position mode after the mapping relationship verification is successful. In this mode, the master station needs to send a new position command to the servo driver every interpolation period, so that the motor runs to the specified position. The specific implementation steps are as follows:

[0058] Interpolation period setting: The choice of interpolation period is related to the processing capability of the master station. The shorter the interpolation period, the higher the position control accuracy. In this embodiment, a master station implementation scheme without an operating system is used. There is no task scheduling or context switching during EtherCAT communication, enabling exclusive access to hardware resources and thus supporting shorter interpolation period settings. Specifically, compared to the conventional 1ms, 500μs, or 200μs periods, this embodiment selects 100μs as the interpolation period.

[0059] Timer configuration: Configure the auto-reload register of the programmable timer / counter TIMER5, and ensure that the interrupt period is consistent with the set interpolation period to ensure accurate triggering of the interpolation task;

[0060] Interrupt Service Routine: In the timer interrupt service routine, the master station performs cycle data exchange: writing the new cycle instruction position data to the driver, and simultaneously reading the actual position data of the previous cycle, completing the synchronous update of process data. This ensures that the cycle of the automatic reload register remains consistent with the interpolation cycle.

[0061] refer to Figure 9 To evaluate the communication jitter performance of the EtherCAT master station scheme proposed in this invention, under test conditions with an interpolation period set to 100μs, an analysis method combining General Purpose Input / Output (GPIO) level toggling and oscilloscope waveform capture was adopted. The specific implementation steps are as follows: Timing Marking Strategy: GPIO pin level toggling operations were set at three key nodes in the periodic data processing (triggered before data transmission, triggered after data transmission / reception, and triggered after data reception) to construct a complete communication process timing marking chain. Test System Configuration: A hardware platform based on an RK3568 multi-core processor was used. A precision clock synchronization module ensured strict timing alignment between the GPIO trigger signal and the EtherCAT communication task. A 4-channel digital oscilloscope (sampling rate ≥2GS / s) was used for waveform acquisition and time analysis. Jitter Quantization Analysis: (The text continues with further details on jitter quantization analysis.) Figure 9As shown, statistical analysis was performed on 1000 consecutive cycles of waveform data captured by an oscilloscope to calculate the root mean square value of the time difference and the maximum deviation value of each trigger signal within adjacent cycles. Experimental data shows that, under a 100μs interpolation period, the jitter of the periodic data read / write operation implemented by this scheme is effectively controlled within ±1μs.

[0062] This embodiment demonstrates the design and implementation of an EtherCAT master system based on an operating system-free architecture by developing an EtherCAT master application, and verifies its communication and control performance in periodic synchronous position mode. This method not only implements EtherCAT master functionality on an operating system-free platform, but also provides a high-real-time, low-jitter EtherCAT master solution for the industrial automation field.

[0063] This invention proposes a design and implementation method for an EtherCAT master station based on an operating system-free platform. Compared to EtherCAT masters based on non-real-time operating systems such as Windows / Linux, this method offers shorter communication frame cycles and higher system stability. This high deterministic communication performance is primarily attributed to the operating system-free architecture, which reduces the interference of non-real-time factors such as task scheduling, context switching, and memory management on communication performance. Through precise control of hardware timers and an optimized protocol stack, the system achieves a communication cycle of 100μs, suppressing communication jitter to within ±1μs. This high real-time performance and low jitter provides reliable technical support for high-precision control applications such as precision motion control and multi-axis synchronization in industrial automation scenarios, meeting the stringent requirements of high reliability and high real-time performance in modern industrial control.

[0064] Example 2

[0065] refer to Figure 10 In a second aspect, the present invention provides an implementation device for an EtherCAT master station system without an operating system, comprising: a first implementation module, used to adapt the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station through byte order processing based on bitmasks and phased shift strategies, and EtherCAT frame transmission and reception control based on circular buffer index management; a second implementation module, used to adapt the SOEM protocol stack to the operating system abstraction layer of the EtherCAT master station through non-real-time task priority scheduling processing based on hardware timers, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring; and a third implementation module, used to adapt the EtherCAT master station application layer through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and the periodic position mode of the slave station.

[0066] Furthermore, the third implementation module includes: a partitioning unit, used to partition a fixed-bit byte space in the slave station's memory, the byte space being used to store the slave station's process data; a mapping unit, used to construct mapping configuration instructions based on the CoE protocol standard; configure the slave station's PDO mapping table via mailbox communication, and establish a mapping relationship between the master station's memory space and the slave station's memory space; and a determination unit, used to determine whether the slave station device is in a safe operating state, and to verify whether the mapping relationship is correct.

[0067] Example 3

[0068] refer to Figure 11 In a third aspect, the present invention provides an electronic device comprising: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the operating system-based EtherCAT master station system implementation method of the first aspect of the present invention.

[0069] Electronic device 500 may include a processing unit (e.g., a central processing unit, a graphics processing unit, etc.) 501, which can perform various appropriate actions and processes according to a program stored in read-only memory (ROM) 502 or a program loaded from storage device 508 into random access memory (RAM) 503. The RAM 503 also stores various programs and data required for the operation of electronic device 500. The processing unit 501, ROM 502, and RAM 503 are interconnected via bus 504. An input / output (I / O) interface 505 is also connected to bus 504.

[0070] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 508 including, for example, hard disks; and communication devices 509. Communication device 509 allows electronic device 500 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 11 An electronic device 500 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively. Figure 11 Each box shown can represent a device or multiple devices as needed.

[0071] Specifically, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 509, or installed from a storage device 508, or installed from a ROM 502. When the computer program is executed by a processing device 501, it performs the functions defined in the methods of embodiments of this disclosure. It should be noted that the computer-readable medium described in embodiments of this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of computer-readable storage media may include, but are not limited to: electrical connections having one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. Program code contained on a computer-readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0072] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device. The aforementioned computer-readable medium carries one or more computer programs, which, when executed by the electronic device, cause the electronic device to:

[0073] Computer program code for performing the operations of embodiments of this disclosure can be written in one or more programming languages ​​or a combination thereof. Programming languages ​​include object-oriented programming languages—such as Java, Smalltalk, C++, and Python—and conventional procedural programming languages—such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0074] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for implementing an EtherCAT master station system without an operating system, characterized in that, include: By using byte order processing based on bitmasks and a phased shift strategy, and EtherCAT frame transmission and reception control based on circular buffer index management, the SOEM protocol stack is adapted to the hardware abstraction layer of the EtherCAT master station. Based on non-real-time task priority scheduling and processing using hardware timers, a single-threaded event-driven main loop, and a blocking communication synchronization mechanism combined with timer timeout monitoring, the SOEM protocol stack is adapted to the EtherCAT master station operating system abstraction layer. Through network scanning and communication parameter configuration, a memory management mechanism based on CoE standard mapping, and the periodic location mode of the slave station, the adaptation of the EtherCAT master station application layer is achieved.

2. The method for implementing an EtherCAT master station system without an operating system according to claim 1, wherein the byte order processing based on bitmasks and a staged shift strategy includes: For 16-bit data conversion: a combination of bit mask and shift operation is used to perform a bitwise AND operation on the original data with 0xFF00, then shift it right by 8 bits, and finally combine the results through an OR operation. For 32-bit data conversion: perform a 24 / 16 / 8-bit phased shift combination; For 64-bit data conversion: split the 64-bit data into two 32-bit data, perform 32-bit data conversion on each 32-bit data separately, and then merge the conversion results.

3. The method for implementing an EtherCAT master station system without an operating system according to claim 1, wherein the non-real-time task priority scheduling processing includes: The main station tasks are divided into high real-time periodic communication tasks and event-driven non-real-time tasks; Periodic communication tasks are used for real-time data exchange and precise motion control, while non-real-time tasks are used for instruction calculation, status monitoring, and fault handling.

4. The method for implementing an EtherCAT master station system without an operating system according to claim 1, wherein the blocking communication synchronization mechanism combined with timer timeout monitoring includes: Based on the blocking communication mechanism, the master station immediately enters the receiving waiting state after sending a data frame; While continuously detecting returned frames, the system monitors the waiting time and terminates the waiting process when the waiting time exceeds a preset threshold.

5. The method for implementing an EtherCAT master station system without an operating system according to claim 1, wherein the memory management mechanism based on CoE standard mapping includes: A fixed-bit byte space is allocated in the slave station's memory, and the byte space is used to store the slave station's process data; Construct mapping configuration instructions based on the CoE protocol standard; Configure the PDO mapping table of the slave station via email communication and establish the mapping relationship between the master station memory space and the slave station memory space. Determine whether the slave device is in a safe operating state and verify whether the mapping relationship is correct.

6. The method for implementing an EtherCAT master station system based on an operating system-free architecture according to claim 1, wherein the periodic position mode of the slave station includes: Set the interpolation cycle for the position command; every interpolation cycle, the master station sends a new position command to the servo driver; Ensure that the period of the automatic reload register is consistent with the interpolation period.

7. A device for implementing an EtherCAT master station system without an operating system, characterized in that, include: The first implementation module is used to adapt the SOEM protocol stack to the hardware abstraction layer of the EtherCAT master station through byte order processing based on bit mask and staged shift strategy, and EtherCAT frame transmission and reception control based on ring buffer index management. The second implementation module is used for non-real-time task priority scheduling based on hardware timers, single-threaded event-driven main loop, and blocking communication synchronization mechanism combined with timer timeout monitoring to realize the adaptation of the SOEM protocol stack to the EtherCAT master station operating system abstraction layer. The third implementation module is used to adapt the EtherCAT master station application layer by using network scanning and communication parameter configuration, memory management mechanism based on CoE standard mapping, and periodic location mode of the slave station.

8. The apparatus for implementing an EtherCAT master station system without an operating system according to claim 7, characterized in that, The third implementation module includes: A partitioning unit is used to partition a fixed-bit byte space in the slave station's memory, the byte space being used to store the slave station's process data; The mapping unit is used to construct mapping configuration instructions based on the CoE protocol standard; it configures the PDO mapping table of the slave station and establishes the mapping relationship between the master station memory space and the slave station memory space through mailbox communication. The determination unit is used to determine whether the slave device is in a safe operating state and to verify whether the mapping relationship is correct.

9. An electronic device, comprising: One or more processors; A storage device for storing one or more programs, which, when executed by one or more processors, cause the one or more processors to implement the EtherCAT master station system implementation method based on an operating system as described in any one of claims 1 to 6.

10. A computer-readable medium having a computer program stored thereon, wherein, When the computer program is executed by the processor, it implements the EtherCAT master station system implementation method based on any one of claims 1 to 6.

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