Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, and the semiconductor structure comprises a substrate which is provided with a device region, a first isolation region and a second isolation region, and the second isolation region is disposed between the device region and the first isolation region; the second isolation region is further provided with a first semiconductor material region, and the first semiconductor material region is arranged adjacent to the first isolation region. According to the semiconductor structure provided by the embodiment of the invention, a part of the semiconductor material region is reserved in the isolation region adjacent to the device region, so that the size difference between the device region and the isolation region caused by the pattern density difference is compensated, and the semiconductor structure with higher yield is obtained.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic random access memory (DRAM) is widely used for data storage. DRAM includes a plurality of memory cells composed of transistors and capacitors. These memory cells are arranged in an array, wherein word lines extend along the rows of the array, and bit lines extend along the columns of the array. The word lines can be coupled to the transistors in the memory cells. Each memory cell can be uniquely addressed by a combination of one of the word lines and one of the bit lines.

[0003] As the integration of semiconductor devices increases, manufacturing processes are constantly updated, and the mutual influence between various process steps becomes increasingly important to product yield. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure with a higher yield and a method for forming the same.

[0005] Problems to be solved by the technical spirit of the present disclosure are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

[0006] Some embodiments of the present disclosure provide a semiconductor structure including: a substrate having a device region, a first isolation region and a second isolation region, wherein the second isolation region is arranged between the device region and the first isolation region; the second isolation region is also provided with a first semiconductor material region, wherein the first semiconductor material region is arranged adjacent to the first isolation region.

[0007] The device region of the semiconductor structure provided by the embodiment of the present disclosure includes a plurality of second semiconductor material regions arranged at intervals, a first conductive structure corresponding to each second semiconductor material region, and an isolation structure isolating each first conductive structure. In a direction perpendicular to the substrate, an extension depth of the isolation structure is less than an extension depth of the first isolation region or the second isolation region, and an extension depth of the second isolation region is not greater than an extension depth of the first isolation region.

[0008] The device region of the semiconductor structure provided by the embodiment of the present disclosure also includes a second conductive structure, which is arranged corresponding to multiple second semiconductor material regions. The isolation structure is also arranged between each first conductive structure and the second conductive structure, and the second conductive structure is connected to each corresponding second semiconductor material region.

[0009] The surface of the second conductive structure in the device region of the semiconductor structure provided by the embodiment of the present disclosure is not lower than the surfaces of the first isolation region and the second isolation region.

[0010] The first isolation region of the semiconductor structure provided by the embodiment of the present disclosure includes at least one isolation material, and the second isolation region includes at least two isolation materials. At least one isolation material in the second isolation region is different from the isolation material in the first isolation region.

[0011] At least one surface of the first semiconductor material region of the semiconductor structure provided by the embodiment of the present disclosure is not exposed by the surface of the second isolation region.

[0012] The isolation structure of the semiconductor structure provided by the embodiment of the present disclosure includes at least two isolation materials, and the isolation material in the isolation structure is the same as the isolation material in the second isolation region, and at least one isolation material in the isolation structure is different from the isolation material in the first isolation region.

[0013] The embodiments of the present disclosure also provide a method for forming a semiconductor structure, including: providing a substrate, patterning the substrate, and forming a first isolation region in the substrate; patterning the substrate, forming a device region and a second isolation region in the substrate, wherein the second isolation region is arranged between the device region and the first isolation region; wherein, when patterning the substrate to form the second isolation region, a portion of the substrate located in the second isolation region is retained to form a first semiconductor material region, and the first semiconductor material region is arranged adjacent to the first isolation region.

[0014] In the method for forming a semiconductor structure provided by an embodiment of the present disclosure, a substrate has a first surface and a second surface, the first surface and the second surface are arranged relative to each other, the substrate is patterned, and a device area and a second isolation area are formed in the substrate, including: patterning the first surface of the substrate, forming a plurality of first grooves and a second groove in the substrate, the substrate is divided by the plurality of first grooves to form a plurality of second semiconductor material areas arranged at intervals; filling each of the first grooves and the second grooves, forming an isolation structure in each of the first grooves, and forming a second isolation area in the second grooves; forming a first conductive structure between the isolation structure and each of the second semiconductor material areas, the first conductive structure, each of the second semiconductor material areas and the isolation structure forming a device area; wherein, in a direction perpendicular to the substrate, an extension depth of the isolation structure is less than an extension depth of the second isolation area or an extension depth of the first isolation area, and an extension depth of the second isolation area is not greater than an extension depth of the first isolation area.

[0015] The method for forming a semiconductor structure provided by an embodiment of the present disclosure further includes forming a second conductive structure in the device region, including:

[0016] The second surface of the substrate is thinned so that part of the substrate in the device area is retained and the substrate in the first isolation area and the second isolation area is removed; a second conductive structure is formed on the surface of the substrate retained in the device area, and the second conductive structure connects the corresponding second semiconductor material areas.

[0017] In the method for forming a semiconductor structure provided by the embodiment of the present disclosure, when thinning the second surface of the substrate, the first isolation region is used as a thinning stop region.

[0018] In the method for forming a semiconductor structure provided by an embodiment of the present disclosure, when thinning the second surface of the substrate, the second isolation region is not thinned, and the surface of the first semiconductor region is exposed by the surface of the second isolation region.

[0019] The semiconductor structure provided by the embodiment of the present disclosure retains a portion of the semiconductor material region in the isolation region adjacent to the device region, thereby compensating for the size difference between the device region and the isolation region due to the difference in pattern density, thereby obtaining a semiconductor structure with a higher yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated in and constitute a part of the specification, illustrate embodiments consistent with the embodiments of the present disclosure, and together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0021] Figure 1 A schematic flow chart of a method for forming a semiconductor structure provided in an embodiment of the present disclosure.

[0022] Figure 2 , Figure 4 as well as Figure 6 It is a top view of the semiconductor structure corresponding to the process of forming the semiconductor structure.

[0023] Figure 3 , Figure 5 , Figures 7 to 13 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure.

[0024] The above drawings show clear embodiments of the present disclosure, which will be described in more detail below. These drawings and text descriptions are not intended to limit the scope of the present disclosure in any way, but to illustrate the concepts of the present disclosure for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below in conjunction with the drawings in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant disclosure, rather than to limit the disclosure. It should also be noted that, for ease of description, only relevant parts are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects.

[0026] Figure 1 A schematic flow chart of forming a semiconductor structure according to some embodiments is shown. The corresponding method of forming a semiconductor structure includes the following steps:

[0027] S11: providing a substrate, patterning the substrate, and forming a first isolation region in the substrate.

[0028] S12: Patterning the substrate to form a device region and a second isolation region in the substrate, wherein the second isolation region is disposed between the device region and the first isolation region; wherein, when patterning the substrate to form the second isolation region, a portion of the substrate located in the second isolation region is retained to form a first semiconductor material region, wherein the first semiconductor material region is disposed adjacent to the first isolation region.

[0029] The method for forming a semiconductor structure provided by an embodiment of the present disclosure is described in detail below in conjunction with the corresponding drawings.

[0030] First execute S11, see Figure 2 and Figure 3 , Figure 2 is a schematic top view of a semiconductor structure provided by some embodiments of the present disclosure, Figure 3 1 is a schematic cross-sectional view of a semiconductor structure provided in some embodiments of the present disclosure. The semiconductor structure provided in step S11 includes a substrate 100, and the substrate 100 has a first isolation region 200. The first isolation region 200 disposed in the substrate 100 is mainly used to separate the substrate 100, so as to divide the substrate 100 into an electrical region and an isolation region. Figure 2 and Figure 3As shown, the substrate 100 can be divided into a device region I and an isolation region II, wherein the device region I is an electrical region composed of a plurality of substrates 100 extending in the Y direction and isolated from each other in the X direction, the substrates 100 in the device region I provide an active region for subsequent formation of semiconductor devices, and the spaced substrates 100 in the device region I are isolated from each other by the first dielectric layer 300. The isolation region II is an isolation region including the substrate 100, and the first isolation region 200 is disposed on the substrate 100 in the isolation region II. Figure 3 They respectively indicate the Figure 2 The cross-sectional structure schematic diagram along the A1-A2 line and the B1-B2 line, the A1-A2 line and the B1-B2 line are respectively parallel to the Y direction, the X direction and the Y direction are perpendicular to each other, the A1-A2 line is a schematic line extending along the Y direction and virtually set in the substrate 100 for the cross-sectional position, and the B1-B2 line is a schematic line extending along the Y direction and virtually set between adjacent substrates 100 for the cross-sectional position.

[0031] In some embodiments, the step of patterning the substrate 100 and forming the first isolation region 200 in the substrate 100 may be performed by mask deposition, photolithography to define the mask pattern, etching the mask pattern, and transferring the mask pattern to the substrate 100 to form the first isolation region 200 .

[0032] In some embodiments, the substrate 100 may be made of or may include various types of semiconductor materials, including, for example, silicon, germanium, III to V groups, or other types of suitable materials. In some embodiments, the substrate 100 is made of silicon (doped or undoped), and in alternative embodiments, the substrate 100 is a silicon-on-insulator (SOI) wafer or a silicon carbide wafer. Alternatively, any other suitable semiconductor material may be used for the substrate 100, such as a semiconductor composite material, such as gallium arsenide (GaAs), indium phosphide (InP), and any suitable ternary semiconductor composite material or quaternary semiconductor composite material, such as indium gallium arsenide (InGaAs). In these embodiments, the substrate 100 may be a thin or ultra-thin substrate or wafer, such as having a thickness ranging from about a few microns to about a few hundred microns, such as ranging from about 5 μm to about 100 μm, such as having a thickness less than about 100 μm or less than about 50 μm.

[0033] In some embodiments, the material of the first dielectric layer 300 may be dielectric materials such as silicon oxide, silicon nitride, silicon carbonitride, etc. The material filled in the first isolation region 200 may be insulating dielectric materials such as silicon oxide, silicon nitride, silicon carbonitride, etc. or other types of dielectric materials. In some embodiments, the first dielectric layer 300 and the first isolation region 200 contain the same dielectric material.

[0034] Continue to see Figure 3In some embodiments, the substrate 100 has a first surface 100A and a second surface 100B disposed opposite to the first surface 100A, and the first isolation region 200 extends along the first surface 100A toward the second surface 100B. In this extension direction, the first isolation region 200 has a first extension depth H1, and the first extension depth H1 is not greater than the extension depth of the substrate 100 in the first region I. In some embodiments, the first surface 100A of the substrate 100 in the device region I is coplanar with the surface of the first isolation region 200, that is, the surfaces of the two are flush or substantially flush. In these embodiments, the first dielectric layer 300 also extends in a direction perpendicular to the X direction or the Y direction. In this extension direction, the first dielectric layer 300 has a second extension depth H2 in the device region I. The second extension depth H2 may be equal to or substantially equal to the first extension depth H1, for example, the difference between the two is controlled within 10-20 nm; the second extension depth H2 may also be less than the first extension depth H1, for example, the difference between the two is greater than 20 nm.

[0035] Execute S12 to form a device region and a second isolation region. In some embodiments, forming the device region and the second isolation region includes the following steps:

[0036] S121: patterning the first surface of the substrate, forming a plurality of first grooves and second grooves in the substrate, and the substrate is divided by the plurality of first grooves to form a plurality of second semiconductor material regions arranged at intervals.

[0037] Combine the following Figure 4 and Figure 5 The above steps are explained in detail. Figure 4 is a schematic top view of a semiconductor structure provided by some embodiments of the present disclosure, Figure 5 1 is a schematic cross-sectional view of a semiconductor structure provided by some embodiments of the present disclosure. The first surface of the patterned substrate includes: forming a mask layer 400 on the first surface 100A of the substrate 100, and the mask layer 400 also covers the surface of the first isolation region 200. A mask pattern is formed on the mask layer 400, and the mask pattern includes a mask pattern 402 arranged on the device region I and a mask pattern 401 arranged on the first isolation region 200. Among them, a plurality of grooves 403 are arranged between the mask patterns 402 on the device region I, and each groove 403 exposes the surface of the mask layer 400. No grooves are arranged in the mask pattern 401 on the first isolation region 200, that is, the mask pattern 401 completely covers the mask layer 400 on the first isolation region 200. In some embodiments, a groove 404 is also arranged between the mask pattern 402 and the mask pattern 401, and the mask layer 400 exposed by the groove 404 corresponds to the isolation region III in the substrate 100. Figure 5 They respectively indicate the Figure 4From the cross-sectional structural diagrams along the A1-A2 line and the B1-B2 line, it can be seen that the mask pattern 402 and the groove 403 are also formed on the first dielectric layer 300 at the same time. In order to more clearly illustrate the corresponding relationship between the mask pattern and the substrate, Figure 4 The mask layer 400 is omitted.

[0038] In some embodiments, the width of trench 403 is smaller than the width of trench 404 .

[0039] In some embodiments, the isolation region III may have a plurality of trenches 404, and the number of trenches 404 on the isolation region III is less than the number of trenches 403 on the device region I. In the embodiment of the present disclosure, the number of trenches 404 is shown as 1, but is not limited thereto.

[0040] Continue to see Figure 6 and Figure 7 , Figure 6 is a schematic top view of a semiconductor structure provided by some embodiments of the present disclosure, Figure 7 4 is a schematic cross-sectional view of a semiconductor structure provided by some embodiments of the present disclosure. After the grooves 403 and 404 are formed, the substrate 100 and the first dielectric layer 300 are etched downward along the grooves 403 and 404 by an etching process, and the first groove 101 and the second groove 103 are formed in the substrate 100. The first groove 101 and the second groove 103 are also formed in the first dielectric layer 300 at the same time. In the Y direction, the first groove 101 divides the substrate 100 on the device area I into a plurality of second semiconductor material areas 102 arranged at intervals from each other; at the same time, the first groove 101 divides the first dielectric layer 300 into a plurality of dielectric structures 105 spaced from each other. After the first groove 101 and the second groove 103 are formed, the mask layer 400 and the mask patterns thereon are removed.

[0041] In some embodiments, the second semiconductor material region 102 has the same or different structure as the substrate 100 .

[0042] Continue to see Figure 6 and Figure 7 In some embodiments, when the substrate 100 on the isolation region III is etched downward along the trench 404 to form the second trench 103 , a portion of the substrate 100 located on the isolation region III is retained to form the first semiconductor material region 104 .

[0043] In some embodiments, in the device region I, the first trench 101 between the second semiconductor material regions 102 adjacent in the Y direction has a third extension depth H3 in the direction from the first surface 100A to the second surface 100B of the substrate 100; in the isolation region III, the second trench 103 between the second semiconductor material regions 102 and the first semiconductor material regions 104 adjacent in the Y direction has a fourth extension depth H4. In addition, in the device region I, the first trench 101 between the dielectric structures 105 adjacent in the Y direction has a fifth extension depth H5; in the isolation region III, the second trench 103 between the dielectric structures 105 and the first isolation region 200 adjacent in the Y direction has a sixth extension depth H6.

[0044] In some embodiments, the values ​​of the third extension depth H3 to the sixth extension depth H6 are all less than the first extension depth H1. In other embodiments, the values ​​of the third extension depth H3 to the sixth extension depth H6 are also less than the second extension depth H2. In the above embodiments, the third extension depth H3 is less than the fourth extension depth H4, the fifth extension depth H5 is less than the sixth extension depth H6, and the difference between the third extension depth H3 and the fourth extension depth H4 is controlled within a first predetermined numerical range, for example, the difference between the two is between 10nm-50nm, and the difference between the fifth extension depth H5 and the sixth extension depth is controlled within a second predetermined numerical range, for example, the difference between the two is between 10nm-50nm. In some embodiments, while the third extension depth H3 is less than the fourth extension depth H4, and the fifth extension depth H5 is less than the sixth extension depth H6, the third extension depth H3 is less than the fifth extension depth H5, and the fourth extension depth H4 is less than the sixth extension depth H6. In other embodiments, the fourth extension depth H4 may be equal to or substantially equal to the sixth extension depth H6, and the difference between the two is controlled within 10nm-50nm.

[0045] In these embodiments, it is necessary to overcome the problem of different etching rates caused by the etched material not being a single component. For example, during the etching process, the etched object includes a substrate and a first dielectric layer isolating each substrate. The substrate and the first dielectric layer exhibit different etching rates. For example, when the substrate is made of silicon and the first dielectric layer is made of silicon oxide, the etching rate of silicon oxide is greater than the etching rate of silicon, which results in a difference between the fourth extension depth and the sixth extension depth. At the same time, since the density of the mask pattern in the device region I is greater than the density of the mask pattern in the isolation region III, according to the etching load effect, the difference between the fourth extension depth and the sixth extension depth will be further amplified. The excessive difference between the two will have an adverse effect on subsequent processes. This phenomenon of excessive etching of the material in the isolation region III may even cause the fourth extension depth H4 and the sixth extension depth H6 to be greater than the first extension depth H1. To improve this problem, in these embodiments, when forming the second trench between the second semiconductor material region and the first isolation region, part of the substrate is retained on the sidewall of the second trench to form the first semiconductor material region. The retained first semiconductor material region can alleviate the etching load effect when etching to form the first trench and the second trench, shorten the fourth extension depth and the sixth extension depth, avoid the fourth extension depth or the sixth extension depth exceeding the first extension depth, and improve the reliability of subsequent processes.

[0046] In some embodiments, the first semiconductor material region 104 is disposed adjacent to the first isolation region 200. Figure 7 That is, during the etching process, part of the substrate adjacent to the first isolation region 200 is retained, and at this time, the surface of the first semiconductor material region 104 is lower than the surface of the first isolation region 200. In other embodiments, the first semiconductor material region 104 may be disposed adjacent to the second semiconductor material region, that is, during the etching process, part of the substrate adjacent to the device region I is retained.

[0047] After step S121 , step S122 is performed to fill each of the first trenches and the second trenches, form an isolation structure in each of the first trenches, and form a second isolation region in the second trenches.

[0048] Combine the following Figure 8 and Fig. 9 To elaborate, Figure 8 and Fig. 9 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure.

[0049] See first Figure 8, the second dielectric layer 301 and the third dielectric layer 302 are used to fill the first trench 101 and the second trench 103 respectively. The second dielectric layer 301 and the third dielectric layer 302 form a stacked structure filling the first trench 101 and the second trench 103, wherein the second dielectric layer 301 is formed in the first trench 101 and the second trench 103 before the third dielectric layer 302. In some embodiments, the second dielectric layer 301 and the third dielectric layer 302 are different materials. For example, the second dielectric layer 301 can be at least one of silicon oxide, silicon nitride, silicon carbonitride and the like, and the third dielectric layer 302 is another of silicon oxide, silicon nitride, silicon carbonitride and the like. Figure 8 As shown, the second dielectric layer 301 and the third dielectric layer 302 are also formed on the surface of the first isolation region 200 at the same time.

[0050] Continue to see Fig. 9 After the first trench 101 and the second trench 103 are filled, the redundant second dielectric layer 301 and the third dielectric layer 302 are removed, and only the second dielectric layer 301 and the third dielectric layer 302 located in the first trench 101 and the second trench 103 and the second dielectric layer 301 and the third dielectric layer 302 located on the first isolation region 200 are retained. The second dielectric layer 301 and the third dielectric layer 302 retained in the first trench form an isolation structure 31 located in the first trench, and the second dielectric layer 301 and the third dielectric layer 302 retained in the second trench form a second isolation region 32 located in the second trench. The isolation structure 31 is simultaneously formed between each second semiconductor material region 102 and each dielectric structure 105 in the device region I; the second isolation region 32 is simultaneously formed between the second semiconductor material region 102 and the first isolation region 200 and between the dielectric structure 105 and the first isolation region 200 in the isolation region III.

[0051] After step S122, step S123 is performed to form a first conductive structure between the isolation structure and each second semiconductor material region, and the first conductive structure, each second semiconductor material region and the isolation structure form a device region.

[0052] Combine the following Fig.10 Step S123 is described in detail. Fig.10 A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure.

[0053] After forming the isolation structure and the second isolation region, a first conductive structure 106 is formed between each second semiconductor material region 102 in the device region I. The first conductive structure 106 includes a plurality of first conductive structures 106 extending along the X direction and surrounding and covering each second semiconductor material region 102. The plurality of first conductive structures 106 are spaced apart from each other in the Y direction. In these embodiments, a conduction control layer 107 is further disposed between the first conductive structure 106 and each second semiconductor material region 102. The conduction control layer 107 covers the surface of each second semiconductor material region 102. In the above embodiments, the first conductive structure is also formed between each dielectric structure 105 in the device region I at the same time.

[0054] In some embodiments, each second semiconductor material region 102 and its corresponding conduction control layer 107 and the corresponding first conductive structure 106 form a transistor structure, that is, the second semiconductor material region 102 can be an active region, the conduction control layer 107 can be a gate dielectric layer, the first conductive structure 106 can be a gate, and the formed transistor structure can be a GAA (Gate All Around) transistor.

[0055] In some embodiments, in order to form the first conductive structure 106 in the device region I, it is necessary to first Fig. 9 On the basis of the present invention, a portion of the second dielectric layer 301 is etched away along the first surface of the substrate 100 in the device region I, thereby forming a gap between each second semiconductor material region 102 and the third dielectric layer 302. At the same time, each dielectric structure 105 and the second dielectric layer 301 on the B1-B2 line is also partially removed, thereby forming a gap between each third dielectric layer 302 on the B1-B2 line. After the above-mentioned gaps are formed, the dielectric layer is backfilled in the above-mentioned gaps, thereby forming Fig.10 The dielectric structure 303 is shown in FIG. 1 . At this time, the dielectric structure 303, the second dielectric layer 301, and the third dielectric layer 302 form the isolation structure 31 of each first conductive structure 106. At the same time, the dielectric structure 303 is also formed in the second isolation region 32. In some embodiments, the dielectric structure 303 and the third dielectric layer 302 are made of the same material, for example, both are made of one of silicon oxide, silicon nitride, and silicon carbonitride. At this time, in the second isolation region 32 and the isolation structure 31, the dielectric structure 303 and the third dielectric layer 302 may not be directly distinguished, and there is no obvious boundary between the two.

[0056] In some embodiments, when the dielectric structure 303 is backfilled in these gaps, the gaps on the A1-A2 line are completely filled, and the gaps between the third dielectric layers 302 on the B1-B2 line are partially filled, that is, the gaps on the B1-B2 line are only partially filled with the dielectric structure 303, and the unfilled gaps are used in subsequent steps to continue etching downward the second dielectric layer 301 and the windows of the dielectric structure 105 to provide space for the first conductive structure 106 to be formed subsequently.

[0057] Continue to see Fig.10 After the first conductive structure 106 is formed, the device region I at this time includes the first conductive structure 106, each second semiconductor material region 102 and an isolation structure isolating each second semiconductor material region 102 and each first conductive structure 106. The isolation structure of the device region I includes a second dielectric layer 301, a third dielectric layer 302 and a dielectric structure 303. Since the third dielectric layer 302 and the dielectric structure 303 in the device region I are made of the same material, Fig.10 In the figure, the dielectric structure 303 is used to identify the third dielectric layer 302 and the dielectric structure 303 at the same time.

[0058] Continue to see Figure 7 and Fig.10 Since the isolation structure and the second isolation region are formed by filling the first trench 101 and the second trench 103 respectively, in some embodiments, in the direction from the first surface 100A to the second surface 100B of the substrate 100, that is, in the direction perpendicular to the substrate 100, the extension depth of the formed isolation structure is less than the extension depth of the second isolation region 32 or less than the extension depth of the first isolation region 200. In some embodiments, the extension depth of the isolation structure is less than the extension depth of the first isolation region 200 and the second isolation region 32 at the same time.

[0059] Continue to see Fig.10 In some embodiments, after forming the isolation structure, the second isolation region, and the first conductive structure, the surface of the semiconductor structure is planarized to remove excess material from the surface of each region and keep the surfaces of the device region I, the isolation region II, and the isolation region III flush or substantially flush.

[0060] In these embodiments, the surface of the first semiconductor material region 104 adjacent to the first surface 100A of the substrate 100 is covered by the second isolation region 32, that is, the top surface of the first semiconductor material region 104 is not exposed by the second isolation region 32. In other embodiments, the top surface of the first semiconductor material region 104 may also be exposed by the second isolation region 32, that is, the top surface of the first semiconductor material region 104 is coplanar with the second isolation region 32, the first isolation region 200, and the top surface of the isolation structure in the device region I.

[0061] In some embodiments, after forming the isolation structure, the second isolation region, and the first conductive structure, a charge storage structure is further formed in the device region I.

[0062] Combine the following Fig.11 The process of forming the charge storage structure is described in detail. Fig.11 A schematic cross-sectional view of a semiconductor structure provided in an embodiment of the present disclosure. A lower electrode 503, a dielectric layer 502 and an upper electrode 501 are deposited on the surfaces of the formed isolation structure and the second isolation region, respectively. The lower electrode 503 is in electrical contact with each second semiconductor material region 102 in the device region I. The dielectric layer 502 covers the surface of the lower electrode 503. The upper electrode 501 covers the surface of the dielectric layer 502. The upper electrode 501, the lower electrode 503 and the dielectric layer 502 constitute a charge storage structure. Each first conductive structure 106 in the device region I controls the disconnection of each second semiconductor material region 102 from the charge storage structure. Each first conductive structure 106 can be a word line of a DRAM storage structure. Each second semiconductor material region 102 is responsible for providing a transmission channel and charge supply for the charge in the charge storage structure. Each second semiconductor material region 102 can be an active region of a DRAM transistor.

[0063] In some embodiments, see Fig.11 An isolation dielectric layer 500 is formed on the first isolation region 200 and the second isolation region 32. The isolation dielectric layer 500 is used to isolate the charge storage structure from the surrounding environment. The isolation dielectric layer 500 can be made of the same or different material as the first isolation region 200. For example, the isolation dielectric layer 500 can be one or more of silicon oxide, silicon nitride, and silicon carbonitride.

[0064] In some embodiments, after executing step S122, step S123 is also included. Step S123 includes forming a second conductive structure in the device area, including: thinning the second surface of the substrate so that part of the substrate in the device area is retained, and the substrate in the first isolation area and the second isolation area is removed; forming a second conductive structure on the surface of the substrate retained in the device area, and the second conductive structure is connected to the second semiconductor material area.

[0065] Combine the following Fig.12 and Fig.13 Step S123 is described in detail. Fig.12 and Fig.13A schematic cross-sectional view of a semiconductor structure provided for an embodiment of the present disclosure. After forming the charge storage structure, the semiconductor structure is flipped 180°, and the second surface 100B of the substrate 100 is used as the surface to be processed, and the substrate 100 is thinned. In this process, the substrate 100 on the A1-A2 line, that is, the bottom of the second semiconductor material area 102 will be partially removed, and the retained part of the substrate is marked as the substrate 108. At the same time, the bottom surface of the first semiconductor material area 104 in the second isolation area 32 will also be partially removed, and the substrate on the first isolation area 200 and the substrate 100 on the B1-B2 line will also be removed synchronously until the dielectric structure 105 is exposed. In some embodiments, in the above-mentioned thinning process, the surface of the first isolation area 200 is used as a thinning stop area, that is, when thinning, when the first isolation area 200 is contacted, the thinning process will stop. In the above embodiment, the second isolation region 32 may not be thinned, for example, the thinning process stops at the second dielectric layer 301 ; the second isolation region 32 may also be thinned, for example, the thinning process stops at the third dielectric layer 302 .

[0066] When the semiconductor structure is thinned, since in the aforementioned process steps, the difference in extension depth between the isolation structure in the device region I and / or the second isolation region and the first isolation region is reduced by retaining a portion of the first semiconductor material region in the second isolation region, the second isolation region and the isolation structure are prevented from having a deeper extension depth in the direction toward the second surface of the substrate. If the extension depth of the second isolation region and the isolation structure is too deep, when the substrate is thinned, as the thinning proceeds, the second isolation region 32 and the isolation structure will be exposed before the first isolation region 200 or even the substrate 100, and the thinning of the substrate 100 and the dielectric structure 105 will only be carried out after they are further thinned. This requires further thinning of the isolation structure and / or the dielectric in the second isolation region during the thinning process, which introduces serious risks to the thinning process, not only increasing the cost of the thinning process, but also affecting the yield of the process. For example, when the first isolation region 200 is used as the thinning process stop area, it is only necessary to thin the substrate 100 of the device region I, the isolation region II, and the isolation region III. This is because the extension depths of the isolation structure, the second isolation region 32, etc. at this time do not exceed the extension depth of the first isolation region 200, and the isolation structure and the second isolation region 32 will not have adverse effects on the thinning process, and the thinning process is more stable. On the contrary, when the extension depths of the isolation structure and the second isolation region 32 exceed the first isolation region 200, the thinning process needs to thin the substrate 100, the second dielectric layer 301, and even the third dielectric layer 302 at the same time. In this thinning process, it is necessary to balance the thinning uniformity of the silicon substrate, the second dielectric layer, and the third dielectric layer, and the process difficulty is greatly increased.

[0067] In the above embodiments, the thinning process may be implemented by a chemical mechanical polishing process or other surface planarization processes.

[0068] Continue to see Fig.13 , a second conductive structure 109 is formed on the thinned substrate 108 in the device region I, and the second conductive structure 109 is directly in contact with the substrate 108. The process for forming the second conductive structure 109 may adopt a conductive film deposition process, and after the conductive film deposition is completed, an annealing treatment may be performed to achieve efficient electrical connection between the second conductive structure 109 and the substrate 108, for example, an ohmic contact between the second conductive structure 109 and the substrate 108 is achieved through annealing.

[0069] In some embodiments, the second conductive structure 109 is formed on the surface of the substrate 108 corresponding to the second semiconductor material region 102, and the region between the adjacent second semiconductor material regions 102 in the X direction, that is, the region where the dielectric structure 105 is located, is not provided with the second conductive structure 109. The second conductive structure 109 is arranged vertically with the first conductive structure 106, and the first conductive structure 106 connects a plurality of second semiconductor material regions 102 extending in the X direction, and the second conductive structure 109 connects a plurality of second semiconductor material regions 102 extending in the Y direction. The second conductive structure 109 is used to implement the read and write operations of the capacitor in the charge storage structure, and the second conductive structure 109 can be a bit line of a DRAM storage structure. The number of the second conductive structures 109 is the same as the first conductive structure 106, and can be multiple, each first conductive structure 106 extends in the X direction and is arranged at intervals in the Y direction, and each second conductive structure 109 extends in the Y direction and is arranged at intervals in the X direction.

[0070] In some embodiments, the material of the first conductive structure 106 can be one or more metals such as titanium, tungsten, cobalt, nickel, platinum, gold or their silicides, and the material of the second conductive structure 109 can be one or more metals such as titanium, tungsten, cobalt, nickel, platinum, gold or their silicides.

[0071] Continue to see Fig.13 In some embodiments, after forming the second conductive structure 109, an isolation dielectric layer 600 is deposited on the surface of the semiconductor structure, and a contact pad 700 interconnected with the second conductive structure 109 in the device region I is formed in the isolation dielectric layer 600, and the second conductive structure 109 is interconnected with other functional units through the contact pad 700.

[0072] In some embodiments, during the substrate thinning process, a surface of the first semiconductor material region 104 is also exposed, and therefore, the second conductive structure 109 may also be formed on the surface of the first semiconductor material region 104 .

[0073] Some embodiments of the present disclosure also provide a semiconductor structure, which includes: a substrate, the substrate having a device region, a first isolation region and a second isolation region, wherein the second isolation region is arranged between the device region and the first isolation region; the second isolation region is also provided with a first semiconductor material region, and the first semiconductor material region is arranged adjacent to the first isolation region.

[0074] The schematic diagram of the semiconductor structure can be found in Fig.13 As shown in the figure, the semiconductor structure includes a device region I, an isolation region II and an isolation region III, and the isolation region III is arranged between the device region I and the isolation region II. The device region I has a substrate 108, and the substrate 108 is a semiconductor substrate; the isolation region II is provided with a first isolation region 200, the isolation region III is provided with a second isolation region 32, and the second isolation region 32 is further provided with a first semiconductor material region 104, and the first semiconductor material region 104 can be arranged adjacent to the first isolation region 200, and can also be arranged adjacent to the device region I. Fig.13 FIG. 4 illustrates a situation where the first semiconductor material region 104 is disposed adjacent to the first isolation region 200 .

[0075] In some embodiments, the first semiconductor material region 104 may be a part of the substrate 108 or may be made of the same material as the substrate 108 .

[0076] In some embodiments, the first semiconductor material region 104 is formed between the adjacent second isolation region 32 and the first isolation region 200 on the A1-A2 line, and the first semiconductor material region 104 is not formed between the adjacent second isolation region 32 and the first isolation region 200 on the B1-B2 line. At least one surface of the first semiconductor material region 104 is not exposed by the second isolation region 32, that is, at least one surface of the first semiconductor material region 104 is not exposed on the surface of the isolation region III. The positions of the A1-A2 line and the B1-B2 line in the semiconductor structure can be referred to Figure 3 and description of the corresponding drawings.

[0077] In the semiconductor structure provided in the embodiment of the present disclosure, a semiconductor structure with a higher yield is obtained by retaining a portion of the semiconductor material region in the isolation region adjacent to the device region to compensate for the size difference between the device region and the isolation region due to the difference in pattern density.

[0078] Continue to see Fig.13The device region I of the semiconductor structure includes a plurality of second semiconductor material regions 102 arranged in an interval in the X direction and the Y direction, a first conductive structure 106 corresponding to each second semiconductor material region 102, and an isolation structure (301+302+303) isolating each first conductive structure. The second semiconductor material regions 102 arranged along the Y direction share a substrate 108, and a dielectric structure 105 is arranged between the second semiconductor material regions 102 arranged along the X direction, for isolating each second semiconductor material region 102 in the X direction. Each first conductive structure 106 extends in the X direction and is isolated from each other along the Y direction. Each first conductive structure 106 extending in the X direction is connected and arranged corresponding to each row of second semiconductor material regions 102 arranged along the X direction. The isolation structure is arranged between each second semiconductor material region 102 adjacent in the X direction and the Y direction and between each first conductive structure 106 adjacent to each other in the Y direction, so as to achieve isolation of each second semiconductor material region 102 and isolation of each first conductive structure 106.

[0079] In some embodiments, the first semiconductor material region 104 and the second semiconductor material region 102 are both from the substrate 108 or made of the same material as the substrate 108 .

[0080] In some embodiments, the isolation structure includes a second dielectric layer 301 and a dielectric structure 303, wherein the isolation structure close to the substrate 108 includes a stacked structure consisting of the second dielectric layer 301 and the third dielectric layer 302, and the isolation structure away from the substrate 108 includes a composite structure consisting of the third dielectric layer 302 and the dielectric structure 303. The second dielectric layer 301 and the third dielectric layer 302 can be different dielectric materials, for example, the second dielectric layer 301 is silicon oxide, and the third dielectric layer 302 is silicon nitride, or vice versa. The third dielectric layer 302 and the dielectric structure 303 can be the same dielectric material, for example, both are dielectric materials such as silicon nitride or silicon oxide.

[0081] In some embodiments, the first isolation region 200 may include at least one isolation material, such as silicon nitride or silicon oxide. In other embodiments, the first isolation region 200 may also include two or more types of isolation materials to achieve a better isolation effect.

[0082] In some embodiments, the second isolation region 32 includes at least two isolation materials, for example, a stacked structure consisting of a second dielectric layer 301 and a third dielectric layer 302 .

[0083] In some embodiments, in a direction perpendicular to the substrate 108, that is, in a direction perpendicular to the X direction and the Y direction, the extension depth of the isolation structure is less than the extension depth of the first isolation region 200 or the second isolation region 32, and the extension depth of the second isolation region 32 is not greater than the extension depth of the first isolation region 200. The difference in extension depth between the isolation structure and the first isolation region or the second isolation region in the semiconductor structure obtained in the embodiment of the present disclosure can be further reduced, and the extension depth value of the second isolation region can be prevented from being too large, thereby affecting the performance of the semiconductor structure.

[0084] In some embodiments, the device region I of the semiconductor structure further includes a second conductive structure 109, and the second conductive structure 109 is arranged corresponding to the plurality of second semiconductor material regions 102. There are multiple second conductive structures 109, and each second conductive structure 109 extends along the Y direction and is arranged at intervals in the X direction, and the second conductive structures 109 are arranged vertically with the first conductive structures 106. Each second conductive structure 109 is respectively connected to each second semiconductor material region 102 arranged in the Y direction. The second conductive structures 109 that are in a row in the X direction are electrically isolated by the dielectric structure 105. The first conductive structure 106 and the second conductive structure 109 are isolated by an isolation structure, for example, by a second dielectric layer 301.

[0085] In the semiconductor structure provided in the above embodiment, the first conductive structure 106 in the device region I may be a word line, the second conductive structure 109 may be a bit line, and the second semiconductor material region 102 may be an active region constituting a transistor. The device region I also includes a conduction control layer 107, which may be a gate dielectric layer of the transistor.

[0086] In some embodiments, the device region I further includes a charge storage structure, which is composed of an upper electrode 501, a dielectric layer 502, and a lower electrode 503, and each charge storage structure is connected to a corresponding second semiconductor material region 102. The charge storage structure may be a DRAM capacitor.

[0087] In some embodiments, the semiconductor structure further includes an isolation dielectric layer 500 disposed on the first isolation region 200 and / or the second isolation region 32 . The isolation dielectric layer 500 is further disposed at the periphery of the charge storage structure for isolating the charge storage structure.

[0088] In the above embodiment, the first conductive structure 106 is disposed between the second conductive structure 109 and the capacitor storage structure.

[0089] In some embodiments, the semiconductor structure further includes an isolation dielectric layer 600, which is disposed on the device region I, the isolation region II, and the isolation region III, and covers the second conductive structure 109 and the dielectric structure 105 as well as the first isolation region 200 and the second isolation region 32. A contact pad 700 is disposed in the isolation dielectric layer 600 to realize the interconnection between the second conductive structure 109 and other functional units.

[0090] In some embodiments, the surface of the second conductive structure 109 is not lower than the surfaces of the first isolation region 200 and the second isolation region 32. The surface of the second conductive structure 109 here refers to the surface of the second conductive structure 109 away from the substrate 108, and the surfaces of the first isolation region 200 and the second isolation region 32 also refer to the surfaces in the same direction.

[0091] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure comprising: A substrate having a device region; First quarantine area; a second isolation region, the second isolation region being disposed between the device region and the first isolation region; The second isolation region is further provided with a first semiconductor material region, and the first semiconductor material region is provided adjacent to the first isolation region.

2. The semiconductor structure according to claim 1, characterized in that: The device region includes a plurality of second semiconductor material regions arranged at intervals, a first conductive structure corresponding to each of the second semiconductor material regions, and an isolation structure isolating each of the first conductive structures. In a direction perpendicular to the substrate, an extension depth of the isolation structure is less than an extension depth of the first isolation region or the second isolation region, and an extension depth of the second isolation region is not greater than an extension depth of the first isolation region.

3. The semiconductor structure according to claim 2, characterized in that: The device region also includes a second conductive structure, which is arranged corresponding to multiple second semiconductor material regions. The isolation structure is also arranged between each of the first conductive structures and the second conductive structure, and the second conductive structure is connected to each corresponding second semiconductor material region.

4. The semiconductor structure according to claim 3, characterized in that: A surface of the second conductive structure is not lower than surfaces of the first isolation region and the second isolation region.

5. The semiconductor structure according to claim 1, characterized in that: The first isolation region includes at least one isolation material, and the second isolation region includes at least two isolation materials, and at least one isolation material in the second isolation region is different from the isolation material in the first isolation region.

6. The semiconductor structure according to claim 1, characterized in that At least one surface of the first semiconductor material region is not exposed by a surface of the second isolation region.

7. The semiconductor structure according to claim 1, characterized in that: The isolation structure includes at least two isolation materials, and the isolation material in the isolation structure is the same as the isolation material in the second isolation region, and at least one isolation material in the isolation structure is different from the isolation material in the first isolation region.

8. A method for forming a semiconductor structure, comprising: Providing a substrate, patterning the substrate, and forming a first isolation region in the substrate; Patterning the substrate to form a device region and a second isolation region in the substrate, wherein the second isolation region is disposed between the device region and the first isolation region; When the substrate is patterned to form the second isolation region, a portion of the substrate located in the second isolation region is retained to form a first semiconductor material region, and the first semiconductor material region is disposed adjacent to the first isolation region.

9. The forming method according to claim 8, characterized in that: The substrate has a first surface and a second surface, the first surface and the second surface are arranged opposite to each other, and the substrate is patterned to form a device region and a second isolation region in the substrate, including: Patterning the first surface of the substrate to form a plurality of first grooves and second grooves in the substrate, wherein the substrate is divided by the plurality of first grooves to form a plurality of second semiconductor material regions arranged at intervals; Filling each of the first trenches and the second trenches, forming an isolation structure in each of the first trenches, and forming a second isolation region in the second trenches; A first conductive structure is formed between the isolation structure and each of the second semiconductor material regions, and the first conductive structure, each of the second semiconductor material regions and the isolation structure form the device region; wherein, In a direction perpendicular to the substrate, an extension depth of the isolation structure is less than an extension depth of the second isolation region or an extension depth of the first isolation region, and an extension depth of the second isolation region is not greater than an extension depth of the first isolation region.

10. The forming method according to claim 9, characterized in that: The invention also includes forming a second conductive structure in the device region, including: Thinning the second surface of the substrate so that a portion of the substrate in the device region is retained and the substrate in the first isolation region and the second isolation region is removed; The second conductive structure is formed on the surface of the substrate where the device region is retained, and the second conductive structure connects the corresponding second semiconductor material regions.

11. The forming method according to claim 10, characterized in that: When thinning the second surface of the substrate, the first isolation region is used as a thinning stop region.

12. The forming method according to claim 10, characterized in that: When the second surface of the substrate is thinned, the second isolation region is not thinned, and a surface of the first semiconductor region is exposed by a surface of the second isolation region.

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