Switched capacitor and capacitor array layout structure

Abstract

The invention discloses a switched capacitor and a capacitor array layout structure, the switched capacitor comprises an upper pole plate with an upper pole plate metal wire and a lower pole plate with two opposite lower pole plate metal wires, the upper pole plate metal wire is located between the two lower pole plate metal wires and forms an interdigital structure, and the lower pole plate further comprises an upper metal cover plate and a lower metal cover plate; the upper metal cover plate is located on the upper layer of the upper pole plate metal wire and the lower pole plate metal wire, the lower metal cover plate is located on the lower layer of the upper pole plate metal wire and the lower pole plate metal wire, and the upper metal cover plate and the lower metal cover plate are connected with the lower pole plate metal wire through through holes; the upper pole plate metal wire is surrounded among the two opposite lower pole plate metal wires, the upper metal cover plate and the lower metal cover plate so as to reduce stray capacitance and signal attenuation from the upper pole plate to the ground. According to the invention, the stray capacitance from the upper pole plate to the ground is greatly reduced, the signal attenuation is reduced, and the problem that the upper pole plate of the existing interdigital capacitor is easily influenced by noise on external wiring is also solved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a switch capacitor and a capacitor array layout structure. Background Art

[0002] In digital-to-analog converters, switched capacitor circuits are one of the most commonly used circuits. The design of capacitor arrays and connected capacitor switches is the key point of digital-to-analog converters. In the integrated circuit layout, the matching of the capacitor array and the circuit parasitic capacitance will directly affect the design accuracy of the digital-to-analog converter.

[0003] Existing capacitors are usually used as Figure 1 In the structure of the interdigital capacitor shown in the figure, the two plates of the existing interdigital capacitor are usually distributed left and right, and are stacked up and down in the same way through multiple layers of metal. However, this structure will cause a large parasitic capacitance from the two plates to the ground, which will cause significant attenuation of the signal. In addition, since there is no shielding around the plates of the interdigital capacitor, the upper plate will be seriously affected by the noise of the surrounding circuits.

[0004] Based on this, a new technical solution is needed. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a switch capacitor and a capacitor array layout structure to at least solve the problem that the parasitic capacitance of the existing interdigital capacitor is large and the upper plate is easily affected by the surrounding circuit noise.

[0006] The embodiment of the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a switched capacitor, comprising an upper plate having an upper plate metal wire and a lower plate having two opposite lower plate metal wires, wherein the upper plate metal wire is located between the two lower plate metal wires and forms an interdigitated structure, the upper plate metal wire and the corresponding two lower plate metal wires are located in the same metal layer, the lower plate further comprises an upper metal cover plate and a lower metal cover plate, and both the upper metal cover plate and the lower metal cover plate are metal plate structures;

[0008] The upper metal cover plate is located at the upper metal layer of the upper plate metal wire and the lower plate metal wire, the lower metal cover plate is located at the lower metal layer of the upper plate metal wire and the lower plate metal wire, and the upper metal cover plate and the lower metal cover plate are both connected to the lower plate metal wire through a through hole;

[0009] The upper electrode plate metal wire is surrounded by the two lower electrode plate metal wires spaced apart in the horizontal left-right direction, and the upper electrode plate metal wire is surrounded by the upper metal cover plate and the lower metal cover plate in the vertical up-down direction.

[0011] Furthermore, the upper electrode plate metal wire includes an upper electrode plate main metal wire and a plurality of upper electrode plate finger metal wires, and the plurality of upper electrode plate finger metal wires cross the upper electrode plate main metal wire along an extension direction of the upper electrode plate main metal wire.

[0012] Further, the lower electrode plate metal wire includes a plurality of lower electrode plate finger metal structures, and the finger metal structures include at least two lower electrode plate finger metal wires arranged at intervals and a lower electrode plate connecting metal wire connecting the two lower electrode plate finger metal wires;

[0013] The portion of the upper plate finger metal wire located on one side of the upper plate main metal wire is inserted into the corresponding lower plate finger metal structure or between two adjacent lower plate finger metal structures.

[0014] Furthermore, the upper plate metal wire and the lower plate metal wire are both multi-layer structures, and in each layer of the structure, the upper plate metal wire is located between the two lower plate metal wires;

[0015] Wherein, adjacent upper plate metal wires and adjacent lower plate metal wires are connected via through holes.

[0016] Furthermore, the two lower electrode plate metal wires, the upper metal cover plate and the lower metal cover plate are located in different metal layers, and the upper metal cover plate and the lower metal cover plate at least completely cover the upper electrode plate metal wires.

[0017] Furthermore, an outlet for connecting the upper plate metal wire to an external device is reserved between the two lower plate metal wires.

[0018] Furthermore, the spacing between the upper plate metal wire and the lower plate metal wire is the minimum spacing required by design rules.

[0019] The present invention also provides a capacitor array layout structure, comprising a capacitor array composed of a plurality of switch capacitors as described above;

[0020] Among them, the upper plate metal wire of the switching capacitor is connected in sequence through the opening reserved between the two lower plate metal wires, and the lower plate cover or upper plate cover of the switching capacitor is connected in sequence, so that each upper plate of the capacitor array is surrounded by the lower plate of the capacitor array.

[0021] Furthermore, the capacitor array layout also includes a capacitor switch array, and the capacitor switch array includes a plurality of capacitor switches;

[0022] The capacitor switch array is disposed at a lower layer of the capacitor array, and each of the switch capacitors is connected to a capacitor switch at the lower layer through a through hole.

[0023] Furthermore, the capacitor array layout structure also includes:

[0024] A shielding metal layer is arranged on an upper layer of the capacitor array so as to make the parasitic capacitance of the lower plate of the switch capacitor proportionally matched.

[0025] Compared with the prior art, the at least one technical solution adopted in the embodiment of the present invention can achieve the following beneficial effects:

[0026] A switching capacitor of the present invention is provided with an upper metal cover plate on the upper layer of an upper plate metal wire, a lower metal cover plate on the lower layer of the upper plate metal wire, and the upper plate metal wire is provided between two opposite lower plate metal wires on the same layer, so that the two lower plate metal wires, the upper metal cover plate and the lower metal cover plate surround the upper plate metal wire, thereby greatly reducing the parasitic capacitance from the upper plate to the ground, reducing signal attenuation, and also solving the problem that the upper plate of the existing interdigital capacitor is easily affected by noise on the external wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0028] Figure 1 It is a structural schematic diagram of an existing interdigital capacitor;

[0029] Figure 2 is a schematic diagram of an existing SAR ADC switched capacitor circuit;

[0030] Figure 3 A side view of a switch capacitor having a single-layer upper plate in the present application;

[0031] Figure 4 A side view of a switch capacitor having a double-layer upper plate in the present application;

[0032] Figure 5 A schematic diagram of the positions of an upper plate and a lower plate in a switched capacitor of the present application;

[0033] Figure 6 A top view of a switched capacitor of the present application;

[0034] Figure 7 A top view of a lower plate metal wire of different shapes in a switch capacitor of the present application;

[0035] Figure 8 A schematic diagram of a capacitor array of the present application;

[0036] Fig. 9 A test schematic diagram of a capacitor array layout structure of the present application.

[0037] The accompanying drawings of the present invention are as follows:

[0038] 1. Switching capacitor;

[0039] 10. upper electrode plate; 11. upper electrode plate metal wire; 111. upper electrode plate main metal wire; 112. upper electrode plate finger metal wire;

[0040] 20. Lower plate; 21. Lower plate metal wire; 211. Lower plate finger metal structure; 22. Upper metal cover; 23. Lower metal cover; 24. Exit;

[0041] 2. Capacitor array;

[0042] 3. Capacitive switch array;

[0043] 4. Shielding metal layer;

[0044] 5. Through hole. DETAILED DESCRIPTION

[0045] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0046] The following describes the implementation methods of the present application through specific examples, and those skilled in the art can easily understand other advantages and effects of the present application from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation methods, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, in the absence of conflict, the following embodiments and the features in the embodiments can be combined with each other. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work belong to the scope of protection of the present application.

[0047] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present application, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspect described herein can be used to implement the device and / or practice the method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this device and / or practice this method.

[0048] It should also be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. The drawings only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0049] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the examples can be practiced without these specific details.

[0050] like Figure 2 As shown, Figure 2 This is the schematic diagram of a common SAR ADC switch capacitor circuit. Nodes Vp and Vn are input signals, switches SW1 and SW2 are signal input switches, and capacitors 16X, 8X, 4X, 2X, and 1X form a capacitor array, where the numbers represent the ratio of the capacitors, 1X is the unit capacitor, and 16X is 16 times the unit capacitor. The upper plates of all capacitors are connected together, and the lower plates of the capacitors are connected to the corresponding switches SWB1 and SWB0 respectively, and the lower plates of each capacitor are not connected.

[0051] Among them, the key parameters that affect the performance of SAR ADC include the following:

[0052] 1. The matching of the capacitor array, that is, the ratio of the capacitance values ​​must be kept accurate to improve the linearity of the capacitor array 2;

[0053] 2. The parasitic capacitance from the top plate of the capacitor array to the ground (Cp_top in the figure) should be minimized to reduce signal attenuation;

[0054] 3. The upper plate of the capacitor is noise sensitive;

[0055] 4. The parasitic capacitance from the lower plate of the capacitor to the ground (Cp_16X, ..., Cp_1X in the figure) should be matched as proportionally as possible. This capacitance will affect the charge distribution on the lower plate of the capacitor in the capacitor array, thereby affecting the linearity of the entire capacitor array.

[0056] Since the existing interdigital capacitors are distributed left and right, and multiple layers of metal are stacked up and down in the same way, although this type of interdigital capacitor has a simple structure and high capacitance density, its use in the ADC capacitor array will cause large parasitic capacitance from both plates to the ground, which has a great impact on signal attenuation. In addition, since the upper plate of the capacitor is not shielded, the upper plate will be greatly affected by the surrounding capacitor noise, which will undoubtedly affect the key parameters of the SAR ADC performance.

[0057] Based on this, this specification embodiment proposes a processing solution: Figures 3 to 5 As shown, a switching capacitor 1 of the present invention is composed of at least three layers of metal, wherein the top and bottom layers are metal cover plates formed by a whole piece of metal, and the middle layer or layers of metal are interdigitated capacitor structures. In addition, the switching capacitor 1 of the present invention is changed from the original left and right plates to inner and outer plates, so that the upper plate 10 of the capacitor is completely surrounded by the lower plate 20, thereby greatly reducing the parasitic capacitance to the ground, reducing signal attenuation, and the noise of the external routing is not easily coupled to the upper plate 10 of the capacitor.

[0058] The technical solutions provided by various embodiments of the present application are described below in conjunction with the accompanying drawings.

[0059] Example 1

[0060] like Figures 3 to 5 As shown, a switch capacitor 1 of the present invention comprises an upper plate 10 having an upper plate metal wire 11 and a lower plate 20 having two opposite lower plate metal wires 21, the upper plate metal wire 11 is located between the two lower plate metal wires 21 and forms an interdigitated structure, the upper plate metal wire 11 and the corresponding two lower plate metal wires are located in the same metal layer, the lower plate 20 further comprises an upper metal cover plate 22 and a lower metal cover plate 23, both of which are metal plate structures; the upper metal cover The plate 22 is located at the upper metal layer of the upper plate metal wire 11 and the lower plate metal wire 21, and the lower metal cover plate 23 is located at the lower metal layer of the upper plate metal wire 11 and the lower plate metal wire 21. The upper metal cover plate 22 and the lower metal cover plate 23 are both connected to the lower plate metal wire 21 through the through hole 5; wherein, the upper plate metal wire 11 is surrounded by two opposite lower plate metal wires 21, the upper metal cover plate 22, and the lower metal cover plate 23 to reduce the parasitic capacitance and signal attenuation from the upper plate 10 to the ground.

[0061] The upper plate metal wire 11 is surrounded by two lower plate metal wires 21 arranged at intervals in the horizontal left-right direction, and the upper plate metal wire 11 is surrounded by an upper metal cover plate 22 and a lower metal cover plate 23 in the vertical up-down direction, so as to fully surround the upper plate metal wire 11 in the horizontal left-right direction and the vertical up-down direction, so as to avoid generating parasitic capacitance or coupling of external noise to the upper plate 10.

[0062] The two lower electrode plate metal wires 21 , the upper metal cover plate 22 and the lower metal cover plate 23 are located in different metal layers, and the upper metal cover plate 22 and the lower metal cover plate 23 at least completely cover the upper electrode plate metal wire 11 .

[0063] Specifically, the interdigital structure formed between the upper electrode plate metal wire 11 and the lower electrode plate metal wire 21 is located on the same metal layer, the upper metal cover plate 22 is located on the upper metal layer of the upper electrode plate metal wire 11 and the lower electrode plate metal wire 21, and the lower metal cover plate 23 is located on the lower metal layer of the upper electrode plate metal wire 11 and the lower electrode plate metal wire 21.

[0064] The upper plate 10 metal cover and the lower plate 20 metal cover are both metal covers formed of a whole piece of metal, so they can isolate the noise on the external wiring and prevent the noise on the external wiring from coupling to the upper plate 10 of the capacitor.

[0065] The present application utilizes upper and lower metal cover plates 23 to surround the upper electrode plate metal wire 11 in the longitudinal direction, and utilizes two opposite lower electrode plate metal wires 21 to surround the upper electrode plate metal wire 11 in the transverse direction, thereby achieving full enclosure of the upper electrode plate 10 by the lower electrode plate 20, so as to effectively reduce the parasitic capacitance from the upper electrode plate 10 to the ground, and reduce signal attenuation and external noise interference, thereby significantly improving the performance and reliability of the digital-to-analog / analog-to-digital converter.

[0066] In some of the embodiments, the inter-finger capacitor formed between the upper plate metal line 11 and the lower plate metal line 21 may be the same as that in the prior art.

[0067] In some of the embodiments, Figures 6-7 As shown, the upper electrode plate metal wire 11 includes an upper electrode plate main metal wire 111 and a plurality of upper electrode plate finger metal wires 112, and the plurality of upper electrode plate finger metal wires 112 cross the upper electrode plate main metal wire 111 along the extension direction of the upper electrode plate main metal wire 111; the lower electrode plate metal wire 21 includes a plurality of lower electrode plate finger metal structures 211, and the finger metal structure includes at least two spaced lower electrode plate 20 finger metal wires and a lower electrode plate 20 connecting metal wire connecting the two lower electrode plate 20 finger metal wires; the portion of the upper electrode plate finger metal wire 112 located on one side of the upper electrode plate main metal wire 111 is inserted into the corresponding lower electrode plate finger metal structure 211 or between two adjacent lower electrode plate finger metal structures 211 to form a finger capacitor structure.

[0068] Among them, the upper plate metal wire 11 as a whole can be a comb structure or a cross-shaped structure, and the upper plate metal wire 11 on the same metal layer is surrounded by the lower plate metal wires 21 on both sides thereof.

[0069] Among them, by distributing a plurality of upper plate finger metal wires 112 along the extension direction of the upper plate main metal wire 111, after forming the switched capacitor 1 in cooperation with the lower plate metal wire 21, the effective area of the switched capacitor 1 can be increased and the capacitance can be improved.

[0070] Among them, the lower plate finger metal structure 211 can be a "匚" structure, and at least a part of the upper plate finger metal wire 112 is inserted into the lower plate finger metal structure 211.

[0071] More specifically, the lower plate metal wire 21 is formed by juxtaposing or spacing a plurality of lower plate finger metal structures 211 to surround the upper plate finger metal wire 112.

[0072] For example, as Figure 7 shown, the lower plate metal wire 21 can be an E-shaped structure or two "匚" structures arranged at intervals up and down.

[0073] Among them, both the upper plate metal wire 11 and the lower plate metal wire 21 are made of high-conductivity materials.

[0074] Further, an outlet 24 for connecting the upper plate metal wire 11 to an external device is reserved between the two lower plate metal wires 21, so that the upper plates 10 between different switched capacitors 1 can be connected through the reserved outlet 24 to form a capacitor array 2.

[0075] In some of the embodiments, both the upper plate metal wire 11 and the lower plate metal wire 21 are multi-layer structures, and the upper plate metal wire 11 is located between the two lower plate metal wires 21 in each layer structure; among them, the adjacent upper plate metal wires 11 and the adjacent lower plate metal wires 21 are connected through through-holes.

[0076] Specifically, an upper plate metal wire 11 and lower plate metal wires 21 located on both sides of the upper plate metal wire 11 are provided in each metal layer.

[0077] For example, as Figure 4 shown, both the upper plate metal wire 11 and the lower plate metal wire 21 are two-layer structures and are located on different metal layers, and the upper plate metal wire 11 and the lower plate metal wire 21 on the upper and lower metal layers are connected to each other through a through-hole 5.

[0078] Further, the distance between the upper plate metal wire 11 and the lower plate metal wire 21 is the minimum distance required by the design rules.

[0079] The focus of the present invention is that the lower plate 20 includes an upper metal cover plate and a lower metal cover plate, and the cover plate is a complete metal, so as to tightly wrap the upper plate 10 in the middle of the lower plate 20, so that an internal and external structure is formed between the upper plate 10 and the lower plate 20, so as to greatly reduce the parasitic capacitance of the upper plate, and avoid external line noise from coupling to the upper plate 10, thereby improving the working stability and reliability of the switching capacitor 1 in a complex environment.

[0080] Example 2

[0081] like Figures 8-9 As shown, a capacitor array layout structure of the present invention includes a capacitor array 2 composed of multiple switch capacitors 1 as described in any one of Example 1; wherein, the upper plate metal wire 11 of the switch capacitor 1 is connected in sequence from the opening reserved between the two lower plate metal wires 21, and the lower plate 20 cover plate or the upper plate 10 cover plate of the switch capacitor 1 is connected in sequence, so that the upper plate 10 in the capacitor array 2 is always surrounded by the lower plate 20 of the capacitor array 2.

[0082] Among them, the upper plates 10 of multiple switching capacitors 1 are connected through the front and rear outlets 24, and the lower plates 20 are connected at the upper metal cover plate 22 or the lower metal cover plate 23, so as to form a capacitor array 2 with different multiples of unit capacitance (such as 1X, 2X, 4X... capacitor array 2). After such connection, the upper plate 10 in the capacitor array 2 is always surrounded by the lower plate 20 of the capacitor array 2, so as to reduce parasitic capacitance and prevent external line noise from coupling to the upper plate 10.

[0083] Among them, after the capacitor array 2 is formed, the value of each unit capacitance of the additional capacitance caused by the connection of the upper electrode plate 10 is the same, and the additional capacitance caused by the connection of the lower electrode plate 20 is also very small and can be ignored, thereby ensuring the linearity of the capacitor array 2.

[0084] The lower electrode plate 20 of this embodiment can surround the upper electrode plate 10 in both the horizontal left-right direction and the vertical up-down direction, thereby effectively reducing external interference and parasitic capacitance, so that the switching capacitor 1 has better electrical performance and environmental adaptability, thereby significantly improving the reliability and accuracy of the overall circuit.

[0085] In some of the embodiments, the capacitor array 2 layout structure also includes a capacitor switch array 3, which includes multiple capacitor switches; the capacitor switch array 3 is arranged in the lower layer of the capacitor array 2, and each switch capacitor 1 is connected to a capacitor switch in the lower layer through a through hole to simplify the connection between the capacitor switch and the switch capacitor 1, thereby improving the matching degree of the parasitic capacitance of the capacitor lower plate 20.

[0086] Specifically, by disposing the capacitor switch array 3 below the capacitor array 2 and disposing a capacitor switch at the lower layer of each switch capacitor 1 (unit capacitor), the parasitic capacitance from the capacitor lower plate 20 to the ground can be proportionally matched.

[0087] In this embodiment, the layout of the capacitor switch array 3 is set below the layout of the capacitor array 2. Since the bottom layer of the lower electrode plate 20 is a flat plate (lower metal cover plate 23), the capacitor switch can be easily connected to the capacitor lower electrode plate 20, and the connection lines for each switch capacitor 1 are the same, thereby reducing the mismatch caused by different connections, thereby improving the linearity of the capacitor array 2.

[0088] Furthermore, the layout structure of the capacitor array 2 also includes a shielding metal layer 4, which is arranged on the upper layer of the capacitor array 2 to make the parasitic capacitance of the lower plate 20 of the switching capacitor 1 proportionally matched and prevent the upper layer wiring from interfering with the noise of the capacitor lower plate 20.

[0089] For example, in actual applications, the capacitor switch array 3 is set in the first metal layer, the second metal layer, and the third metal layer (the first metal layer is the bottom layer), the switch capacitor 1 array is set in the fourth metal layer, the fifth metal layer, and the sixth metal layer, and the capacitor switch and the switch capacitor 1 are connected through a through hole; the shielding metal layer 4 is applied as the shielding metal layer 4, and the shielding metal layer 4 is not connected to the switch capacitor 1.

[0090] The upper plate 10 of the capacitor of the present invention is surrounded by the lower plate 20 of the capacitor, leaving only the front and rear outlets 24, thereby reducing the parasitic capacitance from the upper plate 10 to the ground and preventing noise interference; and the switch layout of the capacitor array 2 is arranged directly below the capacitor, which simplifies the connection between the switch and the capacitor, improves the matching degree of the parasitic capacitance of the lower plate 20 of the capacitor, effectively reduces the parasitic capacitance from the upper plate 10 to the ground, avoids the noise of the external line interfering with the upper plate 10 and the lower plate 20, and at the same time makes the parasitic capacitance from the lower plate 20 to the ground proportionally matched to ensure the linearity of the entire capacitor array 2.

[0091] In this specification, the same or similar parts between the various embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the product embodiment described later, since it corresponds to the method, the description is relatively simple, and the relevant parts can be referred to the partial description of the system embodiment.

[0092] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A switched capacitor, comprising an upper plate having an upper plate metal wire and a lower plate having two opposite lower plate metal wires, wherein the upper plate metal wire is located between the two lower plate metal wires to form an interdigitated structure, characterized in that: The upper electrode plate metal wire and the corresponding two lower electrode plate metal wires are located in the same metal layer, and the lower electrode plate further comprises an upper metal cover plate and a lower metal cover plate, and the upper metal cover plate and the lower metal cover plate are both metal plate structures; The upper metal cover plate is located at the upper metal layer of the upper plate metal wire and the lower plate metal wire, and the lower metal cover plate is located at the lower metal layer of the upper plate metal wire and the lower plate metal wire; the upper metal cover plate and the lower metal cover plate are both connected to the lower plate metal wire through through holes to reduce the parasitic capacitance of the upper plate; The upper electrode plate metal wire is surrounded by the two lower electrode plate metal wires spaced apart in the horizontal left-right direction, and the upper electrode plate metal wire is surrounded by the upper metal cover plate and the lower metal cover plate in the vertical up-down direction.

2. The switched capacitor according to claim 1, characterized in that: The upper electrode plate metal wire comprises an upper electrode plate main metal wire and a plurality of upper electrode plate finger metal wires, wherein the plurality of upper electrode plate finger metal wires cross the upper electrode plate main metal wire along an extension direction of the upper electrode plate main metal wire.

3. The switched capacitor according to claim 2, characterized in that: The lower electrode plate metal wire comprises a plurality of lower electrode plate finger metal structures, wherein the finger metal structures comprise at least two lower electrode plate finger metal wires arranged at intervals and a lower electrode plate connecting metal wire connecting the two lower electrode plate finger metal wires; The portion of the upper plate finger metal wire located on one side of the upper plate main metal wire is inserted into the corresponding lower plate finger metal structure or between two adjacent lower plate finger metal structures.

4. The switched capacitor according to any one of claims 1 to 3, characterized in that: The upper plate metal wire and the lower plate metal wire are both multi-layer structures, and the upper plate metal wire in each layer structure is located between the two lower plate metal wires; Wherein, adjacent upper plate metal wires and adjacent lower plate metal wires are connected via through holes.

5. The switched capacitor according to claim 1, characterized in that: The two lower electrode plate metal wires, the upper metal cover plate and the lower metal cover plate are located in different metal layers, and the upper metal cover plate and the lower metal cover plate at least completely cover the upper electrode plate metal wires.

6. The switched capacitor according to claim 1, characterized in that: An outlet for connecting the upper plate metal wire to an external device is reserved between the two lower plate metal wires.

7. The switched capacitor according to claim 1, characterized in that: The spacing between the upper plate metal wire and the lower plate metal wire is the minimum spacing required by the design rules.

8. A capacitor array layout structure, characterized in that: A capacitor array comprising a plurality of switch capacitors as claimed in any one of claims 1 to 7; Among them, the upper plate metal wire of the switching capacitor is connected in sequence through the opening reserved between the two lower plate metal wires, and the lower plate cover or upper plate cover of the switching capacitor is connected in sequence, so that each upper plate of the capacitor array is surrounded by the lower plate of the capacitor array.

9. The capacitor array layout structure according to claim 8, characterized in that: Also included is a capacitive switch array, the capacitive switch array comprising a plurality of capacitive switches; The capacitor switch array is disposed at a lower layer of the capacitor array, and each of the switch capacitors is connected to a capacitor switch at the lower layer through a through hole.

10. The capacitor array layout structure according to claim 8, characterized in that: Also includes: A shielding metal layer is arranged on an upper layer of the capacitor array so as to make the parasitic capacitance of the lower plate of the switch capacitor proportionally matched.

Images