Semiconductor Structure and Method for Forming the Same

Abstract

An embodiment of the present disclosure provides a semiconductor structure and a method for forming the same. The method for forming the semiconductor structure includes: forming a patterned first metal nitride layer on a substrate structure; performing an oxidation treatment on the sidewalls and the top surface exposed by the first metal nitride layer; the first dielectric layer includes a first metal oxide layer and a first metal oxynitride layer located between the first metal oxide layer and the remaining first metal nitride layer; forming a patterned second metal nitride layer on the exposed substrate structure and on the first dielectric layer.

Description

Technical Field

[0001] The present disclosure relates to, but is not limited to, a semiconductor structure and a method for forming the same. Background Art

[0002] In semiconductor integrated circuits, integrated capacitors fabricated on the same chip as transistor circuits are widely used. With the continuous improvement of the requirements for semiconductor integrated circuit density and the continuous increase in the demand for capacitor capacitance, capacitors also face many challenges during the manufacturing process. Summary of the Invention

[0003] According to a first aspect of an embodiment of the present disclosure, there is provided a method for forming a semiconductor structure, including: providing a substrate structure; forming a patterned first metal nitride layer on the substrate structure; performing an oxidation treatment on sidewalls and a top surface exposed by the first metal nitride layer to form a first dielectric layer covering the remaining first metal nitride layer; the first dielectric layer includes a first metal oxide layer and a first metal oxynitride layer located between the first metal oxide layer and the remaining first metal nitride layer; forming a patterned second metal nitride layer on the exposed substrate structure and on the first dielectric layer.

[0004] In some embodiments, forming the patterned first metal nitride layer on the substrate structure includes: forming a first metal nitride material layer on the substrate structure; performing photolithography and etching processes on the first metal nitride material layer to form the patterned first metal nitride layer.

[0005] In some embodiments, when performing the oxidation treatment on sidewalls and the top surface exposed by the first metal nitride layer, the oxidation temperature ranges from 150 °C to 300 °C.

[0006] In some embodiments, when performing the oxidation treatment on sidewalls and the top surface exposed by the first metal nitride layer, the oxidation gas includes oxygen or ozone.

[0007] In some embodiments, the material of the first metal nitride layer includes titanium nitride or tantalum nitride.

[0008] In some embodiments, the thickness range of the first metal oxide layer and the thickness range of the first metal oxynitride layer are both from 1 nm to 10 nm.

[0009] In some embodiments, the method further includes: oxidizing sidewalls and a top surface of the exposed second metal nitride layer to form a second dielectric layer covering the remaining second metal nitride layer; the second dielectric layer includes a second metal oxide layer and a second metal oxynitride layer located between the second metal oxide layer and the remaining second metal nitride layer; forming a patterned third metal nitride layer on the second dielectric layer and the exposed first dielectric layer.

[0010] In some embodiments, the method further includes: oxidizing sidewalls and a top surface of the exposed third metal nitride layer to form a third dielectric layer covering the remaining third metal nitride layer; the third dielectric layer includes a third metal oxide layer and a third metal oxynitride layer located between the third metal oxide layer and the remaining third metal nitride layer; forming a fourth metal nitride material layer on the third dielectric layer, the exposed second dielectric layer, and the exposed substrate structure; performing photolithography and etching processes on the fourth metal nitride material layer to form a patterned fourth metal nitride layer.

[0011] In some embodiments, the substrate structure includes a device layer and an interconnect layer located on the device layer; the device layer includes a plurality of semiconductor devices, the interconnect layer includes a plurality of interconnect structures, and the semiconductor devices are connected to the interconnect structures; the method further includes: forming an insulating layer covering the third metal nitride layer; forming a first contact structure and a second contact structure in the insulating layer; the first contact structure penetrates through the third metal nitride layer, the second dielectric layer, and the second metal nitride layer and is connected to the interconnect structure; the second contact structure penetrates through the third metal nitride layer, the first dielectric layer, and the first metal nitride layer and is connected to the interconnect structure.

[0012] According to a second aspect of embodiments of the present disclosure, there is provided a semiconductor structure, the semiconductor structure including: a capacitor; the capacitor includes: a first electrode plate including a first metal nitride structure; a second electrode plate including a second metal nitride structure at least partially located on the first metal nitride structure; a dielectric layer including a first dielectric structure; the first dielectric structure covers sidewalls and a top surface of the first metal nitride structure; the first dielectric structure includes a first metal oxide structure and a first metal oxynitride structure located between the first metal oxide structure and the first metal nitride structure.

[0013] In an embodiment of the present disclosure, after forming a patterned first metal nitride layer, the sidewalls and the top surface of the patterned first metal nitride layer are oxidized, so as to form a first dielectric layer on the top surface and the sidewalls of the remaining first metal nitride layer, wherein the remaining first metal nitride layer can be used as a capacitor plate, and the formed first dielectric layer can be used as the dielectric layer between the plates. In a first aspect, in the present disclosure, forming the dielectric layer does not require lithography and etching after a deposition process. In the embodiment of the present disclosure, the dielectric layer is obtained by oxidizing the sidewalls and the top surface of the patterned first metal nitride layer, so as to avoid damage to the device and the capacitor caused by high temperature in the deposition process. In a second aspect, the dielectric layer in the embodiment of the present disclosure is formed in a self-aligned manner without lithography and etching, which simplifies the process steps, saves the process cost, and improves the production efficiency. In a third aspect, after oxidizing the exposed sidewalls and the top surface of the patterned first metal oxide layer, the formed first dielectric layer includes a first metal oxide layer and a first metal oxynitride layer. The first metal oxynitride layer can be used as a buffer layer between the first metal oxide layer and the remaining first metal nitride layer, improving the interface quality between the first metal nitride layer and the first metal oxide layer, enhancing the adhesion between the first metal nitride layer and the first metal oxide layer, and playing a role in stress matching so that the first metal oxide layer is not easily peeled off. In a fourth aspect, the first metal oxynitride layer can be used as a barrier layer for fluorine diffusion in subsequent etching processes. The first metal oxynitride layer can reduce the adsorption and diffusion of fluorine during the etching process, thereby protecting the semiconductor device and the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0015] Figure 2 is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present disclosure Figure 1 ;

[0016] Figure 3 is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present disclosure Figure 2 ;

[0017] Figure 4 is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present disclosure Figure 3 ;

[0018] Figure 5 is a schematic structural diagram of the formation process of a semiconductor structure according to an embodiment of the present disclosure Figure 4 ;

[0019] Figure 6Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 5 ;

[0020] Figure 7 Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 6 ;

[0021] Figure 8 Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 7 ;

[0022] Figure 9 Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 8 ;

[0023] Figure 10 Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 9 ;

[0024] Figure 11 Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 10 ;

[0025] Figure 12 Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 10 One;

[0026] Figure 13 Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 10 Two;

[0027] Figure 14 Schematic of the formation process of a semiconductor structure provided by an embodiment of the present disclosure Figure 10 Three;

[0028] Figure 15 Schematic of the semiconductor structure provided by an embodiment of the present disclosure Figure 1 ;

[0029] Figure 16 Schematic of the semiconductor structure provided by an embodiment of the present disclosure Figure 2 ;

[0030] Figure 17 Schematic of the semiconductor structure provided by an embodiment of the present disclosure Figure 3 。 Detailed implementation manners

[0031] Exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure can be more thoroughly understood and the scope of the present disclosure can be completely conveyed to those skilled in the art.

[0032] In the following description, numerous specific details are given to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present disclosure may be practiced without one or more of these details. In other instances, well-known features of some technologies are not described in order to avoid confusion with the present disclosure; that is, not all features of the actual embodiments are described here, and the well-known functions and structures are not described in detail.

[0033] In the drawings, for clarity, the dimensions of layers, regions, elements, and their relative dimensions may be exaggerated. Like reference numerals throughout the drawings denote like elements.

[0034] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Thus, without departing from the teachings of the present disclosure, the first element, component, region, layer, or portion discussed below may be referred to as the second element, component, region, layer, or portion. And when discussing the second element, component, region, layer, or portion, it does not imply that there must be a first element, component, region, layer, or portion in the present disclosure.

[0035] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures with other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are also intended to include different orientations of the device in use and operation. For example, if the device in the drawings is flipped, then an element or feature described as "under other elements" or "beneath them" or "below them" will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0036] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present disclosure. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0037] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are only for reference and illustration purposes and are not used to limit the embodiments of the present disclosure.

[0038] In semiconductor integrated circuits, integrated capacitors fabricated on the same chip as transistor circuits are widely used. Their forms mainly include metal-insulator-metal (MIM) capacitors and metal-oxide-metal (MOM) capacitors. MIM capacitors use upper and lower layer metals as capacitor plates, and the capacitance mainly depends on the area occupied by the capacitor.

[0039] With the continuous increase in the demand for capacitance in chips, it is necessary to select a HiK dielectric layer with a higher dielectric constant as the dielectric material for the capacitor in the process. Commonly used high dielectric constant thin films for capacitors currently are: zirconia, hafnium oxide, alumina, silicon nitride, etc. Titanium oxide (TiO2) and tantalum oxide (TaO2) thin films are also common high-K dielectric materials, but due to their relatively high film formation temperature, they will cause damage to the device and the capacitor, and are less used in MIM capacitor structures.

[0040] An embodiment of the present disclosure provides a method for forming a semiconductor structure, as Figure 1 shown, including the following steps: Step S1001: Provide a substrate structure; Step S1002: Form a patterned first metal nitride layer on the substrate structure; Step S1003: Oxidize the sidewalls and top surface of the exposed first metal nitride layer to form a first dielectric layer covering the remaining first metal nitride layer; the first dielectric layer includes a first metal oxide layer and a first metal oxynitride layer located between the first metal oxide layer and the remaining first metal nitride layer; Step S1004: Form a patterned second metal nitride layer on the exposed substrate structure and on the first dielectric layer.

[0041] In the embodiment of the present disclosure, after forming the patterned first metal nitride layer, the sidewalls and top surface of the patterned first metal nitride layer are oxidized, so as to form a first dielectric layer on the top surface and sidewalls of the remaining first metal nitride layer, wherein the remaining first metal nitride layer can be used as the electrode plate of the capacitor, and the formed first dielectric layer can be used as the dielectric layer between the electrode plates. First, in the present disclosure, forming the dielectric layer does not require lithography and etching after the deposition process. In the embodiment of the present disclosure, the dielectric layer is obtained by oxidizing the sidewalls and top surface of the patterned first metal nitride layer, so as to avoid damage to the device and the capacitor caused by high temperature in the deposition process; Second, the dielectric layer in the embodiment of the present disclosure is self-aligned and does not require lithography and etching, which simplifies the process steps, saves process costs, and improves production efficiency; Third, after oxidizing the sidewalls and top surface of the exposed patterned first metal oxide layer, the formed first dielectric layer includes a first metal oxide layer and a first metal oxynitride layer. The first metal oxynitride layer can be used as a buffer layer between the first metal oxide layer and the remaining first metal nitride layer, improving the interface quality between the first metal nitride layer and the first metal oxide layer, enhancing the adhesion between the first metal nitride layer and the first metal oxide layer, and playing a role in stress matching so that the first metal oxide layer is not easily peeled off; Fourth, the first metal oxynitride layer can be used as a barrier layer for fluorine diffusion in the subsequent etching process. The first metal oxynitride layer can reduce the adsorption and diffusion of fluorine during the etching process, thereby protecting the semiconductor device and the capacitor.

[0042] Figures 2 to 14 is a process schematic diagram of the method for forming a semiconductor structure provided by the embodiment of the present disclosure. The following will be combined with Figures 1 to 14 to further introduce the method for forming a semiconductor structure.

[0043] In step S1001, mainly a substrate structure is provided.

[0044] AsFigure 2 As shown, a substrate structure 101 is provided. In some specific examples, a substrate 114 may be provided first, a corresponding dielectric layer is formed on the substrate 114, and corresponding semiconductor devices and interconnect layers are formed in the dielectric layer.

[0045] In some embodiments, the substrate structure 101 includes a device layer and an interconnect layer located on the device layer; the device layer includes a plurality of semiconductor devices, and the interconnect layer includes a plurality of interconnect structures 115, and the semiconductor devices are connected to the interconnect structures 115.

[0046] In some specific examples, the material of the substrate 114 may include at least one of semiconductor materials such as silicon, germanium, and silicon germanide, and the semiconductor devices include but are not limited to CMOS transistors. The interconnect structure 115 includes a contact structure extending in the Z-axis direction and a conductive wire extending in a direction perpendicular to the Z-axis direction. The material of the dielectric layer includes but is not limited to silicon nitride and silicon oxide.

[0047] In some specific examples, the material of the contact structure and the material of the conductive wire both include a conductive material. Here, the conductive material may be a doped semiconductor material (for example, doped silicon, doped germanium, etc.), a conductive metal nitride (for example, titanium nitride, tantalum nitride, etc.), a metal material (for example, aluminum, copper, tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (for example, tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0048] In step S1002, mainly a patterned first metal nitride layer is formed on the substrate structure.

[0049] In some embodiments, forming the patterned first metal nitride layer on the substrate structure includes: as Figure 3 shown, a first metal nitride material layer 107 is formed on the substrate structure 101; as Figure 4 shown, a photolithography and etching process is performed on the first metal nitride material layer 107 to form a patterned first metal nitride layer 102.

[0050] In some specific examples, the first metal nitride material layer 107 can be formed by a deposition process. The deposition process includes but is not limited to Chemical Vapor Deposition (CVD), Low-Pressure Chemical Vapor Deposition (LPCVD), Plasma-Enhanced Chemical Vapor Deposition (PECVD), Physical Vapor Deposition (PVD), and Atomic Layer Deposition (ALD).

[0051] In some specific examples, a cleaning process is also required after etching. The etching process includes but is not limited to Plasma Etching (PE), Sputtering Etching (SE), Ion Beam Etching (IBE), and Reactive Ion Etching (RIE).

[0052] In some embodiments, the material of the first metal nitride layer 102 includes but is not limited to titanium nitride or tantalum nitride.

[0053] It should be noted that the materials of the first metal nitride layer 102 given in the above embodiments are only examples and are not used to limit the materials of the first metal nitride layer 102 in the embodiments of the present disclosure.

[0054] In step S1003, as Figure 5 shown, mainly the sidewalls and the top surface of the exposed first metal nitride layer 102 are oxidized to form a first dielectric layer 103 covering the remaining first metal nitride layer 102; as Figure 6 shown, the first dielectric layer 103 includes a first metal oxide layer 104 and a first metal oxynitride layer 105 located between the first metal oxide layer 104 and the remaining first metal nitride layer 102.

[0055] In the embodiments of the present disclosure, the first dielectric layer 103, the second dielectric layer and the third dielectric layer in the following text are all high-K dielectric materials, including dielectric materials having a high dielectric constant, for example, greater than the dielectric constant 3.9 of thermally oxidized silicon.

[0056] In the embodiments of the present disclosure, the material of the first metal oxynitride layer 105 is related to the materials of the first metal oxide layer 104 and the first metal nitride layer 102. Exemplarily, the material of the first metal oxide layer 104 is titanium nitride, the material of the first metal nitride layer 102 is titanium oxide, and the material of the first metal oxynitride layer 105 is titanium oxynitride. Exemplarily, the material of the first metal oxide layer 104 is tantalum nitride, the material of the first metal nitride layer 102 is tantalum oxide, and the material of the first metal oxynitride layer 105 is tantalum oxynitride.

[0057] In the embodiments of the present disclosure, along the direction from the first metal oxynitride layer to the first metal oxide layer, the mass proportion of nitrogen element in the first dielectric layer gradually decreases.

[0058] In some embodiments, when oxidizing the exposed sidewalls and top surface of the first metal nitride layer 102, the oxidation temperature ranges from 150 °C to 300 °C.

[0059] In some embodiments, when oxidizing the exposed sidewalls and top surface of the first metal nitride layer 102, the oxidation gas includes oxygen or ozone.

[0060] In some embodiments, the thickness ranges of both the first metal oxide layer 104 and the first metal oxynitride layer 105 are from 1 nm to 10 nm.

[0061] In the embodiments of the present disclosure, the oxidation degree can be controlled by controlling the oxidation time and oxidation temperature, so as to control the thicknesses of the first metal oxide layer 104 and the first metal oxynitride layer 105, reduce the adsorption of fluorine, thereby reducing the influence of fluorine on the capacitance, and improving the yield and reliability of the device.

[0062] In step S1004, a patterned second metal nitride layer is mainly formed on the exposed substrate structure and the first dielectric layer.

[0063] In some embodiments, forming a patterned second metal nitride layer on the exposed substrate structure and the first dielectric layer includes: as Figure 7 shown, forming a second metal nitride material layer 109 on the exposed substrate structure 101 and the first dielectric layer 103; as Figure 8 shown, performing photolithography and etching processes on the second metal nitride material layer 109 to form a patterned second metal nitride layer 106.

[0064] In some specific examples, the etching process herein includes, but is not limited to, plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE). A fluorine-containing etching gas is used in the etching process of the second metal nitride material layer 109, the third metal nitride material layer described hereinafter, and the fourth metal nitride material layer described hereinafter.

[0065] In some specific examples, the second metal nitride material layer 109 can be formed by a deposition process.

[0066] In some specific examples, the etching process can form a selectivity ratio by using the etching rate of the metal oxide and nitride layer, and stop on the first metal oxide layer 104.

[0067] In some embodiments, the material of the second metal nitride layer 106 includes titanium nitride or tantalum nitride.

[0068] It should be noted that the materials of the second metal nitride layer 106 given in the above embodiments are only examples and are not used to limit the materials of the first metal nitride layer 102 in the embodiments of the present disclosure.

[0069] The material of the first metal nitride layer 102 and the material of the second metal nitride layer 106 can be the same or different.

[0070] In some embodiments, as Figure 9 shown, the method further includes: oxidizing the exposed sidewalls and top surface of the second metal nitride layer 106 to form a second dielectric layer 108 covering the remaining second metal nitride layer 106; the second dielectric layer 108 includes a second metal oxide layer and a second metal oxynitride layer located between the second metal oxide layer and the remaining second metal nitride layer 106.

[0071] In the embodiments of the present disclosure, after forming the patterned second metal nitride layer 106, the sidewalls and top surface of the patterned second metal nitride layer 106 are oxidized, so as to form a second dielectric layer 108 on the top surface and sidewalls of the remaining second metal nitride layer 106, wherein the remaining second metal nitride layer 106 can be used as the electrode plate of the capacitor, and the formed second dielectric layer 108 can be used as the dielectric layer between the electrode plates.

[0072] In the embodiments of the present disclosure, during the process of etching the second metal nitride material layer 109, part of the first dielectric layer 103 may be consumed. When the sidewalls and the top surface of the patterned second metal nitride layer 106 are oxidized, the exposed first dielectric layer 103 and the first metal nitride layer 102 below the exposed first dielectric layer 103 will be further oxidized to achieve self-repair, playing a better isolation role and reducing the capacitance leakage current.

[0073] In some embodiments, when oxidizing the exposed sidewalls and the top surface of the second metal nitride layer 106, the oxidation temperature ranges from 150°C to 300°C.

[0074] In some embodiments, when oxidizing the exposed sidewalls and the top surface of the second metal nitride layer 106, the oxidation gas includes oxygen or ozone.

[0075] In some embodiments, the thickness range of the second metal oxide layer and the thickness range of the second metal oxynitride layer are both 1 nm to 10 nm.

[0076] In some embodiments, the method further includes: forming a patterned third metal nitride layer on the second dielectric layer and the exposed first dielectric layer.

[0077] In some embodiments, forming the patterned third metal nitride layer on the second dielectric layer and the exposed first dielectric layer includes: as Figure 10 shown, forming a third metal nitride material layer 112 on the second dielectric layer 108, the exposed first dielectric layer 103, and the exposed substrate structure 101; as Figure 11 shown, performing photolithography and etching on the third metal nitride material layer 112 to form a patterned third metal nitride layer 110.

[0078] In the embodiments of the present disclosure, the remaining first metal nitride layer 102 and the third metal nitride layer 110 can jointly serve as the first electrode plate of the capacitor, thereby increasing the capacitance density.

[0079] In some embodiments, the material of the third metal nitride layer 110 includes titanium nitride or tantalum nitride.

[0080] In the embodiments of the present disclosure, the material of the third metal oxide layer is the same as or different from that of the first metal oxide layer 104. The material of the third metal oxide layer is the same as or different from that of the second metal oxide layer.

[0081] In some specific examples, the third metal nitride material layer 112 can be formed by a deposition process.

[0082] In some specific examples, the etching process can utilize the etching rate selectivity of the metal oxide and nitride layers during etching to stop on the second metal oxide layer.

[0083] In some embodiments, the method further includes: as Figure 12 shown, forming an insulating layer 120 covering the third metal nitride layer 110; as Figure 13 shown, forming a first contact structure 116 and a second contact structure 117 in the insulating layer 120; the first contact structure 116 penetrates through the third metal nitride layer 110, the second dielectric layer 108, and the second metal nitride layer 106, and is connected to the interconnect structure 115; the second contact structure 117 penetrates through the third metal nitride layer 110, the first dielectric layer 103, and the first metal nitride layer 102, and is connected to the interconnect structure 115.

[0084] In some embodiments, as Figure 13 shown, the method further includes forming a third contact structure 118. The third contact structure 118 is connected to the interconnect structure 115.

[0085] In some specific examples, the material of the insulating layer 120 includes but is not limited to silicon oxide, silicon nitride.

[0086] In some embodiments, the method further includes forming a first conductive line 119 in the insulating layer 120.

[0087] In the embodiments of the present disclosure, as Figure 13 shown, the first conductive line 119 extends along the X-axis direction, and the first contact structure 116, the second contact structure 117, and the third contact structure 118 all extend along the Z-axis direction.

[0088] In some specific examples, the materials of the first conductive line 119, the first contact structure 116, the second contact structure 117, and the third contact structure 118 all include conductive materials. Here, the conductive material can be one of doped semiconductor materials (such as doped silicon, doped germanium, etc.), conductive metal nitrides (such as titanium nitride, tantalum nitride, etc.), metal materials (such as aluminum, copper, tungsten, titanium, tantalum, etc.), and metal semiconductor compounds (such as tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0089] In the embodiments of the present disclosure, the remaining second nitride layer is not entirely used to form the capacitor plates. For example, the second metal nitride layer includes as Figure 13The first part 124 and the second part 125 shown in [reference], the first part 124 of the second metal nitride layer is not connected to the second part 125, wherein the first part 124 of the second metal nitride layer is used as the electrode plate of the capacitor, while the second part 125 of the second metal nitride layer is not used as the electrode plate of the capacitor. The third metal nitride layer is not entirely used to form the electrode plate of the capacitor. For example, the third metal nitride layer includes the third part 126, the fourth part 127, and the fifth part 128 shown in [reference], and the third part 126, the fourth part 127, and the fifth part 128 are not connected to each other. Among them, neither the third part 126 nor the fifth part 128 is used as the electrode plate of the capacitor, and the fourth part 127 is used as the electrode plate of the capacitor. The second dielectric layer 108 is not entirely used as the dielectric layer of the capacitor. For example, the second dielectric layer 108 includes the sixth part 129 and the seventh part 130 shown in [reference], and the sixth part 129 is not connected to the seventh part 130. Among them, the sixth part 129 is used as the dielectric layer of the capacitor, while the seventh part 130 is not used as the dielectric layer of the capacitor. Figure 13 In the embodiment of the present disclosure, the first part 124 can be used as the second electrode plate of the capacitor, the fourth part 127 and the first metal nitride layer 102 can be used together as the first electrode plate of the capacitor, the first dielectric layer 103 and the sixth part 129 of the second dielectric layer 108 can be used together as the dielectric layer of the capacitor, the first contact structure 116 is connected to the second electrode plate of the capacitor, and the second contact structure 117 is connected to the first electrode plate of the capacitor. Figure 13 The first contact structure 116 penetrates through the first part 124, the sixth part 129, and the third part 126, the second contact structure 117 penetrates through the first metal nitride layer 102, the first dielectric layer 103, and the fourth part 127, and the third contact structure 118 penetrates through the second part 125, the seventh part 130, and the fifth part 128. That is to say, the number of dielectric layers and the number of metal nitride layers penetrated by the first contact structure 116, the second contact structure 117, and the third contact structure 118 are the same. This makes the environments of the contact holes at different positions similar when etching to form the corresponding contact holes, and reduces the etching load effect.

[0090] It should be noted that the patterned first metal nitride layer 102, the patterned second metal nitride layer 106, and the patterned third metal nitride layer 110 shown in [reference] are only one example. The pattern can also be adjusted by changing the mask in photolithography according to requirements, but it is necessary to ensure that the first contact structure 116 and the second contact structure 117 can respectively lead out the first electrode plate and the second electrode plate of the capacitor, and it is necessary to ensure that the number of metal nitride layers penetrated by the first contact structure 116, the second contact structure 117, and the third contact structure 118 is the same.

[0091] The first part 124 and the second part 125 shown in [reference], the first part 124 is not connected to the second part 125. Among them, the first part 124 of the second metal nitride layer is used as the electrode plate of the capacitor, while the second part 125 is not used as the electrode plate of the capacitor. The third metal nitride layer is not entirely used to form the electrode plate of the capacitor. For example, the third metal nitride layer includes the third part 126, the fourth part 127, and the fifth part 128 shown in [reference], and the third part 126, the fourth part 127, and the fifth part 128 are not connected to each other. Among them, neither the third part 126 nor the fifth part 128 is used as the electrode plate of the capacitor, and the fourth part 127 is used as the electrode plate of the capacitor. The second dielectric layer 108 is not entirely used as the dielectric layer of the capacitor. For example, the second dielectric layer 108 includes the sixth part 129 and the seventh part 130 shown in [reference], and the sixth part 129 is not connected to the seventh part 130. Among them, the sixth part 129 is used as the dielectric layer of the capacitor, while the seventh part 130 is not used as the dielectric layer of the capacitor.

[0092] It should be noted that Figure 13 The patterned first metal nitride layer 102, the patterned second metal nitride layer 106, and the patterned third metal nitride layer 110 shown in [reference] are only one example. The pattern can also be adjusted by changing the mask in photolithography according to requirements, but it is necessary to ensure that the first contact structure 116 and the second contact structure 117 can respectively lead out the first electrode plate and the second electrode plate of the capacitor, and it is necessary to ensure that the number of metal nitride layers penetrated by the first contact structure 116, the second contact structure 117, and the third contact structure 118 is the same.

[0093] In some embodiments, as Figure 14 shown, the method further includes: oxidizing sidewalls and a top surface of the exposed third metal nitride layer 110 to form a third dielectric layer 111 covering the remaining third metal nitride layer 110; the third dielectric layer 111 includes a third metal oxide layer and a third metal oxynitride layer located between the third metal oxide layer and the remaining third metal nitride layer 110; forming a fourth metal nitride material layer on the third dielectric layer 111, the exposed second dielectric layer 108, and the exposed substrate structure 101; performing photolithography and etching processes on the fourth metal nitride material layer to form a patterned fourth metal nitride layer 113.

[0094] In an embodiment of the present disclosure, sidewalls and a top surface of the exposed patterned third metal nitride layer 110 may be further oxidized to form a third dielectric layer 111 covering the remaining third metal nitride layer 110, thereby further increasing the capacitance density.

[0095] In as Figure 14 shown structure, a first electrode plate of the capacitor includes two metal nitride layers (a first metal nitride layer 102, a third metal nitride layer 110), a second electrode plate of the capacitor includes two metal nitride layers (a second metal nitride layer 106, a fourth metal nitride layer 113), a first contact structure 116 is connected to the second electrode plate, and a second contact structure 117 is connected to the first electrode plate.

[0096] In some embodiments, when oxidizing sidewalls and a top surface of the exposed third metal nitride layer 110, the oxidation temperature ranges from 150°C to 300°C.

[0097] In some embodiments, when oxidizing sidewalls and a top surface of the exposed third metal nitride layer 110, the oxidation gas includes oxygen or ozone.

[0098] In some embodiments, the thickness range of the third metal oxide layer and the thickness range of the third metal oxynitride layer are both from 1 nm to 10 nm.

[0099] In some embodiments, the material of the fourth metal nitride layer 113 includes titanium nitride or tantalum nitride. The material of the fourth metal nitride layer 113 may be the same as or different from the materials of the first metal nitride layer 102, the second metal nitride layer 106, and the third metal nitride layer 110.

[0100] Based on the above method for forming a semiconductor structure, an embodiment of the present disclosure further provides a semiconductor structure, as Figure 15As shown, the semiconductor structure includes: a capacitor; the capacitor includes: a first electrode plate 121, including a first metal nitride structure 131; a second electrode plate 122, including a second metal nitride structure 132 at least partially located on the first metal nitride structure 131; a dielectric layer 123, including a first dielectric structure 135; the first dielectric structure 135 covers the sidewalls and the top surface of the first metal nitride structure 131; the first dielectric structure 135 includes a first metal oxide structure and a first metal oxynitride structure located between the first metal oxide structure and the first metal nitride structure 131.

[0101] In some embodiments, as Figure 16 As shown, the semiconductor structure includes: a capacitor; the capacitor includes: a first electrode plate 121, including a first metal nitride structure 131 and a third metal nitride structure 133 located on the first metal nitride structure 131; a second electrode plate 122, including a second metal nitride structure 132; the second metal nitride structure 132 is at least located between the first metal nitride structure 131 and the third metal nitride structure 133; a dielectric layer 123, including a first dielectric structure 135 and a second dielectric structure 136; the first dielectric structure 135 covers the sidewalls and the top surface of the first metal nitride structure 131, and the second dielectric structure 136 covers the sidewalls and the top surface of the second metal nitride structure 132; the first dielectric structure 135 includes a first metal oxide structure and a first metal oxynitride structure located between the first metal oxide structure and the first metal nitride structure 131, and the second dielectric structure 136 includes a second metal oxide structure and a second metal oxynitride structure located between the second metal oxide structure and the second metal nitride structure 132.

[0102] In some embodiments, as Figure 17 As shown, the second electrode plate 122 further includes a fourth metal nitride structure 134 located on the second metal nitride structure 132; the third metal nitride structure 133 is at least located between the second metal nitride structure 132 and the fourth metal nitride structure 134; the dielectric layer 123 further includes a third dielectric structure 137; the third dielectric structure 137 covers the sidewalls and the top surface of the third metal nitride structure 133, and the third dielectric structure 137 includes a third metal oxide structure and a third metal oxynitride structure located between the third metal oxide structure and the third metal nitride structure 133.

[0103] In some embodiments, as Figure 15 、 Figure 16 and Figure 17As shown, the semiconductor structure further includes a first contact structure 116 and a second contact structure 117. The first contact structure 116 is connected to the second electrode plate 122, and the second contact structure 117 is connected to the first electrode plate 121.

[0104] In some embodiments, the materials of the first metal nitride structure, the second metal nitride structure, and the third metal nitride structure include, but are not limited to, titanium nitride or tantalum nitride.

[0105] In some embodiments, the materials of the first metal oxynitride structure, the second metal oxynitride structure, and the third metal oxynitride structure include, but are not limited to, titanium oxynitride or tantalum oxynitride.

[0106] In some embodiments, the materials of the first metal oxide structure, the second metal oxide structure, and the third metal oxide structure include, but are not limited to, titanium oxide or tantalum oxide.

[0107] In the embodiments of the present disclosure, the first metal nitride structure may be a part of the first metal nitride layer, the second metal nitride structure may be a part of the second metal nitride layer, the third metal nitride structure may be a part of the third metal nitride layer, and the fourth metal nitride structure may be a part of the fourth metal nitride layer. The first dielectric structure may be a part of the first dielectric layer, the second dielectric structure may be a part of the second dielectric layer, and the third dielectric structure may be a part of the third dielectric layer.

[0108] For other details of the semiconductor structure, reference may be made to the related introduction in the above-mentioned method for forming the semiconductor structure.

[0109] It should be understood that the term "one embodiment" or "an embodiment" mentioned throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of the present disclosure. Therefore, the appearances of "in one embodiment" or "in an embodiment" throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that in various embodiments of the present disclosure, the magnitudes of the sequence numbers of the above processes do not mean the order of execution, and the order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of the present disclosure. The sequence numbers of the embodiments of the present disclosure above are only for description and do not represent the advantages or disadvantages of the embodiments.

[0110] In the method embodiments disclosed in several method embodiments provided by the present disclosure, the methods can be arbitrarily combined without conflict to obtain new method embodiments.

[0111] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate structure; Forming a patterned first metal nitride layer on the substrate structure; Then, performing an oxidation treatment on the sidewalls and the top surface of the exposed first metal nitride layer to obtain a first dielectric layer covering the remaining first metal nitride layer; the first dielectric layer includes a first metal oxide layer and a first metal oxynitride layer located between the first metal oxide layer and the remaining first metal nitride layer; Directly forming a patterned second metal nitride layer on the exposed substrate structure and on the first dielectric layer; Performing an oxidation treatment on the sidewalls and the top surface of the exposed patterned second metal nitride layer to obtain a second dielectric layer covering the remaining second metal nitride layer; The second dielectric layer includes a second metal oxide layer and a second metal oxynitride layer located between the second metal oxide layer and the remaining second metal nitride layer; when performing the oxidation treatment on the sidewalls and the top surface of the exposed patterned second metal nitride layer, the exposed first dielectric layer and the first metal nitride layer under the exposed first dielectric layer will be further oxidized to achieve self-repair; Directly forming a patterned third metal nitride layer on the second dielectric layer and the exposed first dielectric layer.

2. The forming method according to claim 1, wherein The forming the patterned first metal nitride layer on the substrate structure includes: forming a first metal nitride material layer on the substrate structure; performing photolithography and etching on the first metal nitride material layer to form the patterned first metal nitride layer.

3. The forming method according to claim 1, wherein When performing the oxidation treatment on the sidewalls and the top surface of the first metal nitride layer, the oxidation temperature ranges from 150°C to 300°C.

4. The forming method according to claim 1, characterized in that, When performing the oxidation treatment on the sidewalls and the top surface of the first metal nitride layer, the oxidation gas includes oxygen or ozone.

5. The forming method according to claim 1, wherein The material of the first metal nitride layer includes titanium nitride or tantalum nitride.

6. The forming method according to claim 1, characterized in that, The thickness range of the first metal oxide layer and the thickness range of the first metal oxynitride layer are both 1 nm to 10 nm.

7. The forming method according to claim 1, wherein The forming method further includes: Performing an oxidation treatment on the sidewalls and the top surface of the exposed patterned third metal nitride layer to obtain a third dielectric layer covering the remaining third metal nitride layer; the third dielectric layer includes a third metal oxide layer and a third metal oxynitride layer located between the third metal oxide layer and the remaining third metal nitride layer; Directly forming a fourth metal nitride material layer on the third dielectric layer, the exposed second dielectric layer and the exposed substrate structure; Performing photolithography and etching on the fourth metal nitride material layer to form a patterned fourth metal nitride layer.

8. The forming method according to claim 1, wherein The substrate structure includes a device layer and an interconnect layer located on the device layer; the device layer includes a plurality of semiconductor devices, the interconnect layer includes a plurality of interconnect structures, and the semiconductor devices are connected to the interconnect structures; the forming method further includes: Forming an insulating layer covering the third metal nitride layer; A first contact structure and a second contact structure are formed in the insulating layer; the first contact structure penetrates through the third metal nitride layer, the second dielectric layer, and the second metal nitride layer and is connected to the interconnect structure; the second contact structure penetrates through the third metal nitride layer, the first dielectric layer, and the first metal nitride layer and is connected to the interconnect structure.

9. A semiconductor structure, characterized in that, The semiconductor structure is obtained by the formation method as described in claim 1, and the semiconductor structure includes: a capacitor; the capacitor includes: a first electrode plate including a first metal nitride structure; a second electrode plate including a second metal nitride structure at least partially located on the first metal nitride structure; a dielectric layer including a first dielectric structure; the first dielectric structure covers the sidewalls and the top surface of the first metal nitride structure; the first dielectric structure includes a first metal oxide structure and a first metal oxynitride structure located between the first metal oxide structure and the first metal nitride structure.

Images