Semiconductor device and electronic device including the same

Abstract

The invention relates to a semiconductor device and an electronic apparatus including the same. The semiconductor device includes a channel layer including a semiconductor material, a gate electrode, a ferroelectric layer between the channel layer and the gate electrode, a first insulating layer between the ferroelectric layer and the gate electrode, a charge trapping layer between the ferroelectric layer and the first insulating layer and including a compound including a first element, and a second insulating layer between the channel layer and the ferroelectric layer, in which the charge trapping layer includes a first layer, a second layer, and a third layer, and the highest value of the concentration gradient in the first layer is a first concentration value, the lowest value of the concentration gradient in the second layer is a second concentration value, and the third layer is a third concentration value. The highest value in the concentration gradient in the third layer is a third concentration value, and the second concentration value is lower than the first concentration value and the third concentration value.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0174830 filed on December 5, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device and an electronic device including the same. Background Art

[0004] Ferroelectrics are materials with ferroelectric properties that maintain spontaneous polarization by arranging (aligning) internal dipole moments even when no electric field is applied to them from the outside. Even if a certain voltage is applied to the ferroelectric and the voltage is restored to 0V, the polarization in the ferroelectric is maintained semi-permanently. Research is continuing on applying such ferroelectric properties to logic devices or memory devices. For example, in the case of a ferroelectric field effect transistor including a ferroelectric, the threshold voltage of the ferroelectric field effect transistor may vary with the polarization direction within the ferroelectric. Logic devices or memory devices can be implemented by using the threshold voltage variation characteristics of the ferroelectric field effect transistor. Summary of the invention

[0005] Provided are a semiconductor device and an electronic device including the same.

[0006] Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.

[0007] According to one aspect of the present disclosure, a semiconductor device includes: a channel layer including a semiconductor material; a gate electrode spaced apart from the channel layer in a first direction; a ferroelectric layer between the channel layer and the gate electrode, the ferroelectric layer including a ferroelectric material; a first insulating layer between the ferroelectric layer and the gate electrode; a charge trapping layer between the ferroelectric layer and the first insulating layer, the charge trapping layer including a compound containing a first element; and a second insulating layer between the channel layer and the ferroelectric layer, wherein the charge trapping layer includes a third layer, a second layer, and a first layer sequentially stacked on the ferroelectric layer in the first direction, and the first layer, the second layer, and the third layer each have a different concentration of the first element (different concentrations of the first element), and wherein the highest value in the concentration gradient in the first layer is a first concentration value, the lowest value in the concentration gradient in the second layer is a second concentration value, the highest value in the concentration gradient in the third layer is a third concentration value, and the second concentration value is lower than the first concentration value and the third concentration value.

[0008] The first concentration value may be higher than the third concentration value.

[0009] The thickness of the second layer may be 50% or more of the total thickness of the charge trapping layer.

[0010] In the concentration gradient of the second layer, a length of a region having a concentration lower than the third concentration value in the first direction may be 60% or more of the thickness of the second layer.

[0011] The thickness of the second layer may be greater than the thickness of the first layer and the thickness of the third layer.

[0012] The thickness of the third layer may be 1% or more of the total thickness of the charge trapping layer.

[0013] The thickness of the third layer may be greater than the thickness of the first layer.

[0014] The charge-trapping layer may include nitrogen.

[0015] The first layer, the second layer, and the third layer may each independently include a compound represented by MN, wherein M represents a first element and includes one or more elements selected from the group consisting of Al, Ga, Ge, Si, C, In, Y, Sc, and Zr, and N represents nitrogen.

[0016] The first layer, the second layer, and the third layer may each independently include a nitride of the first element, wherein the nitrogen content may be less than the stoichiometric amount.

[0017] The first layer, the second layer, and the third layer may each independently include Si 3 N 4-x , where 0 <x≤2。

[0018] The second insulating layer may include an oxide of the material of the channel layer.

[0019] The ferroelectric material of the ferroelectric layer may include a hafnium oxide based material.

[0020] The ferroelectric material may further include at least one of the following as a dopant: Zr, La, Al, Si, Y, B or Sc.

[0021] The first element may include one or more elements selected from the group consisting of Al, Ga, Ge, Si, C, In, Y, Sc, and Zr.

[0022] According to another aspect of the present disclosure, a semiconductor device includes: a channel layer including a semiconductor material; a gate electrode spaced apart from the channel layer in a first direction; a ferroelectric layer between the channel layer and the gate electrode, the ferroelectric layer including a ferroelectric material; a first insulating layer between the ferroelectric layer and the gate electrode; a charge trapping layer between the ferroelectric layer and the first insulating layer, the charge trapping layer including silicon nitride (silicon nitride); and a second insulating layer between the channel layer and the ferroelectric layer, wherein the charge trapping layer includes a third layer, a second layer, and a first layer sequentially stacked on the ferroelectric layer in the first direction, and the first layer, the second layer, and the third layer each have a different concentration, so that the silicon concentration in the charge trapping layer is lowest in the second layer and highest in the first layer.

[0023] The first layer, the second layer, and the third layer may each independently include Si 3 N 4-x , where 0 <x≤2。

[0024] According to another aspect of the present disclosure, an electronic device includes a semiconductor substrate and a plurality of memory cells stacked on the semiconductor substrate, wherein each of the plurality of memory cells may include: a channel layer including a semiconductor material; a gate electrode spaced apart from the channel layer in a first direction; a ferroelectric layer between the channel layer and the gate electrode, the ferroelectric layer including a ferroelectric material; a first insulating layer between the ferroelectric layer and the gate electrode; a charge trapping layer between the ferroelectric layer and the first insulating layer, the charge trapping layer including a compound including a first element; and a second insulating layer between the channel layer and the ferroelectric layer, wherein the charge trapping layer includes a third layer, a second layer, and a first layer sequentially stacked on the ferroelectric layer in the first direction, and the first layer, the second layer, and the third layer each have a different concentration of the first element, the highest value in the concentration gradient in the first layer is a first concentration value, the lowest value in the concentration gradient in the second layer is a second concentration value, the highest value in the concentration gradient in the third layer is a third concentration value, and the second concentration value is lower than the first concentration value and the third concentration value, and wherein the first direction is perpendicular to the stacking direction of the plurality of memory cells.

[0025] Spacers including an insulating material may be further included such that the spacers are between adjacent gate electrodes.

[0026] The adjacent gate electrodes and spacers may have a shell shape having connected inner surfaces. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] These and / or other aspects will become more apparent and more readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0028] Figure 1 is a cross-sectional view of a schematic structure of a semiconductor device according to at least one embodiment;

[0029] Figure 2is used to describe the Figure 1 A conceptual diagram of a multilayer structure of a charge trapping layer in a semiconductor device and a concentration distribution of each layer;

[0030] Figure 3 is a graph illustrating a concept of a memory window indicated by a semiconductor device according to at least one embodiment;

[0031] Figure 4A is a conceptual diagram illustrating charge distribution in a semiconductor device according to at least one embodiment when the semiconductor device is in a programmed state;

[0032] Figure 4B An example of charge density in a semiconductor device according to at least one embodiment is described when the semiconductor device is in a programmed state;

[0033] Figure 5A is a conceptual diagram illustrating charge distribution in a semiconductor device according to at least one embodiment when the semiconductor device is in an erase state;

[0034] Figure 5B An example of charge density in a semiconductor device according to at least one embodiment is described when the semiconductor device is in an erase state;

[0035] Figure 6 is a cross-sectional view of a schematic structure of a semiconductor device according to a comparative example;

[0036] Fig. 7A and 7B An example of charge density in a semiconductor device according to a comparative example when the semiconductor device is in a programmed state and an erased state is described;

[0037] Fig. 8A is a cross-sectional view showing a schematic structure of a memory device of at least one embodiment, and Figure 8B yes Fig. 8A A cross-sectional view of a memory device taken along line AA′;

[0038] Fig. 9 is an equivalent circuit of a memory device according to at least one embodiment;

[0039] Fig.10 is a schematic circuit diagram of a neural network device according to at least one embodiment; and

[0040] Fig.11 is a schematic block diagram of an electronic device including a neural network device according to at least one embodiment. DETAILED DESCRIPTION

[0041] The embodiments of the invention will now be described in detail, with examples thereof illustrated in the accompanying drawings, wherein the same reference numerals represent the same elements throughout. In this regard, the embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Therefore, the embodiments are described below only by reference to the accompanying drawings to explain aspects. As used herein, the term "and / or" includes any and all combinations of one or more of the related enumerated items. Expressions such as "at least one (kind) of..." modify the entire list of elements and do not modify the individual elements of the list when before or after the list of elements.

[0042] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. The embodiments described below are examples only, and various modifications are available from the embodiments. Throughout the accompanying drawings, the same reference numerals represent the same elements, and the sizes of the components in the accompanying drawings may be exaggerated for ease of explanation and clarity.

[0043] Hereinafter, when a constituent element is disposed "on" or "above" another constituent element, the constituent element may only be directly on the other constituent element or above the other constituent element in a non-contact manner. In addition, it will be understood that, in addition to the orientation shown in the figures, spatially relative terms, such as "above", "top", etc., are intended to cover different orientations of the device in use or operation, and the device may be oriented in other ways (rotated 90 degrees or other orientations), and the spatially relative terms used herein are interpreted accordingly.

[0044] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another. These terms do not limit the materials or structures of the components to be different from each other.

[0045] As used herein, the singular forms "a (one) (indefinite article, a, an)" and "the" also include plural forms, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising" used herein specify the presence of the features or components (components) described, but do not exclude the presence or addition of one or more other features or components (components).

[0046] In addition, terms such as "...part", "...unit", "...module" and "...block" stated in the specification may represent a unit for processing at least one function or operation, and the unit may be embodied and / or implemented by a processing circuit system such as hardware, software or a combination of hardware and software. For example, the processing circuit system may more specifically include, but not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc. The processing circuit system may include at least one of electrical components such as transistors, resistors, capacitors, etc. and / or an electronic circuit including the components.

[0047] The use of the terms "a (indefinite article, a, an)", "said" and similar indicators in the context of describing the present disclosure is interpreted to cover both the singular and the plural. In addition, whenever a range of values ​​is listed, the range includes all values ​​within the range, just as if explicitly recorded, and may further include the boundaries of the range. Therefore, the range of "X" to "Y" includes all values ​​between X and Y, including X and Y. In addition, when the terms "about" and / or "substantially" are used in this specification with respect to numerical values ​​and / or geometric terms, it is intended that the relevant numerical values ​​include manufacturing tolerances (e.g., ±10%) around the stated numerical values. In addition, whether or not numerical values ​​and / or geometric terms are modified to "about" or "substantially", it will be understood that these values ​​should be interpreted as including manufacturing or operating tolerances (e.g., ±10%) around the stated numerical values ​​and / or geometric shapes.

[0048] The operation of all methods described herein can be performed in any suitable order, unless otherwise specified herein or clearly contradicted by context. In addition, the use of any and all examples or language (e.g., "such as") provided herein is intended only to better illustrate the present disclosure, and is not intended to impose limitations on the scope of the present disclosure, unless otherwise stated.

[0049] Figure 1 is a cross-sectional view of a schematic structure of a semiconductor device 100 according to at least one embodiment.

[0050] The semiconductor device 100 may include: a channel layer 111 including a semiconductor material; a ferroelectric layer 140 disposed above the channel layer 111 and including a ferroelectric material; a gate electrode 170 disposed above the ferroelectric layer 140; a first insulating layer 160 disposed between the ferroelectric layer 140 and the gate electrode 170; a charge trapping layer 150 disposed between the first insulating layer 150 and the ferroelectric layer 140; and a second insulating layer 130 disposed between the channel layer 111 and the ferroelectric layer 140.

[0051] The semiconductor device 100 according to at least one embodiment may include a charge trapping layer 150 having multiple types of stoichiometries for memory window expansion. For example, the charge trapping layer 150 may include a compound including a first element, and the concentration of the first element within the charge trapping layer 150 may vary according to the position within the charge trapping layer 150. In at least one embodiment, for example, the charge trapping layer 150 may include a plurality of layers having different concentration gradient characteristics of the first element, and may include, for example, a third layer 153, a second layer 152, and a first layer 151 disposed on the ferroelectric layer 140. In other words, the concentrations of the first element in the first layer 151, the second layer 152, and the third layer 153 may be different from each other along the stacking direction. In at least one embodiment, the interface between the third layer 153, the second layer 152, and the first layer 151 may be visually blurred (difficult to clearly identify).

[0052] The charge trapping layer 150 may include one or more nitrides. The charge trapping layer 150 may include, for example, a nitride of a first element. The charge trapping layer 150 may include, for example, a material that can implement charge trapping (traps) that is 1 eV or more less than the conduction band of the material. In at least one embodiment, the first layer 151, the second layer 152, and the third layer 153 may each independently include a compound represented by MN, wherein M represents an element including one or more elements selected from the following: Al, Ga, Ge, Si, C, In, Y, Sc, and Zr, and N represents nitrogen. The charge trapping layer 150 may include, for example, at least one of the following: AlN, GaN, GeN, SiN, CN, InN, YN, ScN, or ZrN. For example, when the charge trapping layer 140 includes silicon nitride, the first element may be Si. This is only an example, and in order to make the trapping (trapping) energy level of the second layer 152 the deepest among the first layer 151, the second layer 151, and the third layer 153, the concentration gradient of the first element as the element included in the compound forming the charge trapping layer 150 may be differently set in each layer. Therefore, the ratio of M to N may vary based on the position in the charge trapping layer 150.

[0053] For example, the first layer 151, the second layer 152, and the third layer 153 may each independently include a nitride of a first element, wherein the nitrogen content is less than the stoichiometric amount. 3 N 4-x (0 <x≤2)。

[0054] Refer to the following Figure 2 The specific structure of the charge trapping layer 150 and the concept of extending the memory window through the charge trapping layer 250 are described in detail.

[0055] The semiconductor device 100 is a field effect transistor that exhibits different threshold voltages according to a voltage applied to the gate electrode 170 .

[0056] The channel layer 111 may be included in the substrate 110 including a semiconductor material. For example, the channel layer 111 may be defined as a region between a source region 113 and a drain region 116 spaced apart from each other in the substrate 110 including a semiconductor material, and / or defined as a region between the source region 113 and the drain region 116 on the substrate 110 on which the source region 113 and the drain region 116 are formed.

[0057] In at least one embodiment, the source region 113 and the drain region 116 may be doped with a first conductivity type, and the substrate 110 may be doped with a second conductivity type that is electrically opposite to the first conductivity type. For example, the substrate 110 may include a p-type semiconductor and the source region 113 and the drain region 116 may include an n-type semiconductor, or the substrate 110 may include an n-type semiconductor and the source region 113 and the drain region 116 may include a p-type semiconductor. The substrate 110 may be approximately 10 16 / cm 3 Up to 10 17 / cm 3 The source region 113 and the drain region 116 may be doped at a relatively low concentration of about 10 19 / cm 3 Up to 10 21 / cm 3 The source region 113 and the drain region 116 may be formed by doping opposite sides of the upper portion of the substrate 110, respectively. The upper region of the substrate 110 where the source region 113 and the drain region 116 are not formed may become the channel layer 111.

[0058] The channel layer 111 may include a simple (element) (eg, Group IV) semiconductor, a compound semiconductor, a two-dimensional semiconductor, and / or an oxide semiconductor. The channel layer 111 may include, for example, Si, Ge, SiGe, MoS 2 ,WSe 2 , graphene, indium gallium zinc oxide (IGZO), tungsten-doped indium oxide (IWO) and / or ZnSnO. In addition, the channel layer 111 may include a III-V compound semiconductor, a II-VI compound semiconductor and / or the like. In addition, in at least some embodiments, the channel layer 111 may be (and / or include) a semiconductor material deposited on the substrate 110.

[0059] The substrate 110 , the source region 113 , and the drain region 116 may include the same base materials as described above with respect to the channel layer 111 .

[0060] When the substrate 110, the channel layer 111, the source region 113, and the drain region 116 include Si, Ge, SiGe, and / or the like, the substrate 110 and the channel layer 111 may each be doped with a dopant of at least one of boron (B), Al, Ga, and In, and the source region 113 and the drain region 116 may each be doped with a dopant of at least one of phosphorus (P), arsenic (As), and antimony (Sb). In these cases, the semiconductor device 100 may be referred to as an n-channel metal oxide semiconductor field effect transistor (NMOS). Alternatively, in contrast, the substrate 110 and the channel layer 111 may each be doped with a dopant of at least one of P, As, and Sb, and the source region 113 and the drain region 116 may each be doped with a dopant of at least one of B, Al, Ga, and In. In these cases, the semiconductor device 100 may be referred to as a p-channel metal oxide semiconductor field effect transistor (PMOS).

[0061] The ferroelectric layer 140 may include a ferroelectric material. A ferroelectric material is a material having ferroelectricity in which spontaneous polarization is maintained due to internal dipole moment alignment even when no externally applied electric field is maintained thereto. The threshold voltage of the semiconductor device 100 may vary according to the following: the polarization direction of the ferroelectric layer 140 is, for example, a direction from the gate electrode 170 to the channel layer 111, or conversely, a direction from the channel layer 110 to the gate electrode 170.

[0062] In at least one embodiment, the ferroelectric material included in the ferroelectric layer 140 may include a hafnium oxide material or an aluminum nitride material. The ferroelectric material may have a structure in which a dopant is inserted into a hafnium oxide-based material or a structure in which a dopant is inserted into an aluminum nitride-based material. When the ferroelectric material included in the ferroelectric layer 140 is a hafnium oxide-based material, the dopant may include Zr, lanthanum (La), Al, Si, or Y. When the ferroelectric material included in the ferroelectric layer 140 is an aluminum nitride-based material, the dopant may include B or Sc.

[0063] Ferroelectric layer 140 may include an orthorhombic phase and / or a tetragonal phase. In some cases, ferroelectric layer 140 may include more orthorhombic phase than tetragonal phase. The distribution of crystal phases may be confirmed, for example, by transmission electron microscopy (TEM), grazing incidence X-ray diffraction (GIXRD), and / or the like.

[0064] In addition, the ferroelectric layer 140 may include, for example, a ferroelectric material having at least one of the following structures: a fluorite structure, a perovskite structure, and a wurtzite structure. The ferroelectric material having the fluorite structure may include, for example, hafnium oxide HfO 2. Hafnium oxide may be doped with at least one element such as Zr, La, Al, Si, Y, gadolinium (Gd) and / or the like. The ferroelectric layer 140 may also include a semi-ferroelectric material. For example, the semi-ferroelectric material may include zirconium oxide. Zirconium oxide may be doped with at least one element such as hafnium (Hf), La, Al, Si, Y and Gd. A ferroelectric material having a perovskite structure may include, for example, lead zirconate titanate (PZT). A ferroelectric material having a wurtzite structure may include, for example, zinc oxide (ZnO) or aluminum nitride (AlN). A ferroelectric material having a wurtzite structure may be doped with at least one element such as B and Sc. In addition, the ferroelectric layer 140 may include not only the above-mentioned ferroelectric materials, but also a semi-ferroelectric material. For example, the ferroelectric layer 140 may include ZrO 2 .

[0065] In at least one embodiment, the ferroelectric layer 140 may include at least one of Hf and Zr. The ferroelectric layer 140 may include Hf and Zr (e.g., Hf 0.5 Zr 0.5 O 2 ), and in addition, may be doped with at least one of the following elements in a proportion of less than 10 atomic %: La, Al, Si, Y and / or Gd.

[0066] The thickness of the ferroelectric layer 140 may be, for example, about 5 nm to about 20 nm. However, the present disclosure is not limited thereto.

[0067] The gate electrode 170 may include one or more conductive materials selected from, for example, metal, metal nitride, metal carbide, polysilicon, and / or a combination thereof. For example, the metal may include Al, tungsten (W), molybdenum (Mo), titanium (Ti), or tantalum (Ta), the metal nitride film may include a titanium nitride film (TiN film) or a tantalum nitride film (TaN film), and the metal carbide may include a metal carbide doped with (or containing) aluminum or silicon, and as a detailed example, may include TiAlC, TaAlC, TiSiC, or TaSiC. The gate electrode 170 may have a stacked structure of multiple materials. For example, the gate electrode 170 may have a stacked structure of a metal nitride layer / metal layer, such as TiN / Al and / or the like, or a stacked structure of a metal nitride layer / metal carbide layer / metal layer, such as TiN / TiAlC / W. The gate electrode 170 may include a titanium nitride (TiN) film or Mo, and the above examples may be used in a variety of modified forms. In addition, the gate electrode 170 may include a conductive two-dimensional material other than the above materials. For example, the conductive two-dimensional material may include at least one of graphene, black phosphorus, amorphous boron nitride, two-dimensional hexagonal boron nitride (h-BN), and phosphorene.

[0068] The first insulating layer 160 disposed between the charge trapping layer 150 and the gate electrode 170 may include one or more insulating materials. The first insulating layer 160 may include, for example, SiO 2 、Al 2 O 3 MgO 2 or AlN. When a sufficiently high voltage (e.g., a write voltage or an erase voltage) is applied to the gate electrode 170, the first insulating layer 160 may transfer charges from the gate electrode 170 to the charge trapping layer 150 by a tunnel effect. When no voltage or a low voltage (e.g., a standby voltage or a read voltage) is applied to the gate electrode 170, the first insulating layer 160 may prevent charges trapped at the interface of the ferroelectric layer 140 from leaking through the gate electrode 170. The first insulating layer 160 may be referred to as a tunnel barrier (blocking) layer.

[0069] The first insulating layer 160, together with the charge trapping layer 150, can contribute to the expansion of the memory window. For example, the capacitance generated between the gate electrode 170 and the ferroelectric layer 140 can be reduced by the first insulating layer 160, and therefore, the memory window can be expanded. The thickness of the first insulating layer 160 can be about 1 nm or more, about 5 nm or less, or about 3 nm or less. For example, the thickness of the first insulating layer 160 can be within the range of 1 nm to 5 nm and / or 1 nm to 3 nm, inclusive; however, this is an example, and the present disclosure is not limited thereto.

[0070] The second insulating layer 130 disposed between the channel layer 111 and the ferroelectric layer 140 may include various insulating materials. The second insulating layer 130 may include an oxide of a material included in the channel layer 111. For example, when the channel layer 111 includes Si, the second insulating layer 130 may include SiO 2 When the channel layer 111 includes Ge, the second insulating layer 130 may include GeO 2 When the channel layer 111 includes SiGe, the second insulating layer 130 may include SiGeO 4 The second insulating layer 130 may be formed as follows: a portion of the semiconductor material included in the channel layer 111 is naturally oxidized as above. Alternatively, depending on the desired thickness of the second insulating layer 130, an additional deposition process and / or the like may be further performed. The second insulating layer 130 may include a plurality of layers.

[0071] Figure 2 is used to describe the Figure 1 A conceptual diagram of a multilayer structure of a charge trapping layer 150 and a concentration distribution of each layer in a semiconductor device 100 is shown in FIG.

[0072] The first element included in the compound forming the charge trapping layer 150 may have a certain concentration gradient in the first layer 151, the second layer 152, and the third layer 153. Figure 2 As shown in , the first layer 151, the second layer 152 and the third layer 153 may respectively present a first concentration gradient CG1, a second concentration gradient CG2 and a third concentration gradient CG3 according to the thickness direction DR thereof. The charge trapping layer 150 may include silicon nitride, and the first element may include Si. However, the present disclosure is not limited thereto.

[0073] When the highest value of the first concentration gradient CG1 appearing in the first layer 151 is the first concentration value V1, the lowest value of the second concentration gradient CG2 appearing in the second layer 152 is the second concentration value V2, and the highest value of the third concentration gradient CG3 appearing in the third layer 153 is the third concentration value V3, the second concentration value V2 may be less than the first concentration value V1 and the third concentration value V3. The first concentration value V1 may be greater than the third concentration value V3. In other words, the first concentration value V1 (for example, representing the atomic ratio of Si to N in the first layer 151) may be greater than the second concentration value V2 (representing the atomic ratio of Si to N in the second layer 152), and / or the third concentration value V3 (representing the atomic ratio of Si to N in the third layer 153).

[0074] The second layer 152 is a layer that forms deep traps, and therefore may have a trapping energy level deeper than those of the first layer 151 and the third layer 153. In order to form deep traps, the second concentration gradient CG2 appearing in the second layer 152 may have a shape in which the concentration of the first element decreases along the first direction DR and then increases. The thickness direction DR may be a stacking direction in which the third layer 153, the second layer 152, and the first layer 151 are stacked on the ferroelectric layer 140. The term "stacking direction" may be used interchangeably with "thickness direction" and / or "first direction". As shown in the figure, the second concentration gradient CG2 of the second layer 152 may have a shape in which the concentration of the first element decreases sharply along the thickness direction DR, maintains a low concentration, and then increases sharply. The specific shape shown is an example, and the present disclosure is not limited thereto. The charges stored in the deep traps of the second layer 152 do not escape well, which may make a substantial contribution to the expansion of the storage window.

[0075] The first layer 151 is a layer forming a shallow trap and can be used to capture charges from the gate electrode 170 into a deep trap of the second layer 152. The thickness t1 of the first layer 151 may be defined as a range indicating a concentration ranging from a first concentration value V1 which is a highest value of the first concentration gradient CG1 to 90% of the first concentration value V1.

[0076] The third layer 153 may represent an intermediate energy level between the first layer 151 and the second layer 152, that is, a capture energy level deeper than the first layer 151 and shallower than the second layer 152. The third layer 153 may be used as a reservoir: it replenishes the charges escaping from the deep capture of the second layer 152. The boundary between the third layer 153 and the second layer 152 may be defined as the position of the inflection point that first appears in the thickness direction DR in the concentration gradient including the third concentration gradient CG3 and the second concentration gradient CG2. Based on the above definition, the thickness t3 of the third layer 153 may be defined.

[0077] The thickness t2 of the second layer 152 may be 50% or more of the total thickness TT of the charge trapping layer 150. Alternatively, the thickness t2 of the second layer 152 may be 40% or more, 60% or more, and / or 70% or more of TT. The thickness t2 of the second layer 152 may be greater than both the thickness t3 of the third layer 153 and / or the thickness t1 of the first layer 151.

[0078] The thickness of the region representing a concentration lower than the third concentration value V3 in the second concentration gradient CG2 of the second layer 152 (length tc in the thickness direction DR) may be 60% or more, 50% or more, 70% or more, and / or 80% or more of the thickness t2 of the second layer 52.

[0079] The thickness t3 of the third layer 153 may be greater than the thickness t1 of the first layer 151. The thickness t3 of the third layer 153 may be, for example, 105% or more, or 110% or 120% or more of the thickness t1 of the first layer 151.

[0080] The thickness t3 of the third layer 153 may be 5% or more of the total thickness TT of the charge trapping layer 150, and the thickness t1 of the first layer 151 may be less than 5% and greater than 0 of the total thickness TT of the charge trapping layer 150. Alternatively, the thickness t3 of the third layer 153 may be 10% or more of the total thickness TT of the charge trapping layer 150, and the thickness t1 of the first layer 151 may be less than 10% and greater than 0 of the total thickness TT of the charge trapping layer 150. Alternatively, the thickness t3 of the third layer 153 and the thickness t1 of the first layer 151 may each be 25% or less of the total thickness TT of the charge trapping layer 150, and the thickness t3 of the third layer 152 may be greater than the thickness t1 of the first layer 151.

[0081] Alternatively, the thickness of the first layer 151 may be 1% or more, 2% or more, or 3% or more of the total thickness TT of the charge trapping layer 150. The thickness of the third layer 153 may be 1% or more, 2% or more, or 3% or more of the total thickness TT of the charge trapping layer 150.

[0082] The first layer 151, the second layer 152, and the third layer 153 having different concentration gradients of the first element may be manufactured by controlling an atomic layer deposition (ALD) cycle. For example, when forming a SiN layer, Si 1-cycle and N 1-cycle may be repeated alternately. For example, the first layer 151 and the third layer 153 may each be formed by performing a Si 2-cycle and a N 1-cycle, and the second layer 152 may be formed by performing a Si 1-cycle and a N 2-cycle. The number of cycles may be controlled depending on the concentration difference between the first layer 151, the second layer 152, and the third layer 153.

[0083] Figure 3 is a graph conceptually illustrating a memory window indicated by a semiconductor device according to at least one embodiment.

[0084] The two graphs indicated by programming PGM and erasing ERS show the drain current to the gate voltage VG in the programming state and the erased state. The memory window MW is the difference between two different threshold voltages of the semiconductor device 100. As the memory window MW increases, the operational reliability of the semiconductor device 100 can be improved. For example, the memory window MW of the semiconductor device 100 can be about 6.5V or more.

[0085] Figure 4A is a conceptual diagram illustrating charge distribution in a semiconductor device according to at least one embodiment when the semiconductor device is in a programmed state. Figure 4B An example of charge density in a semiconductor device according to at least one embodiment is shown when the semiconductor device is in a programmed state.

[0086] Reference Figure 4A , when the semiconductor device 100 is an NMOS, in the ferroelectric layer 140, positive charges may move toward the channel layer 111 and negative charges may move toward the gate electrode 170, and the semiconductor device 100 may be in a programmed state. In the programmed state, negative charges may be accumulated in the second insulating layer 130, and positive charges may be accumulated in the charge trapping layer 150. In the second insulating layer 130, negative charges may be accumulated at the interface with the ferroelectric layer 140, and in the charge trapping layer 150, positive charges may be accumulated at the interface with the ferroelectric layer 140. In this programmed state, electrons may easily flow along the channel layer 111, and the threshold voltage of the semiconductor device 100 may be reduced.

[0087] exist Figure 4B In the figure, the vertical axis represents charge density, and the gate electrode 170, the first insulating layer 160, the charge trapping layer 150, the ferroelectric layer 140, the second insulating layer 130 and the channel layer 111 in the semiconductor device 100 are located in the horizontal axis direction.

[0088] Reference Figure 4B, in the charge trapping layer 150, the charge density Q of the positive charges trapped at the interface with the ferroelectric layer 140 it,I1 The polarization value P of the ferroelectric layer 140 may be greater than r In the second insulating layer 130, the charge density Q of the negative charges trapped at the interface with the ferroelectric layer 140 is it,I2 The absolute value of the polarization value -P of the ferroelectric layer 140 may be smaller than r The absolute value of .

[0089] Figure 5A is a conceptual diagram illustrating charge distribution in a semiconductor device according to at least one embodiment when the semiconductor device is in an erase state. Figure 5B An example of charge density in a semiconductor device according to at least one embodiment when the semiconductor device is in an erase state is shown.

[0090] Reference Figure 5A , when the semiconductor device 100 is an NMOS, in the ferroelectric layer 140, negative charges may move toward the channel layer 111 and positive charges may move toward the gate electrode 170, and the semiconductor device 100 may be in an erased state. By applying a positive breakdown voltage or a negative breakdown voltage to the gate electrode 170 of the semiconductor device 100, a programming state and an erased state may be selectively switched. In the erased state, positive charges may be accumulated in the second insulating layer 130, and negative charges may be accumulated in the charge trapping layer 150. In the second insulating layer 130, positive charges may be accumulated at the interface with the ferroelectric layer 140, and further, in the charge trapping layer 150, negative charges may be accumulated at the interface with the ferroelectric layer 140. In this erased state, it may be difficult for electrons to flow along the channel layer 111, and the threshold voltage of the semiconductor device 100 may be increased.

[0091] Reference Figure 5B , in the charge trapping layer 150, the charge density Q of the negative charges trapped at the interface with the ferroelectric layer 140 it,I1 The absolute value of the polarization value of the ferroelectric layer 140 may be greater than the polarization value -P r In the second insulating layer 130, the charge density Q of the positive charges trapped at the interface with the ferroelectric layer 140 is it,I2 The polarization value P of the ferroelectric layer 140 may be less than r .

[0092] exist FIG. 4A to FIG. 5B In the description of FIG. 1 , although the case where the semiconductor device 100 is an NMOS is described, the same principle can be applied to the case where the semiconductor device 100 is a PMOS. For example, in the case where the semiconductor device 100 is a PMOS, Figures 4A to 5B The polarizations of the charges described in may be opposite to each other.

[0093] Since the semiconductor device 100 according to at least one embodiment includes the charge trapping layer 150 designed to increase the amount of charge trapping, the memory window of the semiconductor device 100 may be increased.

[0094] The memory window of the semiconductor device 100 may be expressed by Equation 1 below.

[0095] [Equation 1]

[0096] In equation 1, ΔP represents the polarization of the ferroelectric layer 140, and ΔQ it,I2 represents the amount of charge trapped at the interface between the ferroelectric layer 140 and the second insulating layer 130, ΔQ it,I1 represents the amount of charge trapped at the interface between the ferroelectric layer 140 and the charge trapping layer 150, C Ferro represents the capacitance of the ferroelectric layer 140, and C I1 represents the capacitance of the layer between the gate electrode 170 and the ferroelectric layer 140 .

[0097] As described above, the charge trapping layer 150 has a specific structure such as material, concentration and / or the like to increase ΔQ it,I1 The semiconductor device 100 according to at least one embodiment may have a large memory window.

[0098] Figure 6 is a cross-sectional view showing a schematic structure of a semiconductor device 1 according to a comparative example. Fig. 7A and 7B An example of charge density in the semiconductor device 1 according to the comparative example when the semiconductor device is in a programmed state and an erased state is shown.

[0099] According to the semiconductor device 1 of the comparative example and Figure 1 The semiconductor device 100 is different in that only the first insulating layer 160 is provided between the ferroelectric layer 140 and the gate electrode 170, and no Figure 1 The charge trapping layer 150 in the embodiment of the present invention.

[0100] Reference Fig. 7A , in the programmed state, the charge density Q of the positive charges trapped in the first insulating layer 160 at the interface with the ferroelectric layer 140 it,I1 is smaller than the polarization value P of the ferroelectric layer 140 r .Will Fig. 7A and Figure 4B For comparison, Fig. 7A Q it,I1 Can have less than Figure 4B The charge density Q of the positive charges trapped at the interface between the charge trapping layer 150 and the ferroelectric layer 140 is it,I1 The value of .

[0101] Reference Figure 7B , in the erased state, the charge density Q of the negative charges trapped in the first insulating layer 160 at the interface with the ferroelectric layer 140 is it,I1 The absolute value of the polarization value -P of the ferroelectric layer 140 may be smaller than r The absolute value of Figure 7B and Figure 5B For comparison, Figure 7B Q it,I1 The absolute value of Figure 5B The charge density Q of the negative charges trapped at the interface between the charge trapping layer 150 and the ferroelectric layer 140 is it,I1 The absolute value of .

[0102] When Equation 1 about the memory window is applied to the semiconductor device 1 according to the comparative example, at this time, ΔQ it,I1 represents the amount of charges trapped at the interface between the ferroelectric layer 140 and the first insulating layer 160. Therefore, the semiconductor device 1 according to the comparative example may be analyzed to have a smaller memory window than the semiconductor device 100 according to at least one embodiment.

[0103] In other words, in the semiconductor device 100 according to at least one embodiment, since the charge trapping layer 150 having the above-described concentration gradient characteristics is further provided between the gate electrode 170 and the ferroelectric layer 140 in addition to the first insulating layer 160 , the memory window may be further increased.

[0104] The semiconductor device 100 can be applied to various electronic devices, for example, as a separate memory cell in a memory device. The memory device can have a three-dimensional structure, a gate all around (GAA) structure, a vertical structure, and / or the like, such as a vertical NAND (VNAND) structure.

[0105] Fig. 8A is a cross-sectional view showing a schematic structure of a memory device 300 according to at least one embodiment, and Figure 8B yes Fig. 8A 1 is a cross-sectional view of the memory device 300 taken along line AA′.

[0106] Reference Fig. 8A , the memory device 300 may include a substrate 301 and a cell string CS formed on the substrate 301. Although one cell string CS is shown in the figure, this is an example, and the memory device 300 may include a plurality of cell strings CS. For example, the cell strings CS may be arranged two-dimensionally in two directions perpendicular to a direction (Z direction) away from the substrate 301. The cell strings CS may be arranged in a k*n matrix form, as will be described below. Fig. 9As shown in the circuit diagram, it can be called CSij (1≤i≤k, 1≤j≤n) according to the corresponding row and column positions.

[0107] The substrate 301 may be a semiconductor substrate. The substrate 301 may include a silicon material doped with a first type of impurity. For example, the substrate 301 may include a silicon material doped with a p-type impurity. For example, the substrate 301 may be a p-type well (e.g., a pocket pwell). However, the present disclosure is not limited thereto, and the substrate 301 may include various semiconductor materials.

[0108] The common source region 305 is provided on the substrate 301. The common source region 305 may be of a different type than the semiconductor material included in the substrate 301, for example, an n-type. The common source region 305 may be connected to, for example, Fig. 9 The common source line CSL indicated in the circuit diagram.

[0109] The cell string CS may have a ring-shaped (circuit) cross section, such as Figure 8B In other words, the cell string CS may have a cylindrical shape with a central axis parallel to the Z direction. However, this is an example, and the cell string CS may have other shapes, and, for example, may be deformed into the shape of an elliptical column or a polygonal column.

[0110] The plurality of gate electrodes 370 may be spaced apart from each other in an axial direction of the cell string CS, for example, in the Z direction, and spacers 380 including an insulating material may be disposed between the gate electrodes 370 .

[0111] The gate electrode 370 and the spacer 380 may have a cylindrical shell shape having connected inner surfaces, and the first insulating layer 360 may be conformally formed on the inner surface. Next, the charge trapping layer 350 may be conformally formed on the first insulating layer 360. The charge trapping layer 350 may include a first layer 351, a second layer 352, and a third layer 353, which are respectively and substantially Figure 1 and Figure 2 The first layer 151, the second segment 152, and the third segment 153 described in 1 are the same. The ferroelectric layer 340 is conformally formed on the charge trapping layer 350, and then, the second insulating layer 330 and the channel layer 310 may be conformally formed.

[0112] The central portion of the cell string CS may be filled with the cylindrical insulating layer 320. However, this is an example, and the insulating layer 320 may be omitted or formed in a cylindrical shell shape.

[0113] The channel layer 310, the second insulating layer 330, the ferroelectric layer 340, the charge trapping layer 350, the first insulating layer 360 and the gate electrode 370 may include Figure 1The materials of the channel layer 111, the second insulator layer 130, the ferroelectric layer 140, the charge trapping layer 150, the first insulator layer 160 and the gate electrode 170 described in FIG.

[0114] One end of the channel layer 310, ie, a region of the channel layer 310 located in the lowermost end of the cell string CS, may be in contact with the common source region 305. Therefore, a repeated description thereof is omitted.

[0115] The drain 390 may be provided on the cell string CS. The drain 390 may include, for example, a silicon material doped with an n-type. The other end of the channel layer 310 (ie, a region of the channel layer 310 located in the uppermost end of the cell string CS) may contact the drain 390. The drain 390 may be connected to the bit line through a contact plug.

[0116] One region of the gate electrode 370 and the first insulating layer 360 , the charge trapping layer 350 , the ferroelectric layer 340 , the second insulating layer 330 , and the channel layer 310 in the region facing the gate electrode 370 constitute a memory cell MC.

[0117] As the memory cells MC are continuously arranged in the vertical direction (Z direction), a cell string CS is formed. The common source region 305 and the drain region 390 connected to opposite ends of the cell string CS may be connected to a common source line CSL and a bit line BL, respectively, as shown in FIG. Fig. 9 In the circuit diagram of FIG. 370, the gate electrode 370 is connected to the word line WL. By applying voltage to the word line WL, the common source line CSL and the bit line BL, the memory cell MC can be programmed, read and erased.

[0118] As described above, the ferroelectric layer 340 is a material in which the polarization value (polarization) is semi-permanently maintained even when a certain voltage is applied thereto and lowered back to 0V, and the polarity (direction) of the residual polarization may depend on the polarity (direction) of the voltage applied externally. The region of the ferroelectric layer 340 corresponding to each memory cell MC may have a residual polarization corresponding to the electric field formed in the ferroelectric layer 340 by the voltage applied to the gate electrode 370. Through the polarization direction of the ferroelectric layer 340, a conductivity difference (conduction difference) may be generated in the region of the channel layer 310 corresponding to the memory cell MC, through which information may be written or confirmed.

[0119] Furthermore, since the memory device 300 according to at least one embodiment includes the charge trap layer 350 having a certain concentration gradient to increase a memory window, reliability of a memory operation may be improved.

[0120] Fig. 9 is an equivalent circuit of a memory device according to at least one embodiment. Fig. 9, the memory device may include a plurality of memory cell strings CS11 to CSkn. The memory cell strings CS11 to CSkn are arranged two-dimensionally in the row direction and the column direction, and may form rows and columns. Each cell string CSij (1≤i≤k and 1≤j≤n) may be connected to a bit line BL, a string selection line SSL, a word line WL, and a common source line CSL.

[0121] The cell string CSij may include a memory cell MC and a string selection transistor SST. The memory cell MC and the string selection transistor SST of each cell string CSij may be stacked in a height direction.

[0122] The rows of cell strings CSij are respectively connected to different string selection lines SSL1 to SSLk. For example, string selection transistors SST of cell strings CS11 to CS1n are commonly connected to string selection line SSL1. String selection transistors SST of cell strings CSk1 to CSkn are commonly connected to string selection line SSLk.

[0123] The columns of the cell strings CSij are respectively connected to different bit lines BL1 to BLn. For example, the memory cells MC and string selection transistors SST of the cell strings CS11 to CSk1 may be commonly connected to the bit line BL1, and the memory cells MC and string selection transistors SST of the cell strings CS1n to CSkn may be commonly connected to the bit line BL (BLn).

[0124] Rows of cell strings CSij may be respectively connected to different common source lines CSL1 to CSLk. For example, string selection transistors SST of cell strings CS11 to CS1n may be commonly connected to a common source line CSL1, and string selection transistors SST of cell strings CSk1 to CSkn may be commonly connected to a common source line CSLk.

[0125] Located at Fig. 8A String selection transistors SST or memory cells MC at the same height of the substrate 301 may be commonly connected to one of the word lines WL1 to WLm, and memory cells MC located at different heights may be respectively connected to word lines WL1 to WLm different from each other.

[0126] In the structure, write and read operations can be performed in units of rows of memory cell strings CS11 to CSkn. For example, memory cell strings CS11 to CSkn can be selected in units of a row through a common source line CSL and a string selection line SSL. Write and read operations can be performed on the selected row of memory cell strings CS11 to CSkn in units of pages. For example, the page can be a row of memory cells MC connected to one word line WL. In the selected row of memory cell strings CS11 to CSkn, memory cells MC can be selected in units of pages through the word line WL. Each memory cell MC can be connected to Fig. 8AThe memory cells MC are the same as (and / or substantially similar to) the semiconductor device 100 and may include the semiconductor device 100 and / or may include a semiconductor device modified therefrom.

[0127] The circuit structure shown is an example. For example, the number of rows of cell strings CSij (1≤i≤k and 1≤j≤n) can be increased or decreased. As the number of rows of cell strings CS changes, the number of string selection lines connected to the rows of cell strings CS and the number of cell strings CS connected to one bit line BL can change. As the number of rows of cell strings CS changes, the number of common source lines connected to the rows of cell strings CS can also change.

[0128] The number of columns of cell strings CSij may increase or decrease. As the number of columns of cell strings CSij changes, the number of bit lines BL connected to the columns of cell strings CSij and the number of cell strings CSij connected to one string selection line may also change.

[0129] The height of the cell string CSij may be increased or decreased. For example, the number of memory cells MC stacked on each of the cell strings CSij may be increased or decreased. As the number of memory cells MC stacked on each of the cell strings CSij changes, the number of word lines WL may also change. For example, the string selection transistors provided to each of the cell strings CSij may increase. As the number of string selection transistors provided to each of the cell strings CSij changes, the number of string selection lines or common source lines may also change. As the number of string selection transistors increases, the string selection transistors may be stacked in the same form as the memory cells MC.

[0130] Fig.10 is a schematic circuit diagram of a neural network device 400 according to at least one embodiment. Fig.10 According to at least one embodiment, the neural network device 400 may include an array of a plurality of synaptic devices 410 arranged in two dimensions. Each of the synaptic devices 410 may include an access transistor (access transistor) 411 and a ferroelectric field effect transistor 412. The ferroelectric field effect transistor 412 may be a Figures 1 to 5B The semiconductor device 100 described in , or a semiconductor device modified therefrom. The access transistor 411 may be used as a selection device to turn on / off the synapse device 410.

[0131] The neural network device 400 may further include a plurality of word lines WL, a plurality of bit lines BL, a plurality of input lines IL, and a plurality of output lines OL. In the access transistor 411, the gate may be electrically connected to any one of the word lines WL, the source may be electrically connected to any one of the bit lines BL, and the drain may be electrically connected to the gate of the ferroelectric field effect transistor 412. In addition, in the ferroelectric field effect transistor 412, the source may be electrically connected to any one of the input lines IL, and the drain may be electrically connected to any one of the output lines OL.

[0132] In the training operation of the neural network device 400, the access transistor 411 is individually turned on through the individual word line WL, and a programming pulse can be applied to the gate of the ferroelectric field effect transistor 412 through the bit line BL. The signal of the training data can be applied through the input line IL. Through the process, a weight can be stored in each of the ferroelectric field effect transistors 412.

[0133] During the inference operation of the neural network device 400, all access transistors 411 are turned on through all word lines WL, and a read voltage Vread may be applied through the bit line BL. Then, the sum of the currents from the synaptic devices 410 connected in parallel to the output lines OL may flow in each of the output lines OL. When the output circuit is connected to the output lines OL, the current flowing in each of the output lines OL may be converted into a digital signal.

[0134] Fig.11 is a schematic block diagram of an electronic device 500 including a neural network device according to at least one embodiment. Fig.11 , the electronic device 500 may extract effective information by analyzing input data in real time based on a neural network and perform context determination based on the extracted information, or may control components of a device on which the electronic device 500 is installed. For example, the electronic device 500 may be applied to a robot device such as a drone, an advanced driver assistance system (ADAS) and / or the like, a smart TV, a smart phone, a medical device, a mobile device, an image display device, a measuring device, an IoT device and / or the like, and may be additionally installed on at least one of a plurality of types of devices.

[0135] The electronic device 500 may include a processor 510, a random access memory (RAM) 520, a neural network device 530, a memory 540, a sensor module 550, and a communication module (Tx / Rx module) 560. The electronic device 500 may further include an input / output module, a security module, a power control device, and / or the like. Some of the hardware components of the electronic device 500 may be mounted on at least one semiconductor chip.

[0136] Processor 510 controls the overall operation of electronic device 500. Processor 510 may include one processor core (single core) or multiple processor cores (multi-core). Processor 510 may process or execute programs and / or data stored in memory 540. In some embodiments, processor 510 may control the functions of neural network device 530 by executing programs stored in memory 540. Processor 510 may be implemented by a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), and / or the like.

[0137] The RAM 520 may temporarily store programs, data, or instructions. For example, the programs and / or data stored in the memory 540 may be temporarily stored in the RAM 520 under the control of the processor 510 or according to a boot (startup) code. The RAM 520 may be implemented by a memory such as a dynamic RAM (DRAM), a static RAM (SRAM), and / or the like.

[0138] The neural network device 530 may be configured to perform neural network operations based on received input data, and generate information signals based on the results of the operations. The neural network may include a convolutional neural network (CNN), a recurrent neural network (RNN), a feedforward neural network (FNN), a long short-term memory (LSTM), a stacked neural network (SNN), a state-space dynamic neural network (SSDNN), a deep belief network (DBN), a restricted Boltzmann machine (RBM), and / or the like, but the present disclosure is not limited thereto. The neural network device 530 may be a neural network dedicated hardware accelerator itself or a device including the same. The neural network device 530 may not only perform neural network operations, but also perform read or write operations. The neural network device 530 may correspond to Fig.10 A neural network device 400 according to at least one embodiment is shown in FIG.

[0139] The information signal may include one of various types of recognition signals, such as a voice recognition signal, an object (target) recognition signal, an image recognition signal, a biometric information recognition signal, and / or the like. For example, the neural network device 530 may receive frame data included in a video stream as input data, and generate a recognition signal for an object included in an image represented by the frame data from the frame data. However, the present disclosure is not limited thereto, and based on the type or function of the device on which the electronic device 500 is installed, the neural network device 530 may receive various types of input data and generate a recognition signal according to the input data.

[0140] The neural network device 530 may be configured to perform, for example, machine learning models such as linear regression, logistic regression, statistical clustering, Bayesian classification, decision trees, principal component analysis, and / or expert systems, and / or machine learning models of integration techniques such as random forests and / or the like. These machine learning models may be used to provide various services such as image classification services, user authentication services based on biometric information or biometric data, ADAS, voice assistant services, automatic speech recognition (ASR) services, and / or the like.

[0141] The memory 540 , which is a place for storing data, may store an operating system (OS), various programs, and various pieces of data. In at least one embodiment, the memory 540 may store intermediate results generated during the operation of the neural network device 530 .

[0142] The memory 540 may include DRAM, but the present disclosure is not limited thereto. The memory 540 may include at least one of volatile memory or non-volatile storage. The non-volatile memory may include a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FRAM), and / or the like. The volatile memory may include a dynamic RAM (DRAM), a static RAM (SRAM), a synchronous DRAM (SDRAM), a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a ferroelectric RAM (FeRAM), and / or the like. In at least one embodiment, the memory 540 may include at least one of the following: a hard disk drive (HDD), a solid state drive (SSD), a compact flash (CF), a secure digital (SD), a micro secure digital (Micro-SD), a mini secure digital (Mini-SD), or a memory stick (memory stick).

[0143] The sensor module 550 may collect information around the device on which the electronic device 500 is mounted. The sensor module 550 may sense or receive a signal (e.g., an image signal, a voice signal, a magnetic signal, a bio-signal, a touch signal, and / or the like) from outside the electronic device 500, and convert the sensed or received signal into data. To this end, the sensor module 550 may include at least one of various types of sensing devices, such as a microphone, an imaging device, an image sensor, a light detection and ranging (LIDAR) sensor, an ultrasonic sensor, an infrared sensor, a bio-sensor, a touch sensor, and / or the like.

[0144] The sensor module 550 may provide the converted data as input data to the neural network device 530. For example, the sensor module 550 may include an image sensor, and may generate a video stream by photographing the external environment of the electronic device 500, and provide continuous data frames of the video stream as input data to the neural network device 530. However, the present disclosure is not limited thereto, and the sensor module 550 may provide various types of data to the neural network device 530.

[0145] The communication module 560 may include various wired or wireless interfaces for communicating with external devices. For example, the communication module 560 may include a communication interface capable of accessing a mobile cellular network and / or the like, such as a wired local area network (LAN), a wireless local area network (WLAN) such as wireless fidelity (Wi-Fi), a wireless personal area network such as Bluetooth, a wireless universal serial bus (USB), Zigbee, near field communication (NFC), radio frequency identification (RFID), power line communication (PLC), or third generation (3G), fourth generation (4G), long term evolution (LTE) and / or the like.

[0146] The semiconductor device described above can operate as a field effect transistor with an increased memory window.

[0147] The semiconductor device described above may have improved operational reliability and may be used as a memory cell of a memory device.

[0148] It should be understood that the semiconductor device and the electronic device including the same described herein should be considered in a descriptive sense only and not for limiting purposes. The description of features or aspects within each embodiment should typically be considered to be applicable to other similar features or aspects in other embodiments.

[0149] Although one or more embodiments have been described with reference to the drawings, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the following claims.

Claims

1. Semiconductor devices, including: a channel layer comprising a semiconductor material; a gate electrode spaced apart from the channel layer in a first direction; a ferroelectric layer between the channel layer and the gate electrode, the ferroelectric layer comprising a ferroelectric material; a first insulating layer between the ferroelectric layer and the gate electrode; a charge trapping layer between the ferroelectric layer and the first insulating layer, the charge trapping layer comprising a compound including a first element; as well as a second insulating layer between the channel layer and the ferroelectric layer, wherein the charge trapping layer includes a third layer, a second layer, and a first layer sequentially stacked on the ferroelectric layer in the first direction, and the first layer, the second layer, and the third layer each have a different concentration of the first element, and The highest value in the concentration gradient in the first layer is the first concentration value, the lowest value in the concentration gradient in the second layer is the second concentration value, the highest value in the concentration gradient in the third layer is the third concentration value, and the second concentration value is lower than the first concentration value and the third concentration value. 2 . The semiconductor device according to claim 1 , wherein the first concentration value is higher than the third concentration value. 3 . The semiconductor device according to claim 1 , wherein a thickness of the second layer is 50% or more of a total thickness of the charge trapping layer.

4. The semiconductor device according to claim 1, wherein: In the concentration gradient of the second layer, a length in the first direction of a region having a concentration lower than the third concentration value is 60% or more of a thickness of the second layer. 5 . The semiconductor device according to claim 1 , wherein a thickness of the second layer is greater than a thickness of the first layer and a thickness of the third layer. 6 . The semiconductor device according to claim 1 , wherein a thickness of the third layer is 1% or more of a total thickness of the charge trapping layer. 7 . The semiconductor device according to claim 1 , wherein a thickness of the third layer is greater than a thickness of the first layer.

8. The semiconductor device of claim 1, wherein the charge trapping layer further comprises nitrogen.

9. The semiconductor device of claim 1, wherein the first layer, the second layer, and the third layer each independently include a compound represented by MN, wherein M represents the first element and includes one or more elements selected from the group consisting of Al, Ga, Ge, Si, C, In, Y, Sc, and Zr, and N represents nitrogen.

10. The semiconductor device of claim 8, wherein the first layer, the second layer, and the third layer each independently comprise a nitride of the first element, wherein a nitrogen content is less than stoichiometric. 11 . The semiconductor device of claim 1 , wherein the second insulating layer comprises an oxide of a material of the channel layer.

12. The semiconductor device of claim 1, wherein the ferroelectric material of the ferroelectric layer comprises a hafnium oxide-based material.

13. The semiconductor device of claim 12, wherein the ferroelectric material further comprises at least one of the following as a dopant: Zr, La, Al, Si, Y, B or Sc.

14. The semiconductor device of claim 1, wherein the first element comprises one or more elements selected from the group consisting of Al, Ga, Ge, Si, C, In, Y, Sc, and Zr.

15. Semiconductor devices, including: a channel layer comprising a semiconductor material; a gate electrode spaced apart from the channel layer in a first direction; a ferroelectric layer between the channel layer and the gate electrode, the ferroelectric layer comprising a ferroelectric material; a first insulating layer between the ferroelectric layer and the gate electrode; a charge trapping layer between the ferroelectric layer and the first insulating layer, the charge trapping layer comprising silicon nitride; as well as a second insulating layer between the channel layer and the ferroelectric layer, The charge trapping layer includes a third layer, a second layer and a first layer sequentially stacked on the ferroelectric layer in the first direction, and the first layer, the second layer and the third layer each have a different concentration, so that the silicon concentration in the charge trapping layer is the lowest in the second layer and the highest in the first layer.

16. The semiconductor device according to claim 10 or 15, wherein the first layer, the second layer and the third layer each independently comprise Si3N 4-x , where 0 <x≤2。 17. Electronic equipment, including: Semiconductor substrates; and a plurality of memory cells stacked on the semiconductor substrate, wherein each of the plurality of memory cells comprises a semiconductor device as claimed in any one of claims 1 to 16, and The first direction is perpendicular to the stacking direction of the plurality of storage units.

18. The electronic device of claim 17, further comprising: Spacers including insulating material are provided between the plurality of memory cells such that the spacers are between adjacent gate electrodes.

19. The electronic device of claim 18, wherein the adjacent gate electrodes and the spacer have a shell shape having connected inner surfaces.

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