Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a driving array layer, wherein the driving array layer comprises a functional layer and an insulating layer; the driving array layer comprises a first transistor and a second transistor, an active layer of the first transistor comprises silicon, and an active layer of the second transistor comprises an oxide semiconductor; the driving array layer further comprises a first capacitor and a second capacitor, the first capacitor comprises a first polar plate and a second polar plate, and the second capacitor comprises a third polar plate and a fourth polar plate; wherein the first polar plate and the second polar plate are respectively located at any two functional layers in the functional layers, and the third polar plate and the fourth polar plate are respectively located at any two functional layers in the functional layers. The functional layer where the capacitor plate is located can be flexibly arranged according to the positions of the first capacitor and the second capacitor in the circuit structure.

Description

[0001] This application is a divisional application with the application date of October 23, 2020, application number 202011150331.5, and invention name “Display panel and display device”. Technical Field

[0002] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] Organic Light Emitting Diode (OLED) has the characteristics of self-luminescence, fast response, wide color gamut, large viewing angle, high brightness, etc. It can be used to make thin display devices and flexible display devices, and has gradually become the focus of research in the current display technology field. When used in the display field, it is necessary to set a drive array layer in the display panel to drive the organic light-emitting diode to emit light to achieve display. The drive array layer includes a complex circuit structure composed of multiple transistors. Usually, the transistors in the circuit structure of the drive array layer are all transistors of the same type, and each transistor can be made in the same process, thereby simplifying the manufacturing process of the drive array layer. However, the role of each transistor in the circuit structure is not necessarily the same. If each transistor is a transistor of the same type, it is difficult to meet the different requirements for transistor characteristics in the circuit structure. It also limits the freedom of setting other components in the circuit structure. Summary of the invention

[0004] Embodiments of the present invention provide a display panel and a display device to solve the technical problem of low degree of freedom in setting circuit elements in a driving array layer in the prior art.

[0005] In a first aspect, an embodiment of the present invention provides a display panel, including: A driving array layer, the driving array layer comprising a functional layer and an insulating layer; The driving array layer includes a first transistor and a second transistor, the active layer of the first transistor includes silicon, and the active layer of the second transistor includes an oxide semiconductor; The driving array layer further includes a first capacitor and a second capacitor, the first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate; wherein, The first electrode plate and the second electrode plate are respectively located at any two functional layers in the functional layer, and the third electrode plate and the fourth electrode plate are respectively located at any two functional layers in the functional layer.

[0006] In a second aspect, an embodiment of the present invention further provides a display device, comprising the display panel provided by any embodiment of the present invention.

[0007] The display panel and display device provided by the embodiments of the present invention have the following beneficial effects: the drive array layer includes a first transistor and a second transistor, the first transistor and the second transistor are of different types, and the first transistor and the second transistor can respectively provide different characteristic performances to meet different requirements for transistors in the circuit structure. Moreover, the arrangement of the first transistor and the second transistor can increase the film layer structure of the drive array layer, and the two plates of the first capacitor and the two plates of the second capacitor in the drive array layer can be respectively arranged in any functional layer of the drive array layer. The present invention can flexibly arrange the functional layer where the capacitor plates are located according to the positions of the first capacitor and the second capacitor in the circuit structure, thereby increasing the degree of freedom of arrangement of the functional layer where the two plates of the first capacitor and the two plates of the second capacitor are located. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0009] Figure 1 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention; Figure 2 A film layer structure diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Figure 3 A film layer structure diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Figure 4 A film layer structure diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Figure 5 A film layer structure diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Figure 6 A film layer structure diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Figure 7 A schematic diagram of an optional implementation of a pixel circuit in a display panel provided by an embodiment of the present invention; Figure 8 A schematic diagram of a structure of a driving circuit provided by an embodiment of the present invention; Fig. 9 A schematic structural diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Fig.10 A schematic structural diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Fig.11 A schematic structural diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Fig.12 A schematic diagram of another optional implementation of a pixel circuit in a display panel provided by an embodiment of the present invention; Fig.13 for Fig.12 A schematic diagram of a film layer structure of a display panel provided in an embodiment; Fig.14 A schematic diagram of a film layer structure of another optional implementation of a display panel provided in an embodiment of the present invention; Fig.15 A schematic diagram of another optional implementation of a pixel circuit in a display panel provided by an embodiment of the present invention; Fig.16 for Fig.15 A timing diagram of a pixel circuit in a display panel provided in an embodiment; Fig.17 for Fig.15 A pixel circuit wiring diagram in a display panel provided in an embodiment; Fig.18 for Fig.17 A schematic diagram of a film layer structure of a display panel provided in an embodiment; Fig.19 A schematic diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Fig. 20 A schematic diagram of another optional implementation of a pixel circuit of a display panel provided in an embodiment of the present invention; Fig.21 for Fig. 20 A timing diagram of a pixel circuit provided in an embodiment; Fig. 22 A pixel circuit wiring diagram of another optional implementation of a display panel provided in an embodiment of the present invention; Fig.23 for Figure 7 A timing diagram of a pixel circuit provided in an embodiment; Fig.24 for Fig. 22 A schematic diagram of a film layer structure of a display panel provided in an embodiment; Fig.25 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0010] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0011] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0012] Based on the problems in the related art, an embodiment of the present invention provides a display panel, which includes a drive array layer and a light-emitting device layer, wherein the light-emitting device layer includes a plurality of light-emitting elements, wherein the light-emitting elements are organic light-emitting diodes. By setting the drive array layer to include different types of transistors, different requirements for transistor performance in different circuit structures can be met. At the same time, the degree of freedom of setting the film layer position of the element in the circuit structure is increased.

[0013] An embodiment of the present invention provides a display panel. Figure 1 A schematic diagram of a film layer structure of a display panel provided by an embodiment of the present invention, such as Figure 1 As shown, the display panel includes a drive array layer 101 and a light emitting device layer 102, and a packaging layer 103 located on the light emitting device layer 102. The drive array layer 101 includes a functional layer (not shown) and an insulating layer (not shown); wherein the functional layer is provided with electrodes, or wirings, or capacitor plates in the circuit structure. The insulating layer is used to separate two adjacent functional layers. Figure 1 As shown in the figure, the driving array layer 101 includes a first transistor T1 and a second transistor T2, the active layer of the first transistor T1 is a first active layer w1, the first active layer w1 includes silicon, and the active layer of the second transistor T2 is a second active layer w2, the second active layer w2 includes an oxide semiconductor. That is, the first transistor T1 and the second transistor T2 are of different types. In one embodiment, the first transistor T1 is a low-temperature polysilicon transistor, and the second transistor T2 is an oxide transistor. Among them, the film layer where the first gate g1 of the first transistor T1 is located, the film layer where the first active layer w1 of the first transistor T1 is located, the film layer where the second gate g2 of the second transistor T2 is located, the film layer where the second active layer w2 of the second transistor T2 is located, the first source s1 and the first drain d1 of the first transistor T1, and the film layer where the second source and the second drain of the second transistor are located are all functional layers. Figure 1In the figure, only the first transistor T1 and the second transistor T2 are shown as top-gate structures. In the actual driving array layer, the first transistor and the second transistor can also be bottom-gate structure transistors. The driving array layer 101 can also include other functional layers not shown. In addition, the light-emitting device layer 102 includes a light-emitting element OL ( Figure 1 Only one is shown in the figure), the light emitting element OL includes an anode a, a light emitting layer b and a cathode c stacked in sequence. The encapsulation layer 103 is used to encapsulate and protect the light emitting element OL. The encapsulation layer 103 can be a rigid encapsulation, including encapsulation glass, and the encapsulation glass is bonded and fixed to the drive array layer by a frame sealant. The encapsulation layer 103 can also be a flexible encapsulation, including at least one organic encapsulation layer and at least one inorganic encapsulation layer.

[0014] In the embodiment of the present invention, the driving array layer 101 further includes a first capacitor (not shown) and a second capacitor (not shown), the first capacitor includes a first electrode plate and a second electrode plate, and the second capacitor includes a third electrode plate and a fourth electrode plate; wherein the first electrode plate and the second electrode plate are respectively located at any two functional layers among the functional layers, and the third electrode plate and the fourth electrode plate are respectively located at any two functional layers among the multiple functional layers.

[0015] In the display panel provided by the embodiment of the present invention, the driving array layer includes a first transistor and a second transistor. The first transistor and the second transistor are of different types. The first transistor and the second transistor can respectively provide different characteristic performances to meet different requirements for transistors in the circuit structure. Moreover, the arrangement of the first transistor and the second transistor can increase the film layer structure of the driving array layer. The two plates of the first capacitor and the two plates of the second capacitor in the driving array layer can be respectively arranged in any functional layer of the driving array layer. The present invention can flexibly arrange the functional layer where the capacitor plates are located according to the positions of the first capacitor and the second capacitor in the circuit structure, thereby increasing the degree of freedom of arrangement of the functional layer where the two plates of the first capacitor and the two plates of the second capacitor are located.

[0016] In one embodiment, one plate of the first capacitor and one plate of the second capacitor are located in the same functional layer. Figure 2 A film layer structure diagram of another optional implementation of a display panel provided in an embodiment of the present invention. The figure only schematically shows the drive array layer 101. The film layer where the gate g1 of the first transistor T1 is located, the film layer where the active layer w1 of the first transistor T1 is located, the film layer where the gate g2 of the second transistor T2 is located, the film layer where the active layer w2 of the second transistor T2 is located, the source s1 and drain d1 of the first transistor T1, and the source s2 and drain d2 of the second transistor T2 are all functional layers. In addition, an additional conductive layer may be added to the drive array layer as a functional layer. Figure 2As shown, the first capacitor C1 includes a first plate c11 and a second plate c12, and the second capacitor C2 includes a third plate c23 and a fourth plate c24. The first plate c11 and the third plate c23 are located in the same functional layer, and the second plate c12 and the fourth plate c24 are located in different functional layers. In the embodiment of the present invention, according to the connection relationship between the first capacitor C1 and the second capacitor C2 and other circuit elements (such as transistors) in the circuit structure where the first capacitor C1 and the second capacitor C2 are respectively located, the functional layers where the two plates of the first capacitor C1 are respectively located are set, and the functional layers where the two plates of the second capacitor C2 are respectively located are set. In this embodiment, the first plate of the first capacitor and the third plate of the second capacitor are located in the same functional layer, and the first plate and the third plate can be made in the same process. The functional layer where the second plate is located can be set according to the capacitance value requirement of the first capacitor and the connection relationship between the first capacitor and the circuit element, and at the same time, the functional layer where the fourth plate is located can also be set according to the capacitance value requirement of the second capacitor and the connection relationship between the second capacitor and the circuit element.

[0017] In another embodiment, one electrode plate of the first capacitor and one electrode plate of the second capacitor are located in the same functional layer. Another electrode plate of the first capacitor and another electrode plate of the second capacitor are also located in the same functional layer. Figure 3 This is another optional film layer structure diagram of the display panel provided in the embodiment of the present invention. Figure 3 As shown, the first capacitor C1 includes a first plate c11 and a second plate c12, and the second capacitor C2 includes a third plate c23 and a fourth plate c24. The first plate c11 and the third plate c23 are located in the same functional layer, and the second plate c12 and the fourth plate c24 are located in the same functional layer. In this embodiment, the first plate and the third plate are located in the same functional layer, and the first plate and the third plate can be manufactured in the same process; the second plate and the fourth plate are located in the same functional layer, and the second plate and the fourth plate can be manufactured in the same process. While meeting the performance requirements of the first capacitor and the second capacitor, it is beneficial to further reduce the film thickness of the drive array layer.

[0018] In another embodiment, Figure 4 This is another optional film layer structure diagram of the display panel provided in the embodiment of the present invention. Figure 4As shown, the first capacitor C1 includes a first plate c11 and a second plate c12, and the second capacitor C2 includes a third plate c23 and a fourth plate c24. The first plate c11, the second plate c12, the third plate c23 and the fourth plate c24 are respectively located in different functional layers. This embodiment can set the functional layers where the first plate and the second plate are located according to the capacitance value requirements of the first capacitor and the connection relationship between the first capacitor and the circuit element. At the same time, the functional layers where the third plate and the fourth plate are located can also be set according to the capacitance value requirements of the second capacitor and the connection relationship between the second capacitor and the circuit element. Thereby increasing the design freedom of the first capacitor and the second capacitor, the circuit structure applicable to the first capacitor and the second capacitor is more extensive.

[0019] Optionally, the electrode plate of the first capacitor and / or the second capacitor may also be arranged in the same layer as the active layer of the transistor. The electrode plate of the capacitor is arranged in the same layer as the first active layer of the first transistor or in the same layer as the second active layer of the second transistor. Figure 4 As shown in FIG. 1 , the third electrode plate c23 of the second capacitor C2 is disposed on the same layer as the second active layer w2 of the second transistor T2. Specifically, in another embodiment, Figure 5 This is another optional film layer structure diagram of the display panel provided in the embodiment of the present invention. Figure 5As shown, the driving array layer 101 includes a first transistor T1 and a second transistor T2, the active layer of the first transistor T1 is a first active layer w1, the first active layer w1 includes silicon, the active layer of the second transistor T2 is a second active layer w2, and the second active layer w2 includes an oxide semiconductor. The first plate c11 of the first capacitor C1 is arranged in the same layer as the first active layer w1, and the second plate c12 of the first capacitor C1 is arranged in the same layer as the first gate g1 of the first transistor T1. The third plate c23 of the second capacitor C2 is arranged in the same layer as the second active layer w2, and the fourth plate C24 of the second capacitor C2 is arranged in the same layer as the second gate g2. In the manufacturing process, a semiconductor material containing silicon is used to simultaneously form the pattern of the first plate c11 in the patterning process of the first active layer w1, and then the pattern of the first plate c11 is processed by an ion doping process to increase the conductivity of the first plate c11. The first active layer w11 includes a channel region and an electrode contact region. The first source s1 and the first drain d2 of the first transistor T1 are electrically connected to different electrode contact regions, respectively. After the patterning process, the semiconductor material containing silicon is treated by an ion doping process to increase its conductivity and form an electrode contact region. Then the ion doping process of the first electrode plate c11 can be carried out simultaneously with the ion doping process of the electrode contact region, and the production of the first electrode plate c11 does not require additional process steps. Similarly, the pattern of the third electrode plate s23 can be formed simultaneously in the patterning process of the second active layer w2. The second active layer w2 is made of oxide semiconductor. After the patterning process, the local area of ​​the second active layer w2 needs to be conductorized to form an electrode contact region. The conductorization process of the third electrode plate c23 can be carried out simultaneously with the conductorization process of the electrode contact region of the second active layer w2. Then the production of the third electrode plate c23 does not require additional process steps.

[0020] Furthermore, the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor. The first capacitor and the second capacitor having different capacitance values ​​are arranged in the driving array layer, which can meet the requirements of the capacitance value of the capacitor in different circuit structures in the driving array layer, or the requirements of the capacitance value of the capacitor in different functional modules in the same circuit structure. In practical applications, the first capacitor and the second capacitor can be arranged according to specific circuit requirements.

[0021] Optionally, in a specific embodiment, Figure 6 This is another optional film layer structure diagram of the display panel provided in the embodiment of the present invention. Figure 6As shown, the driving array layer 101 includes a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 which are sequentially away from the base substrate 110, wherein the first gate g1, the first plate c11 of the first capacitor C1, and the third plate c23 of the second capacitor C2 are located in the first metal layer M1, the second plate c12 of the first capacitor C1 is located in the second metal layer M1, the second gate g2 of the second transistor is located in the third metal layer M3, the first source s1 and the first drain d1 of the first transistor T1, the second source s2 and the second drain d2 of the second transistor T2, and the fourth plate c24 of the second capacitor C2 are all located in the fourth metal layer M4. The production of the capacitor plates does not increase the process, and the film layer where the capacitor plates are located can be set to adjust the distance between the two plates of the capacitor, so as to meet the requirements of the capacitor on the capacitance value.

[0022] It should be noted that the following embodiments will involve the description that the second transistor includes a second gate and a third gate, the second active layer is located between the second gate and the third gate, the second gate is located in the second metal layer, and the third gate is located in the third metal layer. Figure 6 The description of the embodiment does not contradict the following embodiment. When understanding the specific embodiment of the present invention, please refer to the specific film layer position and the specific transistor structure for understanding.

[0023] In one embodiment, the driving array layer includes a pixel circuit, and the pixel circuit includes a driving transistor. Figure 7 A schematic diagram of an optional implementation of a pixel circuit in a display panel provided in an embodiment of the present invention is shown in FIG. Figure 7 As shown, the light emitting element OL is also schematically shown, and the pixel circuit is electrically connected to the light emitting element OL. The pixel circuit includes a first capacitor C1 and a second capacitor C2; the first capacitor C1 is connected between the first power signal terminal PV1 and the gate of the driving transistor Tm, and is used to store the signal transmitted to the gate of the driving transistor Tm. Figure 7 The pixel circuit shown in the figure includes a data writing module 10, a light emitting control module 20, a threshold compensation module 30, a light emitting element reset module 40 and a bias adjustment module 50, as well as a first node N1, a second node N2, a third node N3, and a fourth node N4. The light emitting control terminal E, the first scanning signal terminal S1, the second scanning signal terminal S2, the third scanning signal terminal S3, the data signal terminal Vdata, the reset signal terminal Vref, and the bias adjustment signal terminal Dv are also shown.

[0024] Optional, such as Figure 7As shown, the control end (gate) of the driving transistor Tm is connected to the first node N1, the first electrode of the driving transistor Tm is connected to the second node N2, and the second electrode of the driving transistor Tm is connected to the third node N3; the first end of the data writing module 10 is connected to the data signal end Vdata, the second end of the data writing module 10 is connected to the second node N2, the control end of the data writing module 10 is connected to the second scanning signal end S2, and the data writing module 10 is used to write data signals; the first end of the threshold compensation module 30 is connected to the first node N1, the second end of the threshold compensation module 30 is connected to the third node N3, and the control end of the threshold compensation module 30 is connected to the first scanning signal end S1.

[0025] Optionally, the light control module 20 includes a first light control module 201 and a second light control module 202, wherein a first end of the first light control module 201 is connected to a first power signal end PV1, a second end of the first light control module 201 is connected to a second node N2, a first end of the second light control module 202 is connected to a third node N3, and a second end of the second light control module 202 is connected to a fourth node N4. The control end of the first light control module 201 and the control end of the second light control module 202 are both connected to a light control end E, and the light control module 20 is used to control whether the light emitting element OL emits light.

[0026] Continue to refer Figure 7 Optionally, the pixel circuit in the display panel also includes a bias adjustment module 50, a first end of the bias adjustment module 50 is connected to the bias adjustment signal end Dv, a second end of the bias adjustment module 50 is connected to the third node N3, a control end of the bias adjustment module 50 is connected to the third scan signal end S3, and the bias adjustment module 50 is used to adjust the bias state of the driving transistor.

[0027] Optionally, the pixel circuit further includes a storage capacitor, a first end of the storage capacitor is connected to the first power signal terminal PV1, a second end of the storage capacitor is connected to the first node N1, and the storage capacitor is used to stabilize the gate potential of the driving transistor Tm.

[0028] Figure 7 In the embodiment, the first capacitor C1 is shown as a storage capacitor, one plate of the second capacitor C2 is connected to the third node N3, and the other plate is connected to the light-emitting control terminal E1 for illustration. In this embodiment, the pixel circuit includes a first capacitor and a second capacitor, wherein the first capacitor is a storage capacitor, and the second capacitor is an auxiliary capacitor. The second capacitor can pull up the potential of the third node N3 when the signal provided by the light-emitting control terminal E is a rising edge, so that the potential of the third node N3 is higher than the potential of the first node N1, and can be used to adjust the bias state of the driving transistor Tm to improve the threshold drift caused by the hysteresis effect caused by the forward bias of the driving transistor Tm in the light-emitting stage. Figure 7Only one connection relationship between the first capacitor and the second capacitor and the circuit element in the pixel circuit is illustrated. In other embodiments, the second capacitor may be a storage capacitor and the first capacitor may be an auxiliary capacitor. In subsequent specific embodiments of the pixel circuit, the connection relationship between the capacitor (referring to the first capacitor and the second capacitor) and the circuit element in the pixel circuit, as well as the role of the capacitor in the pixel circuit will be described in detail.

[0029] In another embodiment, the drive array layer includes a drive circuit, which provides a control signal to the pixel circuit of the display panel. Figure 7 Taking the illustrated pixel circuit as an example, the light emitting control terminal E1 , the scanning control terminal S1 , the scanning control terminal S2 , and the scanning control terminal S3 are provided with signals by different driving circuits respectively. Figure 8 A schematic diagram of a driving circuit provided by an embodiment of the present invention. Figure 8 As shown, the driving circuit includes an output terminal OUT and an output module 20; the driving circuit includes a first capacitor C1 and a second capacitor C2; the first capacitor C1 is connected between the control terminal of the output module 20 (i.e., the first node N1 in the circuit) and the output terminal OUT. The output module 20 includes a first transistor M1 and a second transistor M2, the control terminal of the first transistor M1 is electrically connected to the first node N1, the first terminal of the first transistor M1 is electrically connected to the clock signal terminal CK1, and the second terminal of the first transistor M1 is electrically connected to the output terminal OUT; the control terminal of the second transistor M2 is electrically connected to the second node N2, the first terminal of the second transistor M2 is electrically connected to the level signal terminal VGH, and the second terminal of the second transistor M2 is electrically connected to the output terminal OUT.

[0030] Figure 8The figure also illustrates a first input module 70, a second input module 80, a first protection module 60 and a second protection module 90 in the driving circuit. The first input module 70 includes a third transistor M3 and a fourth transistor, the control end of the third transistor M3 is electrically connected to the clock signal end CK2, the first end of the third transistor M3 is electrically connected to the input end IN, and the second end of the third transistor M3 is electrically connected to the third node N3; the control end of the fourth transistor M4 is electrically connected to the level signal end VGL, the first end of the fourth transistor M4 is electrically connected to the third node N3, and the second end of the fourth transistor M4 is electrically connected to the first node N1. The first input module 70 is used to write a voltage signal to the first node N1. The second input module 80 includes a seventh transistor M7, the control end of the seventh transistor M7 is electrically connected to the clock signal end CK2, the first end of the seventh transistor M7 is electrically connected to the level signal end VGL, and the second end of the seventh transistor M7 is electrically connected to the second node N2. The second input module 80 is used to write a voltage signal to the second node N2. The first protection module 60 includes a fifth transistor M5 and a sixth transistor M6, wherein the control end of the fifth transistor M5 is electrically connected to the clock signal end CK1, the first end of the fifth transistor M5 is electrically connected to the second end of the sixth transistor M6, and the second end of the fifth transistor M5 is electrically connected to the third node N3; the control end of the sixth transistor M6 is electrically connected to the second node N2, and the first end of the sixth transistor M6 is electrically connected to the level signal end VGH. The first protection module 60 is used to control the high level signal to be provided to the first node N1 when the second node N2 is at a low level, so as to achieve the opposite potential of the first node N1 and the second node N2. The second protection module 90 includes an eighth transistor M8, wherein the control end of the eighth transistor M8 is electrically connected to the third node N3, the first end of the eighth transistor M8 is electrically connected to the clock signal end CK2, and the second end of the eighth transistor M8 is electrically connected to the second node N2. The second protection module 90 is used to provide a high level signal to the second node when the first node N1 is at a low level, so as to achieve the opposite potential of the first node N1 and the second node N2.

[0031] The circuit structure in this embodiment is only schematically represented and is not used as a limitation of the present invention. It is only to illustrate the position of the first capacitor in the drive circuit in the embodiment of the present invention, wherein the first capacitor is connected between the control end and the output end of the output module, and the first capacitor is used to stabilize the potential of the control end of the output module to ensure that the output end can stably output the corresponding level signal. The present invention does not limit the connection relationship between the second capacitor and other functional modules in the drive circuit. Based on the concept of the present invention, in the drive circuit including the first capacitor and the second capacitor, the functional layer where the two plates of the first capacitor are located can be set according to the capacitance value requirement of the first capacitor in the circuit structure and the connection relationship between the first capacitor and other circuit elements. At the same time, the functional layer where the two plates of the second capacitor are located can be set according to the capacitance value requirement of the second capacitor in the circuit structure and the connection relationship between the second capacitor and other circuit elements.

[0032] In another embodiment, the driving array layer includes a pixel circuit and a driving circuit, the driving circuit provides a control signal for the pixel circuit; the pixel circuit includes a first capacitor, and the driving circuit includes a second capacitor. The first capacitor in the pixel circuit can be Figure 7 The capacitor connected between the first power signal terminal PV1 and the gate of the driving transistor Tm in the embodiment may also be other capacitors in the pixel circuit. The second capacitor in the driving circuit may be Figure 8 The capacitor between the control terminal and the output terminal OUT connected to the output module 20 is shown in the figure, and it can also be a capacitor connected to other functional modules in the driving circuit. In the application, the first capacitor can be set in the pixel circuit according to the specific design requirements, and the functional layer where the two plates of the first capacitor are located is set according to the capacitance value requirement of the first capacitor in the circuit structure and the connection relationship between the first capacitor and other circuit elements. At the same time, the second capacitor is set in the driving circuit, and the functional layer where the two plates of the second capacitor are located is set according to the capacitance value requirement of the second capacitor in the circuit structure and the connection relationship between the second capacitor and other circuit elements. In one embodiment, one plate of the first capacitor and one plate of the second capacitor are located in the same functional layer of the driving array layer. In another embodiment, one plate of the first capacitor and one plate of the second capacitor are located in the same functional layer of the driving array layer, and another plate of the first capacitor and another plate of the second capacitor are also located in the same functional layer of the driving array layer. In another embodiment, the first capacitor and the second capacitor have a total of four plates, which are respectively located in different functional layers. In the application, the functional layer where the capacitor plates are located can be flexibly set according to the positions of the first capacitor and the second capacitor in the circuit structure.

[0033] Specifically, in one embodiment, the pixel circuit includes a first transistor and a first capacitor, the driving circuit includes a second transistor and a second capacitor, the active layer of the first transistor includes silicon, and the active layer of the second transistor includes an oxide semiconductor. In the pixel circuit, the first transistor is a low-temperature polysilicon transistor, the first transistor can be a driving transistor in the pixel circuit, or a switching transistor in the circuit, and when the first transistor in the pixel circuit is a switching transistor, its driving transistor can be an oxide transistor; the first capacitor in the pixel circuit can be a storage capacitor or other auxiliary capacitor. The second transistor in the driving circuit is an oxide transistor, and the second capacitor in the driving circuit can be a capacitor connected between the output end of the driving circuit and the control end of the output module. In the projection direction perpendicular to the surface of the display panel, the first capacitor and the first transistor of the pixel circuit at least partially overlap; the second capacitor and the second transistor do not overlap each other. In this embodiment, the first capacitor and the first transistor are set in the pixel circuit to overlap at least partially, which can reduce the size of a pixel circuit, and then reduce the spacing between adjacent pixel circuits, and more pixel circuits can be set within a certain area of ​​the driving array layer, which is conducive to improving the sub-pixel setting density in the display panel to improve the display resolution. In addition, the light transmittance of the display panel can be improved, and the optical performance can be improved when applied to the under-screen optical element solution or the transparent display panel solution. In addition, the space occupied by the drive circuit set in the non-display area of ​​the display panel will not affect the resolution of the display panel. The second capacitor and the second transistor are set in the drive circuit so that they do not overlap with each other, which can reduce the crosstalk between the drive circuit components, thereby ensuring the stability of the drive performance of the drive circuit, which is conducive to ensuring the stability of the display performance of the display panel.

[0034] In another embodiment, the pixel circuit includes a first transistor and a first capacitor, the driving circuit includes a second transistor and a second capacitor, the active layer of the first transistor includes silicon, and the active layer of the second transistor includes an oxide semiconductor. In the pixel circuit, the first transistor is a low-temperature polysilicon transistor, the first transistor can be a driving transistor in the pixel circuit, or a switching transistor in the circuit, and when the first transistor in the pixel circuit is a switching transistor, the driving transistor can be an oxide transistor; the first capacitor in the pixel circuit can be a storage capacitor or other auxiliary capacitor. The second transistor in the driving circuit is an oxide transistor, and the second capacitor in the driving circuit can be a capacitor connected between the output end of the driving circuit and the control end of the output module. In the projection direction perpendicular to the surface of the display panel, the overlapping area between the first capacitor and the first transistor of the pixel circuit is greater than the overlapping area between the second capacitor and the second transistor. In this embodiment, the size of a pixel circuit can be reduced, which is conducive to increasing the density of sub-pixels in the display panel to improve the display resolution. It can also improve the transmittance of the display panel, and can improve the optical performance when applied to the under-screen optical element solution or the transparent display panel solution. In addition, setting the overlap between the second capacitor and the second transistor can reduce the space occupied by the driving circuit in the non-display area, which is beneficial to reducing the area of ​​the non-display area and improving the screen-to-body ratio. At the same time, this embodiment can achieve a balance between improving display resolution, avoiding crosstalk between driving circuit components, and ensuring display performance stability by setting the overlap between the capacitor and the transistor in the pixel circuit and the overlap between the capacitor and the transistor in the driving circuit, thereby ensuring that the display panel has an overall better performance.

[0035] In some embodiments, the pixel circuit includes a first transistor and a third transistor, the active layer of the first transistor includes silicon, and the active layer of the third transistor includes an oxide semiconductor; the driving circuit includes a second transistor and a fourth transistor, the active layer of the second transistor includes an oxide semiconductor, and the active layer of the fourth transistor includes silicon. Specifically, in one embodiment, the first transistor in the pixel circuit is a driving transistor, and the third transistor is a switching transistor; in another embodiment, the first transistor in the pixel circuit is a switching transistor, and the third transistor is a driving transistor. In the driving circuit, according to the requirements of the specific functional module for the transistor characteristics, the transistor can be set to a second transistor whose active layer includes an oxide semiconductor, or a fourth transistor whose active layer includes silicon. In this embodiment, the width of the channel region of the first transistor is W1 and the length is L1; the width of the channel region of the second transistor is W2 and the length is L2; ​​the width of the channel region of the third transistor is W3 and the length is L3; the width of the channel region of the fourth transistor is W4 and the length is L4. In the driving array board, the active layers of the first transistor and the fourth transistor both include silicon, and the active layers of the second transistor and the third transistor both include oxide semiconductors. Among them, the active layer of the first transistor and the active layer of the fourth transistor can be manufactured in the same process, the active layer of the second transistor and the active layer of the third transistor can be manufactured in the same process, and the sizes of the channel regions of the first transistor, the second transistor, the third transistor and the fourth transistor are different. Then, the pixel circuit and the driving circuit can meet the characteristics of transistors of different functional modules by setting different types of transistors, so as to improve the circuit performance stability of the pixel circuit and the driving circuit respectively.

[0036] Further, the pixel circuit includes a first transistor and a third transistor, the active layer of the first transistor includes silicon, the active layer of the third transistor includes an oxide semiconductor, the driving circuit includes a second transistor and a fourth transistor, the active layer of the second transistor includes an oxide semiconductor, and the active layer of the fourth transistor includes silicon. Wherein, the first transistor and the third transistor are both switch transistors of the pixel circuit; |W1 / L1-W4 / L4|<|W2 / L2-W3 / L3|. In the display panel, the absolute value of the difference between the width-to-length ratio of the first transistor in the pixel circuit and the width-to-length ratio of the fourth transistor in the driving circuit is smaller than the absolute value of the difference between the width-to-length ratio of the third transistor in the pixel circuit and the width-to-length ratio of the second transistor in the driving circuit; in other words, the difference between the width-to-length ratio of the silicon-based transistors in the pixel circuit and the driving circuit is smaller than the difference between the width-to-length ratio of the oxide transistors; since the number of silicon-based transistors in the display panel of the prior art is greater than the number of oxide transistors, the occupied area of ​​the silicon-based transistors in the driving array layer is larger, and if the difference in the width-to-length ratio of the silicon-based transistors in the pixel circuit and the driving circuit is too large, it will affect the etching uniformity in the preparation process. Furthermore, |W1 / L1-W4 / L4|<|W2 / L2-W3 / L3| can not only ensure the preparation process of the silicon-based transistors, but also the difference in the width-to-length ratio of the oxide transistors can be greater than the difference in the width-to-length ratio of the silicon-based transistors, so that the width-to-length ratio of oxide transistors in different positions and functions can be set according to actual needs.

[0037] Further, the pixel circuit includes a first transistor and a third transistor, the active layer of the first transistor includes silicon, the active layer of the third transistor includes an oxide semiconductor, the driving circuit includes a second transistor and a fourth transistor, the active layer of the second transistor includes an oxide semiconductor, and the active layer of the fourth transistor includes silicon. The first transistor is a driving transistor of the pixel circuit, the third transistor is a switching transistor of the pixel circuit, and |W1 / L1-W4 / L4|>5×|W2 / L2-W3 / L3|. When the first transistor is a driving transistor, the first transistor in the pixel circuit requires a larger width-to-length ratio to enhance the driving performance, while the fourth transistor in the driving circuit does not require a large width-to-length ratio as a switching transistor, so |W1 / L1-W4 / L4| is greater than |W2 / L2-W3 / L3|; further, |W1 / L1-W4 / L4|>5×|W2 / L2-W3 / L3|, generally the width-to-length ratio of the driving transistor is five times or more than that of the switching transistor, and the driving performance of the driving transistor and the switching capability of the switching transistor are both optimized. By setting |W1 / L1-W4 / L4| to be at least five times greater than |W2 / L2-W3 / L3|, it can be ensured that the width-to-length ratio of the first transistor and the width-to-length ratios of other switching transistors can meet the requirements of their respective performance.

[0038] Further, the pixel circuit includes a first transistor and a third transistor, the active layer of the first transistor includes silicon, the active layer of the third transistor includes an oxide semiconductor, and the driving circuit includes a second transistor and a fourth transistor, the active layer of the second transistor includes an oxide semiconductor, and the active layer of the fourth transistor includes silicon. Wherein, the first transistor is a switching transistor of the pixel circuit, the third transistor is a driving transistor of the pixel circuit, and 5×|W1 / L1-W4 / L4|<|W2 / L2-W3 / L3|. When the first transistor is a switching transistor, the width-to-length ratio of the first transistor cannot be set too large, otherwise it will affect the turn-off capability of the switching transistor. Based on the same principle as above, the width-to-length ratio of the driving transistor is generally five times or more than that of the switching transistor, and the driving performance of the driving transistor and the switching capability of the switching transistor are both optimal. By setting |W2 / L2-W3 / L3| to be at least five times greater than |W1 / L1-W4 / L4|, it can be ensured that the width-to-length ratio of the first transistor and the width-to-length ratio of other switching transistors can meet the needs of their respective performance.

[0039] In some embodiments, the drive array layer is disposed on the base substrate; the drive array layer includes a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer that are sequentially away from the base substrate. That is, in the display panel provided in the embodiment of the present invention, the drive array layer includes at least four metal layers, and the four metal layers are all functional layers for setting electrodes or wiring in the circuit elements.

[0040] Specifically, in one embodiment, Fig. 9 A schematic diagram of another optional implementation of a display panel provided in an embodiment of the present invention is shown in FIG. Fig. 9As shown, the driving array layer includes a first metal layer M1, a second metal layer M2, a third metal layer M3 and a fourth metal layer M4 which are sequentially away from the base substrate 110, and an insulating layer is also provided between adjacent metal layers. The first transistor T1 includes a first gate g1, a first source s1, a first drain d1 and a first active layer w1; the second transistor T2 includes a second gate g2, a third gate g3, a second source s2, a second drain d2 and a second active layer w2; the first gate g1 is located in the first metal layer M1, the second gate g2 is located in the second metal layer M2, the third gate g3 is located in the third metal layer M3, and at least one of the first source s1, the first drain d1, the second source s2 and the second drain d2 is located in the fourth metal layer M4; the first active layer w1 is located on the side of the first gate g1 close to the base substrate 110, and the second active layer w2 is located between the second gate g2 and the third gate g3. The first active layer w1 includes silicon, and the first transistor T1 is a top-gate structure transistor. On the one hand, the top-gate structure transistor can increase the distance between the gate and the metal shielding film on the back of the display panel, which can effectively prevent the coupling crosstalk between the gate potential change and the metal shielding film on the side of the display panel away from the light-emitting surface; on the other hand, the top-gate structure transistor is reused as a mask for differential ion implantation during the active layer ion implantation process. The second active layer w2 includes an oxide semiconductor. In the embodiment of the present invention, a gate (the second gate g2 is shown in the figure) is arranged on the side of the second active layer w2 close to the substrate 110 to block the influence of hydrogen in the insulating layer on the second active layer w2, thereby ensuring the performance stability of the second transistor T2.

[0041] Fig. 9 In the figure, the first source s1, the first drain d1, the second source s2, and the second drain d2 are all located in the fourth metal layer M4. The first source s1, the first drain d1, the second source s2, and the second drain d2 are all formed in the same metal layer, which can reduce the number of metal layers and is conducive to reducing the thickness of the display panel. In another embodiment, Fig.10 A schematic diagram of another optional implementation of a display panel provided in an embodiment of the present invention is shown in FIG. Fig.10 As shown, Fig. 9 The difference between the embodiments is that the first source s1, the second source s2, and the second drain d2 are all located in the fourth metal layer M4, and the first drain d1 is located in the third metal layer M3. In this embodiment, the first source and the first drain of the first transistor T1 are located in different metal layers, and the metal layer where the source and the drain of the first transistor are located can be set according to the connection relationship between the source and the drain of the first transistor and other components in the circuit to achieve reasonable wiring and reduce winding or vias. In another embodiment, the second source and the second drain of the second transistor can also be set in different metal layers according to the circuit design requirements, which is not illustrated in the figure.

[0042] Further, in Fig. 9 Based on the embodiment, the first electrode plate is located in the first metal layer, and the second electrode plate is located in the second metal layer. The first electrode plate located in the first metal layer and the second electrode plate located in the second metal layer constitute a first capacitor, and the capacitance value requirement of the first capacitor can be met by setting the manufacturing material of the insulating layer between the first metal layer and the second metal layer and the thickness of the insulating layer. Among them, one insulating layer or two or three insulating layers may be included between the first metal layer and the second metal layer. In one embodiment, the capacitance value requirement of the first capacitor can be met by adjusting the dielectric constant of the material making the insulating layer.

[0043] Specifically, in one embodiment, the driving array layer includes a pixel circuit, the first transistor is a driving transistor of the pixel circuit, that is, the active layer of the driving transistor includes silicon; the pixel circuit includes a first capacitor, the first capacitor is connected between the first power signal terminal and the gate of the driving transistor, and is used to store the signal transmitted to the gate of the driving transistor. The connection relationship between the first capacitor and other components in the pixel circuit can be referred to the above Figure 7 In the embodiment, the first capacitor C1 is connected between the first power signal terminal PV1 and the gate of the driving transistor Tm, that is, the first capacitor C1 is connected between the first power signal terminal PV1 and the gate of the first transistor in the present invention. Fig.11 A schematic diagram of another optional implementation scheme of a display panel provided in an embodiment of the present invention, combined with Fig.11 For understanding, see Fig.11 As shown, the first electrode plate c11 is located in the first metal layer M1, and the second electrode plate c12 is located in the second metal layer M2. The first gate g1 of the first transistor T1 is reused as the first electrode plate c11, and in the projection perpendicular to the surface direction of the display panel, the first capacitor c11 overlaps at least partially with the first transistor t1. In this embodiment, the first transistor is a driving transistor, and the first capacitor is a storage capacitor in the pixel circuit. One electrode plate of the first capacitor needs to be connected to the gate of the driving transistor, that is, one electrode plate of the first capacitor needs to be connected to the first gate of the first transistor. Reusing the first gate of the first transistor as the first electrode plate of the first capacitor can reduce the connection line between the first electrode plate and the first gate, simplify the wiring in the panel, and at the same time, can achieve at least partial overlap of the first capacitor and the first transistor, can reduce the size of a pixel circuit, and then can reduce the spacing between adjacent pixel circuits, and can set more pixel circuits within a certain area of ​​the driving array layer, which is conducive to improving the density of sub-pixels in the display panel to improve the display resolution. In addition, it can also improve the transmittance of the display panel, and can improve the optical performance when applied to the under-screen optical element solution or the transparent display panel solution.

[0044] In another embodiment, the driving array layer includes a pixel circuit, the second transistor is a driving transistor of the pixel circuit, that is, the active layer of the driving transistor includes an oxide semiconductor. The pixel circuit includes a first capacitor, and the first capacitor is used to store a signal transmitted to the gate of the driving transistor. Fig.12 A schematic diagram of another optional implementation of a pixel circuit in a display panel provided in an embodiment of the present invention. Fig.13 for Fig.12 A schematic diagram of a film layer structure of a display panel provided in an embodiment. Fig.12 As shown, the pixel circuit includes a driving transistor Tm and a switching transistor Tn, and the pixel circuit is electrically connected to the light emitting element OL. The first power signal terminal PV1, the data signal terminal Vdata, and the scanning control terminal S are also shown. One plate of the first capacitor C1 is connected to the gate of the driving transistor Tm, and the other plate is connected to the light emitting element OL. Fig.13 As shown, the first electrode c11 is located on the first metal layer M1, and the second electrode c12 is located on the second metal layer M2. The second gate g2 is reused as the second electrode c12, and in the projection perpendicular to the surface direction of the display panel, the first capacitor C1 and the second transistor T2 at least partially overlap. In this embodiment, the second transistor T2 is a driving transistor, that is, the active layer of the driving transistor includes an oxide semiconductor. Among them, the driving transistor including the oxide semiconductor is an n-type transistor. Fig.12 It is also indicated that the switching transistor Tn is a p-type transistor. The first capacitor C1 is a storage capacitor in the pixel circuit. One plate of the first capacitor C1 needs to be connected to the gate of the driving transistor (i.e., the second transistor T2). In this embodiment, the second transistor T2 includes a second gate g2 and a third gate g3. The second gate g2 of the second transistor is reused as the second plate c12 of the first capacitor C1, which can reduce the connection line between the second plate and the gate of the second transistor T2 and simplify the wiring in the panel. At the same time, at least part of the first capacitor and the second transistor can overlap, which can reduce the size of a pixel circuit, and then reduce the spacing between adjacent pixel circuits. More pixel circuits can be set within a certain area of ​​the driving array layer, which is conducive to increasing the density of sub-pixels in the display panel to improve the display resolution. In addition, the transmittance of the display panel can also be improved, and the optical performance can be improved when applied to the under-screen optical element solution or the transparent display panel solution.

[0045] In an embodiment of the present invention, the first electrode plate of the first capacitor is located in the first metal layer, and the second electrode plate of the first capacitor is located in the second metal layer. The third electrode plate and the fourth electrode plate are respectively located in any two layers of the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the first active layer or the second active layer. The third electrode plate is located in the film layer where the first metal layer, the second metal layer or the first active layer is located; the fourth electrode plate is located in the film layer where the third metal layer, the fourth metal layer or the second active layer is located. The present invention can flexibly set the functional layer where the capacitor electrode plates are located according to the positions of the first capacitor and the second capacitor in the circuit structure, thereby increasing the degree of freedom of setting the functional layer where the two electrodes of the first capacitor and the two electrodes of the second capacitor are located.

[0046] Specifically, in one embodiment, refer to Fig.11 As shown in the figure, the first plate c11 of the first capacitor C1 is located in the first metal layer M1, and the second plate c12 of the first capacitor C1 is located in the second metal layer M2. The third plate c23 of the second capacitor C2 is located in the first metal layer M1, and the fourth plate c24 of the second capacitor C2 is located in the first active layer. That is, the fourth plate c24 is located in the same layer as the active layer of the first transistor T1. In this embodiment, the first plate and the third plate are located in the same functional layer, and the second plate and the fourth plate are located in different functional layers.

[0047] In an embodiment in which the first plate of the first capacitor and the third plate of the second capacitor are located in the same functional layer, and the second plate of the first capacitor and the fourth plate of the second capacitor are located in different functional layers, the first plate and the third plate can also be located in the first metal layer, and the second plate can be located in the second metal layer; wherein the fourth plate is located in the third metal layer, or the fourth plate is located in the fourth metal layer, or the fourth plate is located in the second active layer.

[0048] In another embodiment, the first electrode is located in the first metal layer, the second electrode is located in the second metal layer, the third electrode is located in the first metal layer, and the fourth electrode is located in the second metal layer. That is, one electrode of the first capacitor and one electrode of the second capacitor are located in the same functional layer, and another electrode of the first capacitor and another electrode of the second capacitor are located in the same functional layer.

[0049] In some embodiments, the first electrode plate is located in the first metal layer, the second electrode plate is located in the second metal layer, and the third electrode plate and the fourth electrode plate are located in any two of the third metal layer, the fourth metal layer, the first active layer or the second active layer, respectively. Optionally, the third electrode plate is located in the third metal layer, and the fourth electrode plate is located in the fourth metal layer; Optionally, the third electrode plate is located in the fourth metal layer, and the fourth electrode plate is located in the first active layer; Optionally, the third electrode plate is located in the first active layer, and the fourth electrode plate is located in the second active layer.

[0050] Specifically, the first electrode plate is located in the first metal layer, the second electrode plate is located in the second metal layer, the third electrode plate is located in the film layer where the first metal layer, the second metal layer or the first active layer is located; the fourth electrode plate is located in the film layer where the third metal layer, the fourth metal layer or the second active layer is located.

[0051] Furthermore, the second capacitor further includes a fifth electrode plate, which is connected to the third electrode plate or the fourth electrode plate; the fifth electrode plate is located on a side of the fourth electrode plate away from the third electrode plate. Fig.14 A schematic diagram of a film structure of another optional implementation of a display panel provided in an embodiment of the present invention. Fig.14 As shown, the second capacitor C2 also includes a fifth plate c25, which is connected to the third plate c23; the fifth plate c25 is located on the side of the fourth plate c24 away from the third plate c23. By providing the fifth plate, which is connected to the third plate, the capacitance value of the second capacitor can be increased, thereby reducing the space occupied by the second capacitor in the drive array layer, and reducing the space occupied by the pixel circuit as a whole, which is conducive to increasing the density of sub-pixels in the display panel to improve the display resolution. Fig.14 When only the second capacitor includes three plates, the third plate c23 and the first gate g1 of the first transistor T1 are located on the same layer, the fourth plate c24 and the second active layer w2 of the second transistor T2 are located on the same layer, and the fifth plate c25 and the second source s2 and the second drain d2 of the second transistor T2 are located on the same layer. Fig.14 Only one arrangement of the three plates of the second capacitor is illustrated. In practical applications, the three plates of the second capacitor can be arranged in any three film layers of the first metal layer, the second metal layer, the third metal layer, the fourth metal layer, the first active layer, and the second active layer according to specific design requirements.

[0052] Further, in one embodiment, the driving array layer includes a pixel circuit, the first transistor is a driving transistor of the pixel circuit; the second transistor is a threshold compensation transistor of the pixel circuit; the control end of the driving transistor is electrically connected to the first node, the first end of the driving transistor is electrically connected to the second node, the second end of the driving transistor is electrically connected to the third node, the first end of the threshold compensation transistor is electrically connected to the third node, the second end of the threshold compensation transistor is electrically connected to the first node, and the control end of the threshold compensation transistor is electrically connected to the first scanning signal end. The pixel circuit includes a first capacitor and a second capacitor; the first capacitor is connected between the first power signal end and the gate of the driving transistor, and is used to store the signal transmitted to the gate of the driving transistor. In this embodiment, the active layer of the driving transistor includes silicon, and the active layer of the threshold compensation transistor includes an oxide semiconductor. Then the threshold compensation transistor has a small leakage current in the off state, which can reduce the influence of the leakage current on the gate potential of the driving transistor in the off state, thereby stabilizing the gate voltage of the driving transistor, improving the working stability of the driving transistor, and thus ensuring the stability of the driving current. When the pixel circuit is applied to the display panel, the uniformity of the light emitting brightness of the light emitting element can be guaranteed.

[0053] An embodiment in which the pixel circuit includes the first capacitor and the second capacitor is described in detail below.

[0054] Specifically, in one embodiment, Fig.15 A schematic diagram of another optional implementation of a pixel circuit in a display panel provided in an embodiment of the present invention. Fig.16 for Fig.15 The timing diagram of the pixel circuit in the display panel provided in the embodiment, Fig.17 for Fig.15 A pixel circuit wiring diagram in a display panel provided in an embodiment. Fig.18 for Fig.17 A schematic diagram of a film layer structure of a display panel provided in an embodiment.

[0055] like Fig.15 and Fig.17As shown, the first transistor T1 is a driving transistor Tm of the pixel circuit; the second transistor T2 is a threshold compensation transistor M1 of the pixel circuit; the gate of the driving transistor Tm is electrically connected to the first node N1, the second end of the driving transistor Tm is electrically connected to the second node N2, the second end of the driving transistor Tm is electrically connected to the third node N3, the first end of the threshold compensation transistor M1 is electrically connected to the third node N3, the second end of the threshold compensation transistor M1 is electrically connected to the first node N1, and the gate of the threshold compensation transistor M1 is electrically connected to the first scan signal terminal S1. The pixel circuit includes a data writing transistor M2, a second scan signal terminal S2 and a data signal terminal Vdata, the gate of the data writing transistor M2 is electrically connected to the second scan signal terminal S2, the first end of the data writing transistor M2 is electrically connected to the data signal terminal Vdata, and the second end of the data writing transistor M2 is electrically connected to the second node N2. The pixel circuit includes a second capacitor C2, a third plate c23 is connected to the gate of the driving transistor Tm, and a fourth plate c24 is connected to the second scan signal terminal S2. The second capacitor C2 is used to latch the potential of the gate of the driving transistor Tm.

[0056] The pixel circuit further includes a first light-emitting control transistor M3, a second light-emitting control transistor M4, a reset transistor M5, and a bias adjustment transistor M6. The gates of the first light-emitting control transistor M3 and the second light-emitting control transistor M4 are both electrically connected to the light-emitting control terminal E, the first end of the first light-emitting control transistor M3 is electrically connected to the third node N3, and the second end of the first light-emitting control transistor M3 is electrically connected to the anode of the light-emitting element OL; the first end of the second light-emitting control transistor M4 is electrically connected to the first power signal terminal PV1, and the second end of the second light-emitting control transistor M4 is electrically connected to the second node N2. The gate of the reset transistor M5 is electrically connected to the third scan signal terminal S3, the first end of the reset transistor M5 is electrically connected to the reset signal terminal Vref, and the second end of the reset transistor M5 is electrically connected to the anode of the light-emitting element OL; the cathode of the light-emitting element OL is electrically connected to the second power signal terminal PV2. The gate of the bias adjustment transistor M6 is electrically connected to the fourth scan signal terminal S4, the first end of the bias adjustment transistor M6 is electrically connected to the bias signal terminal DV, and the second end of the bias adjustment transistor M6 is electrically connected to the third node N3. The bias adjustment transistor M6 is used to adjust the bias state of the driving transistor Tm. When the pixel circuit is working in the light-emitting stage, the potential of the first node N1 is higher than the potential of the third node N3, causing the driving transistor Tm to produce a hysteresis effect, resulting in the Id-Vg curve (the relationship curve between the drain current and the gate voltage of the transistor) to shift, thereby causing the threshold voltage of the driving transistor to shift. In this embodiment, the bias adjustment transistor M6 can reverse bias the driving transistor, thereby alleviating the threshold voltage shift caused by the hysteresis effect of the driving transistor. The third scan signal terminal S3 and the fourth scan signal terminal S4 can provide signals by two adjacent shift registers in a driving circuit. Fig.17 Only the third scanning signal terminal S3 is marked.

[0057] refer to Fig.16 As shown in the timing diagram, due to the setting of the second capacitor C2, when the signal jump directions of the first scan signal terminal S1 and the second scan signal terminal S2 are opposite, the effect of the signal jump of the first scan signal terminal S1 on the first node N1 will be offset to a certain extent by the signal jump of the second scan signal terminal S2. In this embodiment, the second capacitor C2 can pull up the potential of the first node N1 when the signal of the second scan signal terminal S2 is a rising edge, so as to stabilize the potential of the first node N1.

[0058] like Fig.18As shown in FIG. 1 , in this embodiment, the gate of the driving transistor Tm (i.e., the first gate g1 of the first transistor T1) is reused as the first plate c11 of the first capacitor C1, the gate of the driving transistor Tm is located in the first metal layer M1, and the second plate c12 of the first capacitor C1 is located in the second metal layer M2. The threshold compensation transistor M1 is the second transistor T2, the second gate g2 of the second transistor T2 is located in the second metal layer, and the third gate g3 of the second transistor is located in the third metal layer M3. The first source s1 and the first drain d1 of the first transistor T1, and the second source s2 and the second drain d2 of the second transistor T2 are located in the fourth metal layer M4. The third plate c23 is connected to the gate of the driving transistor Tm, and the fourth plate c24 is connected to the second scanning signal terminal S2. The third plate c23 of the second capacitor C2 is located in the same layer as the active layer of the threshold compensation transistor M1 (i.e., the second active layer w2 of the second transistor T2), and the fourth plate c24 of the second capacitor C2 is located in the same layer as the gate of the driving transistor Tm. In this embodiment, the film layer positions where the plates of the two capacitors are located are set according to the connection relationship between the two capacitors and other transistor devices in the pixel circuit, which can simplify the wiring method of the pixel circuit in the display panel and save space.

[0059] Specifically, Fig.15 In the embodiment, the threshold compensation transistor M1 is a p-type transistor, and the driving transistor and other switch transistors in the pixel circuit are all n-type transistors.

[0060] Furthermore, Fig.19 A schematic diagram of another optional implementation of a display panel provided in an embodiment of the present invention. Fig.15 Based on the embodiment, the pixel circuit further includes a first auxiliary transistor, such as Fig.19 As shown, the gate and the first end of the first auxiliary transistor M7 are electrically connected to the second scan signal terminal S2, and the second end of the first auxiliary transistor M7 is electrically connected to a plate of the second capacitor C2. The third plate c23 of the second capacitor C2 is connected to the gate of the driving transistor Tm, and the fourth plate c24 of the second capacitor C2 is electrically connected to the second end of the first auxiliary transistor M7. The first auxiliary transistor M7 is a p-type transistor, and optionally, the active layer of the first auxiliary transistor M7 includes an oxide semiconductor. This embodiment adds a first auxiliary transistor between the second capacitor and the second scan signal terminal S2, and the first auxiliary transistor is controlled by the second scan signal terminal S2 to ensure that the first auxiliary transistor M7 is turned on only when the signal at the second scan signal terminal S2 is a rising edge to maintain the potential of the first node N1.

[0061] In another embodiment, Fig.18 A schematic diagram of another optional implementation of a pixel circuit of a display panel provided in an embodiment of the present invention, Fig.21 for Fig. 20A timing diagram of a pixel circuit provided in an embodiment.

[0062] like Fig. 20 As shown, the first transistor T1 is a driving transistor Tm of the pixel circuit; the second transistor T2 is a threshold compensation transistor M1 of the pixel circuit; the gate of the driving transistor Tm is electrically connected to the first node N1, the second end of the driving transistor Tm is electrically connected to the second node N2, the second end of the driving transistor Tm is electrically connected to the third node N3, the first end of the threshold compensation transistor M1 is electrically connected to the third node N3, the second end of the threshold compensation transistor M1 is electrically connected to the first node N1, and the gate of the threshold compensation transistor M1 is electrically connected to the first scan signal terminal S1. The pixel circuit includes a data writing transistor M2, a second scan signal terminal S2 and a data signal terminal Vdata, the gate of the data writing transistor M2 is electrically connected to the second scan signal terminal S2, the first end of the data writing transistor M2 is electrically connected to the data signal terminal Vdata, and the second end of the data writing transistor M2 is electrically connected to the second node N2.

[0063] The pixel circuit further includes a first light emission control transistor M3, a second light emission control transistor M4, a reset transistor M5, and a bias adjustment transistor M6. The gates of the first light emission control transistor M3 and the second light emission control transistor M4 are both electrically connected to the light emission control terminal E, the first end of the first light emission control transistor M3 is electrically connected to the third node N3, and the second end of the first light emission control transistor M3 is electrically connected to the anode of the light emitting element OL; the first end of the second light emission control transistor M4 is electrically connected to the first power signal terminal PV1, and the second end of the second light emission control transistor M4 is electrically connected to the second node N2. The gate of the reset transistor M5 is electrically connected to the third scan signal terminal S3, the first end of the reset transistor M5 is electrically connected to the reset signal terminal Vref, and the second end of the reset transistor M5 is electrically connected to the anode of the light emitting element OL; the cathode of the light emitting element OL is electrically connected to the second power signal terminal PV2. The gate of the bias adjustment transistor M6 is electrically connected to the third scan signal terminal S3, the first end of the bias adjustment transistor M6 is electrically connected to the bias signal terminal DV, and the second end of the bias adjustment transistor M6 is electrically connected to the third node N3. The bias adjustment transistor M6 is used to adjust the bias state of the driving transistor Tm. When the pixel circuit operates in the light-emitting stage, the potential of the first node N1 is higher than the potential of the third node N3, and the driving transistor Tm produces a hysteresis effect, resulting in a threshold voltage shift. In this embodiment, the bias adjustment transistor M6 can reverse bias the driving transistor, thereby compensating for the threshold voltage shift caused by the hysteresis effect of the driving transistor.

[0064] Specifically, Fig. 20In the embodiment, the threshold compensation transistor M1 is a p-type transistor, and the driving transistor and other switch transistors in the pixel circuit are n-type transistors. The pixel circuit includes a second capacitor C2, a third plate connected to the gate of the driving transistor Tm, and a fourth plate connected to the third scanning signal terminal S3. The second capacitor C2 is used to maintain the potential of the gate of the driving transistor. Fig.21 As shown in FIG. 1 , when the signal at the third scan signal terminal S3 is at a rising edge, the second capacitor C2 can pull up the potential of the first node N1 to stabilize the potential of the first node N1.

[0065] Fig. 20 In the embodiment, the gate of the bias adjustment transistor M6 and the gate of the reset transistor M5 are both connected to the third scanning signal terminal S3, that is, the light emitting element OL is reset while the bias adjustment of the driving transistor Tm is performed. Optionally, in another embodiment, the gate of the bias adjustment transistor M6 and the gate of the reset transistor M5 are connected to different signal terminals, so that the bias adjustment of the driving transistor Tm and the resetting of the light emitting element OL are respectively achieved at different times.

[0066] Specifically, in another embodiment, the pixel circuit in the display panel can refer to the above Figure 7 The examples in the embodiments are as follows: Fig. 22 A pixel circuit wiring diagram of another optional implementation manner of a display panel provided in an embodiment of the present invention. Fig.23 for Figure 7 A timing diagram of a pixel circuit provided in an embodiment. Fig.24 for Fig. 22 A schematic diagram of a film layer structure of a display panel provided in an embodiment.

[0067] Also refer to Figure 7 and Fig.23 As shown, the first transistor T1 is a driving transistor Tm of the pixel circuit; the second transistor T2 is a threshold compensation transistor M1 of the pixel circuit; the gate of the driving transistor Tm is electrically connected to the first node N1, the second end of the driving transistor Tm is electrically connected to the second node N2, the second end of the driving transistor Tm is electrically connected to the third node N3, the first end of the threshold compensation transistor M1 is electrically connected to the third node N3, the second end of the threshold compensation transistor M1 is electrically connected to the first node N1, and the gate of the threshold compensation transistor M1 is electrically connected to the first scan signal terminal S1. The pixel circuit includes a data writing transistor M2, a second scan signal terminal S2 and a data signal terminal Vdata, the gate of the data writing transistor M2 is electrically connected to the second scan signal terminal S2, the first end of the data writing transistor M2 is connected to the data signal terminal Vdata, and the second end of the data writing transistor M2 is electrically connected to the second node N2.

[0068] The pixel circuit further includes a first light-emitting control transistor M3, a second light-emitting control transistor M4, a reset transistor M5, and a bias adjustment transistor M6. The gates of the first light-emitting control transistor M3 and the second light-emitting control transistor M4 are both electrically connected to the light-emitting control terminal E, the first end of the first light-emitting control transistor M3 is electrically connected to the third node N3, and the second end of the first light-emitting control transistor M3 is electrically connected to the anode of the light-emitting element OL; the first end of the second light-emitting control transistor M4 is electrically connected to the first power signal terminal PV1, and the second end of the second light-emitting control transistor M4 is electrically connected to the second node N2. The gate of the reset transistor M5 is electrically connected to the third scan signal terminal S3, the first end of the reset transistor M5 is electrically connected to the reset signal terminal Vref, and the second end of the reset transistor M5 is electrically connected to the anode of the light-emitting element OL; the cathode of the light-emitting element OL is electrically connected to the second power signal terminal PV2. The gate of the bias adjustment transistor M6 is electrically connected to the third scan signal terminal S3, the first end of the bias adjustment transistor M6 is electrically connected to the bias signal terminal Dv, and the second end of the bias adjustment transistor M6 is electrically connected to the third node N3. The bias adjustment transistor M6 is used to adjust the bias state of the driving transistor Tm. Figure 7 In the embodiment, the gate of the bias adjustment transistor M6 and the gate of the reset transistor M5 are both connected to the third scanning signal terminal S3, that is, the light emitting element OL is reset while the bias adjustment of the driving transistor Tm is performed. Optionally, in another embodiment, the gate of the bias adjustment transistor M6 and the gate of the reset transistor M5 are connected to different signal terminals, so that the bias adjustment of the driving transistor Tm and the resetting of the light emitting element OL are respectively performed at different times.

[0069] Specifically, Figure 7 In the embodiment, the threshold compensation transistor M1 is a p-type transistor, and the driving transistor and other switch transistors in the pixel circuit are n-type transistors. The pixel circuit includes a second capacitor C2, a fourth electrode c24 connected to a third node N3, a third electrode c23 connected to a light emitting control terminal E, and a second capacitor C2 for reverse biasing the driving transistor. Fig.24 As shown in the figure, when the signal at the light emitting control terminal E is at a rising edge, the second capacitor C2 can pull up the potential of the third node N3. When the pixel circuit is working in the light emitting stage, the potential of the first node N1 is higher than the potential of the third node N3, and the driving transistor Tm generates a hysteresis effect, resulting in a shift in the threshold voltage of the driving transistor. In this embodiment, the second capacitor C2 can pull up the potential of the third node N3 when the signal at the light emitting control terminal E is at a rising edge, thereby reverse biasing the driving transistor, thereby further compensating for the shift in the threshold voltage caused by the hysteresis effect of the driving transistor.

[0070] Specifically, Fig. 22In the embodiment, the threshold compensation transistor M1 is a p-type transistor, and the driving transistor and other switch transistors in the pixel circuit are n-type transistors. Fig.24 As shown, in this embodiment, the gate of the driving transistor Tm (that is, the first gate g1 of the first transistor T1) is reused as the first plate c11 of the first capacitor C1, and the second plate of the first capacitor C1 is located on the second metal layer M2. The fourth plate c24 is located on the same layer as the active layer of the driving transistor Tm (that is, the first active layer w1 of the first transistor T1), and the third plate c23 is located on the same layer as the first gate g1 of the first transistor T1. In this embodiment, according to the connection relationship between the two capacitors and other transistor devices in the pixel circuit, the film layer position where the plates of the two capacitors are located is set, which can simplify the wiring method of the pixel circuit in the display panel and save space.

[0071] Further, in Figure 7 Based on the embodiment, the pixel circuit further includes a second auxiliary transistor, wherein the gate and the first end of the second auxiliary transistor are electrically connected to the light emitting control end, and the second end of the second auxiliary transistor is electrically connected to a plate of the second capacitor. The drawings are not shown here. The second auxiliary transistor is a p-type transistor, and optionally, the active layer of the second auxiliary transistor includes an oxide semiconductor. In this embodiment, the second auxiliary transistor is controlled by the light emitting control end to ensure that the second auxiliary transistor is turned on only when the signal at the light emitting control end is a rising edge, and the potential of the third node N3 is pulled up to adjust the bias state of the driving transistor Tm.

[0072] In one embodiment, the first capacitor C1 and the second capacitor C2 in the driving array layer 101 include a first insulating layer 31 between the first electrode plate c11 and the second electrode plate c12, and a second insulating layer 32 between the third electrode plate c23 and the fourth electrode plate c24. Optionally, other insulating layers may be included between the first electrode plate c11 and the second electrode plate c12, and other insulating layers may be included between the third electrode plate c23 and the fourth electrode plate c24.

[0073] For details, please refer to the above Fig.18As shown in the figure, a first insulating layer 31 is included between the first electrode plate c11 and the second electrode plate c12, and a second insulating layer 32 is included between the third electrode plate c23 and the fourth electrode plate c24. The hydrogen content in the first insulating layer 31 is greater than the hydrogen content in the second insulating layer 32. In the embodiment where the first capacitor C1 is a storage capacitor of the pixel circuit and the second capacitor C2 is an auxiliary capacitor, the first electrode plate c11 of the first capacitor C1 is located in the first metal layer M1, and the second electrode plate c12 is located in the second metal layer M2. The first capacitor C1 is closer to the first transistor (that is, the driving transistor), and the first active layer of the first transistor T1 includes silicon. By setting the first insulating layer 31 to have a large hydrogen content, when the first active layer w1 is subjected to the hydrogenation process, the first insulating layer 31 can provide hydrogen ions for the first active layer w1, so that the first active layer w1 of the first transistor T1 can be hydrogen-rich to ensure the driving performance of the first transistor. In addition, the third electrode c23 and the second active layer w2 of the second transistor T2 are located in the same layer, and the fourth electrode c24 is located in the first metal layer M1, so the second capacitor C2 is closer to the second transistor T2, and the second active layer w2 of the second transistor T2 includes an oxide semiconductor. In order to ensure the performance of the second transistor T2, the second active layer w2 needs to be oxygen-rich. If the hydrogen content in the insulating layer close to the second active layer w2 is high, it is easy to cause the oxide semiconductor to be conductive. In this embodiment, the hydrogen content of the second insulating layer 32 between the second capacitor C2 is set to be low, which can avoid the second insulating layer 32 from causing adverse effects on the second active layer w2 of the second transistor T2, and ensure the performance stability of the second transistor T2.

[0074] Furthermore, the oxygen content in the first insulating layer 31 is less than the oxygen content in the second insulating layer 32. In the embodiment where the first capacitor C1 is close to the first transistor T1 and the second capacitor C2 is close to the second transistor T2, the first insulating layer 31 is set to have a smaller oxygen content, which can reduce the occurrence of oxygen in the first insulating layer 31 and hydrogen in the first active layer w1, so as to ensure that the first active layer w1 is hydrogen-rich and the performance stability of the first transistor T1 is ensured. At the same time, the second insulating layer 32 is set to have a larger oxygen content, which can prevent the second active layer w2 from being conductive and affecting the device performance.

[0075] In another embodiment, continue to refer to the above Fig.18 As shown, a first insulating layer 31 and a second insulating layer 32 are stacked between the third electrode plate c23 and the fourth electrode plate c24. Fig.18 In the figure, the first insulating layer 31 is located on a side close to the fourth plate c24, and the second insulating layer 32 is located on a side close to the third plate c23. In another embodiment, the two plates of the second capacitor are connected to Fig.18The positions of the first insulating layer and the second insulating layer can be interchanged if the embodiments are different. The first insulating layer and the second insulating layer can be matched to meet the requirements of the capacitance value of the second capacitor in the circuit structure and the hydrogen or oxygen content on the side close to the transistor active layer, so as to meet the requirements of the capacitance performance and the transistor stability at the same time.

[0076] Specifically, in one embodiment, the material of the first insulating layer 31 includes silicon nitride, and the material of the second insulating layer 32 includes silicon oxide. Then, the oxygen content of the first insulating layer can be less than the oxygen content of the second insulating layer, and the hydrogen content of the first insulating layer can be greater than the hydrogen content of the second insulating layer.

[0077] Furthermore, in the insulating layer between the third plate and the fourth plate; the oxygen content near the third plate is greater than the oxygen content near the fourth plate; the hydrogen content near the third plate is less than the hydrogen content near the fourth plate. In practice, the insulating layer between the plates of the second capacitor is set according to the connection relationship between the second capacitor and the circuit element in the circuit structure, and the requirement for the capacitance value of the second capacitor. One or more insulating layers may be set between the third plate and the fourth plate. If the oxygen content near the third plate is greater than the oxygen content near the fourth plate, the third plate may be set near the second active layer of the second transistor, and the oxygen in the insulating layer near the third plate can combine with free hydrogen to reduce the amount of free hydrogen combined with the second active layer, thereby ensuring that the second active layer is oxygen-rich and the stability of the second transistor is ensured. If the hydrogen content of the insulating layer near the fourth electrode plate is greater than the hydrogen content of the insulating layer near the third electrode plate, the fourth electrode plate can be set near the first active layer of the first transistor. The hydrogen in the insulating layer near the fourth electrode plate can provide hydrogen ions for the first active layer, so as to make the first active layer of the first transistor hydrogen-rich, thereby ensuring the driving performance of the first transistor.

[0078] In one embodiment, a first insulating layer is included between the first electrode plate and the second electrode plate, and a second insulating layer is included between the third electrode plate and the fourth electrode plate; the thickness of the first insulating layer is less than the thickness of the second insulating layer. According to the capacitance formula, the smaller the thickness of the insulating layer, the greater the capacitance value formed between the two electrode plates. The thickness of the first insulating layer is less than the thickness of the second insulating layer, which is conducive to achieving a capacitance value of the first capacitor greater than the capacitance value of the second capacitor. When the capacitance value of the first capacitor is ensured to be large enough, the area occupied by the first capacitor can be reduced to a certain extent, which is conducive to saving the space occupied by the pixel circuit. When the pixel circuit includes the first capacitor, the space occupied by the pixel circuit can be reduced, which is conducive to increasing the pixel density and improving the resolution of the display panel. When the drive circuit includes the first capacitor, the space occupied by the drive circuit can be reduced, which is conducive to reducing the area of ​​the non-display area and improving the screen ratio.

[0079] Specifically, in one embodiment, a first insulating layer is included between the first plate and the second plate, and a second insulating layer is included between the third plate and the fourth plate; the dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer. The greater the dielectric constant between the two plates of the capacitor, the greater the capacitance value formed between the two plates. The dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer, which is conducive to achieving a capacitance value of the first capacitor greater than the capacitance value of the second capacitor. The capacitance value of the capacitor is differentiated by adjusting the insulating layer material between the two plates of the capacitor.

[0080] Specifically, in one embodiment, the area of ​​the first electrode plate and the second electrode plate is greater than the area of ​​the third electrode plate and the fourth electrode plate. This embodiment adjusts the area of ​​the electrode plate of the first capacitor to achieve that the capacitance value of the first capacitor is greater than the capacitance value of the second capacitor. In an embodiment in which the drive circuit includes the first capacitor, since the drive circuit is arranged in the non-display area, the larger area of ​​the capacitor plate in the drive circuit will not affect the display area.

[0081] In another embodiment, the first plate and the third plate are located in the same functional layer, and the second plate and the fourth plate are located in the same functional layer; a first insulating layer is included between the first plate and the second plate, and a second insulating layer is included between the third plate and the fourth plate; the hydrogen content in the first insulating layer is different from the hydrogen content in the second insulating layer. In an embodiment in which one of the pixel circuit and the drive circuit includes a first capacitor and the other includes a second capacitor, the hydrogen content of the insulating layer between the capacitor plates is different due to the different process steps of the pixel circuit and the drive circuit. In one embodiment, the hydrogen content of the first insulating layer is greater than the hydrogen content of the second insulating layer. In another embodiment, the hydrogen content of the first insulating layer is less than the hydrogen content of the second insulating layer. When applied to different circuit structures, the hydrogen content of the first insulating layer and the hydrogen content of the second insulating layer can be flexibly set according to specific process requirements.

[0082] An embodiment of the present invention further provides a display device, Fig.25 A schematic diagram of a display device provided by an embodiment of the present invention, such as Fig.25 The display device shown includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel has been described in the above embodiment and will not be repeated here. The display device in the embodiment of the present invention can be any device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-book, a television, a smart wearable product, etc.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, It is characterized in that include: A driving array layer, the driving array layer comprising a pixel circuit and a driving circuit, the driving circuit providing a control signal for the pixel circuit; The pixel circuit includes the first transistor and a first capacitor, and the active layer of the first transistor includes silicon; The driving circuit includes the second transistor and the second capacitor, and the active layer of the second transistor includes an oxide semiconductor; wherein, In a projection direction perpendicular to the surface of the display panel, the first capacitor at least partially overlaps with the first transistor, and the second capacitor does not overlap with the second transistor; or, In a projection direction perpendicular to a surface of the display panel, an overlapping area between the first capacitor and the first transistor is larger than an overlapping area between the second capacitor and the second transistor.

2. The display panel according to claim 1, It is characterized in that The first transistor is a driving transistor of the pixel circuit; The first capacitor is connected between the first power signal terminal and the gate of the driving transistor.

3. The display panel according to claim 1, It is characterized in that The driving circuit includes an output terminal and an output module; The second capacitor is connected between the output terminal and the control terminal of the output module.

4. The display panel according to claim 1, It is characterized in that The first capacitor includes a first plate and a second plate, and the second capacitor includes a third plate and a fourth plate; The driving array layer includes a functional layer and an insulating layer, the first electrode plate and the second electrode plate are respectively located at any two functional layers of the functional layer, and the third electrode plate and the fourth electrode plate are respectively located at any two functional layers of the functional layer.

5. The display panel according to claim 4, It is characterized in that The first electrode plate and the third electrode plate are located in the same functional layer, and the second electrode plate and the fourth electrode plate are located in different functional layers; or, The first electrode plate and the third electrode plate are located in the same functional layer, and the second electrode plate and the fourth electrode plate are located in the same functional layer; or, The first electrode plate, the second electrode plate, the third electrode plate and the fourth electrode plate are respectively located in different functional layers.

6. The display panel according to claim 4, It is characterized in that A first insulating layer is included between the first electrode plate and the second electrode plate, and a second insulating layer is included between the third electrode plate and the fourth electrode plate.

7. The display panel according to claim 6, It is characterized in that The thickness of the first insulating layer is smaller than the thickness of the second insulating layer; or, The dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer.

8. The display panel according to claim 6, It is characterized in that The first insulating layer and the second insulating layer are stacked between the third electrode plate and the fourth electrode plate.

9. The display panel according to claim 1, It is characterized in that The areas of the first electrode plate and the second electrode plate are greater than the areas of the third electrode plate and the fourth electrode plate; and / or, The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

10. The display panel according to claim 1, It is characterized in that The driving array layer is located on the base substrate, and the driving array layer includes a first metal layer, a second metal layer, a third metal layer and a fourth metal layer which are sequentially away from the base substrate; The first transistor includes a first gate, a first source, a first drain and a first active layer; The second transistor includes a second gate, a third gate, a second source, a second drain and a second active layer; wherein, The first gate is located in the first metal layer, the second gate is located in the second metal layer, the third gate is located in the third metal layer, and at least one of the first source, the first drain, the second source, and the second drain is located in the fourth metal layer.

11. The display panel according to claim 10, It is characterized in that The first electrode plate is located on the first metal layer, and the second electrode plate is located on the second metal layer.

12. The display panel according to claim 4, It is characterized in that A first insulating layer is included between the first electrode plate and the second electrode plate, and a second insulating layer is included between the third electrode plate and the fourth electrode plate; The hydrogen content in the first insulating layer is greater than the hydrogen content in the second insulating layer.

13. The display panel according to claim 12, It is characterized in that The oxygen content in the first insulating layer is less than the oxygen content in the second insulating layer.

14. A display device, It is characterized in that Comprising a display panel as described in any one of claims 1-13.

15. A display panel, It is characterized in that include: A driving array layer, the driving array layer comprising a pixel circuit and a driving circuit, the driving circuit providing a control signal for the pixel circuit; The driving array layer includes a first transistor, a second transistor, a first capacitor and a second capacitor, the active layer of the first transistor includes silicon, and the active layer of the second transistor includes an oxide semiconductor; The driving circuit includes the second transistor; wherein, In a projection direction perpendicular to the surface of the display panel, the first capacitor at least partially overlaps with the first transistor, and the second capacitor does not overlap with the second transistor; or, In a projection direction perpendicular to a surface of the display panel, an overlapping area between the first capacitor and the first transistor is larger than an overlapping area between the second capacitor and the second transistor.

16. The display panel according to claim 15, It is characterized in that The pixel circuit includes the first transistor; or, The driving circuit includes the first transistor.

17. The display panel according to claim 15, It is characterized in that The pixel circuit includes the first capacitor and the second capacitor; or, The driving circuit includes the first capacitor and the second capacitor.

18. The display panel according to claim 15, It is characterized in that The driving circuit includes the first capacitor, and the pixel circuit includes the second capacitor.

19. The display panel according to claim 15, It is characterized in that The driving circuit includes the first transistor, the second transistor, the first capacitor and the second capacitor.

20. The display panel according to claim 15, It is characterized in that The pixel circuit includes the first transistor, the first capacitor and the second capacitor.

21. The display panel according to claim 15, It is characterized in that The first capacitor includes a first plate and a second plate, and the second capacitor includes a third plate and a fourth plate; The driving array layer includes a functional layer and an insulating layer, the first electrode plate and the second electrode plate are respectively located at any two functional layers of the functional layer, and the third electrode plate and the fourth electrode plate are respectively located at any two functional layers of the functional layer.

22. The display panel according to claim 15, It is characterized in that The areas of the first electrode plate and the second electrode plate are greater than the areas of the third electrode plate and the fourth electrode plate; and / or, The capacitance value of the first capacitor is greater than the capacitance value of the second capacitor.

23. The display panel according to claim 22, It is characterized in that A first insulating layer is included between the first electrode plate and the second electrode plate, and a second insulating layer is included between the third electrode plate and the fourth electrode plate.

24. The display panel according to claim 23, It is characterized in that The thickness of the first insulating layer is smaller than the thickness of the second insulating layer; or, The dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer.

25. A display device, It is characterized in that Comprising a display panel as described in any one of claims 15-24.

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