Display substrate, manufacturing method thereof and display device

Abstract

The invention provides a display substrate, a manufacturing method thereof and a display device. The display substrate comprises a row addressing area, a first pixel driving area and a second pixel driving area. The row addressing area is provided with a row addressing circuit. The first pixel driving area is located on one side of the row addressing area. The first pixel driving area is located on one side of the row addressing area, the second pixel driving area is located on the other side of the row addressing area, and the row addressing area is located between the first pixel driving area and the second pixel driving area. The line addressing circuit comprises a scanning driving circuit, a first gating circuit and a second gating circuit. The first gating circuit is connected with the scanning driving circuit and the pixel circuit in the first pixel driving area, and the second gating circuit is connected with the scanning driving circuit and the pixel circuit in the second pixel driving area. By means of the arrangement, the refresh rate of the first pixel driving area and the refresh rate of the second pixel driving area can be relatively independently adjusted, namely partition frequency conversion is achieved, and therefore display power consumption can be reduced.

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] The market is currently demanding higher and higher battery life for electronic devices such as mobile phones and tablets. This requires reducing the power consumption of the display substrate. Typically, this can be achieved by using partitioned frequency conversion (different areas of the screen support different refresh rates). A screen with partitioned frequency conversion is divided into multiple areas, each of which can be set to a different refresh rate. Partitioned frequency conversion can update the refresh area while the non-refresh area retains the previous frame data, further saving display power consumption.

[0003] Summary of the Invention

[0004] The present application provides a display substrate, a manufacturing method thereof, and a display device.

[0005] According to a first aspect of an embodiment of the present application, a display substrate is provided. The display substrate includes:

[0006] A row addressing area is provided with a row addressing circuit;

[0007] a first pixel driving area, located on one side of the row addressing area, wherein the first pixel driving area is provided with a pixel circuit;

[0008] a second pixel driving area, located on the other side of the row addressing area, wherein the second pixel driving area is provided with a pixel circuit, and the row addressing area is located between the first pixel driving area and the second pixel driving area;

[0009] Wherein, the row addressing circuit includes:

[0010] Scan driving circuit;

[0011] a first gating circuit, located between the scan driving circuit and the first pixel driving area, and connecting the scan driving circuit and the pixel circuits in the first pixel driving area;

[0012] The second gating circuit is located between the scan driving circuit and the second pixel driving area, and connects the scan driving circuit and the pixel circuits in the second pixel driving area.

[0013] In some embodiments, the display substrate further comprises:

[0014] substrate;

[0015] A driving circuit layer is provided on one side of the substrate;

[0016] an organic light-emitting layer, disposed on a side of the driving circuit layer away from the substrate;

[0017] Wherein, the driving circuit layer includes the row addressing circuit of the row addressing area.

[0018] In some embodiments, the driving circuit layer is provided with pixel circuits located in the first pixel driving area and the second pixel driving area, and the pixel circuits include capacitors and multiple thin film transistors, and are configured to control the light emission of the pixels;

[0019] The row addressing circuit in the row addressing area is arranged in the same layer as the pixel circuit.

[0020] In some embodiments, the base includes a rigid substrate and / or a flexible substrate.

[0021] In some embodiments, a bottom shielding layer is disposed between the substrate and the driving circuit layer.

[0022] In some embodiments, the bottom shielding layer includes a connecting wire and a plurality of shielding patterns, and the connecting wire electrically connects the plurality of shielding patterns into a whole.

[0023] In some embodiments, the shielding pattern includes transverse shielding lines extending along a first direction, longitudinal shielding lines extending along a second direction, and a square shielding block disposed at the intersection of the transverse shielding lines and the longitudinal shielding lines.

[0024] In some embodiments, a buffer layer is disposed between the driving circuit layer and the substrate.

[0025] In some embodiments, the driving circuit layer includes:

[0026] a first active layer;

[0027] a first gate layer;

[0028] a second gate layer, disposed on a side of the first active layer and the first gate layer away from the substrate;

[0029] a second active layer;

[0030] The third gate layer is arranged on a side of the second gate layer away from the substrate.

[0031] In some embodiments, the material of the first active layer includes amorphous silicon or polycrystalline silicon.

[0032] In some embodiments, the first active layer includes a plurality of first active regions, each of which corresponds to a thin film transistor or a plurality of electrically connected thin film transistors;

[0033] The row addressing area, the first pixel driving area and the second pixel driving area are all provided with the first active area.

[0034] In some embodiments, the first gate layer located in the first pixel driving area and the second pixel driving area includes a first type of gate line extending along a first direction, and a plurality of gate pattern blocks;

[0035] The gate pattern blocks are block-shaped, and a plurality of the gate pattern blocks are arranged in a row along a first direction.

[0036] In some embodiments, the first gate layer located in the row addressing area includes a first type of gate line extending along the first direction, a second type of gate line extending along both the first direction and the second direction, a plurality of block-shaped gate pattern blocks, and a plurality of U-shaped third type of gate lines.

[0037] In some embodiments, the third type of grid lines include a horizontal connecting line extending along a first direction, and two vertical grid portions respectively disposed at two ends of the horizontal connecting line, the two vertical grid portions being disposed side by side and spaced apart from each other.

[0038] In some embodiments, the first gate layer includes a first gate connection line for connecting gate lines on both sides of the row addressing region.

[0039] In some embodiments, the first gate connection line includes a gate connection end connected to the gate line, a gate away end located in the row addressing area and away from the gate line, and a winding segment located between the gate connection end and the gate away end and connecting the gate connection end and the gate away end, wherein the gate connection end and / or the gate away end extend along a first direction, and the winding segment extends along a second direction.

[0040] In some embodiments, the first gate layer includes a second gate connection line for connecting the gate lines on both sides of the row addressing area, one end of the second gate connection line is connected to the gate line, and the other end of the second gate connection line does not extend to the scan driving circuit area of ​​the row addressing area.

[0041] In some embodiments, the second gate layer located in the first pixel driving area and the second pixel driving area includes a fourth type of gate line extending along the first direction, and a plurality of gate pattern blocks;

[0042] At least a portion of the fourth-type gate lines and a corresponding portion of the first gate layer form a capacitor, and at least a portion of the gate pattern blocks and a corresponding portion of the first gate layer form a capacitor.

[0043] In some embodiments, the second gate layer located in the row addressing area includes a fourth type of gate line extending along the first direction, a fifth type of gate line extending along both the first direction and the second direction, a plurality of block-shaped gate pattern blocks, and a plurality of U-shaped sixth type of gate lines.

[0044] In some embodiments, the sixth type of grid lines include a horizontal connecting line extending along the first direction, and two vertical grid portions respectively provided at both ends of the horizontal connecting line, the two vertical grid portions being provided side by side and spaced apart from each other;

[0045] The gate pattern block and a corresponding portion of the first gate layer form a capacitor.

[0046] In some embodiments, the second gate layer includes a third gate connection line for connecting gate lines on both sides of the row addressing region;

[0047] The third gate connection line includes a middle connection segment, two gate-proximal ends, and a vertical segment, wherein the middle connection segment is located in the middle area of ​​the row addressing area and extends to both sides thereof along the first direction, the two gate-proximal ends are respectively located on opposite sides of the gate connection line along the first direction, and the vertical segment extends along the second direction and is connected between the middle connection segment and the gate-proximal ends.

[0048] In some embodiments, the second active layer is made of metal oxide.

[0049] In some embodiments, the third gate layer located in the first pixel driving area and the second pixel driving area includes a first type of gate line extending along a first direction.

[0050] In some embodiments, the third gate layer located in the row addressing area includes a first type of gate lines extending along the first direction, a second type of gate lines extending along both the first direction and the second direction, and a plurality of third type of gate lines in a U-shape;

[0051] The third type of grid lines include a horizontal connecting line extending along a first direction, and two vertical grid portions respectively arranged at two ends of the horizontal connecting line, wherein the two vertical grid portions are arranged side by side and spaced apart from each other.

[0052] In some embodiments, the third gate layer includes a third gate connection line for connecting gate lines on both sides of the row addressing region;

[0053] The third gate connection line includes a middle connection segment, two gate-proximal ends, and a vertical segment, wherein the middle connection segment is located in the middle area of ​​the row addressing area and extends to both sides thereof along the first direction, the two gate-proximal ends are respectively located on opposite sides of the gate connection line along the first direction, and the vertical segment extends along the second direction and is connected between the middle connection segment and the gate-proximal ends.

[0054] In some embodiments, the display substrate further comprises:

[0055] A second row addressing region is located at one edge of the display substrate, wherein the second row addressing region is provided with a second row addressing circuit;

[0056] a third pixel driving area, located between the second row addressing area and the first pixel driving area;

[0057] Wherein, the second row addressing circuit includes:

[0058] a second scanning driving circuit;

[0059] The third gating circuit is located between the second scanning driving circuit and the third pixel driving area, and connects the second scanning driving circuit and the pixel circuits in the third pixel driving area.

[0060] In some embodiments, the display substrate further comprises:

[0061] a third row addressing region, located at another edge of the display substrate, wherein the third row addressing region is provided with a third row addressing circuit;

[0062] a fourth pixel driving area, located between the second pixel driving area and the third row addressing area;

[0063] Wherein, the third row addressing circuit includes:

[0064] a third scanning driving circuit;

[0065] The fourth gating circuit is located between the third scanning driving circuit and the fourth pixel driving area, and connects the third scanning driving circuit and the pixel circuits in the fourth pixel driving area.

[0066] In some embodiments, the display substrate further comprises:

[0067] a fourth row addressing area, provided with a fourth row addressing circuit;

[0068] a fifth pixel driving area, located between the fourth row addressing area and the third pixel driving area;

[0069] a sixth pixel driving area, located between the fourth row addressing area and the first pixel driving area;

[0070] Wherein, the fourth row addressing circuit includes:

[0071] a fourth scanning driving circuit;

[0072] a fifth gating circuit, located between the fourth scan driving circuit and the fifth pixel driving area, and connecting the fourth scan driving circuit and the pixel circuits in the fifth pixel driving area;

[0073] The sixth gating circuit is located between the fourth scan driving circuit and the sixth pixel driving area, and connects the fourth scan driving circuit and the pixel circuits in the sixth pixel driving area.

[0074] In some embodiments, the number of pixels in each row in the first pixel driving area is equal to the number of pixels in each row in the second pixel driving area;

[0075] And / or, the number of pixels in each row in the fifth pixel driving area is equal to the number of pixels in each row in the sixth pixel driving area.

[0076] In some embodiments, the refresh rate of the first pixel driving region and the refresh rate of the second pixel driving region are independently controlled by a row addressing circuit of the row addressing region.

[0077] According to a second aspect of an embodiment of the present application, a method for manufacturing the aforementioned display substrate is provided, the method comprising:

[0078] providing a substrate;

[0079] A row addressing region, a first pixel driving region, and a second pixel driving region are formed on the substrate, wherein the row addressing region is provided with a row addressing circuit; the first pixel driving region is located on one side of the row addressing region and is provided with a pixel circuit; the second pixel driving region is located on the other side of the row addressing region and is provided with a pixel circuit, and the row addressing region is located between the first pixel driving region and the second pixel driving region;

[0080] Wherein, the row addressing circuit includes:

[0081] Scan driving circuit;

[0082] a first gating circuit, located between the scan driving circuit and the first pixel driving area, and connecting the scan driving circuit and the pixel circuits in the first pixel driving area;

[0083] The second gating circuit is located between the scan driving circuit and the second pixel driving area, and connects the scan driving circuit and the pixel circuits in the second pixel driving area.

[0084] In some embodiments, further comprising:

[0085] forming a driving circuit layer on one side of the substrate, the driving circuit layer including pixel circuits located in the first pixel driving area and the second pixel driving area, and a row addressing circuit located in the row addressing area, wherein both the pixel circuit and the row addressing circuit include capacitors and a plurality of thin film transistors;

[0086] An organic light emitting layer is formed on a side of the driving circuit layer away from the substrate.

[0087] According to a third aspect of an embodiment of the present application, a display device is provided, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] FIG1 is a schematic top view of a display substrate provided by an exemplary embodiment of the present application;

[0089] FIG2 is a schematic top view of a display substrate provided by another exemplary embodiment of the present application;

[0090] FIG3 is a schematic diagram showing the principle of a row addressing circuit located in a row addressing area provided by an exemplary embodiment of the present application;

[0091] FIG4 is a schematic cross-sectional view of a display substrate provided by an exemplary embodiment of the present application;

[0092] FIG5 is a schematic diagram of the layout structure of a bottom shielding layer provided by an exemplary embodiment of the present application;

[0093] FIG6 is a schematic diagram of a layout structure of an active layer provided by an exemplary embodiment of the present application;

[0094] FIG7 is a schematic diagram of a layout structure in which an active layer is superimposed on a bottom shielding layer according to an exemplary embodiment of the present application;

[0095] FIG8 is a schematic diagram of the layout structure of the first gate layer provided by an exemplary embodiment of the present application;

[0096] FIG9 is a schematic diagram of a layout structure in which a first gate layer is superimposed on an active layer, provided by an exemplary embodiment of the present application;

[0097] FIG10 is a schematic diagram of the layout structure of the second gate layer provided by an exemplary embodiment of the present application;

[0098] FIG11 is a schematic diagram of a layout structure in which a second gate layer is superimposed on a first gate layer, provided by an exemplary embodiment of the present application;

[0099] FIG12 is a schematic diagram of a layout structure of an active layer provided by an exemplary embodiment of the present application;

[0100] FIG13 is a schematic diagram of a layout structure in which an active layer is superimposed on a second gate layer, provided by an exemplary embodiment of the present application;

[0101] FIG14 is a schematic diagram of the layout structure of the third gate layer provided by an exemplary embodiment of the present application;

[0102] FIG15 is a schematic diagram of a layout structure in which a third gate layer is superimposed on an active layer, provided by an exemplary embodiment of the present application;

[0103] FIG16 is a schematic diagram of the layout structure of an interlayer dielectric layer provided by an exemplary embodiment of the present application;

[0104] FIG17 is a schematic diagram of the layout structure of a first source-drain electrode layer provided by an exemplary embodiment of the present application;

[0105] FIG18 is a schematic diagram of a layout structure in which a first source-drain electrode layer is superimposed on an interlayer dielectric layer, provided by an exemplary embodiment of the present application;

[0106] FIG19 is a schematic diagram of the layout structure of a first planarization layer provided by an exemplary embodiment of the present application;

[0107] FIG20 is a schematic diagram of the layout structure of a second source-drain electrode layer provided by an exemplary embodiment of the present application;

[0108] FIG21 is a schematic diagram of a layout structure in which a second source-drain electrode layer is superimposed on a first planarization layer, provided by an exemplary embodiment of the present application;

[0109] FIG22 is a schematic diagram of the layout structure of a second planarization layer provided by an exemplary embodiment of the present application;

[0110] FIG23 is a schematic diagram of the layout structure of a transparent electrode layer provided by an exemplary embodiment of the present application;

[0111] FIG24 is a schematic diagram of the layout structure of a third planarization layer provided by an exemplary embodiment of the present application;

[0112] FIG25 is a schematic diagram of the layout structure of the anode layer provided by an exemplary embodiment of the present application;

[0113] FIG26 is a schematic top view of a display substrate provided by another exemplary embodiment of the present application;

[0114] FIG27 is a schematic top view of the structure of a display substrate provided by another exemplary embodiment of the present application. DETAILED DESCRIPTION

[0115] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.

[0116] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. As used in this application and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0117] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0118] The following is a detailed description of the display substrate, its manufacturing method, and the display device in the embodiments of the present application in conjunction with the accompanying drawings. In the absence of conflict, the features of the following embodiments can complement or be combined with each other.

[0119] The embodiment of the present application provides a display substrate. As shown in Figures 1 and 2, the display substrate 100 includes:

[0120] The row addressing area 101 is provided with a row addressing circuit;

[0121] A first pixel driving area 102 is located on one side of the row addressing area 101, and the first pixel driving area 102 is provided with a pixel circuit;

[0122] A second pixel driving area 104 is located on the other side of the row addressing area 101 , and the row addressing area 101 is located between the first pixel driving area 102 and the second pixel driving area 104 ;

[0123] The row addressing circuit of the row addressing area 101 includes:

[0124] Scan driving circuit 1012;

[0125] a first gating circuit 1013 , located between the scan driving circuit 1012 and the first pixel driving area 102 , and connecting the scan driving circuit 1012 and the pixel circuits in the first pixel driving area 102 ;

[0126] The second gating circuit 1015 is located between the scan driving circuit 1012 and the second pixel driving area 104 , and connects the scan driving circuit 1012 and the pixel circuits in the second pixel driving area 104 .

[0127] The display substrate provided by the embodiment of the present application, by setting the row addressing area between the first pixel driving area and the second pixel driving area, enables the row addressing circuit of the same row addressing area to conveniently control the refresh rate of the first pixel driving area and the second pixel driving area located on both sides thereof. In addition, the first gating circuit connected between the scanning driving circuit and the pixel circuit of the first pixel driving area enables the row addressing circuit to relatively independently control the refresh rate of the pixels in the first pixel driving area; the second gating circuit connected between the scanning driving circuit and the pixel circuit of the second pixel driving area enables the row addressing circuit to relatively independently control the refresh rate of the pixels in the second pixel driving area. Therefore, the above-mentioned setting enables the refresh rates of the first pixel driving area and the second pixel driving area located in different areas to be adjusted relatively independently, that is, to realize partitioned frequency conversion, which is conducive to reducing display power consumption.

[0128] In some embodiments, the turn-on voltage can be provided to each row of the row addressing area in a certain order (for example, row by row, alternately, or in a predetermined order) through the scanning drive circuit, and the first selection circuit selectively provides the turn-on voltage applied to each row of the row addressing area to the gate lines of each row of the first pixel driving area according to the control signal it receives, so that the first pixel driving area achieves a predetermined refresh rate; the second selection circuit selectively conducts or does not conduct the turn-on voltage applied to each row of the row addressing area to the gate lines of each row of the second pixel driving area according to the control signal it receives, so that the second pixel driving area achieves a predetermined refresh rate. According to actual needs, the refresh rate of the second pixel driving area can be the same as the refresh rate of the first pixel driving area, or it can be different from the refresh rate of the first pixel driving area. The refresh rate of the first pixel driving area and the refresh rate of the second pixel driving area are independently adjustable.

[0129] In some embodiments, the first pixel driving area 102 , the row addressing area 101 , and the second pixel driving area 104 are sequentially arranged along a first direction X. The row addressing area 101 mainly extends along a second direction Y.

[0130] In some embodiments, the display substrate 100 is applied to a foldable display screen, such as a foldable mobile phone, a foldable notebook, or a foldable tablet, wherein the row addressing region 101 can be disposed in the foldable region to avoid reducing the area of ​​the conventional display region.

[0131] In some embodiments, the scan driver circuit 1012 includes a shift register. Under the control signal of an external circuit, the shift register generates a shift pulse signal (turn-on voltage). The shift pulse signal is used to drive the pixels of the current row to turn on the thin film transistors (TFTs) corresponding to the pixel row, and also serves as a start signal for the next row and an end signal for the previous row. The shift register is generally composed of thin film transistors and capacitors. For example, a 4T1C shift register or scan driver circuit includes four thin film transistors and one capacitor; an 8T1C shift register or scan driver circuit includes eight thin film transistors and one capacitor.

[0132] For non-progressive scanning, the scan driving circuit 1012 may be a circuit other than a shift register, which may also be composed of a plurality of thin film transistors and a number of capacitors to provide the turn-on voltage to each row of the row addressing area in a certain order.

[0133] In some embodiments, the first gating circuit 1013 includes a thin film transistor, for example, the first gating circuit 1013 may be composed of a plurality of thin film transistors in series, and is configured to selectively transmit or not transmit the turn-on voltage applied to each row of the row addressing region to the gate lines of each row of the first pixel driving region according to a control signal received by the first gating circuit 1013. The second gating circuit 1015 includes a thin film transistor, for example, it may be composed of a plurality of thin film transistors in series, and is configured to selectively transmit or not transmit the turn-on voltage applied to each row of the row addressing region to the gate lines of each row of the second pixel driving region according to a control signal received by the second gating circuit 1015.

[0134] An embodiment of the row addressing circuit of the row addressing area 101 is shown in FIG3 .

[0135] In the embodiment shown in FIG. 3 , the first gating circuit 1013 includes a first transistor T1 , a second transistor T2 , and a third transistor T3 to a twelfth transistor T12 .

[0136] In which, the first electrode of the first transistor T1 is connected to the first power supply signal VGHN, the gate of the first transistor T1 is connected to the first clock signal NCK_inv, and the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2; the second electrode of the second transistor T2 is connected to the first electrode of the third transistor T3 and is connected to the first scan signal Nscan[n]_inv, and the gate of the second transistor T2 is connected to the second scan signal Nscan[n-1]; the second electrode of the third transistor T3 is connected to the first electrode of the fourth transistor T4, and the gate of the third transistor T3 is connected to the second scan signal Nscan[n-1]; the second electrode of the fourth transistor T4 is connected to the second power supply signal VGLN, and the gate of the fourth transistor T4 is connected to the second clock signal NCK.

[0137] A first electrode of the fifth transistor T5 is connected to the first power supply signal VGHN, a second electrode of the fifth transistor T5 is connected to the first electrode of the sixth transistor T6, and a gate of the fifth transistor T5 is connected to the third scan signal Nscan[n]; a second electrode of the sixth transistor T6 is connected to the first electrode of the seventh transistor T7, and the gate of the sixth transistor T6 is connected to the second clock signal NCK; a second electrode of the seventh transistor T7 is connected to the first electrode of the eighth transistor T8, and the gate of the seventh transistor T7 is connected to the gate of the first transistor T1 and to the first clock signal NCK_inv; a second electrode of the eighth transistor T8 is connected to the second power supply signal VGLN, and the gate of the eighth transistor T8 is connected to the gate of the fifth transistor T5 and to the third scan signal Nscan[n].

[0138] A first electrode of the ninth transistor T9 is connected to the first power signal VGHN, a second electrode of the ninth transistor T9 is connected to the first electrode of the tenth transistor T10 and to the first clock signal NCK_inv, and a gate of the ninth transistor T9 is connected to the second clock signal NCK. A second electrode of the tenth transistor T10 is connected to the second power signal VGLN, and a gate of the tenth transistor T10 is connected to the second clock signal NCK. A first electrode of the eleventh transistor T11 is connected to the first power signal VGHN, a second electrode of the eleventh transistor T11 is connected to the first electrode of the twelfth transistor T12 and to the third scan signal Nscan[n], and a gate of the eleventh transistor T11 is connected to the first scan signal Nscan[n]_inv. A second electrode of the twelfth transistor T12 is connected to the second power signal VGLN, and a gate of the twelfth transistor T12 is connected to the first scan signal Nscan[n]_inv.

[0139] In the embodiment shown in FIG. 3 , the scan driving circuit 1012 may include a thirteenth transistor T13 , fourteenth transistors T14 to T20 , and a capacitor C0 .

[0140] The first electrode of the thirteenth transistor T13 is connected to the third scan signal Nscan[n], the gate of the thirteenth transistor T13 is connected to the control signal NCX, the second electrode of the thirteenth transistor T13 is connected to the first electrode of the fourteenth transistor T14 and to the first power signal VGHN; the second electrode of the fourteenth transistor T14 is connected to the N11 node, and the gate of the fourteenth transistor T14 is connected to the control signal NCX. The first electrode of the fifteenth transistor T15 is connected to the first power signal VGHN, the gate of the fifteenth transistor T15 is connected to the second scan signal Nscan[n-1], the second electrode of the fifteenth transistor T15 is connected to the first electrode of the sixteenth transistor T16; the second electrode of the sixteenth transistor T16 is connected to the first electrode of the seventeenth transistor T17 and to the N11 node, and the gate of the sixteenth transistor T16 is connected to the third scan signal Nscan[n].

[0141] The second electrode of the seventeenth transistor T17 is connected to the first electrode of the eighteenth transistor T18, and the gate of the seventeenth transistor T17 is connected to the third scan signal Nscan[n]. The second electrode of the eighteenth transistor T18 is connected to the first electrode of the twentieth transistor T20 and is connected to the third power signal VCT. The gate of the eighteenth transistor T18 is connected to the scan signal Nscan[n-1]_inv. The second electrode of the twentieth transistor T20 is connected to the first electrode of the nineteenth transistor T19, and the gate of the twentieth transistor T20 is connected to the second scan signal Nscan[n-1]. The second electrode of the nineteenth transistor T19 is connected to the first plate of the capacitor C0, and the gate of the nineteenth transistor T19 is connected to the first scan signal Nscan[n]_inv. The second plate of the capacitor C0 is connected to the fourth power signal VCL.

[0142] In the embodiment shown in FIG. 3 , the second gating circuit 1015 includes a twenty-first transistor T21 , a twenty-second transistor T22 , and a twenty-third transistor T23 to a twenty-sixth transistor T26 .

[0143] Wherein, a first electrode of the twenty-first transistor T21 is connected to the first power supply signal VGHN, a gate of the twenty-first transistor T21 is connected to the second electrode of the nineteenth transistor T19 and the first plate of the capacitor C0, and a second electrode of the twenty-first transistor T21 is connected to the first electrode of the twenty-third transistor T23; a first electrode of the twenty-second transistor T22 is connected to the first power supply signal VGHN, a gate of the twenty-second transistor T22 is connected to the third scan signal Nscan[n], and a second electrode of the twenty-second transistor T22 is connected to the first electrode of the twenty-third transistor T23.

[0144] A second electrode of the twenty-third transistor T23 is connected to the first electrode of the twenty-fourth transistor T24, and a gate of the twenty-third transistor T23 is connected to the gate of the twenty-first transistor T21; a second electrode of the twenty-fourth transistor T24 is connected to the fifth power supply signal VGL, and a gate of the twenty-fourth transistor T24 is connected to the gate of the twenty-second transistor T22.

[0145] A first electrode of the twenty-fifth transistor T25 is connected to the first power supply signal VGHN, a second electrode of the twenty-fifth transistor T25 is connected to the second electrode of the twenty-sixth transistor T26 and to the output signal Nout[n], and a gate of the twenty-fifth transistor T25 is connected to the second electrode of the twenty-first transistor T21; a first electrode of the twenty-sixth transistor T26 is connected to the fifth power supply signal VGL, a second electrode of the twenty-sixth transistor T26 is connected to the second electrode of the twenty-fifth transistor T25 and to the output signal Nout[n], and a gate of the twenty-sixth transistor T26 is connected to the gate of the twenty-fifth transistor T25.

[0146] The "first electrode of the Mth transistor" herein refers to either the source or drain of the Mth transistor; the "second electrode of the Mth transistor," distinct from the "first electrode of the Mth transistor," refers to the other of the source and drain of the Mth transistor. M is a positive integer, and can be one, two, three, ..., twenty-six, etc.

[0147] It should be noted that FIG3 shows only one embodiment of the row addressing circuit of the row addressing area 101. Other circuits that can achieve the above functions can also be used.

[0148] The cross-sectional schematic diagram of the display substrate 100 of the embodiment of the present application may be shown in Figure 4. As shown in Figure 4, along the third direction Z (i.e., the stacking direction of each film layer) (the third direction Z, the first direction X and the second direction Y are perpendicular to each other), the display substrate 100 sequentially includes a base 20, a driving circuit layer 60 and an organic light-emitting layer. The driving circuit layer 60 includes the row addressing circuit of the row addressing area 101. That is. The row addressing circuit of the row addressing area 101 is arranged in the driving circuit layer 60. The driving circuit layer 60 also includes a pixel circuit located in a conventional display area (including a first pixel driving area 102 and a second pixel driving area 104). The pixel circuit is generally composed of a capacitor and a plurality of thin film transistors, and is used to control the light emission of pixels in the first pixel driving area 102 and the second pixel driving area 104. The row addressing circuit of the row addressing area 101 is arranged on the same layer as the pixel circuit. Since the row addressing area 101 and the pixel circuit have the same components, both mainly including thin film transistors and capacitors, the row addressing area 101 and the pixel circuit can be conveniently formed simultaneously, which is conducive to simplifying the process steps and reducing the production cost.

[0149] In some embodiments, referring to FIG1 and FIG2 , the pixel circuits of the first pixel driving area 102, the row addressing circuits of the row addressing area 101, and the pixel circuits of the second pixel driving area 104 are sequentially arranged along a first direction X; the row addressing area 101 mainly extends along a second direction Y. The first direction X is a row direction, which is a horizontal direction in the figure, and the second direction Y is a column direction, which is a vertical direction in the figure.

[0150] Since the first pixel driving area 102 and the second pixel driving area 104 are conventional display areas, the row addressing area 101 mainly extends along the second direction Y, and the width of the row addressing area 101 in the first direction X (approximately a width of only a few pixels to a dozen pixels) is significantly smaller than the length of the row addressing area 101 in the second direction Y, which is beneficial to increasing the area of ​​the normal display area.

[0151] In some embodiments, the area where the row addressing region 101 is located can emit light like a conventional display area. Correspondingly, an anode, an organic light-emitting material, and a cathode are also provided above the row addressing region 101, and a plurality of pixels for display are provided. The pixels in the area where the row addressing region 101 is located can be driven to emit light by the pixel circuits of the first pixel driving region 102 and / or the second pixel driving region 104.

[0152] In some embodiments, the base 20 includes or is a flexible substrate 25. The material of the flexible substrate 25 may include one or more of polyimide, polyethylene terephthalate, polycarbonate, and organic resin materials. The organic resin material may include epoxy resin, triazine, silicone resin, or polyimide.

[0153] In some embodiments, the base 20 includes or is a rigid substrate 23. The rigid substrate 23 includes any one of a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, etc., or a semiconductor substrate such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon or silicon carbide, a compound semiconductor substrate such as silicon germanium, or an SOI (Silicon On Insulator) substrate.

[0154] In some embodiments, the base 20 includes both a rigid substrate 23 and a flexible substrate 25, wherein the flexible substrate 25 is disposed between the rigid substrate 23 and the drive circuit layer 60. Furthermore, after or during device fabrication, the rigid substrate 23 can be removed to provide the entire device with greater flexibility. The rigid substrate 23 primarily serves to support the flexible substrate 25 and the drive circuit layer 60 during the fabrication process.

[0155] To avoid being affected by external electronic components or external electric fields, a bottom shielding layer 32 may be provided on the front side of the substrate 20. As shown in Figures 4 and 5, the bottom shielding layer 32 may include a shielding pattern 323 and a connecting wire 325. The shielding pattern 323 may include a horizontal shielding line 3234 extending along the first direction X, a vertical shielding line 3232 extending along the second direction Y, and a square shielding block 3236 provided at the intersection of the horizontal shielding line 3234 and the vertical shielding line 3232. The morphology of the shielding pattern 323 may correspond to the morphology of at least part of the conductive elements (e.g., active area, gate line, data line, etc.) in the pixel circuit. The connecting wire 325 is used to electrically connect the various shielding patterns 323 into a whole. The material of the bottom shielding layer 32 may be metal, such as aluminum, copper, silver, etc.

[0156] A barrier layer 34 may be provided on top of the bottom shielding layer 32. The barrier layer may be made of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and is used to prevent the entry of water, oxygen, and the like. A buffer layer 36 (also referred to as a first buffer layer 36) may be provided on top of the barrier layer 34. The buffer layer 36 may be made of insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The buffer layer 36 may have a relatively thick film thickness. The upper surface of the buffer layer 36 is a flat surface. The buffer layer 36 may serve as a flat layer to improve the morphology quality of the film layer formed thereon.

[0157] Continuing with FIG4 and, if necessary, in conjunction with FIG6 , an active layer 42 (also referred to as a first active layer 42) may be disposed above the buffer layer 36. The active layer 42 may be made of amorphous silicon or polycrystalline silicon, for example. The active layer 42 includes multiple active regions 423, each of which is generally strip-shaped and corresponds to a thin-film transistor or multiple electrically connected thin-film transistors. For a first-type active region 4232 with a simple structure, corresponding to only one thin-film transistor, its ends along its length serve as the source region 42323 and drain region 42325 of the thin-film transistor, respectively. The active region portion between the source region 42323 and the drain region 42325 serves as the thin-film transistor channel. A second-type active region 4234 with a complex structure corresponds to two thin-film transistors connected in series. The second-type active region 4234 is sequentially provided with a first source-drain region 42343, a second source-drain region 42345, and a third source-drain region 42347 along its length. The first source / drain region 42343 and the third source / drain region 42347 are located at either end of the second type active region 4234, while the second source / drain region 42345 is located in the middle of the second type active region 4234. The first source / drain region 42343 and the second source / drain region 42345 serve as the source and drain regions of a thin film transistor, respectively. The active region between the first source / drain region 42343 and the second source / drain region 42345 serves as the channel of the thin film transistor. The second source / drain region 42345 and the third source / drain region 42347 serve as the source and drain regions of another thin film transistor, respectively. The active region between the second source / drain region 42345 and the third source / drain region 42347 serves as the channel of the other thin film transistor. The more complex third type active region 4236 is formed by connecting multiple first type active regions 4232 and second type active regions 4234. This allows the third type active region 4236 to correspond to a parallel-parallel structure with more thin film transistors. A portion of the third type active region 4236 extends along the first direction X, and another portion of the active region extends along the second direction Y. This allows the third type active region 4236 to occupy a larger size in both the first direction X and the second direction Y.

[0158] In addition to the strip-shaped active regions, a block-shaped active region 4238 is also provided. The block-shaped active region 4238 has substantially the same size in the first direction X and the second direction Y.

[0159] The active layer 42 is not only provided in the conventional display area, but also in the row addressing area 101. Because the scan driving circuit 1012, the first gating circuit 1013, and the second gating circuit 1015 all include thin film transistors, the active areas corresponding to the thin film transistors are also synchronously distributed in the areas where the scan driving circuit 1012, the first gating circuit 1013, and the second gating circuit 1015 are located.

[0160] Figure 7 shows the overlay of the active layer 42 and bottom shield layer 32 fabrication layouts. The active layer 42 in the conventional display area is primarily shielded by the bottom shield layer 32. Portions of the active layer 42 within the row addressing region 101 may not be shielded by the bottom shield layer 32.

[0161] Continuing with FIG4 , and in conjunction with FIG8 and FIG9 , a gate insulating layer 43 (also referred to as a first gate insulating layer 43 ) and a gate layer 44 (also referred to as a first gate layer 44 ) can be disposed above the active layer 42 . The gate insulating layer 43 can be a complete layer, or it can have a shape and pattern substantially identical to that of the gate layer 44 , as long as it effectively isolates the gate layer 44 from the active layer 42 . The gate insulating layer 43 can be made of silicon oxide, silicon nitride, or silicon oxynitride, among others. The gate layer 44 can be made of a metal material such as aluminum, copper, or silver.

[0162] The gate layer 44 includes a first type of gate line 442 extending along the first direction X and a plurality of gate pattern blocks 444 in a conventional display area (e.g., the first pixel driving area 102 and the second pixel driving area 104). Each gate pattern block 444 is generally block-shaped, and a plurality of gate pattern blocks 444 are arranged in a row along the first direction X. The area directly below the first type of gate line 442 corresponds to the channel of the active layer 42.

[0163] The gate layer 44 includes a first type of gate line 442 extending along the first direction X, a second type of gate line 446 extending both along the first direction X and along the second direction Y, a plurality of block-shaped gate pattern blocks 448, and a plurality of U-shaped third type of gate lines 449 in the first gating circuit 1013, the scan driver circuit 1012, and the second gating circuit 1015. Each of the third type of gate lines 449 includes a horizontal connecting line 4492 extending along the first direction X, and two vertical gate portions 4494 respectively arranged at both ends of the horizontal connecting line 4492. The two vertical gate portions 4494 are arranged side by side and spaced apart from each other. The two vertical gate portions 4494 in the same third type of gate line 449 are located directly above the same active area. Similarly, the area directly below the first type of gate line 442 and the second type of gate line 446 corresponds to the channel of the active layer 42.

[0164] Since the row addressing region 101 (especially the region where the scan driver circuit 1012 is located) is located between adjacent display regions, all or at least a portion of the gate lines need to bypass the row addressing region 101 to connect to the gate lines of the display region on the other side. Therefore, a gate connection line 94 (also referred to as a first gate connection line 94) can be provided in the gate layer 44 to connect the gate lines on both sides of the row addressing region 101 while minimizing the impact on the arrangement of components within the row addressing region 101. Connecting the gate lines on both sides through the gate connection line helps maintain consistency in ESD (electrostatic discharge) protection of the entire device.

[0165] The gate connection line 94 may include a gate connection terminal 942 connected to the gate line, a gate end 946 located in the scan driver circuit 1012 area (or the row addressing area 101) and away from the gate line, and a winding segment 944 located between the gate connection terminal 942 and the gate end 946 and connecting the gate connection terminal 942 and the gate end 946. The gate connection terminal 942 and the gate end 946 may extend along or mainly along the first direction X; the winding segment 944 may extend along or mainly along the second direction Y. Then, through the connection holes provided between the film layers and the connection lines or connection patterns located in other film layers (for example, the gate layer 46 or the gate layer 54), the gate connection line 94 can be connected to other gate connection lines, thereby achieving connection between the gate lines.

[0166] Another type of gate connection line 961 (also referred to as a second gate connection line 961) can also be provided in the gate layer 44. One end of the gate connection line 961 is connected to the gate line, and the other end of the gate connection line 961 does not extend to the scan driver circuit 1012 area but only slightly extends into the row addressing area 101 or extends to an area close to the row addressing area 101, and mainly extends along the second direction Y. Then, through the connection holes provided between the film layers and the connection lines or connection patterns located in other film layers (for example, the gate layer 46 or the gate layer 54), the gate connection line 961 can be connected to other gate connection lines, thereby achieving connection between the gate lines. The connection line or connection pattern connected to the gate connection line 961 must include a portion that crosses the scan driver circuit 1012 area. Only in this way can the gate connection line 961 be better assisted in achieving a wraparound connection to the scan driver circuit 1012 area.

[0167] Referring to Figures 10 and 11 , and in conjunction with Figure 4 , a gate insulating layer 45 (also referred to as a second gate insulating layer 45 ) and a gate layer 46 (also referred to as a second gate layer 46 ) may be disposed above the gate layer 44 . The gate insulating layer 45 may be a complete layer, or may have a shape and pattern substantially identical to that of the gate layer 46 , as long as it effectively isolates the gate layer 46 from the underlying first gate layer 44 . The gate insulating layer 45 may be made of silicon oxide, silicon nitride, or silicon oxynitride, among others. The gate layer 46 may be made of a metal such as aluminum, copper, or silver.

[0168] The gate layer 46 includes a fourth type of gate line 462 extending along the first direction X, and a plurality of gate pattern blocks 464 in a conventional display area (e.g., the first pixel driving area 102 and the second pixel driving area 104). The fourth type of gate line 462 is located directly above the first type of gate line 442 and forms a capacitor with the first type of gate line 442. Each gate pattern block 464 is roughly block-shaped, and a plurality of gate pattern blocks 464 are arranged in a row along the first direction X. The gate pattern block 464 is located directly above the corresponding gate pattern block 444 and forms a capacitor with the corresponding gate pattern block 444. A avoidance hole 4642 is provided inside the gate pattern block 464, and the conductive film layer or electronic component above can be connected to the gate pattern block 444 below through the avoidance hole 4642.

[0169] The gate layer 46 includes a fourth type of gate line 462 extending along the first direction X, a fifth type of gate line 466 extending along both the first direction X and the second direction Y, a plurality of block-shaped gate pattern blocks 468, and a plurality of U-shaped sixth type of gate lines 469 in the row addressing area 101. Each of the sixth type of gate lines 469 includes a horizontal connecting line 4692 extending along the first direction X, and two vertical gate portions 4694 respectively arranged at both ends of the horizontal connecting line 4692. The two vertical gate portions 4694 are arranged side by side and spaced apart from each other. The gate pattern block 468 is located directly above the corresponding gate pattern block 448. The corresponding gate pattern block 468 and the gate pattern block 448 form a capacitor.

[0170] A gate connection line 96 (also referred to as a third gate connection line 96 ) may be provided in the gate layer 46 to connect the gate lines on both sides of the row addressing region 101 (eg, the gate lines located in the gate layer 44 ).

[0171] The gate connection line 96 may include an intermediate connection segment 964 located in a central region of the scan driving circuit 1012 and extending toward both sides thereof along the first direction X. The gate connection line 96 may further include two proximal gate ends 966 located on opposite sides of the gate connection line 96 along the first direction X. The proximal gate ends 966 may be connected to gate lines in other film layers (e.g., the gate layer 44 or the gate layer 54) through connection holes provided between the film layers. The gate connection line 96 may further include a vertical segment 965 extending primarily along the second direction Y and connected between the intermediate connection segment 964 and the proximal gate ends 966.

[0172] In some embodiments, the gate-proximal end 966 of the gate connection line 96 can be connected to the gate connection line 961 in the gate layer 44 through a connection hole provided between film layers, thereby achieving connectivity between gate lines in the gate layer 44 .

[0173] Referring to Figures 4, 12 and 13, a whole buffer layer 47 (second buffer layer 47) can be provided above the gate layer 46. The material of the buffer layer 47 can be an insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. An active layer 52 (also referred to as the second active layer 52) can be provided above the buffer layer 47. The material of the active layer 52 can be a metal oxide, such as amorphous IGZO (Indium Gallium Zinc Oxide). The active layer 52 includes a plurality of active regions 523; each active region 523 extends generally in a strip shape, corresponding to a thin film transistor or a plurality of electrically connected thin film transistors. For the first-type active regions 5230 and 5232, which have a simple structure and correspond to only one thin-film transistor, their ends along the length direction serve as the source regions 52301 and 52323 and drain regions 52303 and 52325 of the thin-film transistor, respectively. The active region portion between the source regions 52301 and 52323 and the drain regions 52303 and 52325 serves as the thin-film transistor channel. The second-type active region 5234, which has a complex structure, corresponds to two thin-film transistors connected in series. The second-type active region 5234 is sequentially provided with a first source-drain region 52343, a second source-drain region 52345, and a third source-drain region 52347 along its length direction. The first source-drain region 52343 and the third source-drain region 52347 are located at either end of the second-type active region 5234, while the second source-drain region 52345 is located in the middle of the second-type active region 5234. The first source / drain region 52343 and the second source / drain region 52345 serve as the source and drain regions of a thin film transistor, respectively. The active region between the first source / drain region 52343 and the second source / drain region 52345 serves as the channel of the thin film transistor. The second source / drain region 52345 and the third source / drain region 52347 serve as the source and drain regions of another thin film transistor, respectively. The active region between the second source / drain region 52345 and the third source / drain region 52347 serves as the channel of the other thin film transistor.

[0174] The active layer 52 is not only provided in the conventional display area, but also in the row addressing area 101. Since the scan driving circuit 1012, the first gating circuit 1013, and the second gating circuit 1015 all include thin film transistors, the active areas corresponding to the thin film transistors can also be synchronously distributed in the areas where the scan driving circuit 1012, the first gating circuit 1013, and the second gating circuit 1015 are located.

[0175] The channel of the first type active region 5230 disposed in the conventional display area includes both a first connection region 52305 extending along the first direction X and a second connection region 52307 extending along the second direction Y. One end of the first connection region 52305 is connected to the source region 52301 and the other end is connected to the second connection region 52307; one end of the second connection region 52307 is connected to the first connection region 52305 and the other end is connected to the drain region 52303.

[0176] Referring to Figures 4 and 14-15 , a gate insulating layer 53 (also referred to as a third gate insulating layer 53 ) and a gate layer 54 (also referred to as a third gate layer 54 ) may be disposed above the active layer 52. The gate insulating layer 53 may be a complete layer, or may have a shape and pattern substantially identical to that of the gate layer 54, as long as it effectively isolates the gate layer 54 from the active layer 52. The gate insulating layer 53 may be made of silicon oxide, silicon nitride, or silicon oxynitride. The gate layer 54 may be made of a metal such as aluminum, copper, or silver.

[0177] The gate layer 54 includes, in a conventional display area, first-type gate lines 542 extending along a first direction X. The area directly below the first-type gate lines 542 corresponds to the channel of the active layer 52 .

[0178] The gate layer 54 includes a first type of gate line 542 extending along a first direction X, a second type of gate line 546 extending both along the first direction X and along a second direction Y, and a plurality of U-shaped third type of gate lines 549 in the row addressing area 101. Each of the third type of gate lines 549 includes a horizontal connecting line 5492 extending along the first direction X, and two vertical gate portions 5494 respectively arranged at both ends of the horizontal connecting line 5492. The two vertical gate portions 5494 are arranged side by side and spaced from each other. The two vertical gate portions 5494 in the same third type of gate line 549 are located directly above the same active area. Similarly, the area directly below the first type of gate line 542 and the second type of gate line 546 corresponds to the channel of the active layer 52.

[0179] A portion of the gate layer 54 in the regular display area and the area where the scan driving circuit 1012 is located is located directly above the gate layer 46 , that is, the gate layer 54 and the gate layer 46 have overlapping areas in the regular display area and the area where the scan driving circuit 1012 is located, and form a capacitor.

[0180] A gate connection line 96 (also referred to as a third gate connection line 96 ) may also be provided in the gate layer 54 to connect the gate lines on both sides of the row addressing region 101 (eg, the gate lines located in the gate layer 44 or the gate layer 46 ).

[0181] The gate connection line 96 located in the gate layer 54 may also include an intermediate connection segment 964 located in the middle area of ​​the row addressing area 101 and extending to both sides thereof along the first direction X. The gate connection line 96 may also include two proximal gate ends 966, which are located on opposite sides of the gate connection line 96 along the first direction X. The proximal gate ends 966 may be connected to gate lines in other film layers (e.g., the gate layer 44 or the gate layer 54) through connection holes provided between the film layers. The gate connection line 96 may also include a vertical segment 965 extending primarily along the second direction Y and connected between the intermediate connection segment 964 and the proximal gate ends 966.

[0182] In some embodiments, the gate-proximal end 966 of the gate connection line 96 can be connected to the gate connection line 961 in the gate layer 44 through a connection hole provided between film layers, thereby achieving connectivity between gate lines in the gate layer 44 .

[0183] At present, some of the better display panels (such as LTPO display panels) have pixel circuits that generally include two types of thin film transistors, namely N-type thin film transistors and P-type thin film transistors. Among them, the above-mentioned first active layer 42 and the first gate layer 44 can be used to make P-type thin film transistors; the above-mentioned second active layer 52 and the third gate layer 54 can be used to make N-type thin film transistors. A portion of the metal pattern in the second gate layer 46 can be used as a connecting line to achieve electrical connection of components in other film layers; a portion of the metal pattern in the second gate layer 46 can be arranged relative to the corresponding portion in the first gate layer 44 to form a capacitor, and another portion of the metal pattern in the second gate layer 46 can be arranged relative to the corresponding portion in the third gate layer 54 to form a capacitor.

[0184] 4 and 16-18 , an interlayer dielectric layer 57 may be disposed above the gate layer 54, and a first source / drain electrode layer 72 may be formed above the interlayer dielectric layer 57. The interlayer dielectric layer 57 may be a single layer. The material of the interlayer dielectric layer 57 may be an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0185] Before forming the first source-drain electrode layer 72, a local etching process can be used to form a plurality of connection holes 572 in the interlayer dielectric layer 57. The layout of the connection holes 572 is shown in FIG16.

[0186] When forming the first source / drain electrode layer 72, the material of the first source / drain electrode layer 72 is simultaneously filled into the connection holes 572, electrically connecting the first source / drain electrode layer 72 to the underlying film layer (e.g., the active layer 52). The first source / drain electrode layer 72, or at least a portion of the first source / drain electrode layer 72, can be considered a wiring pattern or a rewiring layer. The material of the first source / drain electrode layer 72 can be a conductive metal such as aluminum, copper, or silver.

[0187] As shown in Figures 17 and 18, the first source-drain electrode layer 72 may include a first trace 723 extending along the first direction X, a second trace 725 extending along the second direction Y, a third trace 727 extending along both the first direction X and the second direction Y, and a fourth conductive line block 729 in a dot-shaped or block-shaped manner.

[0188] Referring to Figures 4 and 19-21 , a passivation layer 73 may be disposed above the first source-drain electrode layer 72. A planarization layer 74 (also referred to as a first planarization layer 74) may be formed above the passivation layer 73. A second source-drain electrode layer 75 may be formed above the planarization layer 74. The passivation layer 73 may be a single layer. The passivation layer 73 may be made of an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride. The planarization layer 74 may be a single layer. The upper surface of the planarization layer 74 may be a flat surface. The planarization layer 74 may be made of silicon oxide, silicon nitride, silicon oxynitride, or an organic material.

[0189] Before forming the second source-drain electrode layer 75, a local etching process can be used to form a plurality of connection holes 732 and 742 in the planarization layer 74 and the passivation layer 73. The layout of the connection holes 732 and 742 is shown in FIG19.

[0190] When forming the second source-drain electrode layer 75, the material of the second source-drain electrode layer 75 is simultaneously filled into the connection holes 732 and 742, so that the second source-drain electrode layer 75 is electrically connected to the underlying film layer (such as the first source-drain electrode layer 72). The material of the second source-drain electrode layer 75 can be a conductive metal material such as aluminum, copper, or silver.

[0191] As shown in Figures 20 and 21, the second source-drain electrode layer 75 may include a first data line 752 extending along the second direction Y. A plurality of escape holes 7520 are defined within the first data line 752, and the plurality of escape holes 7520 are arranged along the second direction Y. A conductive line block 753 is disposed within the escape holes 7520. The first data lines 752 disposed within the first gating circuit 1013 and the second gating circuit 1015 may be connected as a whole via a conductive line 751. The conductive line 751 extends as a whole along the first direction X.

[0192] The second source-drain electrode layer 75 may further include a second data line 754 extending along the second direction Y. The width of the second data line 754 is significantly smaller than that of the first data line 752 .

[0193] The second source-drain electrode layer 75 may further include third data lines 7562 located in the scan driving circuit 1012 region. Each third data line 7562 extends along the second direction Y. Two or more third data lines 7562 are connected via a conductive line 7564. The conductive line 7564 extends along the first direction X.

[0194] Referring to FIG. 4 and FIG. 22-23 , a planarization layer 76 (also referred to as a second planarization layer 76 ) may be disposed above the second source / drain electrode layer 75 , and a transparent electrode layer 81 may be formed above the planarization layer 76 . The planarization layer 76 may be a single layer. The upper surface of the planarization layer 76 may be flat. The material of the planarization layer 76 may be silicon oxide, silicon nitride, silicon oxynitride, or an organic material.

[0195] Before forming the transparent electrode layer 81, a local etching process can be used to form a plurality of connection holes 762 in the planarization layer 76. The layout of the connection holes 762 is shown in FIG.

[0196] When forming the transparent electrode layer 81, the material of the transparent electrode layer 81 will simultaneously fill the connection hole 762, so that the transparent electrode layer 81 is electrically connected to the underlying film layer (such as the second source and drain electrode layer 75). The material of the transparent electrode layer 81 can be ITO (indium tin oxide).

[0197] As shown in FIG23 , the transparent electrode layer 81 may include a plurality of electrode strips 810. The electrode strips 810 include a first terminal 812, a second terminal 814, and an electrode body 816 located between the first terminal 812 and the second terminal 814. The first terminal 812 and the second terminal 814 are located at opposite ends of the electrode strips 810 in a first direction X. The electrode body 816 generally extends along the first direction X.

[0198] Referring to FIG. 4 and FIG. 24-25 , a planarization layer 83 (also referred to as a third planarization layer 83 ) may be disposed above the transparent electrode layer 81 , and an anode layer 85 may be formed above the planarization layer 83 . The planarization layer 83 may be a single layer. The upper surface of the planarization layer 83 may be flat. The material of the planarization layer 83 may be silicon oxide, silicon nitride, silicon oxynitride, or an organic material.

[0199] Before forming the anode layer 85, a local etching process can be used to form a plurality of connection holes 832 in the planarization layer 83. The layout of the connection holes 832 is shown in FIG.

[0200] When forming the anode layer 85, the material of the anode layer 85 is simultaneously filled into the connection hole 832, thereby electrically connecting the anode layer 85 to the underlying film layer (e.g., the transparent electrode layer 81). The material of the anode layer 85 can be a metal material such as aluminum, copper, or silver, or a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide.

[0201] As shown in FIG25 , the anode layer 85 may include a plurality of anode patterns 850. Each anode pattern 850 may correspond to a sub-pixel. The anode pattern 850 may be of various types, and may be a first anode pattern 852 for a first sub-pixel, a second anode pattern 854 for a second sub-pixel, or a third anode pattern 856 for a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively configured to emit light of different colors. For example, the first sub-pixel may be configured to emit red light, the second sub-pixel may be configured to emit green light, and the third sub-pixel may be configured to emit blue light.

[0202] Each of the anode patterns 850 may include a substantially square anode region 8503 and a connection region 8505 connected to the anode region 8503 . The connection region 8505 is connected to an edge of the anode region 8503 .

[0203] Continuing with FIG4 , a pixel defining layer 87 can be disposed above the anode layer 85. A plurality of grooves 870 are defined within the pixel defining layer 87, each of which exposes an anode pattern 850. Subsequently, an organic light-emitting material (or organic light-emitting layer) can be filled into the grooves 870.

[0204] The first gating circuit 1013 can be configured to be in the shape of an elongated strip, and the length of the first gating circuit 1013 in the second direction Y is significantly greater than the length of the first gating circuit 1013 in the first direction X. Reducing the length of the first gating circuit 1013 in the first direction X can help increase the area of ​​the conventional display region. In some embodiments, the length of the first gating circuit 1013 in the second direction Y is greater than two, three, four, or five times the length of the first gating circuit 1013 in the first direction X. As shown in FIG. 3 , the length of the first gating circuit 1013 in the first direction X can be reduced by arranging the thin film transistors within the first gating circuit 1013 primarily along the second direction Y.

[0205] The second gating circuit 1015 can be configured in an elongated strip shape, and the length of the second gating circuit 1015 in the second direction Y is significantly greater than the length of the second gating circuit 1015 in the first direction X. Reducing the length of the second gating circuit 1015 in the first direction X can help increase the area of ​​the conventional display region. In some embodiments, the length of the second gating circuit 1015 in the second direction Y is greater than two, three, four, or five times the length of the second gating circuit 1015 in the first direction X. As shown in FIG. 3 , the length of the second gating circuit 1015 in the first direction X can be reduced by arranging the thin film transistors within the second gating circuit 1015 primarily along the second direction Y.

[0206] A display substrate provided in another embodiment of the present application is shown in FIG26 . As shown in FIG26 , the display substrate 200 includes:

[0207] substrate;

[0208] The row addressing region 101 (also referred to as the first row addressing region 101 ) is provided on the substrate and is provided with a row addressing circuit;

[0209] A first pixel driving area 102 is provided on the substrate and located on one side of the row addressing area 101. The first pixel driving area 102 is provided with a pixel circuit;

[0210] A second pixel driving area 104 is provided on the substrate and located on the other side of the row addressing area 101. The second pixel driving area 104 is provided with a pixel circuit. The row addressing area 101 is located between the first pixel driving area 102 and the second pixel driving area 104. The refresh rates of the pixels in the first pixel driving area 102 and the refresh rates of the pixels in the second pixel driving area 104 are independently controlled by the row addressing circuit of the row addressing area 101.

[0211] A row addressing region 105 (also referred to as a second row addressing region 105 ) is provided on the substrate. The row addressing region 105 is provided with a second row addressing circuit and is located at an edge of the display substrate 200 .

[0212] a third pixel driving region 106 disposed on the substrate and located between the row addressing region 105 and the first pixel driving region 102 , wherein the third pixel driving region 106 is provided with a pixel circuit;

[0213] Wherein, the second row addressing circuit includes:

[0214] a second scanning driving circuit;

[0215] The third gating circuit is located between the second scanning driving circuit and the third pixel driving area 106 , and connects the second scanning driving circuit and the pixel circuits in the third pixel driving area 106 .

[0216] The above configuration enables the refresh rate of the pixels in the third pixel driving area 106 to be controlled by the second row addressing circuit in the row addressing area 105 .

[0217] By further setting a second row addressing area and a third pixel driving area at one edge of the display substrate, the refresh rates of the first pixel driving area, the second pixel driving area and the third pixel driving area located in different areas can be adjusted relatively independently, that is, partitioned frequency conversion is achieved, which is beneficial to reducing display power consumption.

[0218] In some embodiments, the structure and manufacturing method of the row addressing region 105 are the same as those of the row addressing region 101 .

[0219] In some embodiments, the display substrate 200 further includes:

[0220] A row addressing region 107 (also referred to as a third row addressing region 107 ) is provided on the substrate. The row addressing region 107 is provided with a third row addressing circuit. The row addressing region 107 is located at another edge of the display substrate 200 .

[0221] a fourth pixel driving area 108 , disposed on the substrate, wherein the fourth pixel driving area 108 is provided with a pixel circuit and is located between the second pixel driving area 104 and the row addressing area 107 ;

[0222] Wherein, the third row addressing circuit includes:

[0223] a third scanning driving circuit;

[0224] The fourth gating circuit is located between the third scan driving circuit and the fourth pixel driving area 108 , and connects the third scan driving circuit and the pixel circuits in the fourth pixel driving area 108 .

[0225] The above configuration enables the refresh rate of the pixels in the fourth pixel driving area 108 to be controlled by the third row addressing circuit of the row addressing area 107 .

[0226] By further setting a third row addressing area and a fourth pixel driving area at the other edge of the display substrate, the refresh rates of the first pixel driving area, the second pixel driving area, the third pixel driving area and the fourth pixel driving area located in different areas can be adjusted relatively independently, that is, partitioned frequency conversion is achieved, which is beneficial to reducing display power consumption.

[0227] In some embodiments, the structure and manufacturing method of the row addressing region 107 are the same as those of the row addressing region 101 .

[0228] A display substrate provided in another embodiment of the present application is shown in FIG27 . As shown in FIG27 , the display substrate 300 includes:

[0229] substrate (not shown);

[0230] A row addressing region 101 (also referred to as a first row addressing region 101 ) is provided on the substrate, and a row addressing circuit is provided in the row addressing region 101 ;

[0231] A first pixel driving area 102 is provided on the substrate and located on one side of the row addressing area 101;

[0232] a second pixel driving area 104 disposed on the substrate and located on the other side of the row addressing area 101, wherein the row addressing area 101 is located between the first pixel driving area 102 and the second pixel driving area 104; wherein the refresh rates of the first pixel driving area 102 and the second pixel driving area 104 are independently controlled by the row addressing circuit of the row addressing area 101;

[0233] A row addressing region 105 (also referred to as a second row addressing region 105 ) is provided on the substrate. The row addressing region 105 is provided with a second row addressing circuit. The row addressing region 105 is located at one edge of the display substrate 200 .

[0234] a third pixel driving region 106 disposed on the substrate and located between the row addressing region 105 and the first pixel driving region 102; wherein the refresh rate of the pixels in the third pixel driving region 106 is controlled by the second row addressing circuit of the row addressing region 105;

[0235] A row addressing region 107 (also referred to as a third row addressing region 107 ) is provided on the substrate. The row addressing region 107 is provided with a third row addressing circuit. The row addressing region 107 is located at another edge of the display substrate 200 .

[0236] a fourth pixel driving region 108 disposed on the substrate and located between the second pixel driving region 104 and the row addressing region 107; wherein the refresh rate of the pixels in the fourth pixel driving region 108 is controlled by the third row addressing circuit of the row addressing region 107;

[0237] A row addressing region 109 (also referred to as a fourth row addressing region 109 ) is provided on the substrate, and the row addressing region 109 is provided with a fourth row addressing circuit;

[0238] a fifth pixel driving region 110 , disposed on the substrate and located between the row addressing region 109 and the third pixel driving region 106 ;

[0239] a sixth pixel driving region 111 , disposed on the substrate and located between the row addressing region 109 and the first pixel driving region 102 ;

[0240] Wherein, the fourth row addressing circuit includes:

[0241] a fourth scanning driving circuit;

[0242] a fifth gating circuit, located between the fourth scan driving circuit and the fifth pixel driving area 110 , and connecting the fourth scan driving circuit and the pixel circuits in the fifth pixel driving area 110 ;

[0243] The sixth gating circuit is located between the fourth scanning driving circuit and the sixth pixel driving area 111 , and connects the fourth scanning driving circuit and the pixel circuits in the sixth pixel driving area 111 .

[0244] The above configuration enables the refresh rate of the pixels in the fifth pixel driving area 110 and the refresh rate of the pixels in the sixth pixel driving area 111 to be independently controlled by the fourth row addressing circuit of the row addressing area 109 .

[0245] By further setting up another row addressing area 109 and a fifth pixel driving area 110 and a sixth pixel driving area 111 in the display substrate, the refresh rates of the first pixel driving area, the second pixel driving area, the third pixel driving area, the fourth pixel driving area, the fifth pixel driving area and the sixth pixel driving area located in different areas can be adjusted relatively independently, that is, partitioned frequency conversion is achieved, which is beneficial to reducing display power consumption.

[0246] In some embodiments, the structure and manufacturing method of the row addressing region 109 are the same as those of the row addressing region 101 .

[0247] In some embodiments, the number of pixels in each row of the first pixel drive area 102 is comparable to the number of pixels in each row of the second pixel drive area 104. "Comparable" as used herein includes both situations where the number of pixels is the same as well as situations where the number of pixels is close. For example, if the difference between the two numbers is within ±20%, the two numbers are considered comparable. For two display areas controlled by the same row addressing region, having a comparable number of pixels in each row helps balance the load on both sides of the row addressing region and improves performance.

[0248] In some embodiments, the number of pixels in each row in the fifth pixel driving area 110 is equal to the number of pixels in each row in the sixth pixel driving area 111 .

[0249] The present application also provides a method for manufacturing a display substrate. The method can be used to manufacture the display substrates in the various embodiments described above. The method may include the following steps:

[0250] providing a substrate;

[0251] A row addressing region, a first pixel driving region, and a second pixel driving region are formed on the substrate, wherein the row addressing region is provided with a row addressing circuit; the first pixel driving region is located on one side of the row addressing region and is provided with a pixel circuit; the second pixel driving region is located on the other side of the row addressing region and is provided with a pixel circuit, and the row addressing region is located between the first pixel driving region and the second pixel driving region;

[0252] Wherein, the row addressing circuit includes:

[0253] Scan driving circuit;

[0254] a first gating circuit, located between the scan driving circuit and the first pixel driving area, and connecting the scan driving circuit and the pixel circuits in the first pixel driving area;

[0255] The second gating circuit is located between the scan driving circuit and the second pixel driving area, and connects the scan driving circuit and the pixel circuits in the second pixel driving area.

[0256] In some embodiments, the manufacturing method further comprises:

[0257] forming a driving circuit layer on one side of the substrate, the driving circuit layer including pixel circuits located in the first pixel driving area and the second pixel driving area, and a row addressing circuit located in the row addressing area, wherein both the pixel circuit and the row addressing circuit include capacitors and a plurality of thin film transistors;

[0258] An organic light emitting layer is formed on a side of the driving circuit layer away from the substrate.

[0259] An embodiment of the present application further provides a display device, which includes the display substrate described in any of the above embodiments.

[0260] In some embodiments, the display device further includes a housing, and the display substrate is embedded in the housing.

[0261] The display device provided in the embodiments of the present application may be any appropriate display device, including but not limited to mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigators, e-books, and any other products or components with display functions.

[0262] It should be noted that in the accompanying drawings, the sizes of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when an element or layer is referred to as being "on" another element or layer, it may be directly on the other element, or there may be an intermediate layer. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it may be directly under the other element, or there may be more than one intermediate layer or element. In addition, it will also be understood that when a layer or element is referred to as being "between" two layers or elements, it may be the only layer between the two layers or elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout the text indicate similar elements.

[0263] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, and the true scope and spirit of the present application are indicated by the following claims.

[0264] It should be understood that the present application is not limited to the exact structures described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A display substrate, characterized in that: The display substrate comprises: A row addressing area is provided with a row addressing circuit; A first pixel driving area, located at one side of the row addressing area, wherein the first pixel driving area is provided with a pixel circuit; A second pixel driving area, located at the other side of the row addressing area, the row addressing area is located between the first pixel driving area and the second pixel driving area, and the second pixel driving area is provided with a pixel circuit; Wherein, the row addressing circuit comprises: Scanning drive circuit; a first gating circuit, located between the scanning driving circuit and the first pixel driving area, and connecting the scanning driving circuit and the pixel circuit in the first pixel driving area; The second gating circuit is located between the scanning driving circuit and the second pixel driving area, and connects the scanning driving circuit and the pixel circuit in the second pixel driving area.

2. The display substrate according to claim 1, wherein: The display substrate further comprises: substrate; A driving circuit layer is arranged on one side of the substrate; An organic light-emitting layer is arranged on a side of the driving circuit layer away from the substrate; Wherein, the driving circuit layer includes the row addressing circuit of the row addressing area.

3. The display substrate according to claim 2, wherein: The driving circuit layer is provided with pixel circuits located in the first pixel driving area and the second pixel driving area, wherein the pixel circuits include capacitors and a plurality of thin film transistors and are configured to control the light emission of pixels; The row addressing circuit in the row addressing area is arranged in the same layer as the pixel circuit.

4. The display substrate according to claim 2, wherein: The base includes a rigid substrate and / or a flexible substrate.

5. The display substrate according to claim 2, wherein: A bottom shielding layer is arranged between the substrate and the driving circuit layer.

6. The display substrate according to claim 5, wherein: The bottom shielding layer includes a connecting wire and a plurality of shielding patterns, and the connecting wire electrically connects the plurality of shielding patterns into a whole.

7. The display substrate according to claim 6, wherein: The shielding pattern includes a transverse shielding line extending along a first direction, a longitudinal shielding line extending along a second direction, and a square shielding block arranged at the intersection of the transverse shielding line and the longitudinal shielding line.

8. The display substrate according to claim 2, wherein: A buffer layer is arranged between the driving circuit layer and the substrate.

9. The display substrate according to claim 2, wherein: The driving circuit layer comprises: a first active layer; a first gate layer; A second gate layer, disposed on a side of the first gate layer away from the substrate; a second active layer; The third gate layer is arranged on a side of the second gate layer away from the substrate.

10. The display substrate according to claim 9, wherein: The material of the first active layer includes amorphous silicon or polycrystalline silicon.

11. The display substrate according to claim 9, wherein: The first active layer includes a plurality of first active regions, each of which corresponds to a thin film transistor or a plurality of electrically connected thin film transistors; The row addressing area, the first pixel driving area and the second pixel driving area are all provided with the first active area.

12. The display substrate according to claim 9, wherein: The first gate layer located in the first pixel driving area and the second pixel driving area includes a first type of gate lines extending along a first direction, and a plurality of gate pattern blocks; The gate pattern blocks are block-shaped, and a plurality of the gate pattern blocks are arranged in a row along a first direction.

13. The display substrate according to claim 9, wherein: The first gate layer in the row addressing area includes a first type of gate lines extending along a first direction, a second type of gate lines extending along both the first direction and the second direction, a plurality of block-shaped gate pattern blocks, and a plurality of U-shaped third type of gate lines.

14. The display substrate according to claim 13, wherein: The third type of grid lines include a horizontal connection line extending along a first direction, and two vertical grid portions respectively arranged at two ends of the horizontal connection line, wherein the two vertical grid portions are arranged side by side and spaced apart from each other.

15. The display substrate according to claim 9, wherein: The first gate layer includes a first gate connection line for connecting gate lines at both sides of the row addressing region.

16. The display substrate according to claim 15, wherein: The first gate connection line includes a gate connection end connected to the gate line, a gate away end located in the row addressing area and away from the gate line, and a winding segment located between the gate connection end and the gate away end and connecting the gate connection end and the gate away end, wherein the gate connection end and / or the gate away end extend along a first direction, and the winding segment extends along a second direction.

17. The display substrate according to claim 9, wherein: The first gate layer includes a second gate connection line for connecting gate lines on both sides of the row addressing area, one end of the second gate connection line is connected to the gate line, and the other end of the second gate connection line does not extend to the scan driving circuit area of ​​the row addressing area.

18. The display substrate according to claim 9, wherein: The second gate layer located in the first pixel driving area and the second pixel driving area includes a fourth type of gate lines extending along the first direction, and a plurality of gate pattern blocks; At least a portion of the fourth-type gate lines and a corresponding portion of the first gate layer form a capacitor, and at least a portion of the gate pattern blocks and a corresponding portion of the first gate layer form a capacitor.

19. The display substrate according to claim 9, wherein: The second gate layer located in the row addressing area includes a fourth type of gate lines extending along the first direction, a fifth type of gate lines extending along both the first direction and the second direction, a plurality of block-shaped gate pattern blocks, and a plurality of U-shaped sixth type of gate lines.

20. The display substrate according to claim 19, wherein: The sixth type of grid lines include a horizontal connecting line extending along the first direction, and two vertical grid portions respectively arranged at two ends of the horizontal connecting line, the two vertical grid portions being arranged side by side and spaced from each other; The gate pattern block and a corresponding portion of the first gate layer form a capacitor.

21. The display substrate according to claim 9, wherein: The second gate layer includes a third gate connection line for connecting gate lines on both sides of the row addressing area; The third gate connection line includes a middle connection segment, two near-gate ends and a vertical segment, wherein the middle connection segment is located in the middle area of ​​the row addressing area and extends to both sides thereof along a first direction, the two near-gate ends are respectively located on opposite sides of the gate connection line along the first direction, and the vertical segment extends along a second direction and is connected between the middle connection segment and the near-gate ends.

22. The display substrate according to claim 9, wherein: The material of the second active layer includes metal oxide.

23. The display substrate according to claim 9, wherein: The third gate layer located in the first pixel driving area and the second pixel driving area includes a first type of gate lines extending along a first direction.

24. The display substrate according to claim 9, wherein: The third gate layer located in the row addressing area includes a first type of gate lines extending along the first direction, a second type of gate lines extending along both the first direction and the second direction, and a plurality of third type of gate lines in a U shape; The third type of grid lines include a horizontal connection line extending along a first direction, and two vertical grid portions respectively arranged at two ends of the horizontal connection line, wherein the two vertical grid portions are arranged side by side and spaced apart from each other.

25. The display substrate according to claim 9, wherein: The third gate layer includes a third gate connection line for connecting the gate lines on both sides of the row addressing area; The third gate connection line includes a middle connection segment, two near-gate ends and a vertical segment, wherein the middle connection segment is located in the middle area of ​​the row addressing area and extends to both sides thereof along a first direction, the two near-gate ends are respectively located on opposite sides of the gate connection line along the first direction, and the vertical segment extends along a second direction and is connected between the middle connection segment and the near-gate ends.

26. The display substrate according to claim 1, wherein: The display substrate further comprises: A second row addressing area is located at an edge of the display substrate, and a second row addressing circuit is provided in the second row addressing area; a third pixel driving area, located between the second row addressing area and the first pixel driving area; Wherein, the second row addressing circuit comprises: a second scanning driving circuit; The third gating circuit is located between the second scanning driving circuit and the third pixel driving area, and connects the second scanning driving circuit and the pixel circuit in the third pixel driving area.

27. The display substrate according to claim 26, wherein: The display substrate further comprises: A third row addressing area is located at another edge of the display substrate, and the third row addressing area is provided with a third row addressing circuit; a fourth pixel driving area, located between the second pixel driving area and the third row addressing area; Wherein, the third row addressing circuit comprises: a third scanning driving circuit; The fourth gating circuit is located between the third scanning driving circuit and the fourth pixel driving area, and connects the third scanning driving circuit and the pixel circuit in the fourth pixel driving area.

28. The display substrate according to claim 27, wherein: The display substrate further comprises: A fourth row addressing area is provided with a fourth row addressing circuit; a fifth pixel driving area, located between the fourth row addressing area and the third pixel driving area; a sixth pixel driving region, located between the fourth row addressing region and the first pixel driving region; Wherein, the fourth row addressing circuit comprises: a fourth scanning driving circuit; a fifth gating circuit, located between the fourth scanning driving circuit and the fifth pixel driving area, and connecting the fourth scanning driving circuit and the pixel circuit in the fifth pixel driving area; The sixth gating circuit is located between the fourth scanning driving circuit and the sixth pixel driving area, and connects the fourth scanning driving circuit and the pixel circuit in the sixth pixel driving area.

29. The display substrate according to claim 28, wherein: The number of pixels in each row in the first pixel driving area is equal to the number of pixels in each row in the second pixel driving area; And / or, the number of pixels in each row in the fifth pixel driving area is equal to the number of pixels in each row in the sixth pixel driving area.

30. The display substrate according to claim 1, wherein: The refresh rate of the first pixel driving area and the refresh rate of the second pixel driving area are independently controlled by the row addressing circuit of the row addressing area.

31. A method for manufacturing a display substrate according to any one of claims 1 to 30, characterized in that: The production method comprises: providing a substrate; A row addressing region, a first pixel driving region and a second pixel driving region are formed on the substrate, wherein the row addressing region is provided with a row addressing circuit; the first pixel driving region is located at one side of the row addressing region, and the first pixel driving region is provided with a pixel circuit; the second pixel driving region is located at the other side of the row addressing region, and the second pixel driving region is provided with a pixel circuit, and the row addressing region is located between the first pixel driving region and the second pixel driving region; Wherein, the row addressing circuit comprises: Scanning drive circuit; a first gating circuit, located between the scanning driving circuit and the first pixel driving area, and connecting the scanning driving circuit and the pixel circuit in the first pixel driving area; The second gating circuit is located between the scanning driving circuit and the second pixel driving area, and connects the scanning driving circuit and the pixel circuit in the second pixel driving area.

32. The method of claim 31, wherein: Also includes: A driving circuit layer is formed on one side of the substrate, wherein the driving circuit layer includes pixel circuits located in the first pixel driving area and the second pixel driving area, and a row addressing circuit located in the row addressing area, wherein both the pixel circuit and the row addressing circuit include capacitors and a plurality of thin film transistors; An organic light emitting layer is formed on a side of the driving circuit layer away from the substrate.

33. A display device, characterized in that: The display device comprises the display substrate according to any one of claims 1 to 30.

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