Pixel circuit, driving method, display substrate and display device

Abstract

The invention provides a pixel circuit, a driving method, a display substrate and a display device. The pixel circuit comprises a data write-in circuit, an energy storage circuit, a first control circuit, a second control circuit, a driving circuit and a light-emitting element, the data write-in circuit writes data voltage into the first node under the control of a write-in control signal; the first control circuit controls the connection or disconnection between the first node and the second node under the control of the light-emitting control signal; the second control circuit controls the connection or disconnection between the first voltage end and the second node under the control of the light-emitting control signal; the driving circuit generates a driving current flowing from a second voltage end to the first pole of the light-emitting element under the control of the potential of the second node. According to the embodiment of the invention, whether the driving circuit can drive the light-emitting element to emit light or not in each light-emitting stage can be controlled, and the light-emitting brightness can be controlled by adjusting the display time, so that the display uniformity can be improved.

Description

Pixel circuit, driving method, display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a driving method, a display substrate, and a display device. Background Art

[0002] Micro LEDs (micro light-emitting diodes) have great potential in the display field due to their high brightness, long lifespan, and compact size. Currently, glass-based Micro LEDs cannot achieve high PPI (pixel density) displays due to the size and stability limitations of thin-film transistors (TFTs). However, silicon-based Micro LEDs can significantly reduce the pixel circuit area, thereby significantly improving PPI.

[0003] After actual testing and verification, the main problems with the current Micro LED characteristics are: the main wave peak drifts with the change of current density; and the brightness uniformity is poor at low current density.

[0004] Summary of the Invention

[0005] In one aspect, an embodiment of the present disclosure provides a pixel circuit, including a data writing circuit, an energy storage circuit, a first control circuit, a second control circuit, a driving circuit, and a light-emitting element;

[0006] The data writing circuit is electrically connected to the write control terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the write control signal provided by the write control terminal;

[0007] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0008] The first control circuit is electrically connected to the light-emitting control terminal, the first node, and the second node, respectively, and is configured to control the connection or disconnection between the first node and the second node under the control of a light-emitting control signal provided by the light-emitting control terminal;

[0009] The second control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the second node respectively, and is used to control the connection or disconnection between the first voltage terminal and the second node under the control of the light emitting control signal;

[0010] The driving circuit is electrically connected to the second node, the second voltage terminal and the first electrode of the light-emitting element respectively, and is used to generate a driving current flowing from the second voltage terminal to the first electrode of the light-emitting element under the control of the potential of the second node;

[0011] The second electrode of the light emitting element is electrically connected to the third voltage terminal.

[0012] Optionally, the data writing circuit includes a first transistor and a second transistor; the writing control terminal includes a first writing control terminal and a second writing control terminal;

[0013] The gate of the first transistor is electrically connected to the first write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first node;

[0014] A gate of the second transistor is electrically connected to the second write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the first node.

[0015] Optionally, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or, the first transistor is an n-type transistor, and the second transistor is a p-type transistor.

[0016] Optionally, the first control circuit includes a third transistor, and the second control circuit includes a fourth transistor;

[0017] The gate of the third transistor is electrically connected to the light emitting control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the second node;

[0018] The gate of the fourth transistor is electrically connected to the light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0019] Optionally, the third transistor is a p-type transistor, and the fourth transistor is an n-type transistor; or, the third transistor is an n-type transistor, and the fourth transistor is a p-type transistor.

[0020] Optionally, the energy storage circuit includes a storage capacitor;

[0021] A first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to a DC voltage end.

[0022] Optionally, the driving circuit includes a driving transistor;

[0023] The gate of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the second voltage terminal, and the second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element.

[0024] Optionally, the driving transistor is a p-type transistor, and the first voltage terminal is a first high voltage terminal; or,

[0025] The driving transistor is an n-type transistor, and the first voltage end is a first low voltage end.

[0026] Optionally, the light-emitting element is a silicon-based micro light-emitting diode, and the pixel circuit is arranged on a silicon substrate.

[0027] In a second aspect, an embodiment of the present disclosure provides a driving method, applied to the above-mentioned pixel circuit, wherein a display cycle includes N display time periods; N is an integer greater than 1; the nth display time period may include an nth writing phase and an nth light-emitting phase arranged in sequence; n is a positive integer less than or equal to N;

[0028] In the nth write phase, the data write circuit, under the control of the write control signal, writes the nth data voltage provided by the data line into the first node, and the energy storage circuit maintains the potential of the first node; the second control circuit, under the control of the light emitting control signal, controls the connection between the first voltage terminal and the second node, so as to control the drive circuit to be disconnected under the control of the potential of the second node;

[0029] In the nth light-emitting stage, the first control circuit controls the connection between the first node and the second node under the control of the light-emitting control signal to write the nth data voltage into the second node, and the driving circuit controls whether to drive the light-emitting element to emit light according to the nth data voltage.

[0030] Optionally, the durations of the N lighting phases are different from each other.

[0031] Optionally, at least some of the N light-emitting stages have different durations.

[0032] Optionally, the duration of the nth light-emitting stage is 2n×t0; or, the duration of the nth light-emitting stage is 2n×t0; wherein t0 is the basic light-emitting time.

[0033] In a third aspect, an embodiment of the present disclosure provides a display substrate, comprising a silicon substrate, and the above-mentioned pixel circuit disposed on the silicon substrate.

[0034] In a fourth aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0036] FIG2 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0037] FIG3 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG2 ;

[0038] FIG4 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0039] FIG5 is a circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0040] FIG. 6 is an operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 5 . DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0042] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0043] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0044] The pixel circuit described in the embodiment of the present disclosure includes a data writing circuit, an energy storage circuit, a first control circuit, a second control circuit, a driving circuit and a light-emitting element;

[0045] The data writing circuit is electrically connected to the write control terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the write control signal provided by the write control terminal;

[0046] The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node;

[0047] The first control circuit is electrically connected to the light-emitting control terminal, the first node, and the second node, respectively, and is configured to control the connection or disconnection between the first node and the second node under the control of a light-emitting control signal provided by the light-emitting control terminal;

[0048] The second control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the second node respectively, and is used to control the connection or disconnection between the first voltage terminal and the second node under the control of the light emitting control signal;

[0049] The driving circuit is electrically connected to the second node, the second voltage terminal and the first electrode of the light-emitting element respectively, and is used to generate a driving current flowing from the second voltage terminal to the first electrode of the light-emitting element under the control of the potential of the second node;

[0050] The second electrode of the light emitting element is electrically connected to the third voltage terminal.

[0051] When the pixel circuit according to the embodiment of the present disclosure is in operation, a display cycle may include N display time periods, and the nth display time period may include an nth writing phase and an nth light-emitting phase that are sequentially arranged, wherein the duration of the nth light-emitting phase may be tn; the duration of each light-emitting phase may be different from each other, or at least some of the N light-emitting phases may be different from each other;

[0052] In the nth write phase, the data write circuit, under the control of the write control signal, writes the nth data voltage provided by the data line into the first node, and the energy storage circuit maintains the potential of the first node; in the nth write phase, the second control circuit, under the control of the light emitting control signal, controls the connection between the first voltage terminal and the second node to control the drive circuit to be disconnected;

[0053] In the nth light-emitting stage, the first control circuit controls the connection between the first node and the second node under the control of the light-emitting control signal to write the nth data voltage into the second node, and the driving circuit can control whether to drive the light-emitting element to emit light according to the nth data voltage.

[0054] When the pixel circuit described in the embodiment of the present disclosure is in operation, by controlling the nth data voltage, it can control whether the driving circuit can drive the light-emitting element to emit light in each light-emitting stage, and by adjusting the display time to control the light-emitting brightness, it can perform PWM (pulse width modulation) control to improve display uniformity.

[0055] In a specific implementation, the duration tn of the nth light emitting stage may be 2n×t0, or the duration tn of the nth light emitting stage may be 2n×t0; but not limited thereto; in a specific implementation, tn may also be other values;

[0056] Among them, t0 can be the basic luminescence time;

[0057] Optionally, the first voltage terminal may be a first high voltage terminal, the second voltage terminal may be a second high voltage terminal, and the third voltage terminal may be a low voltage terminal; or,

[0058] The first voltage terminal may be the second low voltage terminal, the second voltage terminal may be the second high voltage terminal, and the third voltage terminal may be the first low voltage terminal.

[0059] In at least one embodiment of the present disclosure, the light-emitting element may be a silicon-based Micro LED (micro light-emitting diode), and the pixel circuit may be disposed on a silicon substrate, but is not limited thereto.

[0060] The embodiments of the present disclosure provide a pixel circuit that implements PWM (pulse width modulation) control, thereby effectively improving the uniformity of display brightness.

[0061] In at least one embodiment of the present disclosure, the pixel circuit can be provided on a silicon substrate. The characteristics of silicon-based transistors are far superior to those of glass-based transistors, so there is no need for threshold voltage compensation, which can further improve PPI.

[0062] As shown in FIG1 , the pixel circuit according to at least one embodiment of the present disclosure includes a data writing circuit 11 , an energy storage circuit 12 , a first control circuit 13 , a second control circuit 14 , a driving circuit 15 and a light emitting element 16 ;

[0063] The data writing circuit 11 is electrically connected to the writing control terminal GL, the data line DL and the first node A respectively, and is used to write the data voltage provided by the data line DL into the first node A under the control of the writing control signal provided by the writing control terminal GL;

[0064] The energy storage circuit 12 is electrically connected to the first node A, and is used to maintain the potential of the first node A;

[0065] The first control circuit 13 is electrically connected to the light emitting control terminal EM, the first node A, and the second node B, respectively, and is used to control the connection or disconnection between the first node A and the second node B under the control of the light emitting control signal provided by the light emitting control terminal EM;

[0066] The second control circuit 14 is electrically connected to the light emitting control terminal EM, the first voltage terminal V1 and the second node B respectively, and is used to control the connection or disconnection between the first voltage terminal V1 and the second node B under the control of the light emitting control signal;

[0067] The driving circuit 15 is electrically connected to the second node B, the second voltage terminal V2, and the first electrode of the light-emitting element 16, respectively, and is used to generate a driving current flowing from the second voltage terminal V2 to the first electrode of the light-emitting element 16 under the control of the potential of the second node B;

[0068] The second electrode of the light emitting element 16 is electrically connected to the third voltage terminal V3.

[0069] In at least one embodiment of the pixel circuit shown in FIG1 of the present disclosure, when in operation, a display cycle may include N display time periods, and the nth display time period may include an nth writing phase and an nth light-emitting phase arranged in sequence, wherein the duration of the nth light-emitting phase may be tn; N may be an integer greater than 1; and n may be a positive integer less than or equal to N.

[0070] In the nth writing phase, the data writing circuit 11 writes the nth data voltage Vdn provided by the data line DL into the first node A under the control of the write control signal, and the energy storage circuit 12 maintains the potential of the first node A. The second control circuit 14 controls the connection between the first voltage terminal V1 and the second node B under the control of the light emitting control signal, and controls the driving circuit 15 to disconnect the electrical connection between the first terminal and the second terminal under the control of the potential of the second node B.

[0071] In the nth light-emitting stage, the first control circuit 13 controls the connection between the first node A and the second node B under the control of the light-emitting control signal to write the nth data voltage Vdn into the second node B, and the driving circuit 15 controls whether to drive the light-emitting element 16 to emit light according to the nth data voltage Vdn.

[0072] When at least one embodiment of the pixel circuit of the present disclosure as shown in Figure 1 is in operation, in the nth write stage, the first control circuit 13 controls the disconnection between the first node A and the second node B under the control of the light-emitting control signal; in the nth light-emitting stage, the data write circuit 11 controls the disconnection between the data line DL and the first node A under the control of the write control signal; and the second control circuit 13 controls the disconnection between the first voltage terminal V1 and the second node B under the control of the light-emitting control signal.

[0073] In at least one embodiment of the pixel circuit shown in FIG. 1 of the present disclosure, the duration of the nth light emitting phase may be tn.

[0074] In at least one embodiment of the pixel circuit shown in FIG1 of the present disclosure, when N is equal to 3, the display cycle may include three display time periods; the first light-emitting stage lasts for a time t1, the second light-emitting stage lasts for a time t2, and the third light-emitting stage lasts for a time t3;

[0075] When the brightness of the light-emitting element corresponds to the binary number 000, the light-emitting element does not emit light in the first light-emitting stage, the second light-emitting stage, and the third light-emitting stage. Then, in the display period, the total light-emitting duration of the light-emitting element is 0.

[0076] When the brightness of the light-emitting element corresponds to the binary number 001, the light-emitting element emits light in the first light-emitting stage; the light-emitting element does not emit light in the second light-emitting stage and the third light-emitting stage. Then, in the display period, the total light-emitting duration of the light-emitting element is t1.

[0077] When the brightness of the light-emitting element corresponds to the binary number 010, the light-emitting element emits light in the second light-emitting stage; the light-emitting element does not emit light in the first light-emitting stage and the third light-emitting stage. In the display period, the total light-emitting duration of the light-emitting element is t2.

[0078] When the brightness of the light-emitting element corresponds to the binary number 011, the light-emitting element emits light in the first and second light-emitting stages; and does not emit light in the third light-emitting stage. In the display period, the total light-emitting duration of the light-emitting element is t1+t2.

[0079] When the brightness of the light-emitting element corresponds to the binary number 100, the light-emitting element does not emit light in the first and second light-emitting stages; and emits light in the third light-emitting stage. In this case, the total light-emitting duration of the light-emitting element in the display period is t3.

[0080] When the brightness of the light-emitting element corresponds to the binary number 101, the light-emitting element emits light in the first and third light-emitting stages; in the second light-emitting stage, the light-emitting element does not emit light. In this case, the total light-emitting duration of the light-emitting element in the display period is t1+t3.

[0081] When the brightness of the light-emitting element corresponds to the binary number 110, the light-emitting element emits light in the first and third light-emitting stages; and does not emit light in the second light-emitting stage. In this case, the total light-emitting duration of the light-emitting element in the display period is t2+t3.

[0082] When the luminous brightness of the light-emitting element corresponds to the binary number 111, the light-emitting element emits light in the first light-emitting stage, the second light-emitting stage and the third light-emitting stage; then in the display period, the total light-emitting duration of the light-emitting element is t1+t2+t3.

[0083] In a specific implementation, t1 may be 2t0, t2 may be 4t0, and t3 may be 6t0; or, t1 may be 2t0, t2 may be 4t0, and t3 may be 8t0; but the present invention is not limited thereto.

[0084] In at least one embodiment of the present disclosure, the data writing circuit includes a first transistor and a second transistor; the writing control terminal includes a first writing control terminal and a second writing control terminal;

[0085] The gate of the first transistor is electrically connected to the first write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first node;

[0086] A gate of the second transistor is electrically connected to the second write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the first node.

[0087] In a specific implementation, the write control end may include a first write control end and a second write control end, the data write circuit may include a first transistor and a second transistor, the type of the first transistor is different from the type of the second transistor, and the first write control signal provided by the first write control end and the second write control signal provided by the second write control end are inverted to each other.

[0088] Optionally, the first transistor is a p-type transistor, and the second transistor is an n-type transistor; or, the first transistor is an n-type transistor, and the second transistor is a p-type transistor.

[0089] In at least one embodiment of the present disclosure, the first control circuit includes a third transistor, and the second control circuit includes a fourth transistor;

[0090] The gate of the third transistor is electrically connected to the light emitting control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the second node;

[0091] The gate of the fourth transistor is electrically connected to the light emitting control terminal, the first electrode of the fourth transistor is electrically connected to the first voltage terminal, and the second electrode of the fourth transistor is electrically connected to the second node.

[0092] In a specific implementation, the first control circuit may include a third transistor, and the second control circuit may include a fourth transistor; the type of the third transistor is different from the type of the fourth transistor, and when the third transistor is turned on, the fourth transistor is turned off; when the fourth transistor is turned on, the third transistor is turned off.

[0093] Optionally, the third transistor is a p-type transistor, and the fourth transistor is an n-type transistor; or, the third transistor is an n-type transistor, and the fourth transistor is a p-type transistor.

[0094] Optionally, the energy storage circuit includes a storage capacitor;

[0095] A first end of the storage capacitor is electrically connected to the first node, and a second end of the storage capacitor is electrically connected to a DC voltage end.

[0096] In a specific implementation, the energy storage circuit may include a storage capacitor, and the storage capacitor is used to maintain the potential of the first node.

[0097] In a specific implementation, the DC voltage terminal may be a common electrode voltage terminal, but is not limited thereto. In actual operation, the DC voltage terminal may also be a low voltage terminal.

[0098] In at least one embodiment of the present disclosure, the driving circuit includes a driving transistor;

[0099] The gate of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the second voltage terminal, and the second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element.

[0100] Optionally, the driving transistor is a p-type transistor, and the first voltage terminal is a first high voltage terminal; or,

[0101] The driving transistor is an n-type transistor, and the first voltage end is a first low voltage end.

[0102] As shown in FIG2 , based on at least one embodiment of the pixel circuit shown in FIG1 ,

[0103] The data writing circuit includes a first transistor M1 and a second transistor M2; the writing control terminal includes a first writing control terminal GLP and a second writing control terminal GLN;

[0104] The gate of the first transistor M1 is electrically connected to the first write control terminal GLP, the source of the first transistor M1 is electrically connected to the data line DL, and the drain of the first transistor M1 is electrically connected to the first node A;

[0105] The gate of the second transistor M2 is electrically connected to the second write control terminal GLN, the source of the second transistor M2 is electrically connected to the data line DL, and the drain of the second transistor M2 is electrically connected to the first node A;

[0106] The first control circuit includes a third transistor M3, and the second control circuit includes a fourth transistor M4;

[0107] The gate of the third transistor M3 is electrically connected to the light emitting control terminal EM, the source of the third transistor M3 is electrically connected to the first node A, and the drain of the third transistor M3 is electrically connected to the second node B;

[0108] The gate of the fourth transistor M4 is electrically connected to the light emitting control terminal EM, the source of the fourth transistor M4 is electrically connected to the first high voltage terminal VDD1, and the drain of the fourth transistor M4 is electrically connected to the second node B;

[0109] The driving circuit includes a driving transistor M0; the light emitting element is a silicon-based micro light emitting diode ML;

[0110] The gate of the driving transistor M0 is electrically connected to the second node B, the source of the driving transistor M0 is electrically connected to the second high voltage terminal VDD2, and the drain of the driving transistor M0 is electrically connected to the anode of the silicon-based micro light emitting diode ML;

[0111] The energy storage circuit includes a storage capacitor C1;

[0112] A first end of the storage capacitor C1 is electrically connected to the first node A, and a second end of the storage capacitor C1 is electrically connected to the common electrode voltage terminal VCOM;

[0113] The cathode of the silicon-based micro light emitting diode ML is electrically connected to the low voltage terminal VSS.

[0114] In at least one embodiment of the pixel circuit shown in FIG. 2 , M1 is a p-type transistor, M2 is an n-type transistor, M3 is a p-type transistor, M4 is an n-type transistor, and M0 is a p-type transistor.

[0115] In at least one embodiment of the pixel circuit shown in FIG. 2 of the present disclosure, when in operation, a display cycle may include N display time periods; N may be an integer greater than 1; and n may be a positive integer less than or equal to N.

[0116] The nth display period may include an nth writing phase and an nth light emitting phase;

[0117] In the nth write phase, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, the data line DL provides the nth data voltage Vdn, and Vdn is written into C1; EM provides a high voltage signal, M3 is disconnected, M4 is turned on, to control the connection between VDD1 and B, and M0 is turned off;

[0118] In the nth light-emitting phase, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and GM2 are disconnected, EM provides a low voltage signal, M3 is turned on, M4 is turned off, and A and B are connected to write Vdn into the second node B;

[0119] When Vdn is a low voltage signal, M0 is turned on and drives ML to emit light; when Vdn is a high voltage signal, M0 is turned off and ML does not emit light.

[0120] When at least one embodiment of the pixel circuit shown in FIG2 is in operation, the difference between the voltage value of the first high voltage signal provided by VDD1 and the voltage value of the second high voltage signal provided by VDD2 is greater than the threshold voltage of M0, so that when VDD1 is connected to B, M0 is turned off.

[0121] In at least one embodiment of the pixel circuit shown in FIG2 , the voltage value of the first high voltage signal provided by VDD1 may be greater than or equal to 2V and less than or equal to 8V, the voltage value of the second high voltage signal provided by VDD2 may be greater than or equal to 2V and less than or equal to 8V, the voltage value of the low voltage signal provided by VSS may be greater than or equal to -5V and less than or equal to 0V, and the voltage value of Vdn may be greater than or equal to 0V and less than or equal to 8V, but the present invention is not limited thereto.

[0122] As shown in FIG3 , when at least one embodiment of the pixel circuit shown in FIG2 is in operation, when N is equal to 3, the display cycle may include a first display time period S1 , a second display time period S2 , and a third display time period S3 , which are set in sequence;

[0123] The first display period S1 includes a first writing stage S11 and a first light-emitting stage S12, the second display period S2 includes a second writing stage S21 and a second light-emitting stage S22, and the third display period S3 includes a third writing stage S31 and a third light-emitting stage S32;

[0124] In the first writing phase S11, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, DL provides the first data voltage Vd1 to C1, EM provides a high voltage signal, M3 is turned off, M4 is turned on, to control the connection between VDD1 and B, and M0 is disconnected;

[0125] In the first light-emitting stage S12, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and M2 are turned off, EM provides a low voltage signal, M3 is turned on, M4 is turned off, and A and B are connected to write Vd1 to the second node B. When Vd1 is a high voltage signal, M0 is turned off and ML does not emit light; when Vd1 is a low voltage signal, M0 is turned on to drive ML to emit light;

[0126] In the second writing phase S21, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, DL provides a second data voltage Vd2 to C1, EM provides a high voltage signal, M3 is turned off, M4 is turned on, to control the connection between VDD1 and B, and M0 is disconnected;

[0127] In the second light-emitting stage S22, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and M2 are turned off, EM provides a low voltage signal, M3 is turned on, M4 is turned off, and A and B are connected to write Vd2 to the second node B. When Vd2 is a high voltage signal, M0 is turned off and ML does not emit light; when Vd2 is a low voltage signal, M0 is turned on to drive ML to emit light;

[0128] In the third writing phase S31, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, DL provides a third data voltage Vd3 to C1, EM provides a high voltage signal, M3 is turned off, M4 is turned on, to control the connection between VDD1 and B, and M0 is disconnected;

[0129] In the third light-emitting stage S32, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and M2 are turned off, EM provides a low voltage signal, M3 is turned on, M4 is turned off, A and B are connected to write Vd3 to the second node B. When Vd3 is a high voltage signal, M0 is turned off and ML does not emit light; when Vd3 is a low voltage signal, M0 is turned on to drive ML to emit light.

[0130] As shown in FIG4 , based on at least one embodiment of the pixel circuit shown in FIG1 ,

[0131] The data writing circuit includes a first transistor M1 and a second transistor M2; the writing control terminal includes a first writing control terminal GLP and a second writing control terminal GLN;

[0132] The gate of the first transistor M1 is electrically connected to the first write control terminal GLP, the source of the first transistor M1 is electrically connected to the data line DL, and the drain of the first transistor M1 is electrically connected to the first node A;

[0133] The gate of the second transistor M2 is electrically connected to the second write control terminal GLN, the source of the second transistor M2 is electrically connected to the data line DL, and the drain of the second transistor M2 is electrically connected to the first node A;

[0134] The first control circuit includes a third transistor M3, and the second control circuit includes a fourth transistor M4;

[0135] The gate of the third transistor M3 is electrically connected to the light emitting control terminal EM, the source of the third transistor M3 is electrically connected to the first node A, and the drain of the third transistor M3 is electrically connected to the second node B;

[0136] The gate of the fourth transistor M4 is electrically connected to the light emitting control terminal EM, the source of the fourth transistor M4 is electrically connected to the second low voltage terminal VSS2, and the drain of the fourth transistor M4 is electrically connected to the second node B;

[0137] The driving circuit includes a driving transistor M0; the light emitting element is a silicon-based micro light emitting diode ML;

[0138] The gate of the driving transistor M0 is electrically connected to the second node B, the source of the driving transistor M0 is electrically connected to the second high voltage terminal VDD2, and the drain of the driving transistor M0 is electrically connected to the anode of the silicon-based micro light emitting diode ML;

[0139] The energy storage circuit includes a storage capacitor C1;

[0140] A first end of the storage capacitor C1 is electrically connected to the first node A, and a second end of the storage capacitor C1 is electrically connected to the common electrode voltage terminal VCOM;

[0141] The cathode of the silicon-based micro light emitting diode ML is electrically connected to the first low voltage terminal VSS1.

[0142] In at least one embodiment of the pixel circuit shown in FIG. 4 , M1 is a p-type transistor, M2 is an n-type transistor, M3 is a p-type transistor, M4 is an n-type transistor, and M0 is an n-type transistor.

[0143] In at least one embodiment of the pixel circuit shown in FIG4 of the present disclosure, when in operation, a display cycle may include N display time periods; N may be an integer greater than 1; and n may be a positive integer less than or equal to N.

[0144] The nth display period may include an nth writing phase and an nth light emitting phase;

[0145] In the nth write phase, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, the data line DL provides the nth data voltage Vdn, and Vdn is written into C1; EM provides a high voltage signal, M3 is disconnected, M4 is turned on, to control the connection between VSS2 and B, and M0 is turned off;

[0146] In the nth light-emitting phase, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and GM2 are disconnected, EM provides a low voltage signal, M3 is turned on, M4 is turned off, and A and B are connected to write Vdn into the second node B;

[0147] When Vdn is a high voltage signal, M0 is turned on and drives ML to emit light; when Vdn is a low voltage signal, M0 is turned off and ML does not emit light.

[0148] When at least one embodiment of the pixel circuit shown in Figure 4 is working, the difference between the voltage value of the second low voltage signal provided by VSS2 and the voltage value of the second high voltage signal provided by VDD2 is less than the threshold voltage of M0, so that when VSS2 and B are connected, M0 is turned off.

[0149] In at least one embodiment of the pixel circuit shown in FIG4 , the voltage value of the second low voltage signal provided by VSS2 may be greater than or equal to 0V and less than or equal to 2V, the voltage value of the second high voltage signal provided by VDD2 may be greater than or equal to 2V and less than or equal to 8V, the voltage value of the first low voltage signal provided by VSS1 may be greater than or equal to -5V and less than or equal to 0V, and the voltage value of Vdn may be greater than or equal to 0V and less than or equal to 8V, but are not limited thereto.

[0150] As shown in FIG5 , based on at least one embodiment of the pixel circuit shown in FIG1 ,

[0151] The data writing circuit includes a first transistor M1 and a second transistor M2; the writing control terminal includes a first writing control terminal GLP and a second writing control terminal GLN;

[0152] The gate of the first transistor M1 is electrically connected to the first write control terminal GLP, the source of the first transistor M1 is electrically connected to the data line DL, and the drain of the first transistor M1 is electrically connected to the first node A;

[0153] The gate of the second transistor M2 is electrically connected to the second write control terminal GLN, the source of the second transistor M2 is electrically connected to the data line DL, and the drain of the second transistor M2 is electrically connected to the first node A;

[0154] The first control circuit includes a third transistor M3, and the second control circuit includes a fourth transistor M4;

[0155] The gate of the third transistor M3 is electrically connected to the light emitting control terminal EM, the source of the third transistor M3 is electrically connected to the first node A, and the drain of the third transistor M3 is electrically connected to the second node B;

[0156] The gate of the fourth transistor M4 is electrically connected to the light emitting control terminal EM, the source of the fourth transistor M4 is electrically connected to the second low voltage terminal VSS2, and the drain of the fourth transistor M4 is electrically connected to the second node B;

[0157] The driving circuit includes a driving transistor M0; the light emitting element is a silicon-based micro light emitting diode ML;

[0158] The gate of the driving transistor M0 is electrically connected to the second node B, the source of the driving transistor M0 is electrically connected to the second high voltage terminal VDD2, and the drain of the driving transistor M0 is electrically connected to the anode of the silicon-based micro light emitting diode ML;

[0159] The energy storage circuit includes a storage capacitor C1;

[0160] A first end of the storage capacitor C1 is electrically connected to the first node A, and a second end of the storage capacitor C1 is electrically connected to the common electrode voltage terminal VCOM;

[0161] The cathode of the silicon-based micro light emitting diode ML is electrically connected to the first low voltage terminal VSS1.

[0162] In at least one embodiment of the pixel circuit shown in FIG. 5 , M1 is a p-type transistor, M2 is an n-type transistor, M3 is an n-type transistor, M4 is a p-type transistor, and M0 is an n-type transistor.

[0163] In at least one embodiment of the pixel circuit shown in FIG5 of the present disclosure, when in operation, a display cycle may include N display time periods; N may be an integer greater than 1; n may be a positive integer less than or equal to N;

[0164] The nth display period may include an nth writing phase and an nth light emitting phase;

[0165] In the nth write phase, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, the data line DL provides the nth data voltage Vdn, and Vdn is written into C1; EM provides a low voltage signal, M3 is disconnected, M4 is turned on, to control the connection between VSS2 and B, and M0 is turned off;

[0166] In the nth light-emitting phase, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and GM2 are disconnected, EM provides a high voltage signal, M3 is turned on, M4 is turned off, and A and B are connected to write Vdn into the second node B;

[0167] When Vdn is a high voltage signal, M0 is turned on and drives ML to emit light; when Vdn is a low voltage signal, M0 is turned off and ML does not emit light.

[0168] When at least one embodiment of the pixel circuit shown in Figure 5 is working, the difference between the voltage value of the second low voltage signal provided by VSS2 and the voltage value of the second high voltage signal provided by VDD2 is less than the threshold voltage of M0, so that when VSS2 and B are connected, M0 is turned off.

[0169] In at least one embodiment of the pixel circuit shown in FIG5 , the voltage value of the second low voltage signal provided by VSS2 may be greater than or equal to 0V and less than or equal to 2V, the voltage value of the second high voltage signal provided by VDD2 may be greater than or equal to 0V and less than or equal to 8V, the voltage value of the first low voltage signal provided by VSS1 may be greater than or equal to -5V and less than or equal to 0V, and the voltage value of Vdn may be greater than or equal to 0V and less than or equal to 8V, but are not limited thereto.

[0170] As shown in FIG6 , when at least one embodiment of the pixel circuit shown in FIG5 is in operation, when N is equal to 3, the display cycle may include a first display time period S1 , a second display time period S2 , and a third display time period S3 that are sequentially set;

[0171] The first display period S1 includes a first writing stage S11 and a first light-emitting stage S12, the second display period S2 includes a second writing stage S21 and a second light-emitting stage S22, and the third display period S3 includes a third writing stage S31 and a third light-emitting stage S32;

[0172] In the first writing phase S11, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, DL provides the first data voltage Vd1 to C1, EM provides a low voltage signal, M3 is turned off, M4 is turned on, to control the connection between VSS2 and B, and M0 is disconnected;

[0173] In the first light-emitting stage S12, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and M2 are turned off, EM provides a high voltage signal, M3 is turned on, M4 is turned off, and A and B are connected to write Vd1 to the second node B. When Vd1 is a low voltage signal, M0 is turned off and ML does not emit light; when Vd1 is a high voltage signal, M0 is turned on to drive ML to emit light;

[0174] In the second writing phase S21, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, DL provides a second data voltage Vd2 to C1, EM provides a low voltage signal, M3 is turned off, M4 is turned on, to control the connection between VDD1 and B, and M0 is disconnected;

[0175] In the second light-emitting stage S22, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and M2 are turned off, EM provides a high voltage signal, M3 is turned on, M4 is turned off, and A and B are connected to write Vd2 to the second node B. When Vd2 is a low voltage signal, M0 is turned off and ML does not emit light; when Vd2 is a high voltage signal, M0 is turned on to drive ML to emit light;

[0176] In the third writing phase S31, GLP provides a low voltage signal, GLN provides a high voltage signal, M1 and M2 are turned on, DL provides a third data voltage Vd3 to C1, EM provides a low voltage signal, M3 is turned off, M4 is turned on, to control the connection between VDD1 and B, and M0 is disconnected;

[0177] In the third light-emitting stage S32, GLP provides a high voltage signal, GLN provides a low voltage signal, M1 and M2 are turned off, EM provides a high voltage signal, M3 is turned on, M4 is turned off, and A and B are connected to write Vd3 to the second node B. When Vd3 is a low voltage signal, M0 is turned off and ML does not emit light; when Vd3 is a high voltage signal, M0 is turned on to drive ML to emit light.

[0178] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned pixel circuit, wherein the display cycle includes N display time periods; N is an integer greater than 1; the nth display time period may include an nth writing phase and an nth light-emitting phase arranged in sequence; n is a positive integer less than or equal to N;

[0179] In the nth write phase, the data write circuit, under the control of the write control signal, writes the nth data voltage provided by the data line into the first node, and the energy storage circuit maintains the potential of the first node; the second control circuit, under the control of the light emitting control signal, controls the connection between the first voltage terminal and the second node, so as to control the drive circuit to be disconnected under the control of the potential of the second node;

[0180] In the nth light-emitting stage, the first control circuit controls the connection between the first node and the second node under the control of the light-emitting control signal to write the nth data voltage into the second node, and the driving circuit controls whether to drive the light-emitting element to emit light according to the nth data voltage.

[0181] In at least one embodiment of the present disclosure, the durations of the N light-emitting phases are different from each other.

[0182] In at least one embodiment of the present disclosure, at least some of the N light-emitting phases have different durations.

[0183] Optionally, the duration of the nth light emitting stage is 2n×t0; or, the duration of the nth light emitting stage is 2n×t0; but not limited thereto;

[0184] Among them, t0 is the basic luminous time.

[0185] The display substrate described in the embodiment of the present disclosure includes a silicon substrate and the above-mentioned pixel circuit disposed on the silicon substrate.

[0186] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0187] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A pixel circuit, comprising a data writing circuit, an energy storage circuit, a first control circuit, a second control circuit, a driving circuit and a light emitting element; The data writing circuit is electrically connected to the writing control terminal, the data line and the first node respectively, and is used to write the data voltage provided by the data line into the first node under the control of the writing control signal provided by the writing control terminal; The energy storage circuit is electrically connected to the first node and is used to maintain the potential of the first node; The first control circuit is electrically connected to the light-emitting control terminal, the first node and the second node respectively, and is used to control the connection or disconnection between the first node and the second node under the control of the light-emitting control signal provided by the light-emitting control terminal; The second control circuit is electrically connected to the light emitting control terminal, the first voltage terminal and the second node respectively, and is used to control the connection or disconnection between the first voltage terminal and the second node under the control of the light emitting control signal; The driving circuit is electrically connected to the second node, the second voltage terminal and the first electrode of the light-emitting element respectively, and is used to generate a driving current flowing from the second voltage terminal to the first electrode of the light-emitting element under the control of the potential of the second node; The second electrode of the light emitting element is electrically connected to the third voltage terminal.

2. The pixel circuit according to claim 1, wherein: The data writing circuit includes a first transistor and a second transistor; the writing control terminal includes a first writing control terminal and a second writing control terminal; The gate of the first transistor is electrically connected to the first write control terminal, the first electrode of the first transistor is electrically connected to the data line, and the second electrode of the first transistor is electrically connected to the first node; A gate of the second transistor is electrically connected to the second write control terminal, a first electrode of the second transistor is electrically connected to the data line, and a second electrode of the second transistor is electrically connected to the first node.

3. The pixel circuit according to claim 2, wherein: The first transistor is a p-type transistor, and the second transistor is an n-type transistor; or, the first transistor is an n-type transistor, and the second transistor is a p-type transistor.

4. The pixel circuit according to claim 1, wherein: The first control circuit includes a third transistor, and the second control circuit includes a fourth transistor; The gate of the third transistor is electrically connected to the light emitting control terminal, the first electrode of the third transistor is electrically connected to the first node, and the second electrode of the third transistor is electrically connected to the second node; A gate of the fourth transistor is electrically connected to the light emitting control terminal, a first electrode of the fourth transistor is electrically connected to the first voltage terminal, and a second electrode of the fourth transistor is electrically connected to the second node.

5. The pixel circuit according to claim 4, wherein: The third transistor is a p-type transistor, and the fourth transistor is an n-type transistor; or, the third transistor is an n-type transistor, and the fourth transistor is a p-type transistor.

6. The pixel circuit according to claim 1, wherein: The energy storage circuit includes a storage capacitor; The first end of the storage capacitor is electrically connected to the first node, and the second end of the storage capacitor is electrically connected to a DC voltage end.

7. The pixel circuit according to any one of claims 1 to 6, wherein: The driving circuit includes a driving transistor; The gate of the driving transistor is electrically connected to the second node, the first electrode of the driving transistor is electrically connected to the second voltage terminal, and the second electrode of the driving transistor is electrically connected to the first electrode of the light emitting element.

8. The pixel circuit according to claim 7, wherein: The driving transistor is a p-type transistor, and the first voltage terminal is a first high voltage terminal; or, The driving transistor is an n-type transistor, and the first voltage terminal is a first low voltage terminal.

9. The pixel circuit according to any one of claims 1 to 6, wherein: The light emitting element is a silicon-based micro light emitting diode, and the pixel circuit is arranged on a silicon substrate.

10. A driving method, applied to the pixel circuit according to any one of claims 1 to 9, wherein the display cycle includes N display time periods; N is an integer greater than 1; the nth display time period may include an nth writing phase and an nth light emitting phase which are arranged successively; n is a positive integer less than or equal to N; In the nth writing phase, the data writing circuit writes the nth data voltage provided by the data line into the first node under the control of the writing control signal, and the energy storage circuit maintains the potential of the first node; second The control circuit controls the connection between the first voltage terminal and the second node under the control of the light emitting control signal, so as to control the drive circuit to be disconnected under the control of the potential of the second node; In the nth light-emitting stage, the first control circuit controls the connection between the first node and the second node under the control of the light-emitting control signal to write the nth data voltage into the second node, and the driving circuit controls whether to drive the light-emitting element to emit light according to the nth data voltage.

11. The driving method according to claim 10, wherein: The durations of the N lighting phases are different from each other.

12. The driving method according to claim 10, wherein: At least some of the N light-emitting phases have different durations.

13. The driving method according to claim 10, wherein: The duration of the nth light-emitting stage is 2n×t0; or, the duration of the nth light-emitting stage is 2n×t0; wherein t0 is the basic light-emitting time.

14. A display substrate comprising a silicon substrate, and a pixel circuit according to any one of claims 1 to 9 disposed on the silicon substrate.

15. A display device comprising the display substrate according to claim 14.

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