Pixel circuit, display device and driving method

Abstract

The invention provides a pixel circuit, a display device and a driving method. The pixel circuit includes: a light emitting device; the driving transistor (T0) generates a driving current for driving the light-emitting device to emit light according to the data voltage signal; the first compensation circuit (10) responds to a signal of a first control signal end (CS1), and provides a first reference signal of a first reference signal end (VREF1) to a first pole of the driving transistor (T0); the second compensation circuit (20) responds to signals of a second control signal end (CS2) and a third control signal end (CS3), and provides threshold voltage of the driving transistor (T0) and a first reference signal input into a first electrode of the driving transistor (T0) to a grid electrode of the driving transistor (T0); the data write-in circuit (30) responds to a signal of a fourth control signal end (CS4) and provides a data voltage signal of a data signal end (DA) to the first node (N1); the coupling control circuit (40) is used for coupling a data voltage signal of the first node (N1) to a grid electrode of the driving transistor (T0); the light-emitting control circuit (50) responds to a signal of a light-emitting control signal end (EM) and drives the light-emitting device (L) to emit light.

Description

Pixel circuit, display device and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a display device, and a driving method. Background Art

[0002] Organic Light Emitting Diode (OLED) displays are a hot topic in today's flat-panel display research. Compared to liquid crystal displays (LCDs), OLED displays offer advantages such as low energy consumption, low production costs, self-luminescence, wide viewing angles, and fast response times. The pixel circuits used to control the light-emitting devices are a core technology of OLED displays and hold significant research significance. However, existing OLED display pixel circuits often include a large number of transistors, leading to complex manufacturing processes, increased production costs, and a large pixel circuit footprint, hindering the ability to achieve high resolutions.

[0003] Summary of the Invention

[0004] The pixel circuit provided by the embodiment of the present disclosure includes:

[0005] Light-emitting devices;

[0006] a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal;

[0007] a first compensation circuit coupled to the driving transistor and configured to provide a first reference signal from a first reference signal terminal to a first electrode of the driving transistor in response to a signal from a first control signal terminal;

[0008] a second compensation circuit coupled to the driving transistor and configured to provide a threshold voltage of the driving transistor and a first reference signal input to a first electrode of the driving transistor to a gate of the driving transistor in response to signals at the second control signal terminal and a third control signal terminal;

[0009] a data writing circuit coupled to the first node and configured to provide the data voltage signal of the data signal terminal to the first node in response to a signal of the fourth control signal terminal;

[0010] a coupling control circuit coupled to the first node and the driving transistor, and configured to couple the data voltage signal of the first node to the gate of the driving transistor;

[0011] The light emitting control circuit is coupled to the light emitting device and the driving transistor, and is configured to connect the first electrode of the driving transistor to the first power supply terminal and the second electrode of the driving transistor to the light emitting device in response to the signal of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

[0012] In some possible implementations, the first compensation circuit includes: a first transistor;

[0013] A gate of the first transistor is coupled to the first control signal terminal, a first electrode of the first transistor is coupled to the first electrode of the driving transistor, and a second electrode of the first transistor is coupled to the first reference signal terminal.

[0014] In some possible implementations, the second compensation circuit includes: a second transistor and a third transistor;

[0015] The gate of the second transistor is coupled to the second control signal terminal, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the second electrode of the driving transistor;

[0016] The gate of the third transistor is coupled to the third control signal terminal, the first electrode of the third transistor is coupled to the gate of the driving transistor, and the second electrode of the third transistor is coupled to the second node.

[0017] In some possible implementations, the second compensation circuit further includes: a fourth transistor;

[0018] The gate of the fourth transistor is coupled to the fifth control signal terminal, the first electrode of the fourth transistor is coupled to the gate of the driving transistor or the second node, and the second electrode of the fourth transistor is coupled to the first initialization signal terminal.

[0019] In some possible implementations, the fifth control signal terminal and the light-emitting control signal terminal may be the same signal terminal.

[0020] In some possible implementations, the data writing circuit includes: a fifth transistor;

[0021] A gate of the fifth transistor is coupled to the fourth control signal terminal, a first electrode of the fifth transistor is coupled to the data signal terminal, and a second electrode of the fifth transistor is coupled to the first node.

[0022] In some possible implementations, the coupling control circuit includes: a first capacitor;

[0023] A first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the gate of the driving transistor.

[0024] In some possible implementations, the light emitting control circuit includes: a sixth transistor and a seventh transistor;

[0025] The gate of the sixth transistor is coupled to the light emitting control signal terminal, the first electrode of the sixth transistor is coupled to the first power supply terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the driving transistor;

[0026] The gate of the seventh transistor is coupled to the light emitting control signal terminal, the first electrode of the seventh transistor is coupled to the second electrode of the driving transistor, and the second electrode of the seventh transistor is coupled to the light emitting device.

[0027] In some possible implementations, the system further includes: a first reset circuit coupled to the light-emitting device and configured to provide a signal from a second initialization signal terminal to the light-emitting device in response to a signal from a sixth control signal terminal.

[0028] In some possible implementations, the first reset circuit includes: an eighth transistor;

[0029] A gate of the eighth transistor is coupled to the sixth control signal terminal, a first electrode of the eighth transistor is coupled to the light emitting device, and a second electrode of the eighth transistor is coupled to the second initialization signal terminal.

[0030] In some possible implementations, the system further includes: a voltage stabilizing circuit coupled to the first node and configured to stabilize the voltage of the first node.

[0031] In some possible implementations, the voltage stabilization circuit includes: a second capacitor;

[0032] A first electrode of the second capacitor is coupled to the first power supply terminal, and a second electrode of the second capacitor is coupled to the first node.

[0033] In some possible implementations, the system further includes: a second reset circuit coupled to the second electrode of the driving transistor, configured to provide a signal from a third initialization signal terminal to the second electrode of the driving transistor in response to a signal from a seventh control signal terminal.

[0034] In some possible implementations, the second reset circuit includes: a ninth transistor;

[0035] A gate of the ninth transistor is coupled to the seventh control signal terminal, a first electrode of the ninth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the ninth transistor is coupled to the third initialization signal terminal.

[0036] In some possible implementations, the system further includes: a third reset circuit coupled to the first node and configured to provide a signal from the second reference signal terminal to the first node in response to a signal from the eighth control signal terminal.

[0037] In some possible implementations, the third reset circuit includes: a tenth transistor;

[0038] A gate of the tenth transistor is coupled to the eighth control signal terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the second reference signal terminal.

[0039] In some possible implementations, the third reset circuit includes: an eleventh transistor and a twelfth transistor;

[0040] The gate of the eleventh transistor is coupled to the eighth control signal terminal, the first electrode of the eleventh transistor is coupled to the first node, and the second electrode of the eleventh transistor is coupled to the third node;

[0041] A gate of the twelfth transistor is coupled to the eighth control signal terminal, a first electrode of the twelfth transistor is coupled to the third node, and a second electrode of the eleventh transistor is coupled to the second reference signal terminal.

[0042] In some possible implementations, the third reset circuit further includes: a thirteenth transistor;

[0043] A gate of the thirteenth transistor is coupled to the ninth control signal terminal, a first electrode of the thirteenth transistor is coupled to the third node, and a second electrode of the thirteenth transistor is coupled to the third reference signal terminal.

[0044] The display device provided by the embodiment of the present disclosure includes the above-mentioned pixel circuit.

[0045] The driving method of the pixel circuit provided in the embodiment of the present disclosure includes:

[0046] In the reset phase, the first compensation circuit provides the first reference signal from the first reference signal terminal to the first electrode of the driving transistor in response to the signal from the first control signal terminal;

[0047] In the threshold compensation stage, the first compensation circuit provides the first reference signal of the first reference signal terminal to the first electrode of the driving transistor in response to the signal of the first control signal terminal; the second compensation circuit provides the threshold voltage of the driving transistor and the first reference signal input to the first electrode of the driving transistor to the gate of the driving transistor in response to the signals of the second control signal terminal and the third control signal terminal;

[0048] In the data writing phase, the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to the signal of the fourth control signal terminal; the coupling control circuit couples the data voltage signal of the first node to the gate of the driving transistor;

[0049] In the light emitting stage, the light emitting control circuit connects the first electrode of the driving transistor to the first power supply terminal and the second electrode of the driving transistor to the light emitting device in response to the signal of the light emitting control signal terminal, thereby driving the light emitting device to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] FIG1 is a schematic diagram of some structures of pixel circuits provided by an embodiment of the present disclosure;

[0051] FIG2 is another schematic diagram of the structure of the pixel circuit provided by the embodiment of the present disclosure;

[0052] FIG3 is a flow chart of a driving method of a pixel circuit provided by an embodiment of the present disclosure;

[0053] FIG4 is a timing diagram of some signals provided by an embodiment of the present disclosure;

[0054] FIG5 is a schematic diagram of some further structures of pixel circuits provided by embodiments of the present disclosure;

[0055] FIG6 is another signal timing diagram provided by an embodiment of the present disclosure;

[0056] FIG7 is a schematic diagram of some further structures of pixel circuits provided by embodiments of the present disclosure;

[0057] FIG8 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0058] FIG9 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0059] FIG10 is a timing diagram of some further signals provided by an embodiment of the present disclosure;

[0060] FIG11 is a schematic diagram of some further structures of pixel circuits provided by an embodiment of the present disclosure;

[0061] FIG12 is a schematic diagram of some further structures of the pixel circuit provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0063] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0064] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0065] The display device provided by the embodiment of the present disclosure may include a display panel. The display panel may include a substrate. The substrate may include a display area and a non-display area (i.e., an area in the substrate except for the area surrounded by the display area). The display area may include a plurality of pixel units arranged in an array. Exemplarily, each pixel unit includes sub-pixels of the same color or sub-pixels of multiple different colors. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that red, green, and blue can be mixed to achieve color display. Alternatively, a pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that red, green, blue, and white can be mixed to achieve color display. Of course, in actual applications, the luminous color of the sub-pixels in the pixel unit can be designed and determined according to the actual application environment, and is not limited here.

[0066] In the disclosed embodiments, each sub-pixel may include a pixel circuit and a light-emitting device coupled to the pixel circuit. The pixel circuit may include a driving transistor to control the light-emitting device to emit light, thereby enabling the display panel to display images. Due to process, aging, and other factors, the threshold voltage Vth of the driving transistor may drift, affecting the generated drive current and resulting in poor display effects. Therefore, the threshold voltage Vth of the driving transistor is compensated. However, the prior art uses the method of compensating the threshold voltage Vth while charging the data, which results in slow compensation and charging speeds, making it unsuitable for high-frequency circuits.

[0067] Based on this, an embodiment of the present disclosure provides a pixel circuit, as shown in FIG1 , comprising:

[0068] Light emitting device L;

[0069] a driving transistor T0 coupled to the light emitting device L and configured to generate a driving current for driving the light emitting device L to emit light according to the data voltage signal;

[0070] The first compensation circuit 10 is coupled to the driving transistor T0 and is configured to provide a first reference signal of the first reference signal terminal VREF1 to a first electrode of the driving transistor T0 in response to a signal of the first control signal terminal CS1;

[0071] The second compensation circuit 20 is coupled to the driving transistor T0 and is configured to provide the threshold voltage Vth of the driving transistor T0 and the first reference signal input to the first electrode of the driving transistor T0 to the gate of the driving transistor T0 in response to the signals of the second control signal terminal CS2 and the third control signal terminal CS3;

[0072] The data writing circuit 30 is coupled to the first node N1 and configured to provide a data voltage signal of the data signal terminal DA to the first node N1 in response to a signal of the fourth control signal terminal CS4;

[0073] The coupling control circuit 40 is coupled to the first node N1 and the driving transistor T0 and is configured to couple the data voltage signal of the first node N1 to the gate of the driving transistor T0;

[0074] The light emitting control circuit 50 is coupled to the light emitting device L and the driving transistor T0, and is configured to connect the first electrode of the driving transistor T0 to the first power supply terminal VDD and the second electrode of the driving transistor T0 to the light emitting device L in response to the signal of the light emitting control signal terminal EM, thereby driving the light emitting device L to emit light.

[0075] The pixel circuit provided by the embodiment of the present disclosure realizes time-sharing compensation of the threshold voltage Vth and data charging through the mutual cooperation of the light-emitting device, the driving transistor, the first compensation circuit, the second compensation circuit, the data writing circuit, the coupling control circuit and the light-emitting control circuit, so that the threshold voltage Vth compensation is no longer restricted, and there is more time for compensation, thereby improving the compensation effect and the display effect at low grayscale.

[0076] Furthermore, by adopting a first compensation circuit to provide the first reference signal of the first reference signal terminal to the first electrode of the driving transistor, and by adopting a second compensation circuit to provide the threshold voltage of the driving transistor and the first reference signal input to the first electrode of the driving transistor to the gate of the driving transistor, the threshold voltage Vth of the driving transistor is compensated, which can further reduce the number of light-emitting control signal terminals required by the light-emitting control circuit, that is, a simple structure and fewer signal lines are adopted to realize driving the light-emitting device to emit light, thereby simplifying the preparation process, reducing production costs and reducing the occupied area, thereby improving the pixel density, and facilitating the realization of higher resolution and improving the display effect.

[0077] For example, as shown in FIG1 , the driving transistor T0 can be configured as a P-type transistor; wherein the first electrode of the driving transistor T0 can be its source electrode, the second electrode of the driving transistor T0 can be its drain electrode, and when the driving transistor T0 is in a saturated state, current flows from the source electrode of the driving transistor T0 to the drain electrode thereof. Of course, the driving transistor T0 can also be configured as an N-type transistor, which is not limited here.

[0078] Exemplarily, as shown in FIG1 , the second electrode of the light-emitting device L is coupled to the second power supply terminal VSS; exemplarily, the light-emitting device L may be an electroluminescent diode. For example, the light-emitting device L may include at least one of: an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro LED), and a mini light-emitting diode (Mini LED). Exemplarily, the light-emitting device L may include a stacked anode, a light-emitting layer, and a cathode. Furthermore, the light-emitting layer may also include film layers such as a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer. Of course, in actual applications, the specific structure of the light-emitting device L can be determined according to the needs of the actual application and is not limited here.

[0079] In the embodiment of the present disclosure, as shown in Figure 2, the first compensation circuit 10 includes: a first transistor T1; wherein the gate of the first transistor T1 is coupled to the first control signal terminal CS1, the first electrode of the first transistor T1 is coupled to the first electrode of the driving transistor T0, and the second electrode of the first transistor T1 is coupled to the first reference signal terminal VREF1.

[0080] For example, the first transistor T1 can be turned on under the control of the active level of the first control signal transmitted on the first control signal terminal CS1, and can be turned off under the control of the inactive level of the first control signal. For example, the first transistor T1 can be configured as an N-type transistor, in which case the active level of the first control signal is a high level, and the inactive level of the first control signal is a low level. Alternatively, the first transistor T1 can be configured as a P-type transistor, in which case the active level of the first control signal is a low level, and the inactive level of the first control signal is a high level.

[0081] In the embodiment of the present disclosure, as shown in Figure 2, the second compensation circuit 20 includes: a second transistor T2 and a third transistor T3; wherein the gate of the second transistor T2 is coupled to the second control signal terminal CS2, the first electrode of the second transistor T2 is coupled to the second node N2, and the second electrode of the second transistor T2 is coupled to the second electrode of the driving transistor T0; the gate of the third transistor T3 is coupled to the third control signal terminal CS3, the first electrode of the third transistor T3 is coupled to the gate of the driving transistor T0, and the second electrode of the third transistor T3 is coupled to the second node N2.

[0082] For example, the second transistor T2 can be turned on under the control of the active level of the second control signal transmitted on the second control signal terminal CS2, and can be turned off under the control of the inactive level of the second control signal. For example, the second transistor T2 can be set as an N-type transistor, in which case the active level of the second control signal is a high level, and the inactive level of the second control signal is a low level. Alternatively, the second transistor T2 can be set as a P-type transistor, in which case the active level of the second control signal is a low level, and the inactive level of the second control signal is a high level.

[0083] For example, the third transistor T3 can be turned on under the control of the active level of the third control signal transmitted on the third control signal terminal CS3, and can be turned off under the control of the inactive level of the third control signal. For example, the third transistor T3 can be configured as an N-type transistor, in which case the active level of the third control signal is a high level, and the inactive level of the third control signal is a low level. Alternatively, the third transistor T3 can be configured as a P-type transistor, in which case the active level of the third control signal is a low level, and the inactive level of the third control signal is a high level.

[0084] In the embodiment of the present disclosure, as shown in Figure 2, the second compensation circuit 20 further includes: a fourth transistor T4; wherein the gate of the fourth transistor T4 is coupled to the fifth control signal terminal CS5, the first electrode of the fourth transistor T4 is coupled to the second node N2, and the second electrode of the fourth transistor T4 is coupled to the first initialization signal terminal VINIT1.

[0085] For example, the fourth transistor T4 can be turned on under the control of the active level of the fifth control signal transmitted on the fifth control signal terminal CS5, and can be turned off under the control of the inactive level of the fifth control signal. For example, the fourth transistor T4 can be set as an N-type transistor, in which case the active level of the fifth control signal is a high level, and the inactive level of the fifth control signal is a low level. Alternatively, the fourth transistor T4 can be set as a P-type transistor, in which case the active level of the fifth control signal is a low level, and the inactive level of the fifth control signal is a high level.

[0086] In the embodiment of the present disclosure, as shown in Figure 2, the data writing circuit 30 includes: a fifth transistor T5; wherein the gate of the fifth transistor T5 is coupled to the fourth control signal terminal CS4, the first electrode of the fifth transistor T5 is coupled to the data signal terminal DA, and the second electrode of the fifth transistor T5 is coupled to the first node N1.

[0087] For example, the fifth transistor T5 can be turned on under the control of the active level of the fourth control signal transmitted on the fourth control signal terminal CS4, and can be turned off under the control of the inactive level of the fourth control signal. For example, the fifth transistor T5 can be set as an N-type transistor, in which case the active level of the fourth control signal is a high level, and the inactive level of the fourth control signal is a low level. Alternatively, the fifth transistor T5 can be set as a P-type transistor, in which case the active level of the fourth control signal is a low level, and the inactive level of the fourth control signal is a high level.

[0088] In the embodiment of the present disclosure, as shown in FIG2 , the coupling control circuit 40 includes: a first capacitor C1 ; wherein a first electrode of the first capacitor C1 is coupled to the first node N1 , and a second electrode of the first capacitor C1 is coupled to the gate of the driving transistor T0 .

[0089] In the embodiment of the present disclosure, as shown in Figure 2, the light-emitting control circuit 50 includes: a sixth transistor T6 and a seventh transistor T7; wherein, the gate of the sixth transistor T6 is coupled to the light-emitting control signal terminal EM, the first electrode of the sixth transistor T6 is coupled to the first power supply terminal VDD, and the second electrode of the sixth transistor T6 is coupled to the first electrode of the driving transistor T0; the gate of the seventh transistor T7 is coupled to the light-emitting control signal terminal EM, the first electrode of the seventh transistor T7 is coupled to the second electrode of the driving transistor T0, and the second electrode of the seventh transistor T7 is coupled to the light-emitting device L.

[0090] For example, the sixth transistor T6 can be turned on under the control of the active level of the light-emitting control signal transmitted on the first light-emitting control signal terminal EM, and can be turned off under the control of the inactive level of the light-emitting control signal. For example, the sixth transistor T6 can be configured as an N-type transistor, in which case the active level of the light-emitting control signal is a high level, and the inactive level of the light-emitting control signal is a low level. Alternatively, the sixth transistor T6 can be configured as a P-type transistor, in which case the active level of the light-emitting control signal is a low level, and the inactive level of the light-emitting control signal is a high level.

[0091] For example, the seventh transistor T7 can be turned on under the control of the active level of the light-emitting control signal transmitted on the first light-emitting control signal terminal EM, and can be turned off under the control of the inactive level of the light-emitting control signal. For example, the seventh transistor T7 can be configured as an N-type transistor, in which case the active level of the light-emitting control signal is a high level, and the inactive level of the light-emitting control signal is a low level. Alternatively, the seventh transistor T7 can be configured as a P-type transistor, in which case the active level of the light-emitting control signal is a low level, and the inactive level of the light-emitting control signal is a high level.

[0092] In the embodiment of the present disclosure, as shown in FIG2 , the first reset circuit 60 is further included, coupled to the light emitting device L and configured to provide the signal of the second initialization signal terminal VINIT2 to the light emitting device L in response to the signal of the sixth control signal terminal CS6 .

[0093] In the embodiment of the present disclosure, as shown in Figure 2, the first reset circuit 60 includes: an eighth transistor T8; wherein the gate of the eighth transistor T8 is coupled to the sixth control signal terminal CS6, the first electrode of the eighth transistor T8 is coupled to the light-emitting device L, and the second electrode of the eighth transistor T8 is coupled to the second initialization signal terminal VINIT2.

[0094] For example, the eighth transistor T8 can be turned on under the control of the active level of the sixth control signal transmitted on the sixth control signal terminal CS6, and can be turned off under the control of the inactive level of the sixth control signal. For example, the eighth transistor T8 can be set as an N-type transistor, in which case the active level of the sixth control signal is a high level, and the inactive level of the sixth control signal is a low level. Alternatively, the eighth transistor T8 can be set as a P-type transistor, in which case the active level of the sixth control signal is a low level, and the inactive level of the sixth control signal is a high level.

[0095] In the embodiment of the present disclosure, as shown in FIG. 2 , the device further includes a voltage stabilizing circuit 70 coupled to the first node N1 and configured to stabilize the voltage of the first node N1 .

[0096] In the embodiment of the present disclosure, as shown in FIG2 , the voltage stabilizing circuit 70 includes: a second capacitor C2 ; wherein a first electrode of the second capacitor C2 is coupled to the first power supply terminal VDD, and a second electrode of the second capacitor C2 is coupled to the first node N1 .

[0097] In the embodiment of the present disclosure, as shown in FIG. 2 , the third reset circuit 90 is further included, coupled to the first node N1 and configured to provide the signal of the second reference signal terminal VREF2 to the first node N1 in response to the signal of the eighth control signal terminal CS8 .

[0098] In the embodiment of the present disclosure, as shown in Figure 2, the third reset circuit 90 includes: an eleventh transistor T11 and a twelfth transistor T12; wherein, the gate of the eleventh transistor T11 is coupled to the eighth control signal terminal CS8, the first electrode of the eleventh transistor T11 is coupled to the first node N1, and the second electrode of the eleventh transistor T11 is coupled to the third node N3; the gate of the twelfth transistor T12 is coupled to the eighth control signal terminal CS8, the first electrode of the twelfth transistor T12 is coupled to the third node N3, and the second electrode of the eleventh transistor T11 is coupled to the second reference signal terminal VREF2.

[0099] For example, the eleventh transistor T11 can be turned on under the control of the active level of the eighth control signal transmitted on the eighth control signal terminal CS8, and can be turned off under the control of the inactive level of the eighth control signal. For example, the eleventh transistor T11 can be set as an N-type transistor, in which case the active level of the eighth control signal is a high level, and the inactive level of the eighth control signal is a low level. Alternatively, the eleventh transistor T11 can be set as a P-type transistor, in which case the active level of the eighth control signal is a low level, and the inactive level of the eighth control signal is a high level.

[0100] For example, the twelfth transistor T12 can be turned on under the control of the active level of the eighth control signal transmitted on the eighth control signal terminal CS8, and can be turned off under the control of the inactive level of the eighth control signal. For example, the twelfth transistor T12 can be set as an N-type transistor, then the active level of the eighth control signal is a high level, and the inactive level of the eighth control signal is a low level. Alternatively, the twelfth transistor T12 can be set as a P-type transistor, then the active level of the eighth control signal is a low level, and the inactive level of the eighth control signal is a high level.

[0101] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0102] Generally, transistors using low-temperature polysilicon (LTPS) as active layers have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, thereby achieving high mobility in the pixel circuit, and allowing it to be made thinner and smaller, with lower power consumption.

[0103] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, to reduce leakage current, in some embodiments of the present disclosure, the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0104] For example, all transistors can be set as LTPS transistors. Alternatively, all transistors can be set as oxide transistors. Alternatively, some transistors can be set as oxide transistors, and the remaining transistors can be set as LTPS transistors. By combining the two processes for preparing LTPS transistors and oxide transistors, an LTPO pixel circuit of low-temperature polysilicon oxide can be prepared, which can reduce the leakage current of the gate of the driving transistor T0 and reduce the power consumption. Thus, the pixel circuit is applied to the display panel, and when the display panel reduces the refresh frequency for display, the uniformity of the display can be guaranteed.

[0105] For example, the first power supply terminal VDD can be configured to load a constant first power supply voltage Vdd, and the first power supply voltage Vdd is generally a positive value, for example, the first power supply voltage Vdd includes 4.6, etc. Furthermore, the second power supply terminal VSS can be loaded with a constant second power supply voltage Vss, and the second power supply voltage Vss is generally a ground voltage or a negative value, for example, the second power supply voltage Vss includes -5, etc. In actual applications, the specific values ​​of the first power supply voltage Vdd and the second power supply voltage Vss can be designed and determined according to the actual application environment and are not limited here.

[0106] In an embodiment of the present disclosure, as shown in FIG3 , a driving method for driving a pixel circuit is provided in an embodiment of the present disclosure, which may include the following steps:

[0107] S100, in a reset phase, the first compensation circuit provides a first reference signal from a first reference signal terminal to a first electrode of the driving transistor in response to a signal from a first control signal terminal;

[0108] S200, in a threshold compensation stage, the first compensation circuit provides a first reference signal from the first reference signal terminal to the first electrode of the driving transistor in response to a signal from the first control signal terminal; the second compensation circuit provides a threshold voltage of the driving transistor and the first reference signal input to the first electrode of the driving transistor to the gate of the driving transistor in response to signals from the second control signal terminal and the third control signal terminal;

[0109] S300, data writing stage, the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to the signal of the fourth control signal terminal; the coupling control circuit couples the data voltage signal of the first node to the gate of the driving transistor;

[0110] S400, light emitting stage, the light emitting control circuit connects the first electrode of the driving transistor to the first power supply terminal and the second electrode of the driving transistor to the light emitting device in response to the signal of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

[0111] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG. 2 as an example and combining it with the signal timing diagram shown in FIG. 4 .

[0112] As shown in Figure 4, em represents the light-emitting signal of the light-emitting control signal terminal EM, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs3 represents the third control signal of the third control signal terminal CS3, cs4 represents the fourth control signal of the fourth control signal terminal CS4, cs5 represents the fifth control signal of the fifth control signal terminal CS5, cs6 represents the sixth control signal of the sixth control signal terminal CS6, cs8 represents the eighth control signal of the eighth control signal terminal CS8, and da represents the data voltage signal of the data signal terminal DA.

[0113] In the reset phase F1, the first transistor T1 is turned on by the low level of the first control signal cs1, the second transistor T2 is turned off by the high level of the second control signal cs2, the third transistor T3 is turned on by the low level of the third control signal cs3, the fourth transistor T4 is turned on by the low level of the fifth control signal cs5, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the light-emitting signal em, the seventh transistor T7 is turned off by the high level of the light-emitting signal em, the eighth transistor T8 is turned on by the low level of the sixth control signal cs6, the eleventh transistor T11 is turned off by the high level of the eighth control signal cs8, and the twelfth transistor T12 is turned off by the high level of the eighth control signal cs8. The turned-on first transistor T1 provides the first reference signal at the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs at the first electrode of the driving transistor T0 is Vref1. The conductive fourth transistor T4 provides the first initialization signal from the first initialization signal terminal VINIT1 to the second node N2, resulting in a voltage VN2 at the second node N2 of Vinit1. The conductive third transistor T3 provides the first initialization signal from the second node N2 to the gate of the driving transistor T0, resulting in a voltage Vg at the gate of the driving transistor T0 of Vinit1. The conductive eighth transistor T8 provides the second initialization signal from the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, resulting in a voltage VL at the anode of the light-emitting device L of Vinit2. Vinit1 represents the voltage of the first initialization signal, Vinit2 represents the voltage of the second initialization signal, and Vref1 represents the voltage of the first reference signal.

[0114] In the threshold compensation phase F2, the first transistor T1 is turned on by the low level of the first control signal cs1, the second transistor T2 is turned on by the low level of the second control signal cs2, the third transistor T3 is turned on by the low level of the third control signal cs3, the fourth transistor T4 is turned off by the high level of the fifth control signal cs5, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the emission signal em, the seventh transistor T7 is turned off by the high level of the emission signal em, the eighth transistor T8 is turned on by the low level of the sixth control signal cs6, the eleventh transistor T11 is turned on by the low level of the eighth control signal cs8, and the twelfth transistor T12 is turned on by the low level of the eighth control signal cs8. The turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs at the first electrode of the driving transistor T0 is Vref1. The conductive second transistor T2 electrically connects the second electrode of the driving transistor T0 to the second node N2, and the conductive third transistor T3 electrically connects the second node N2 to the gate of the driving transistor T0. Since the conductive second transistor T2 and the conductive third transistor T3 can form a diode connection for the driving transistor T0, the first reference signal input to the first electrode of the driving transistor T0 can pass through the diode-connected driving transistor T0 and be input to the gate of the driving transistor T0, thereby compensating the threshold voltage Vth of the driving transistor T0 so that the gate Vg voltage of the driving transistor T0 is Vref1+Vth. Consequently, the voltage VN2 at the second node N2 and the voltage Vd at the second electrode of the driving transistor T0 are Vref1+Vth. The conductive eighth transistor T8 provides the second initialization signal from the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, resulting in a voltage VL at the anode of the light-emitting device L of Vinit2. The conductive twelfth transistor T12 provides the second reference signal at the second reference signal terminal VREF2 to the third node N3. The conductive eleventh transistor T11 provides the second reference signal at the third node N3 to the first node N1. The voltage VN1 at the first node N1 is Vref2. The second capacitor C2 stabilizes the voltage at the first node N1. Vref2 represents the voltage of the second reference signal, and Vth represents the threshold voltage of the driving transistor T0.

[0115] During the data writing phase F3, the first transistor T1 is turned off by the high level of the first control signal cs1, the second transistor T2 is turned off by the high level of the second control signal cs2, the third transistor T3 is turned off by the high level of the third control signal cs3, the fourth transistor T4 is turned off by the high level of the fifth control signal cs5, the fifth transistor T5 is turned on by the low level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the emission signal em, the seventh transistor T7 is turned off by the high level of the emission signal em, the eighth transistor T8 is turned off by the high level of the sixth control signal cs6, the eleventh transistor T11 is turned off by the high level of the eighth control signal cs8, and the twelfth transistor T12 is turned off by the high level of the eighth control signal cs8. The turned-on fifth transistor T5 provides the data voltage signal at the data signal terminal DA to the first node N1. The first capacitor C1 couples the data voltage signal at the first node N1 to the gate of the driving transistor T0. The gate voltage Vg of the driving transistor T0 is Vref1+Vth+Vda-Vref2. The second capacitor C2 stabilizes the voltage of the first node N1 , where Vda represents the voltage of the data voltage signal.

[0116] In the light-emitting phase F4, the first transistor T1 is turned off by the high level of the first control signal cs1, the second transistor T2 is turned off by the high level of the second control signal cs2, the third transistor T3 is turned off by the high level of the third control signal cs3, the fourth transistor T4 is turned on by the low level of the fifth control signal cs5, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned on by the low level of the light-emitting signal em, the seventh transistor T7 is turned on by the low level of the light-emitting signal em, the eighth transistor T8 is turned off by the high level of the sixth control signal cs6, the eleventh transistor T11 is turned off by the high level of the eighth control signal cs8, and the twelfth transistor T12 is turned off by the high level of the eighth control signal cs8. The turned-on fourth transistor T4 provides the first initialization signal of the first initialization signal terminal VINIT1 to the second node N2, and the voltage VN2 at the second node N2 is Vinit1. The conductive sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0. The voltage of the first electrode Vs of the driving transistor T0 is Vdd. The conductive seventh transistor T7 connects the second electrode of the driving transistor T0 to the light-emitting device L, driving the light-emitting device L to emit light. Therefore, the driving transistor T0 operates in the saturation region, and the driving current I generated by it can be expressed as: in, μ represents the mobility of the driving transistor T0 , Cox represents the capacitance per unit area of ​​the gate insulating layer of the driving transistor T0 , and W / L represents the channel width-to-length ratio of the driving transistor T0 .

[0117] For example, the first control signal terminal CS1, the third control signal terminal CS3 and the sixth control signal terminal CS6 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0118] For example, the second control signal terminal CS2 and the eighth control signal terminal CS8 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0119] The present disclosure provides some other schematic structural diagrams of pixel circuits, as shown in Figure 5, which are modifications of the implementation in the above embodiment. The following only describes the differences between this embodiment and the above embodiment, and the similarities are not repeated here.

[0120] In the embodiment of the present disclosure, as shown in Figure 5, the second compensation circuit 20 further includes: a fourth transistor T4; wherein the gate of the fourth transistor T4 is coupled to the fifth control signal terminal CS5, the first electrode of the fourth transistor T4 is coupled to the gate of the driving transistor T0, and the second electrode of the fourth transistor T4 is coupled to the first initialization signal terminal VINIT1.

[0121] 5 , the second control signal terminal CS2 and the third control signal terminal CS3 may be the same signal terminal. The gate of the third transistor T3 is coupled to the second control signal terminal CS2. This can reduce the number of signal lines and the space occupied by wiring.

[0122] In the embodiment of the present disclosure, as shown in Figure 5, the third reset circuit 90 includes: a tenth transistor T10; wherein the gate of the tenth transistor T10 is coupled to the eighth control signal terminal CS8, the first electrode of the tenth transistor T10 is coupled to the first node N1, and the second electrode of the tenth transistor T10 is coupled to the second reference signal terminal VREF2.

[0123] For example, the tenth transistor T10 can be turned on under the control of the active level of the eighth control signal transmitted on the eighth control signal terminal CS8, and can be turned off under the control of the inactive level of the eighth control signal. For example, the tenth transistor T10 can be set as an N-type transistor, in which case the active level of the eighth control signal is a high level, and the inactive level of the eighth control signal is a low level. Alternatively, the tenth transistor T10 can be set as a P-type transistor, in which case the active level of the eighth control signal is a low level, and the inactive level of the eighth control signal is a high level.

[0124] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG5 as an example in combination with the signal timing diagram shown in FIG6 .

[0125] As shown in Figure 6, em represents the light-emitting signal of the light-emitting control signal terminal EM, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs4 represents the fourth control signal of the fourth control signal terminal CS4, cs5 represents the fifth control signal of the fifth control signal terminal CS5, cs6 represents the sixth control signal of the sixth control signal terminal CS6, cs8 represents the eighth control signal of the eighth control signal terminal CS8, da represents the data voltage signal of the data signal terminal DA, and vinit2 represents the second initialization signal of the second initialization signal terminal VINIT2.

[0126] During the reset phase F1, the first transistor T1 is turned on by the low level of the first control signal cs1, the second transistor T2 is turned off by the high level of the second control signal cs2, the third transistor T3 is turned off by the high level of the second control signal cs2, the fourth transistor T4 is turned on by the low level of the fifth control signal cs5, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the emission signal em, the seventh transistor T7 is turned off by the high level of the emission signal em, the eighth transistor T8 is turned on by the low level of the sixth control signal cs6, and the tenth transistor T10 is turned on by the low level of the eighth control signal cs8. The turned-on first transistor T1 provides the first reference signal from the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs at the first electrode of the driving transistor T0 is Vref1. The turned-on fourth transistor T4 provides the first initialization signal from the first initialization signal terminal VINIT1 to the gate of the driving transistor T0, and the voltage Vg at the gate of the driving transistor T0 is Vinit1. The turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, and the voltage VL at the anode of the light-emitting device L is Vinit2. The turned-on tenth transistor T10 provides the second reference signal of the second reference signal terminal VREF2 to the first node N1, and the voltage VN1 at the first node N1 is Vref2. The second capacitor C2 stabilizes the voltage of the first node N1.

[0127] In the threshold compensation phase F2, the first transistor T1 is turned on by the low level of the first control signal cs1, the second transistor T2 is turned on by the low level of the second control signal cs2, the third transistor T3 is turned on by the low level of the second control signal cs2, the fourth transistor T4 is turned off by the high level of the fifth control signal cs5, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the emission signal em, the seventh transistor T7 is turned off by the high level of the emission signal em, the eighth transistor T8 is turned on by the low level of the sixth control signal cs6, and the tenth transistor T10 is turned off by the high level of the eighth control signal cs8. The turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs at the first electrode of the driving transistor T0 is Vref1. The conductive second transistor T2 electrically connects the second electrode of the driving transistor T0 to the second node N2. The conductive third transistor T3 electrically connects the second node N2 to the gate of the driving transistor T0. Since the conductive second transistor T2 and third transistor T3 form a diode connection for the driving transistor T0, the first reference signal input to the first electrode of the driving transistor T0 can pass through the diode-connected driving transistor T0 and be input to the gate of the driving transistor T0. This compensates the threshold voltage Vth of the driving transistor T0, so that the gate voltage Vg of the driving transistor T0 is Vref1 + Vth. Consequently, the voltage VN2 at the second node N2 and the voltage Vd at the second electrode of the driving transistor T0 are Vref1 + Vth. The conductive eighth transistor T8 provides the second initialization signal from the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, resulting in a voltage VL at the anode of the light-emitting device L of Vinit2. The second capacitor C2 stabilizes the voltage at the first node N1.

[0128] During the data writing phase F3, the first transistor T1 is turned off by a high level of the first control signal cs1, the second transistor T2 is turned off by a high level of the second control signal cs2, the third transistor T3 is turned off by a high level of the second control signal cs2, the fourth transistor T4 is turned off by a high level of the fifth control signal cs5, the fifth transistor T5 is turned on by a low level of the fourth control signal cs4, the sixth transistor T6 is turned off by a high level of the emission signal em, the seventh transistor T7 is turned off by a high level of the emission signal em, the eighth transistor T8 is turned off by a high level of the sixth control signal cs6, and the tenth transistor T11 is turned off by a high level of the eighth control signal cs8. The turned-on fifth transistor T5 provides the data voltage signal at the data signal terminal DA to the first node N1. The first capacitor C1 couples the data voltage signal at the first node N1 to the gate of the driving transistor T0, resulting in a gate voltage Vg of the driving transistor T0 of Vref1+Vth+Vda-Vref2. The second capacitor C2 stabilizes the voltage at the first node N1.

[0129] During the light-emitting phase F4, the first transistor T1 is turned off under the control of a high level of the first control signal cs1, the second transistor T2 is turned off under the control of a high level of the second control signal cs2, the third transistor T3 is turned off under the control of a high level of the second control signal cs2, the fourth transistor T4 is turned off under the control of a high level of the fifth control signal cs5, the fifth transistor T5 is turned off under the control of a high level of the fourth control signal cs4, the sixth transistor T6 is turned on under the control of a low level of the light-emitting signal em, the seventh transistor T7 is turned on under the control of a low level of the light-emitting signal em, the eighth transistor T8 is turned off under the control of a high level of the sixth control signal cs6, and the tenth transistor T10 is turned off under the control of a high level of the eighth control signal cs8. The turned-on sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0, so that the voltage of the first electrode Vs of the driving transistor T0 is Vdd. The turned-on seventh transistor T7 connects the second electrode of the driving transistor T0 to the light-emitting device L, driving the light-emitting device L to emit light. Therefore, the driving transistor T0 operates in the saturation region, and the driving current I generated by it can be expressed as:

[0130] For example, the first control signal terminal CS1 and the sixth control signal terminal CS6 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0131] For example, the fifth control signal terminal CS5 and the eighth control signal terminal CS8 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0132] The present disclosure provides further schematic diagrams of pixel circuits, as shown in Figure 7, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0133] 7 , the second control signal terminal CS2 and the eighth control signal terminal CS8 may be the same signal terminal. The gate of the tenth transistor T10 is coupled to the eighth control signal terminal CS8. This can reduce the number of signal lines and the space occupied by wiring.

[0134] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG. 7 as an example and combining it with the signal timing diagram shown in FIG. 8 .

[0135] As shown in Figure 8, em represents the light-emitting signal of the light-emitting control signal terminal EM, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs4 represents the fourth control signal of the fourth control signal terminal CS4, cs5 represents the fifth control signal of the fifth control signal terminal CS5, cs6 represents the sixth control signal of the sixth control signal terminal CS6, da represents the data voltage signal of the data signal terminal DA, and vinit2 represents the second initialization signal of the second initialization signal terminal VINIT2.

[0136] During the reset phase F1, the first transistor T1 is turned on by the low level of the first control signal cs1, the second transistor T2 is turned off by the high level of the second control signal cs2, the third transistor T3 is turned off by the high level of the second control signal cs2, the fourth transistor T4 is turned on by the low level of the fifth control signal cs5, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the emission signal em, the seventh transistor T7 is turned off by the high level of the emission signal em, the eighth transistor T8 is turned on by the low level of the sixth control signal cs6, and the tenth transistor T10 is turned off by the high level of the second control signal cs2. The turned-on first transistor T1 provides the first reference signal from the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs at the first electrode of the driving transistor T0 is Vref1. The turned-on fourth transistor T4 provides the first initialization signal from the first initialization signal terminal VINIT1 to the gate of the driving transistor T0, and the voltage Vg at the gate of the driving transistor T0 is Vinit1. The turned-on eighth transistor T8 provides the second initialization signal of the second initialization signal terminal VINIT2 to the anode of the light emitting device L, and the voltage VL on the anode of the light emitting device L is Vinit2.

[0137] In the threshold compensation phase F2, the first transistor T1 is turned on by the low level of the first control signal cs1, the second transistor T2 is turned on by the low level of the second control signal cs2, the third transistor T3 is turned on by the low level of the second control signal cs2, the fourth transistor T4 is turned off by the high level of the fifth control signal cs5, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the emission signal em, the seventh transistor T7 is turned off by the high level of the emission signal em, the eighth transistor T8 is turned on by the low level of the sixth control signal cs6, and the tenth transistor T10 is turned on by the low level of the second control signal cs2. The turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs at the first electrode of the driving transistor T0 is Vref1. The conductive second transistor T2 electrically connects the second electrode of the driving transistor T0 to the second node N2, and the conductive third transistor T3 electrically connects the second node N2 to the gate of the driving transistor T0. Since the conductive second and third transistors T2 and T3 form a diode connection for the driving transistor T0, the first reference signal input to the first electrode of the driving transistor T0 can pass through the diode-connected driving transistor T0 and be input to the gate of the driving transistor T0. This compensates the threshold voltage Vth of the driving transistor T0, so that the gate Vg voltage of the driving transistor T0 is Vref1 + Vth. Consequently, the voltage VN2 at the second node N2 and the voltage Vd at the second electrode of the driving transistor T0 are Vref1 + Vth. The conductive eighth transistor T8 supplies the second initialization signal from the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, resulting in a voltage VL at the anode of the light-emitting device L of Vinit2. The conductive tenth transistor T10 supplies the second reference signal from the second reference signal terminal VREF2 to the first node N1, resulting in a voltage VN1 at the first node N1 of Vref2. The second capacitor C2 stabilizes the voltage of the first node N1. The second capacitor C2 stabilizes the voltage of the first node N1.

[0138] During the data writing phase F3, the first transistor T1 is turned off by a high level of the first control signal cs1, the second transistor T2 is turned off by a high level of the second control signal cs2, the third transistor T3 is turned off by a high level of the second control signal cs2, the fourth transistor T4 is turned off by a high level of the fifth control signal cs5, the fifth transistor T5 is turned on by a low level of the fourth control signal cs4, the sixth transistor T6 is turned off by a high level of the emission signal em, the seventh transistor T7 is turned off by a high level of the emission signal em, the eighth transistor T8 is turned off by a high level of the sixth control signal cs6, and the tenth transistor T11 is turned off by a high level of the eighth control signal cs8. The turned-on fifth transistor T5 provides the data voltage signal at the data signal terminal DA to the first node N1. The first capacitor C1 couples the data voltage signal at the first node N1 to the gate of the driving transistor T0, resulting in a gate voltage Vg of the driving transistor T0 of Vref1+Vth+Vda-Vref2. The second capacitor C2 stabilizes the voltage at the first node N1.

[0139] During the light-emitting phase F4, the first transistor T1 is turned off under the control of a high level of the first control signal cs1, the second transistor T2 is turned off under the control of a high level of the second control signal cs2, the third transistor T3 is turned off under the control of a high level of the second control signal cs2, the fourth transistor T4 is turned off under the control of a high level of the fifth control signal cs5, the fifth transistor T5 is turned off under the control of a high level of the fourth control signal cs4, the sixth transistor T6 is turned on under the control of a low level of the light-emitting signal em, the seventh transistor T7 is turned on under the control of a low level of the light-emitting signal em, the eighth transistor T8 is turned off under the control of a high level of the sixth control signal cs6, and the tenth transistor T10 is turned off under the control of a high level of the eighth control signal cs8. The turned-on sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0, so that the voltage of the first electrode Vs of the driving transistor T0 is Vdd. The turned-on seventh transistor T7 connects the second electrode of the driving transistor T0 to the light-emitting device L, driving the light-emitting device L to emit light. Therefore, the driving transistor T0 operates in the saturation region, and the driving current I generated by it can be expressed as:

[0140] For example, the first control signal terminal CS1 and the sixth control signal terminal CS6 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0141] The present disclosure provides further schematic diagrams of pixel circuits, as shown in Figure 9, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0142] In the embodiment of the present disclosure, as shown in FIG9 , the fifth control signal terminal CS5 and the light emitting control signal terminal EM may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0143] In the embodiment of the present disclosure, as shown in FIG9 , the second reset circuit 80 is further included, coupled to the second electrode of the driving transistor T0 and configured to provide the signal of the third initialization signal terminal VINIT3 to the second electrode of the driving transistor T0 in response to the signal of the seventh control signal terminal CS7.

[0144] In the embodiment of the present disclosure, as shown in Figure 9, the second reset circuit 80 includes: a ninth transistor T9; wherein the gate of the ninth transistor T9 is coupled to the seventh control signal terminal CS7, the first electrode of the ninth transistor T9 is coupled to the second electrode of the driving transistor T0, and the second electrode of the ninth transistor T9 is coupled to the third initialization signal terminal VINIT3.

[0145] For example, the ninth transistor T9 can be turned on under the control of the active level of the seventh control signal transmitted on the seventh control signal terminal CS7, and can be turned off under the control of the inactive level of the seventh control signal. For example, the ninth transistor T9 can be set as an N-type transistor, in which case the active level of the seventh control signal is a high level, and the inactive level of the seventh control signal is a low level. Alternatively, the ninth transistor T9 can be set as a P-type transistor, in which case the active level of the seventh control signal is a low level, and the inactive level of the seventh control signal is a high level.

[0146] In the embodiment of the present disclosure, as shown in Figure 9, the third reset circuit 90 further includes: a thirteenth transistor T13; wherein the gate of the thirteenth transistor T13 is coupled to the ninth control signal terminal CS9, the first electrode of the thirteenth transistor T13 is coupled to the third node N3, and the second electrode of the thirteenth transistor T13 is coupled to the third reference signal terminal VREF3.

[0147] For example, the thirteenth transistor T13 can be turned on under the control of the active level of the ninth control signal transmitted on the ninth control signal terminal CS9, and can be turned off under the control of the inactive level of the ninth control signal. For example, the thirteenth transistor T13 can be set as an N-type transistor, in which case the active level of the ninth control signal is a high level, and the inactive level of the ninth control signal is a low level. Alternatively, the thirteenth transistor T13 can be set as a P-type transistor, in which case the active level of the ninth control signal is a low level, and the inactive level of the ninth control signal is a high level.

[0148] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG9 as an example in combination with the signal timing diagram shown in FIG10 .

[0149] As shown in Figure 10, em represents the light-emitting signal of the light-emitting control signal terminal EM, cs1 represents the first control signal of the first control signal terminal CS1, cs2 represents the second control signal of the second control signal terminal CS2, cs4 represents the fourth control signal of the fourth control signal terminal CS4, cs5 represents the fifth control signal of the fifth control signal terminal CS5, cs6 represents the sixth control signal of the sixth control signal terminal CS6, cs7 represents the seventh control signal of the seventh control signal terminal CS7, cs8 represents the eighth control signal of the eighth control signal terminal CS8, cs9 represents the ninth control signal of the ninth control signal terminal CS9, da represents the data voltage signal of the data signal terminal DA, and vinit2 represents the second initialization signal of the second initialization signal terminal VINIT2.

[0150] In the reset phase F1, the first transistor T1 is turned off under the control of the high level of the first control signal cs1, the second transistor T2 is turned on under the control of the low level of the second control signal cs2, the third transistor T3 is turned on under the control of the low level of the second control signal cs2, the fourth transistor T4 is turned off under the control of the high level of the emission signal em, the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4, the sixth transistor T6 is turned off under the control of the high level of the emission signal em, the seventh transistor T7 is turned off under the control of the high level of the emission signal em, the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, the ninth transistor T9 is turned on under the control of the low level of the seventh control signal cs7, the eleventh transistor T11 is turned off under the control of the high level of the eighth control signal cs8, the twelfth transistor T12 is turned off under the control of the high level of the eighth control signal cs8, and the thirteenth transistor T13 is turned off under the control of the high level of the ninth control signal cs9. The turned-on ninth transistor T9 provides the third initialization signal from the third initialization signal terminal VINIT3 to the second electrode of the driving transistor T0, and the voltage Vd at the second electrode of the driving transistor T0 is Vinit3. The turned-on second transistor T2 and the turned-on third transistor T3 provide the third initialization signal from the second electrode of the driving transistor T0 to the gate of the driving transistor T0, and the voltage Vg at the gate of the driving transistor T0 is Vinit3. Vinit3 represents the voltage of the third initialization signal.

[0151] In the threshold compensation stage F2, the first transistor T1 is turned on under the control of the low level of the first control signal cs1, the second transistor T2 is turned on under the control of the low level of the second control signal cs2, the third transistor T3 is turned on under the control of the low level of the second control signal cs2, the fourth transistor T4 is turned off under the control of the high level of the emission signal em, the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4, the sixth transistor T6 is turned off under the control of the high level of the emission signal em, the seventh transistor T7 is turned off under the control of the high level of the emission signal em, the eighth transistor T8 is turned on under the control of the low level of the sixth control signal cs6, the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7, the eleventh transistor T11 is turned on under the control of the low level of the eighth control signal cs8, the twelfth transistor T12 is turned on under the control of the low level of the eighth control signal cs8, and the thirteenth transistor T13 is turned off under the control of the high level of the ninth control signal cs9. The conductive first transistor T1 provides the first reference signal at the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, resulting in a voltage Vs at the first electrode of the driving transistor T0 of Vref1. The conductive second transistor T2 connects the second electrode of the driving transistor T0 to the second node N2, and the conductive third transistor T3 connects the second node N2 to the gate of the driving transistor T0. Since the conductive second transistors T2 and third transistors T3 form a diode connection for the driving transistor T0, the first reference signal input to the first electrode of the driving transistor T0 can pass through the diode-connected driving transistor T0 and be input to the gate of the driving transistor T0. This compensates the threshold voltage Vth of the driving transistor T0, so that the gate Vg of the driving transistor T0 is Vref1+Vth. Consequently, the voltage VN2 at the second node N2 and the voltage Vd at the second electrode of the driving transistor T0 are Vref1+Vth. The conductive eighth transistor T8 provides the second initialization signal at the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, resulting in a voltage VL at the anode of the light-emitting device L of Vinit2. The turned-on twelfth transistor T12 provides the second reference signal of the second reference signal terminal VREF2 to the third node N3, and the turned-on eleventh transistor T11 provides the second reference signal on the third node N3 to the first node N1, so that the voltage VN1 on the first node N1 is Vref2. The second capacitor C2 stabilizes the voltage of the first node N1.

[0152] In the data writing phase F3, the first transistor T1 is turned off under the control of the high level of the first control signal cs1, the second transistor T2 is turned off under the control of the high level of the second control signal cs2, the third transistor T3 is turned off under the control of the high level of the second control signal cs2, the fourth transistor T4 is turned off under the control of the high level of the light-emitting signal em, the fifth transistor T5 is turned on under the control of the low level of the fourth control signal cs4, the sixth transistor T6 is turned off under the control of the high level of the light-emitting signal em, the seventh transistor T7 is turned off under the control of the high level of the light-emitting signal em, the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7, the eleventh transistor T11 is turned off under the control of the high level of the eighth control signal cs8, the twelfth transistor T12 is turned off under the control of the high level of the eighth control signal cs8, and the thirteenth transistor T13 is turned off under the control of the high level of the ninth control signal cs9. The turned-on fifth transistor T5 provides the data voltage signal of the data signal terminal DA to the first node N1. The first capacitor C1 couples the data voltage signal of the first node N1 to the gate of the driving transistor T0. The gate voltage Vg of the driving transistor T0 is Vref1+Vth+Vda-Vref2. The second capacitor C2 stabilizes the voltage of the first node N1.

[0153] In the light-emitting stage F4, the first transistor T1 is turned off under the control of the high level of the first control signal cs1, the second transistor T2 is turned off under the control of the high level of the second control signal cs2, the third transistor T3 is turned off under the control of the high level of the second control signal cs2, the fourth transistor T4 is turned on under the control of the low level of the light-emitting signal em, the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4, the sixth transistor T6 is turned on under the control of the low level of the light-emitting signal em, the seventh transistor T7 is turned on under the control of the low level of the light-emitting signal em, the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7, the eleventh transistor T11 is turned off under the control of the high level of the eighth control signal cs8, the twelfth transistor T12 is turned off under the control of the high level of the eighth control signal cs8, and the thirteenth transistor T13 is turned on under the control of the low level of the ninth control signal cs9. The conductive fourth transistor T4 provides the first initialization signal from the first initialization signal terminal VINIT1 to the second node N2, and the voltage VN2 at the second node N2 is Vinit1. The conductive thirteenth transistor T13 provides the third reference signal from the third reference signal terminal VREF3 to the third node N3, and the voltage VN3 at the third node N3 is Vref3. The conductive sixth transistor T6 provides the first power supply voltage Vdd from the first power supply terminal VDD to the first electrode of the driving transistor T0, and the voltage Vs of the first electrode of the driving transistor T0 is Vdd. The conductive seventh transistor T7 connects the second electrode of the driving transistor T0 to the light-emitting device L, driving the light-emitting device L to emit light. Therefore, the driving transistor T0 operates in the saturation region, and the driving current I generated by it can be expressed as: in, μ represents the mobility of the driving transistor T0 , Cox represents the capacitance per unit area of ​​the gate insulating layer of the driving transistor T0 , and W / L represents the channel width-to-length ratio of the driving transistor T0 .

[0154] For example, the first control signal terminal CS1, the sixth control signal terminal CS6, and the eighth control signal terminal CS8 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0155] For example, the light emitting control signal terminal EM and the ninth control signal terminal CS9 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0156] The present disclosure provides further schematic diagrams of pixel circuits, as shown in Figure 11, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0157] For example, as shown in FIG11 , the third reference signal terminal and the first initialization signal terminal VINIT1 may be the same signal terminal, which can reduce the number of signal lines and the space occupied by wiring.

[0158] The signal timing diagram corresponding to the pixel circuit shown in Figure 11 may be shown in Figure 10. Moreover, the specific working process of the pixel circuit shown in Figure 11 combined with the signal timing diagram shown in Figure 10 can refer to the description of the above embodiment and will not be repeated here.

[0159] The present disclosure provides further schematic diagrams of pixel circuits, as shown in Figure 12, which are variations of the implementations in the above embodiments. The following only describes the differences between this embodiment and the above embodiments, and the similarities are omitted.

[0160] The following describes the working process of the pixel circuit provided by the embodiment of the present disclosure by taking the pixel circuit shown in FIG12 as an example and combining it with the signal timing diagram shown in FIG10 .

[0161] In the reset phase F1, the first transistor T1 is turned off by the high level of the first control signal cs1, the second transistor T2 is turned on by the low level of the second control signal cs2, the third transistor T3 is turned on by the low level of the second control signal cs2, the fourth transistor T4 is turned off by the high level of the light-emitting signal em, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the light-emitting signal em, the seventh transistor T7 is turned off by the high level of the light-emitting signal em, the eighth transistor T8 is turned off by the high level of the sixth control signal cs6, the ninth transistor T9 is turned on by the low level of the seventh control signal cs7, the eleventh transistor T11 is turned off by the high level of the eighth control signal cs8, and the twelfth transistor T12 is turned off by the high level of the eighth control signal cs8. The turned-on ninth transistor T9 provides the third initialization signal from the third initialization signal terminal VINIT3 to the second electrode of the driving transistor T0, so that the voltage Vd at the second electrode of the driving transistor T0 is Vinit3. The turned-on second transistor T2 and the turned-on third transistor T3 provide the third initialization signal on the second electrode of the driving transistor T0 to the gate of the driving transistor T0 , and the voltage Vg on the gate of the driving transistor T0 is Vinit3 .

[0162] In the threshold compensation phase F2, the first transistor T1 is turned on by the low level of the first control signal cs1, the second transistor T2 is turned on by the low level of the second control signal cs2, the third transistor T3 is turned on by the low level of the second control signal cs2, the fourth transistor T4 is turned off by the high level of the emission signal em, the fifth transistor T5 is turned off by the high level of the fourth control signal cs4, the sixth transistor T6 is turned off by the high level of the emission signal em, the seventh transistor T7 is turned off by the high level of the emission signal em, the eighth transistor T8 is turned on by the low level of the sixth control signal cs6, the ninth transistor T9 is turned off by the high level of the seventh control signal cs7, the eleventh transistor T11 is turned on by the low level of the eighth control signal cs8, and the twelfth transistor T12 is turned on by the low level of the eighth control signal cs8. The turned-on first transistor T1 provides the first reference signal of the first reference signal terminal VREF1 to the first electrode of the driving transistor T0, and the voltage Vs at the first electrode of the driving transistor T0 is Vref1. The conductive second transistor T2 electrically connects the second electrode of the driving transistor T0 to the second node N2, and the conductive third transistor T3 electrically connects the second node N2 to the gate of the driving transistor T0. Since the conductive second transistor T2 and the conductive third transistor T3 can form a diode connection for the driving transistor T0, the first reference signal input to the first electrode of the driving transistor T0 can pass through the diode-connected driving transistor T0 and be input to the gate of the driving transistor T0, thereby compensating the threshold voltage Vth of the driving transistor T0 so that the gate Vg voltage of the driving transistor T0 is Vref1+Vth. Consequently, the voltage VN2 at the second node N2 and the voltage Vd at the second electrode of the driving transistor T0 are Vref1+Vth. The conductive eighth transistor T8 provides the second initialization signal from the second initialization signal terminal VINIT2 to the anode of the light-emitting device L, resulting in a voltage VL at the anode of the light-emitting device L of Vinit2. The turned-on twelfth transistor T12 provides the second reference signal of the second reference signal terminal VREF2 to the third node N3, and the turned-on eleventh transistor T11 provides the second reference signal on the third node N3 to the first node N1, so that the voltage VN1 on the first node N1 is Vref2. The second capacitor C2 stabilizes the voltage of the first node N1.

[0163] In the data writing phase F3, the first transistor T1 is turned off under the control of the high level of the first control signal cs1, the second transistor T2 is turned off under the control of the high level of the second control signal cs2, the third transistor T3 is turned off under the control of the high level of the second control signal cs2, the fourth transistor T4 is turned off under the control of the high level of the light-emitting signal em, the fifth transistor T5 is turned on under the control of the low level of the fourth control signal cs4, the sixth transistor T6 is turned off under the control of the high level of the light-emitting signal em, the seventh transistor T7 is turned off under the control of the high level of the light-emitting signal em, the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7, the eleventh transistor T11 is turned off under the control of the high level of the eighth control signal cs8, and the twelfth transistor T12 is turned off under the control of the high level of the eighth control signal cs8. The turned-on fifth transistor T5 provides the data voltage signal of the data signal terminal DA to the first node N1. The first capacitor C1 couples the data voltage signal of the first node N1 to the gate of the driving transistor T0. The gate voltage Vg of the driving transistor T0 is Vref1+Vth+Vda-Vref2. The second capacitor C2 stabilizes the voltage of the first node N1.

[0164] In the light-emitting phase F4, the first transistor T1 is turned off under the control of the high level of the first control signal cs1, the second transistor T2 is turned off under the control of the high level of the second control signal cs2, the third transistor T3 is turned off under the control of the high level of the second control signal cs2, the fourth transistor T4 is turned on under the control of the low level of the light-emitting signal em, the fifth transistor T5 is turned off under the control of the high level of the fourth control signal cs4, the sixth transistor T6 is turned on under the control of the low level of the light-emitting signal em, the seventh transistor T7 is turned on under the control of the low level of the light-emitting signal em, the eighth transistor T8 is turned off under the control of the high level of the sixth control signal cs6, the ninth transistor T9 is turned off under the control of the high level of the seventh control signal cs7, the eleventh transistor T11 is turned off under the control of the high level of the eighth control signal cs8, and the twelfth transistor T12 is turned off under the control of the high level of the eighth control signal cs8. The turned-on fourth transistor T4 provides the first initialization signal of the first initialization signal terminal VINIT1 to the second node N2, and the voltage VN2 at the second node N2 is Vinit1. The turned-on sixth transistor T6 provides the first power supply voltage Vdd of the first power supply terminal VDD to the first electrode of the driving transistor T0. Then, the voltage of the first electrode Vs of the driving transistor T0 is Vdd. The turned-on seventh transistor T7 connects the second electrode of the driving transistor T0 to the light-emitting device L, driving the light-emitting device L to emit light. Then, the driving transistor T0 operates in the saturation region, and the driving current I generated by it can be expressed as: in, μ represents the mobility of the driving transistor T0 , Cox represents the capacitance per unit area of ​​the gate insulating layer of the driving transistor T0 , and W / L represents the channel width-to-length ratio of the driving transistor T0 .

[0165] Based on the same disclosed concept, the present disclosure also provides a display device including the aforementioned pixel circuit provided in the present disclosure. The principles of this display device are similar to those of the aforementioned pixel circuit, so the implementation of this display device can refer to the implementation of the aforementioned pixel circuit, and the repeated parts will not be repeated here.

[0166] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0167] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0168] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A pixel circuit comprising: Light-emitting devices; a driving transistor coupled to the light emitting device and configured to generate a driving current for driving the light emitting device to emit light according to a data voltage signal; a first compensation circuit coupled to the driving transistor and configured to provide a first reference signal from a first reference signal terminal to a first electrode of the driving transistor in response to a signal from a first control signal terminal; a second compensation circuit coupled to the driving transistor and configured to provide a threshold voltage of the driving transistor and a first reference signal input to a first electrode of the driving transistor to a gate of the driving transistor in response to signals at the second control signal terminal and a third control signal terminal; a data writing circuit coupled to the first node and configured to provide the data voltage signal of the data signal terminal to the first node in response to a signal of the fourth control signal terminal; a coupling control circuit coupled to the first node and the driving transistor, and configured to couple the data voltage signal of the first node to the gate of the driving transistor; The light emitting control circuit is coupled to the light emitting device and the driving transistor, and is configured to connect the first electrode of the driving transistor to the first power supply terminal and the second electrode of the driving transistor to the light emitting device in response to the signal of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

2. The pixel circuit according to claim 1, wherein: The first compensation circuit includes: a first transistor; A gate of the first transistor is coupled to the first control signal terminal, a first electrode of the first transistor is coupled to the first electrode of the driving transistor, and a second electrode of the first transistor is coupled to the first reference signal terminal.

3. The pixel circuit according to claim 1, wherein: The second compensation circuit includes: a second transistor and a third transistor; The gate of the second transistor is coupled to the second control signal terminal, the first electrode of the second transistor is coupled to the second node, and the second electrode of the second transistor is coupled to the second electrode of the driving transistor; The gate of the third transistor is coupled to the third control signal terminal, the first electrode of the third transistor is coupled to the gate of the driving transistor, and the second electrode of the third transistor is coupled to the second node.

4. The pixel circuit according to claim 3, wherein: The second compensation circuit further includes: a fourth transistor; The gate of the fourth transistor is coupled to the fifth control signal terminal, the first electrode of the fourth transistor is coupled to the gate of the driving transistor or the second node, and the second electrode of the fourth transistor is coupled to the first initialization signal terminal.

5. The pixel circuit according to claim 4, wherein: The fifth control signal terminal and the light emitting control signal terminal may be the same signal terminal.

6. The pixel circuit according to any one of claims 1 to 5, wherein: The data writing circuit includes: a fifth transistor; A gate of the fifth transistor is coupled to the fourth control signal terminal, a first electrode of the fifth transistor is coupled to the data signal terminal, and a second electrode of the fifth transistor is coupled to the first node.

7. The pixel circuit according to any one of claims 1 to 5, wherein: The coupling control circuit includes: a first capacitor; A first electrode of the first capacitor is coupled to the first node, and a second electrode of the first capacitor is coupled to the gate of the driving transistor.

8. The pixel circuit according to any one of claims 1 to 5, wherein: The light emitting control circuit includes: a sixth transistor and a seventh transistor; The gate of the sixth transistor is coupled to the light emitting control signal terminal, the first electrode of the sixth transistor is coupled to the first power supply terminal, and the second electrode of the sixth transistor is coupled to the first electrode of the driving transistor; The gate of the seventh transistor is coupled to the light emitting control signal terminal, the first electrode of the seventh transistor is coupled to the second electrode of the driving transistor, and the second electrode of the seventh transistor is coupled to the light emitting device.

9. The pixel circuit according to any one of claims 1 to 8, wherein: Also includes: The first reset circuit is coupled to the light emitting device and is configured to provide a signal from a second initialization signal terminal to the light emitting device in response to a signal from a sixth control signal terminal.

10. The pixel circuit according to claim 9, wherein: The first reset circuit includes: an eighth transistor; A gate of the eighth transistor is coupled to the sixth control signal terminal, a first electrode of the eighth transistor is coupled to the light emitting device, and a second electrode of the eighth transistor is coupled to the second initialization signal terminal.

11. The pixel circuit according to any one of claims 1 to 8, wherein: Also includes: The voltage stabilizing circuit is coupled to the first node and configured to stabilize the voltage of the first node.

12. The pixel circuit according to claim 11, wherein: The voltage stabilizing circuit includes: a second capacitor; A first electrode of the second capacitor is coupled to the first power supply terminal, and a second electrode of the second capacitor is coupled to the first node.

13. The pixel circuit according to any one of claims 1 to 8, wherein: Also includes: The second reset circuit is coupled to the second electrode of the driving transistor and is configured to provide a signal from a third initialization signal terminal to the second electrode of the driving transistor in response to a signal from a seventh control signal terminal.

14. The pixel circuit according to claim 13, wherein: The second reset circuit includes: a ninth transistor; A gate of the ninth transistor is coupled to the seventh control signal terminal, a first electrode of the ninth transistor is coupled to the second electrode of the driving transistor, and a second electrode of the ninth transistor is coupled to the third initialization signal terminal.

15. The pixel circuit according to any one of claims 1 to 8, wherein: The system further includes: a third reset circuit coupled to the first node and configured to provide a signal from the second reference signal terminal to the first node in response to a signal from the eighth control signal terminal.

16. The pixel circuit according to claim 15, wherein: The third reset circuit includes: a tenth transistor; A gate of the tenth transistor is coupled to the eighth control signal terminal, a first electrode of the tenth transistor is coupled to the first node, and a second electrode of the tenth transistor is coupled to the second reference signal terminal.

17. The pixel circuit according to claim 15, wherein: The third reset circuit includes: an eleventh transistor and a twelfth transistor; The gate of the eleventh transistor is coupled to the eighth control signal terminal, the first electrode of the eleventh transistor is coupled to the first node, and the second electrode of the eleventh transistor is coupled to the third node; A gate of the twelfth transistor is coupled to the eighth control signal terminal, a first electrode of the twelfth transistor is coupled to the third node, and a second electrode of the eleventh transistor is coupled to the second reference signal terminal.

18. The pixel circuit according to claim 17, wherein: The third reset circuit further includes: a thirteenth transistor; A gate of the thirteenth transistor is coupled to the ninth control signal terminal, a first electrode of the thirteenth transistor is coupled to the third node, and a second electrode of the thirteenth transistor is coupled to the third reference signal terminal.

19. A display device, wherein: The method comprises the pixel circuit according to any one of claims 1 to 18.

20. A driving method for a pixel circuit according to any one of claims 1 to 18, wherein: include: In the reset phase, the first compensation circuit provides the first reference signal from the first reference signal terminal to the first electrode of the driving transistor in response to the signal from the first control signal terminal; In the threshold compensation stage, the first compensation circuit responds to the signal of the first control signal terminal and provides the first reference signal of the first reference signal terminal to the first electrode of the driving transistor; the second compensation circuit responds to the signals of the second control signal terminal and the third control signal terminal and adjusts the threshold voltage of the driving transistor to voltage and a first reference signal input to a first electrode of the driving transistor, and provided to a gate of the driving transistor; In the data writing phase, the data writing circuit provides the data voltage signal of the data signal terminal to the first node in response to the signal of the fourth control signal terminal; The coupling control circuit couples the data voltage signal of the first node to the gate of the driving transistor; In the light emitting stage, the light emitting control circuit connects the first electrode of the driving transistor to the first power supply terminal and the second electrode of the driving transistor to the light emitting device in response to the signal of the light emitting control signal terminal, thereby driving the light emitting device to emit light.

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